Spread spectrum clock signal testing device and method based on ATE test machine

Abstract

The present invention belongs to the field of electronic testing, and specifically relates to a spread spectrum clock signal testing device and method based on an ATE test machine. In the scheme of the present invention, the ATE test machine connects a chip under test and a spread spectrum clock test circuit board through a bus interface; the chip under test needs to provide two clocks to the spread spectrum clock test circuit board, and the ATE test machine transmits the working parameter range to the spread spectrum clock test circuit board, and the spread spectrum clock test circuit board completes the spread spectrum clock signal working parameter measurement, compares it with the working parameter range provided by the ATE test machine, and returns the comparison result to the ATE test machine. The present invention realizes the spread spectrum clock test function of the ATE test machine through an externally expanded spread spectrum clock test circuit board, can sample and analyze the spread spectrum clocks of various digital devices, and has low hardware cost, fast test response speed, and can replace expensive desktop test instruments and equipment to a certain extent, and has strong feasibility.

Description

Technical Field

[0001] The invention belongs to the field of electronic testing, and in particular relates to a spread spectrum clock signal testing device and method based on an ATE testing machine. Background Art

[0002] Spread spectrum clock is widely used in engineering projects with electromagnetic compatibility design requirements, such as PCIE 3.0 bus, DDR3 storage and other fields. Figure 1 By frequency modulating the clock signal within a certain frequency range, the signal power is dispersed within a certain frequency domain bandwidth, thereby reducing the peak power of the clock signal in the frequency domain.

[0003] At present, mainstream test instrument manufacturers have test solutions for spread spectrum clocks. For example, Tektronix's DPO7000 series high-performance oscilloscopes integrate DPOJET test software, which can test the modulation period and frequency range parameters of spread spectrum clock signals. Although the DPO7000 series oscilloscopes have mature technology for measuring spread spectrum clocks, the cost of the instruments is high and cannot meet the needs of chip batch testing scenarios. Chip testing needs to be carried out under different test function conditions, working voltage conditions, working environment temperature and other conditions, and the test efficiency will directly affect the test cost.

[0004] In addition, in the field of chip testing, it is mainly based on ATE test machines, such as TERADYNE's ULTRAFLEX and J750 test machines. The test machine has a large number of digital I / O test interfaces. During the test, it is necessary to inject test stimulus signals into the DUT, compare the timing logic of the signal actually output by the DUT with the expected value, and determine whether the function is normal. Since the timing of the spread spectrum clock is difficult to accurately estimate and the digital I / O sampling rate of the ATE test machine is limited, the modulation period and frequency range of the spread spectrum clock signal cannot be tested. Therefore, in order to implement the test of the spread spectrum clock on the ATE test machine, the hardware of the test equipment needs to be designed and expanded to meet the different needs of the spread spectrum clock function test and performance test. Summary of the invention

[0005] In view of this, an object of the present invention is to reduce the cost of chip spread spectrum clock signal testing, improve test efficiency, and facilitate batch testing.

[0006] In order to solve the above technical problems, the present invention provides a spread spectrum clock signal testing device based on an ATE test machine, including an ATE test machine and a spread spectrum clock test circuit board; the ATE test machine is connected to a chip under test and the spread spectrum clock test circuit board through a bus interface; the chip under test needs to provide two clocks to the spread spectrum clock test circuit board, wherein one is a reference clock signal with a stable frequency, and the other is a spread spectrum clock signal; the ATE test machine transmits the working parameter range expected according to the type of the chip under test and required for qualified judgment to the spread spectrum clock test circuit board, the spread spectrum clock test circuit board completes the measurement of the working parameters of the spread spectrum clock signal, compares it with the working parameter range provided by the ATE test machine, and returns the comparison result to the ATE test machine.

[0007] Furthermore, the spread spectrum clock test circuit board includes a first low-pass filter, a second low-pass filter, a mixer, a third low-pass filter, a comparator and a digital detection circuit; the first low-pass filter performs a low-pass filter on the spread spectrum clock signal being tested, and the second low-pass filter performs a low-pass filter on the reference clock signal. The first low-pass filter and the second low-pass filter respectively filter out the higher harmonics of the spread spectrum clock signal being tested and the reference clock, and retain the baseband part; the first low-pass filter and the second low-pass filter send the low-pass filtered signal to the mixer for mixing, and the third low-pass filter performs a low-pass filter on the mixed signal and sends it to the comparator, the comparator performs zero-crossing detection to obtain a digital baseband signal and sends it to the digital detection circuit, the digital detection circuit analyzes the digital baseband signal to obtain working parameters, compares them with the working parameter range provided by the ATE test machine, compares whether the test result is within the qualified range, and returns the comparison result to the ATE test machine.

[0008] Furthermore, the digital detection circuit includes a pulse width repetition period analysis module, a spread spectrum clock modulation period analysis module, a frequency offset analysis module and a comparison module; the pulse width repetition period analysis module analyzes the pulse width of the digital baseband signal to find the repetition period of the pulse signal with the widest or narrowest time width, that is, the modulation period Tmod; the spread spectrum clock modulation period analysis module obtains the modulation period Tssc of the spread spectrum clock being tested based on the frequency relationship between the reference clock signal and the spread spectrum clock signal being tested, Tssc=Tmod; the spread spectrum clock modulation period analysis module analyzes the digital baseband signal to find the pulse width Tmin of the pulse with the narrowest time width, and obtains the approximate value 1 / Tmin of the maximum frequency offset between the spread spectrum clock and the reference clock.

[0009] The present invention also provides a spread spectrum clock signal testing method based on an ATE test machine, using the above-mentioned testing device, which is characterized by comprising:

[0010] Step 1: The ATE test machine connects the chip under test and the spread spectrum clock test circuit board through a bus interface, and connects two clock output ends of the chip under test to the spread spectrum clock test circuit board through signal lines;

[0011] Step 2, the ATE test machine transmits the expected operating parameter range required for qualified judgment based on the type of chip under test to the spread spectrum clock test circuit board;

[0012] Step 3: The chip under test needs to provide two clocks to the spread spectrum clock test circuit board, one of which is a reference clock signal with a stable frequency and the other is a spread spectrum clock signal;

[0013] Step 4: After the spread spectrum clock test circuit board completes the parameter measurement process, it is compared with the working parameter range provided by the ATE test machine, and the test result is returned to the ATE test machine.

[0014] Further, step 4 includes:

[0015] Step 4.1, low-pass filtering is performed on the tested spread spectrum clock signal and the reference clock signal respectively to filter out high-order harmonics and retain the fundamental frequency part;

[0016] Step 4.2, sending the two low-pass filtered signals to the mixer for mixing;

[0017] Step 4.3, low-pass filtering the mixed signal;

[0018] Step 4.4, performing zero-crossing detection on the mixed and low-pass filtered signal to obtain a digital baseband signal;

[0019] Step 4.5, analyze the digital baseband signal to obtain the operating parameters, compare them with the operating parameter range provided by the ATE test machine, compare whether the test results are within the qualified range, and return the comparison results to the ATE test machine.

[0020] Furthermore, the analysis of the digital baseband signal to obtain the working parameters described in step 4.5 is specifically as follows: first, the pulse width of the digital baseband signal obtained by zero-crossing detection is analyzed to find the repetition period of the pulse signal with the widest or narrowest time width, that is, the modulation period Tmod; second, based on the frequency relationship between the reference clock signal and the tested spread spectrum clock signal, the modulation period Tssc of the tested spread spectrum clock is obtained, Tssc=Tmod; third, the digital baseband signal obtained by zero-crossing detection is analyzed to find the pulse width Tmin of the pulse with the narrowest time width, and the approximate value 1 / Tmin of the maximum frequency offset between the spread spectrum clock and the reference clock is obtained.

[0021] Beneficial Effects

[0022] The present invention realizes the spread spectrum clock test function by combining an externally expanded spread spectrum clock test circuit board with an ATE test machine. When testing the chip spread spectrum clock signal, the mixing technology and the zero-crossing detection method of the baseband signal are used to obtain a digital signal with a frequency far lower than the spread spectrum clock, so that the spread spectrum clock of various digital devices such as FPGA, CPLD, ARM microcontroller, PowerPC microcontroller, DSP microcontroller, etc. can be sampled and analyzed, and the hardware cost is low, the test response speed is fast, and it can replace expensive desktop test instruments and equipment to a certain extent, and has strong feasibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of spread spectrum clock;

[0024] Figure 2 It is a component module diagram of the spread spectrum clock signal testing device based on ATE testing machine of the present invention;

[0025] Figure 3 It is the basic structure of the spread spectrum clock signal test circuit board of the test device of the present invention;

[0026] Figure 4 It is a waveform diagram of the signal processing flow of the test device of the present invention;

[0027] Figure 5 is a waveform diagram of a digital baseband signal obtained after zero-crossing detection of the present invention;

[0028] Figure 6 It is a schematic diagram of the spread spectrum signal to be measured in the present invention. DETAILED DESCRIPTION

[0029] The specific implementation modes of the present invention are described in detail below with reference to the accompanying drawings.

[0030] like Figure 2 As shown, the spread spectrum clock signal testing device based on the ATE test machine of the present invention includes an ATE test machine and a spread spectrum clock testing circuit board. The ATE test machine is connected to the chip under test and the spread spectrum clock testing circuit board through a bus interface.

[0031] The spread spectrum clock test circuit board is a special test circuit board for the ATE test machine, which is used to measure the modulation period and frequency deviation parameters of the spread spectrum clock.

[0032] The chip under test needs to provide two clocks to the spread spectrum clock test circuit board, one of which is a reference clock signal with a stable frequency and the other is a spread spectrum clock signal. For example, if the chip under test is an FPGA programmable logic gate array chip, a clock management unit in the chip can be used to generate a reference clock signal, and another clock management unit can be selected to output the spread spectrum clock signal to be tested.

[0033] The frequency of the reference clock signal is generally set to a value close to the frequency of the spread spectrum clock signal being measured. The frequency of the reference clock signal can be less than or equal to the minimum value of the spread spectrum clock signal being measured, or greater than or equal to the maximum value of the spread spectrum clock signal being measured, or between the maximum value and the minimum value of the spread spectrum clock signal being measured. If the difference between the frequency of the reference clock signal and the frequency of the spread spectrum clock signal being measured is too large, the frequency of the clock signal output by the mixer may exceed the operating frequency range supported by the back-end comparator circuit. Therefore, the difference between the frequency of the reference clock signal and the frequency of the spread spectrum signal being measured is determined by the operating frequency range supported by the comparator circuit.

[0034] The measured spread spectrum clock signal is a clock signal output after frequency modulation, and the frequency of the output clock changes periodically between the maximum frequency value and the minimum frequency value; the reference clock signal is a point frequency clock signal with stable frequency. The former is obtained after the first low-pass filter as the RF input signal of the mixer; the latter is used as the local oscillator input signal of the mixer after the second low-pass filter.

[0035] The working process of the spread spectrum clock signal test device based on the ATE test machine is as follows: the ATE test machine transmits the range of working parameters required for qualified determination according to the type of the tested chip to the spread spectrum clock test circuit board. After the spread spectrum clock test circuit board completes the parameter measurement process, it compares it with the working parameter range provided by the ATE test machine and returns the test result, such as "qualified" or "unqualified", to the ATE test machine. According to the actual needs of the user, the fault type feedback signal can be further defined.

[0036] The basic structure of the spread spectrum clock test circuit board in the present invention is as follows: Figure 3 As shown. This solution requires two input clocks, one of which is the spread spectrum clock signal to be tested, and the other is the reference clock signal. The two input clock signals are filtered using low-pass filters, mixed by mixers, and then passed through a low-pass filter. Then, a comparator is used to detect zero crossing of the waveform to obtain a digital baseband signal. Finally, the baseband signal is analyzed based on the digital detection circuit, compared with the expected waveform parameters of the external input, and it is determined whether the test result is within the expected range.

[0037] The waveform diagram of the signal processing flow of the spread spectrum clock signal testing device of the present invention is as follows: Figure 4As shown. First, the two input clock signals are digital signals. The high-order harmonics are filtered out by the low-pass filter, and only the base frequency part is retained. Then, after mixing and low-pass filtering, an analog signal similar to linear frequency modulation is obtained. After zero-crossing detection using a comparator, a digital signal is obtained. In addition, the frequency of the digital signal is much lower than the reference clock signal of the measured spread spectrum clock signal, so it can be easily sampled and parameters such as pulse width can be analyzed.

[0038] On the basis of the above, by analyzing the pulse width of the comparator output signal, we can find the repetition period of the pulse signal with the widest or narrowest time width, that is, the modulation period Tmod, such as Figure 5 As shown. Combining the frequency relationship between the reference clock and the spread spectrum clock, the modulation period Tssc of the spread spectrum clock can be obtained. At the same time, by measuring the minimum pulse width (Tmin) of the comparator output signal, the approximate value of the maximum frequency deviation between the spread spectrum clock and the reference clock can also be obtained.

[0039] Take the upper spread spectrum mode as an example, the explanation is as follows: If the measured spread spectrum clock signal is in the upper spread spectrum mode, the clock frequency after the spread spectrum is higher than the clock frequency before the spread spectrum, such as Figure 6 In this mode, if the reference clock frequency is the same as the clock frequency before spectrum spread, then Figure 5 The obtained modulation period Tmod is the same as the modulation period Tssc of the spread spectrum clock. The maximum frequency deviation Fdev_max of the spread spectrum clock is approximately equal to 1 / Tmin.

[0040] The above are only preferred embodiments of the invention and are not intended to limit the invention. Any modifications, equivalent substitutions, improvements, etc. made within the conceptual principles of the invention should be included in the protection scope of the invention.

Claims

1. A spread spectrum clock signal test device based on an ATE test machine, characterized in that Including ATE test machine and spread spectrum clock test circuit board; The ATE test machine connects the chip under test and the spread spectrum clock test circuit board through a bus interface; The chip under test needs to provide two clocks to the spread spectrum clock test circuit board, one of which is a reference clock signal with a stable frequency and the other is a spread spectrum clock signal; the frequency of the reference clock signal is set to a value close to the frequency of the spread spectrum clock signal under test, and the difference between the reference clock signal frequency and the spread spectrum signal frequency under test is determined by the operating frequency range supported by the comparator circuit; The ATE test machine will pass the expected working parameter range required for qualified judgment based on the type of chip under test to the spread spectrum clock test circuit board. The spread spectrum clock test circuit board completes the measurement of the working parameters of the spread spectrum clock signal, compares it with the working parameter range provided by the ATE test machine, and returns the comparison result to the ATE test machine; the spread spectrum clock test circuit board includes a first low-pass filter, a second low-pass filter, a mixer, a third low-pass filter, a comparator and a digital detection circuit; the first low-pass filter performs low-pass filtering on the spread spectrum clock signal under test, the second low-pass filter performs low-pass filtering on the reference clock signal, and the first The low-pass filter and the second low-pass filter respectively filter out the higher harmonics of the tested spread spectrum clock signal and the reference clock, and retain the baseband part; the first low-pass filter and the second low-pass filter send the low-pass filtered signal to the mixer for mixing, and the third low-pass filter performs low-pass filtering on the mixed signal and sends it to the comparator, the comparator performs zero-crossing detection to obtain a digital baseband signal and sends it to the digital detection circuit, the digital detection circuit analyzes the digital baseband signal to obtain working parameters, and compares them with the working parameter range provided by the ATE test machine to compare whether the test result is within the qualified range, and returns the comparison result to the ATE test machine.

2. The spread spectrum clock signal test device based on ATE test machine as claimed in claim 1, characterized in that The digital detection circuit includes a pulse width repetition period analysis module, a spread spectrum clock modulation period analysis module, a frequency offset analysis module and a comparison module; the pulse width repetition period analysis module analyzes the pulse width of the digital baseband signal to find the repetition period of the pulse signal with the widest or narrowest time width, that is, the modulation period Tmod; the spread spectrum clock modulation period analysis module obtains the modulation period Tssc of the spread spectrum clock under test according to the frequency relationship between the reference clock signal and the spread spectrum clock signal under test, Tssc=Tmod; the spread spectrum clock modulation period analysis module analyzes the digital baseband signal to find the pulse width Tmin of the pulse with the narrowest time width, and obtains the approximate value 1 / Tmin of the maximum frequency offset between the spread spectrum clock and the reference clock.

3. A method for testing a spread spectrum clock signal based on an ATE test machine, using the test device as claimed in any one of claims 1 to 2, characterized in that include: Step 1: The ATE test machine connects the chip under test and the spread spectrum clock test circuit board through a bus interface, and connects two clock output ends of the chip under test to the spread spectrum clock test circuit board through signal lines; Step 2, the ATE test machine transmits the expected operating parameter range required for qualified judgment based on the type of chip under test to the spread spectrum clock test circuit board; Step 3: The chip under test needs to provide two clocks to the spread spectrum clock test circuit board, one of which is a reference clock signal with a stable frequency and the other is a spread spectrum clock signal; Step 4: After the spread spectrum clock test circuit board completes the parameter measurement process, it compares the parameter range with the working parameter range provided by the ATE test machine, and returns the test result to the ATE test machine.

4. The spread spectrum clock signal testing method based on ATE test machine as claimed in claim 3, characterized in that Step 4 includes: Step 4.1, low-pass filtering is performed on the tested spread spectrum clock signal and the reference clock signal respectively to filter out high-order harmonics and retain the fundamental frequency part; Step 4.2, sending the two low-pass filtered signals to the mixer for mixing; Step 4.3, low-pass filtering the mixed signal; Step 4.4, performing zero-crossing detection on the mixed and low-pass filtered signal to obtain a digital baseband signal; Step 4.5, analyze the digital baseband signal to obtain the operating parameters, compare them with the operating parameter range provided by the ATE test machine, compare whether the test results are within the qualified range, and return the comparison results to the ATE test machine.

5. The spread spectrum clock signal testing method based on ATE test machine as claimed in claim 4, characterized in that The specific working parameters obtained by analyzing the digital baseband signal in step 4.5 are as follows: first, the pulse width of the digital baseband signal obtained by zero-crossing detection is analyzed to find the repetition period of the pulse signal with the widest or narrowest time width, that is, the modulation period Tmod; second, based on the frequency relationship between the reference clock signal and the spread spectrum clock signal being tested, the modulation period Tssc of the spread spectrum clock being tested is obtained, where Tssc=Tmod; third, the digital baseband signal obtained by zero-crossing detection is analyzed to find the pulse width Tmin of the pulse with the narrowest time width, and the approximate value 1 / Tmin of the maximum frequency offset between the spread spectrum clock and the reference clock is obtained.

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