Method and system for displaying test waveform of ATE (automatic test equipment)

Abstract

The invention discloses a method and a system for displaying a test waveform of ATE (automatic test equipment), and belongs to the technical field of automatic test, and the method comprises the following steps: receiving a waveform display request sent by an upper computer, the waveform display request comprising a trigger condition for triggering a logic controller to store waveform digital information; triggering conditions in the waveform conversion request are set to a register address corresponding to the logic controller, a pattern program is executed, test data are sent to a tested device, and return data of the tested device are received; after the pattern program is executed, the waveform digital information is obtained from a register address corresponding to the logic controller, and the waveform digital information is all test data and return data which are started to be stored by the logic controller after a trigger condition is met; and analyzing and converting the waveform digital information, and forwarding the waveform digital information to an upper computer for waveform analog signal display. According to the application, a section of waveform at any time node is captured in real time, the time sequence problem of a pattern program is quickly positioned by comparing the captured waveform signal with the pattern time sequence, the debugging period is shortened, and the development difficulty is reduced.

Description

Technical Field

[0001] This application relates to the field of automated test technology, and more specifically, to a method and system for displaying test waveforms of an ATE device. Background Art

[0002] With the continuous development of semiconductor technology, the complexity and integration of integrated circuits have been continuously improved, and the requirements for test equipment have also become higher and higher. During the test process of semiconductor memories, the test equipment needs to be able to accurately capture and display test waveforms so that engineers can quickly locate and solve problems.

[0003] However, in the field of automated test equipment for semiconductor memories, existing tools can only display the digital signals of waveforms and cannot display the analog signals of waveforms. Since the complete waveform information cannot be viewed, engineers need to rely on guesswork and trial during the debugging process, which not only increases the time cost of debugging but also may lead to misjudgments during the debugging process. This limits the engineer's comprehensive understanding of signals, especially in tests involving analog signals, where engineers cannot obtain complete signal information through existing tools. The lack of effective tools to view and analyze waveforms during the debugging process results in low debugging efficiency. Summary of the Invention

[0004] In view of at least one defect or improvement requirement of the prior art, the present invention provides a method and system for displaying test waveforms of an ATE device, which realizes real-time capture of a segment of waveform at any time node, quickly locates the timing problem of the pattern program by comparing the captured waveform signal with the pattern timing, solves the problem of low debugging efficiency, shortens the debugging cycle, and reduces the development difficulty.

[0005] To achieve the above object, according to the first aspect of the present invention, there is provided a method for displaying test waveforms of an ATE device, the method comprising: receiving a waveform display request sent by a host computer, wherein the waveform display request includes a trigger condition for triggering a logic controller to save waveform digital information; setting the trigger condition in the waveform conversion request to a corresponding register address of the logic controller and executing a pattern program, sending test data to a device under test and receiving return data from the device under test; after the pattern program is executed, obtaining the waveform digital information from the corresponding register address of the logic controller, wherein the waveform digital information is all test data and return data saved by the logic controller after reaching the trigger condition; parsing and converting the waveform digital information and forwarding it to the host computer for waveform analog signal display.

[0006] In an exemplary embodiment, before receiving the waveform display request sent by the host computer, the method further includes: determining a first group of the trigger conditions, setting a first trigger value corresponding to the first group, wherein a mode counter in the first group is used to record the number of executions of the test mode; and / or, determining a second group of the trigger conditions, setting a second trigger value corresponding to the second group, wherein the second group includes a plurality of control signals; and / or, determining a third group of the trigger conditions, setting a third trigger value corresponding to the third group, wherein a failure counter in the third group is used to record the number of test failures.

[0007] In an exemplary embodiment, the method further includes: calculating a plurality of control signals through an ALPG module, the plurality of control signals including an X address signal, a Y address signal, a data signal, a data selection signal, a timing setting signal, and a multi-purpose trigger signal; calculating a program counter instruction address value, a data flag, and a mode counter value through a SEQUENCE module; calculating an error bit numerical value and a failure counter value through a comparison module.

[0008] In an exemplary embodiment, the method further includes: using the mode counter as a trigger condition in the first group, setting a mode counter value corresponding to the first group; using the multi-purpose trigger signal, the program counter instruction address value, the X address signal, the Y address signal, the timing setting signal, and the data flag as trigger conditions in the second group, setting a second trigger value corresponding to the second group; using the failure counter as a trigger condition in the third group, setting a failure counter value corresponding to the third group.

[0009] In an exemplary embodiment, the method further includes: selecting any one of the first group, the second group, and the third group as a trigger condition source; when the trigger condition source within the same group includes a plurality of trigger conditions, starting the trigger when the plurality of trigger conditions are simultaneously satisfied.

[0010] In an exemplary embodiment, sending test data to the device under test and receiving the return data from the device under test includes: sending test data to the device under test, and receiving the corresponding return data after the device under test parses the test data; parsing the return data to obtain a register address that satisfies the trigger condition, and caching the waveform digital information of the corresponding system clock cycle into on-chip memory.

[0011] In an exemplary embodiment, before obtaining the waveform digital information from the register address corresponding to the logic controller, the method further includes: detecting the returned trigger completion signal at a preset time interval, and updating the target trigger value of the trigger condition in the case where the trigger completion signal is not detected after exceeding a preset detection threshold; restarting a new round of triggering after resetting the trigger condition based on the target trigger value.

[0012] In an exemplary embodiment, the forwarding the waveform digital information to the host computer for waveform analog signal display after parsing and conversion includes: parsing the waveform digital information, converting and simulating a waveform analog signal of a transmitted signal group in combination with timing information, and sending the waveform analog signal to the host computer for waveform display; comparing the actual value and the expected value returned by the sampling signal group to determine whether the operation on the device under test is correctly completed.

[0013] According to a second aspect of the present invention, there is also provided a display system for testing waveforms of an ATE device, including: a host computer for sending a waveform display request to a slave computer, where the waveform display request includes a trigger condition for triggering the logic controller to save waveform digital information; the slave computer for setting the trigger condition in the waveform conversion request sent by the received host computer to the register address corresponding to the logic controller and executing a pattern program; the logic controller for sending test data to the device under test and receiving the returned data from the device under test, and after the pattern program is executed, transmitting the waveform digital information obtained from the register address corresponding to the logic controller to the slave computer, where the waveform digital information is all the test data and returned data saved by the logic controller after the trigger condition is reached; the slave computer is further configured to forward the waveform digital information saved by the received logic controller to the host computer for waveform analog signal display after parsing and conversion.

[0014] In an exemplary embodiment, the host computer further includes a display main interface, and the display main interface includes a display status information interface, a condition setting interface, and a waveform display interface; the slave computer includes a communication protocol module, a control module, and a first data processing module; the logic controller includes a second data processing module.

[0015] Generally speaking, compared with the prior art by the above technical solution conceived by the present invention, the following beneficial effects can be achieved:

[0016] (1) The present invention provides a method for displaying test waveforms of an ATE device. Trigger conditions can be set on the host computer. When these conditions are met during the test process, the system will automatically capture waveforms. By running a pre-written pattern program, the test device can test the chip according to a predetermined test process. The test device sends excitation signals to the chip according to the pattern program and receives the data returned by the chip. The captured excitation and returned data are displayed in the form of waveforms on the host computer, facilitating engineers to analyze and debug. Through this application, a section of waveform at any time node can be captured in real time. By comparing the captured waveform signals with the pattern timing, the timing problems of the pattern program can be quickly located, shortening the debugging cycle and reducing the development difficulty.

[0017] (2) The method for displaying test waveforms of the ATE device provided by the present invention can display the waveforms of digital signals and analog signals simultaneously, providing engineers with more comprehensive signal information. By capturing and displaying waveforms in real time, engineers can quickly locate problems and reduce debugging time and costs. Users can set different trigger conditions according to their needs to capture waveforms at specific time nodes, improving the flexibility and applicability of the tool. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a schematic flowchart of an optional method for displaying test waveforms of an ATE device provided by an embodiment of the present application;

[0020] Figure 2 It is a schematic structural diagram of an optional system for displaying test waveforms of an ATE device provided by an embodiment of the present application;

[0021] Figure 3 It is a schematic structural diagram of another optional system for displaying test waveforms of an ATE device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] In the description, claims and the above drawings of this application, the terms "first", "second", "third", etc. are used to distinguish different objects rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0024] According to one aspect of the embodiments of the present application, a method for displaying a test waveform of an ATE device is provided. The following will be combined with Figure 1 Describe the method for displaying the test waveform of the ATE device provided by the embodiments of the present application.

[0025] Figure 1 It is a schematic flowchart of an optional method for displaying a test waveform of an ATE device provided by the embodiments of the present application. As Figure 1 shown, the process of this method may include the following steps:

[0026] S102, Receive a waveform display request sent by the host computer. Among them, the waveform display request includes a trigger condition for triggering the logic controller to save waveform digital information;

[0027] S104, Set the trigger condition in the waveform conversion request to the register address corresponding to the logic controller and execute the pattern program, send test data to the device under test and receive the return data from the device under test;

[0028] S106, After the pattern program is executed, obtain the waveform digital information from the register address corresponding to the logic controller. Among them, the waveform digital information is all the test data and return data saved by the logic controller after reaching the trigger condition;

[0029] S108, After parsing and converting the waveform digital information, forward it to the host computer for waveform analog signal display.

[0030] The method for displaying the test waveform of the ATE device in the embodiments of the present application can be applied to the semiconductor integrated circuit automatic test machine BI / FT / CP. Here, BI: Built-In Self-Test (built-in self-test), and the BI test is usually used for the self-diagnosis function inside the chip to verify the functional integrity of the chip through the built-in test logic. FT: Final Test (final test), and the FT test is the last test conducted after the chip packaging is completed to ensure that the chip still meets the design specification requirements after packaging. CP: Chip Probing (chip probing) or Circuit Probing (circuit probing). The CP test is a functional and performance test performed on each die at the wafer stage, aiming to screen out defective chips and avoid wasting packaging costs.

[0031] Exemplarily, this embodiment adopts a waveform display method that grabs the test data sent from the master device to the chip and the waveform of the data returned by the chip based on a trigger. By using a waveform display tool and through an Automatic Test Equipment (ATE), the purpose of detecting the functions and performances of electronic components, circuit boards, or systems is achieved. Optionally, by setting trigger conditions, running a pattern program, sending incentives, receiving data, and displaying the incentives and the chip return data received on the host computer.

[0032] It can be understood that the pattern timing refers to the time arrangement and sequence of a series of excitation signals sent by a test device (such as ATE) to the device under test during the test process. These excitation signals are combined according to a predetermined timing and logic level to verify the functions and performances of the DUT under various working conditions. Usually, when pattern writers debug the pattern, they cannot see the incentives sent to the Device Under Test (DUT) and the data returned from the DUT. The timing debugging is relatively complex, and they can only rely on guessing, trying, and the method of capturing waveforms with traditional tools. The signals seen are relatively few and have large limitations. Through the waveform display tool of the present invention, a section of waveform at any time node can be captured in real time, and it can be quickly determined whether it is a timing problem or a program problem of the pattern.

[0033] Furthermore, Figure 2 is a schematic structural diagram of an optional display system for the test waveform of the ATE device provided by the embodiments of the present application, as Figure 2As shown in the figure, the host computer is used to obtain the user's input and display waveform data; the slave computer is used to receive the waveform display request from the host computer, store the waveform display request in the register specified by the logic controller, and forward the processed data to the host computer after the logic execution is completed; the logic controller obtains the digital information of the waveform according to the trigger condition set by the user and stores it in the specified register.

[0034] For example, the user opens the wavetracer tool, which is a dedicated tool for capturing and displaying the data interaction between the master device and the chip (DUT) during the test of the ATE device, and enables the debug mode in the user program. The wavetracer tool first sets the trigger condition on the UI interface and sends the trigger condition to the slave computer. After receiving the trigger condition, the slave computer sets the relevant information of the trigger condition to the corresponding register address of the logic controller and starts the logic controller to execute. When the logic controller starts to execute, it starts to save all the digital information when it reaches the trigger condition set by the user. After the execution is completed, the slave computer obtains the waveform digital information of all resources from the specified register address, converts it and forwards it to the UI, and finally displays the waveform through the UI interface for the user to view.

[0035] Through the above steps S102 to S108, by receiving the waveform display request sent by the host computer, wherein the waveform display request includes a trigger condition for triggering the logic controller to save the waveform digital information; setting the trigger condition in the waveform conversion request to the corresponding register address of the logic controller and executing the pattern program, sending test data to the device under test and receiving the return data of the device under test; after the pattern program is executed, obtaining the waveform digital information from the corresponding register address of the logic controller, wherein the waveform digital information is all the test data and return data saved by the logic controller after reaching the trigger condition; parsing and converting the waveform digital information and forwarding it to the host computer for waveform analog signal display, the present application realizes real-time capturing of a section of waveform at any time node, quickly locates the timing problem of the pattern program by comparing the captured waveform signal with the pattern timing, shortens the debugging cycle, and reduces the development difficulty.

[0036] In an exemplary embodiment, before receiving the waveform display request sent by the host computer, the method further includes:

[0037] S11, determining a first group of the trigger conditions, setting a first trigger value corresponding to the first group, wherein a mode counter in the first group is used to record the execution times of the test mode; and / or,

[0038] S12. Determine the second group of the trigger conditions and set the second trigger value corresponding to the second group, where the second group includes multiple control signals; and / or,

[0039] S13. Determine the third group of the trigger conditions and set the third trigger value corresponding to the third group, where the failure counter in the third group is used to record the number of test failures.

[0040] Exemplarily, the wavetracer tool provides an intuitive UI interface where users can conveniently set the required trigger conditions. The trigger conditions are the key parameters that determine when to start capturing waveforms. Users need to set them according to specific test requirements, and multiple groups of trigger conditions can be set based on test requirements.

[0041] Optionally, according to test requirements, the mode counter for recording the number of executions of the test mode can be determined as the trigger condition in the first group, and the first trigger value corresponding to the first group, that is, the corresponding mode counter value, can be set. When this mode counter value is met, it is determined that the trigger condition in the first group is satisfied, and waveform capture is enabled.

[0042] Optionally, multiple control signals can be used as the trigger conditions in the second group according to test requirements. The control signals included in the second group can be X address signals, Y address signals, timing setting signals, etc., and the second trigger value corresponding to the second group can be set, that is, the corresponding X address, Y address, etc. Similarly, when the second reach value corresponding to this trigger condition is met, waveform capture can be enabled.

[0043] Optionally, the failure counter for recording the number of test failures can be used as the trigger condition in the third group according to test requirements, and the third reach value corresponding to the third group, that is, the corresponding failure counter value, can be set. When this failure counter value is met, it is determined that the trigger condition in the third group is satisfied, and waveform capture is enabled.

[0044] Through this embodiment, by grouping the trigger conditions and setting the trigger values corresponding to the groups, accurate waveform capture can be achieved when specific trigger conditions are met, thereby achieving rapid problem location.

[0045] In an exemplary embodiment, the method further includes:

[0046] S21. Calculate multiple control signals through the ALPG module, where the multiple control signals include X address signals, Y address signals, data signals, data selection signals, timing setting signals, and multi-purpose trigger signals;

[0047] S22. Calculate the program counter instruction address value, data flag, and mode counter value through the SEQUENCE module;

[0048] S23. Calculate the error bit number value and failure counter value through the comparison module.

[0049] In the embodiments of the present application, the setting of the trigger condition includes control signals such as TIMESET (timing setting signal), DFLAG (data flag), XADDR (X address signal), YADDR (X address signal), D (data signal), SD (data selection signal), SDMUT (multi-purpose trigger signal), PATTERN COUNTER (mode counter), PC (program counter instruction address), FBC (error bit number), etc. The above control signals can be calculated through specific modules in the data processing module of the lower computer.

[0050] Exemplarily, the information calculated by the ALPG module (Algorithmic Pattern Generator, that is, the algorithmic graphics generator) includes multiple control signals such as XADDR, YADDR, D, SD, TIMESET, and MUT. The values calculated by the SEQUENCE module (Sequence Control Module) are the PC instruction address value, DFLAG, and PATTERN COUNTER value. The values calculated after passing through the comparison module are the FBC value and the failure counter value. Some of the signals calculated by the above modules can be used as the trigger conditions for capturing the signal waveform.

[0051] In an exemplary embodiment, the method further includes:

[0052] S31. Use the mode counter as the trigger condition in the first group and set the mode counter value corresponding to the first group;

[0053] S32. Use the multi-purpose trigger signal, program counter instruction address value, X address signal, Y address signal, timing setting signal, and data flag as the trigger conditions in the second group and set the second trigger value corresponding to the second group;

[0054] S33. Use the failure counter as the trigger condition in the third group and set the failure counter value corresponding to the third group.

[0055] In an exemplary embodiment, the method further includes:

[0056] S41. Select any one of the first group, the second group, and the third group as the trigger condition source;

[0057] S42. When there are multiple trigger conditions in the trigger condition source within the same group, the trigger is initiated when the multiple trigger conditions are satisfied simultaneously.

[0058] In an embodiment of the present application, optionally, the PATTERN COUNTER (pattern counter) can be used as a trigger condition in the first group, and the model counter value of this group is set as the trigger value.

[0059] The MUT (multi-purpose trigger signal), PC instruction address value (program counter instruction address value), XADDR (X address signal), YADDR (Y address signal), TIMESET (timing setting signal), and DFALG (data flag) are used as trigger conditions in the second group. The second trigger value corresponding to the second group can be a specific X address, Y address, etc. FAILURECOUNTER is the third group of trigger conditions.

[0060] For the trigger conditions of each group, the triggering rule can be that only one of the three groups can be selected as the trigger condition source each time, that is, any one of the first group, the second group, and the third group is selected as the trigger condition source; multiple trigger conditions can be selected from the trigger condition source within the same group, and the trigger is triggered only when the multiple trigger conditions are satisfied simultaneously. For example, when the second group is used as the trigger condition source and three of the control signals in the second group are selected as the trigger conditions, the trigger is initiated only when the above three trigger conditions are satisfied simultaneously.

[0061] In an exemplary implementation, the sending of test data to the device under test and receiving the return data from the device under test includes:

[0062] S51. Sending test data to the device under test and receiving the corresponding return data after the device under test parses the test data;

[0063] S52. Parsing the register address that meets the trigger condition based on the return data and caching the waveform digital information of the corresponding system clock cycle into the on-chip memory.

[0064] In the embodiments of the present application, after receiving the trigger condition, the lower computer will parse and process it, and accurately set the relevant information of the trigger condition to the register address corresponding to the logic controller. The logic controller is a key component responsible for controlling the signal timing and logical relationship during the test. By setting its registers, specific test operations can be precisely defined to start under certain conditions. After completing the register setting, the logic controller starts to execute, monitors the signal interaction with the device under test (DUT) according to the preset logic and timing relationship, and waits for the trigger condition to be satisfied. By setting the trigger condition, the digital waveform information of all resources saved by the logic controller according to the trigger condition is obtained. After the logic controller saves the waveform, the UI interface displays the waveform to the user.

[0065] Specifically, the trigger condition, the software operation pattern, and the program are set through software (i.e., the aforementioned wavetracer tool). The FPGA (Field-Programmable Gate Array) sends test data to the DUT and receives the data returned by the chip. When the trigger condition is satisfied simultaneously, the FPGA parses the position where the trigger condition is satisfied, caches the data of 256 system clock cycles into the on-chip memory (memory) of the FPGA. The software queries the status of the trigger completion and retrieves the data captured by the FPGA, and finally parses and displays it through the software.

[0066] It should be noted that the software running the pattern program refers to running the pattern program whose timing is not necessarily correct after being written. The timing of the pattern is debugged by looking at the waveform to find the timing that does not conform to the chip manual.

[0067] In an exemplary embodiment, before obtaining the waveform digital information from the register address corresponding to the logic controller, the method further includes:

[0068] S61, detecting the returned trigger completion signal at a preset time interval. In the case where the trigger completion signal is not detected after exceeding the preset detection threshold, update the target trigger value of the trigger condition;

[0069] S62, restart a new round of triggering after resetting the trigger condition based on the target trigger value.

[0070] In the embodiments of the present application, the FPGA sending test data to the DUT and receiving the data returned by the chip means that once the pattern runs, the FPGA will send test data to the DUT. After the DUT parses the test data information (usually a read data command) sent by the FPGA, the DUT will return data to the FPGA.

[0071] After the software runs in the pattern, it will regularly detect the trigger completion signal provided by the FPGA at preset time intervals. If the trigger completion signal is not detected after exceeding the maximum detection time set by the software (i.e., the preset detection threshold), the software can check whether the trigger condition setting is reasonable and start a new trigger after resetting the trigger condition.

[0072] Through this embodiment, by detecting the rationality of the trigger condition setting and continuously detecting and adjusting, the debugging efficiency is improved.

[0073] In an exemplary embodiment, the forwarding the waveform digital information to the host computer for waveform analog signal display after parsing and conversion includes:

[0074] S71, parsing the waveform digital information, converting and simulating the waveform analog signal of the transmitted signal group in combination with the timing information, and sending the waveform analog signal to the host computer for waveform display;

[0075] S72, comparing the actual value and the expected value returned by the sampling signal group to determine whether the operation on the device under test is correctly completed.

[0076] In the embodiment of the present application, when the software (wavetracer tool) detects the trigger completion signal, the data captured by the FPGA can be retrieved from the on-chip memory of the FPGA. After the software retrieves the data (waveform digital information) and parses it, the waveform analog signal of the IO of the transmitted signal group can be simulated according to the retrieved IO data and timing information, and the waveform analog signal is sent to the host computer for waveform display.

[0077] For the signals of the sampling signal group, it is necessary to compare the actual value and the expected value returned by the sampling to determine whether the operation on the chip is correctly completed.

[0078] Through this embodiment, by comparing the captured signal with the pattern timing, it is very convenient to locate the bug problem of the pattern timing, shorten the debugging cycle, and reduce the development difficulty.

[0079] According to another aspect of the embodiment of the present application, a display system for the test waveform of an ATE device is provided. The following combines Figure 2 Describe the display system for the test waveform of the ATE device provided by the embodiment of the present application.

[0080] Figure 2 It is a schematic structural diagram of an optional display system for the test waveform of an ATE device provided by the embodiment of the present application. As Figure 2 shown, the display system for the test waveform of the ATE device may include:

[0081] The host computer is used to send a waveform display request to the slave computer. Among them, the waveform display request includes a trigger condition for triggering the logic controller to save waveform digital information;

[0082] The slave computer is used to set the trigger condition in the waveform conversion request sent by the host computer to the register address corresponding to the logic controller and execute the pattern program;

[0083] The logic controller is used to send test data to the device under test and receive the return data from the device under test. After the pattern program is executed, the waveform digital information obtained from the register address corresponding to the logic controller is transmitted to the slave computer. Among them, the waveform digital information is all the test data and return data saved by the logic controller after the trigger condition is reached;

[0084] The slave computer is also used to forward the waveform digital information saved by the logic controller to the host computer for waveform analog signal display after parsing and conversion.

[0085] The host computer further includes a display main interface, and the display main interface includes a display status information interface, a condition setting interface, and a waveform display interface; the slave computer includes a communication protocol module, a control module, and a first data processing module; the logic controller includes a second data processing module.

[0086] In this embodiment, Figure 3 is a schematic structural diagram of another optional display system for test waveforms of an ATE device provided by an embodiment of the present application. Combining Figure 2 with Figure 3 as shown, the host computer includes a display main interface (UI interface). The display status information interface in the above display main interface is used to display the current status of the test device, such as the running status, error information, etc.; the condition setting interface in the display main interface supports users to set trigger conditions, such as specific signal levels and timings; the waveform display interface in the display main interface displays the captured waveform data in real time, including digital signals and analog signals. The data processing module (i.e., the second data processing module) of the logic controller is used to analyze and process data.

[0087] The communication protocol module in the lower computer is responsible for the communication between the upper computer and the logic controller to ensure the correct transmission of data; the data processing module (i.e., the first data processing module) in the lower computer is responsible for data processing; the control module in the lower computer is responsible for managing and coordinating each module inside the lower computer to ensure the smooth progress of the test process. For example, it receives test instructions and trigger conditions from the upper computer, controls the operation of the test equipment according to the received instructions, such as sending excitation signals, receiving return data, manages the data flow during the test process, and ensures the correct acquisition and processing of data, etc.

[0088] Through this embodiment, users can check whether the waveform data sent by the tester conforms to the rules when testing and verifying NADN and DRAM chips, and quickly locate by comparing the captured signals and the pattern timing, thus improving the debugging efficiency.

[0089] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0090] In the above embodiments, the descriptions of each embodiment have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0091] In several embodiments provided by this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some service interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical or other form.

[0092] The foregoing are only exemplary embodiments of the present disclosure, and thus cannot limit the scope of the present disclosure. That is, all equivalent changes and modifications made in accordance with the teachings of the present disclosure still fall within the scope covered by the present disclosure. Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not recorded in the present disclosure. The specification and embodiments are only regarded as exemplary, and the scope and spirit of the present disclosure are defined by the claims.

[0093] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0094] It is easy for those skilled in the art to understand that the foregoing are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for displaying a test waveform of an ATE device, characterized in that, Including: Receiving a waveform display request sent by a host computer, where the waveform display request includes a trigger condition for triggering a logic controller to save waveform digital information; Setting the trigger condition in the waveform conversion request to the register address corresponding to the logic controller and executing a pattern program, sending test data to the device under test and receiving the return data from the device under test; After the pattern program is executed, obtaining the waveform digital information from the register address corresponding to the logic controller, where the waveform digital information is all the test data and return data saved by the logic controller after reaching the trigger condition; Forwarding the waveform digital information to the host computer for waveform analog signal display after parsing and conversion.

2. The display method of the test waveform of the ATE device according to claim 1, wherein, Before receiving the waveform display request sent by the host computer, the method further includes: Determining a first group of the trigger conditions, setting a first trigger value corresponding to the first group, where a pattern counter in the first group is used to record the execution times of a test mode; and / or, Determining a second group of the trigger conditions, setting a second trigger value corresponding to the second group, where the second group includes multiple control signals; and / or, Determining a third group of the trigger conditions, setting a third trigger value corresponding to the third group, where a failure counter in the third group is used to record the number of test failures.

3. The display method of the test waveform of the ATE device according to claim 2, characterized in that, The method further includes: Calculating multiple control signals through an ALPG module, where the multiple control signals include an X address signal, a Y address signal, a data signal, a data selection signal, a timing setting signal, and a multi-purpose trigger signal; Calculating a program counter instruction address value, a data flag, and a pattern counter value through a SEQUENCE module; Calculating an error bit value and a failure counter value through a comparison module.

4. The display method of the test waveform of the ATE device according to claim 2, wherein, The method further includes: Using the pattern counter as the trigger condition in the first group and setting the pattern counter value corresponding to the first group; Using the multi-purpose trigger signal, the program counter instruction address value, the X address signal, the Y address signal, the timing setting signal, and the data flag as the trigger conditions in the second group and setting the second trigger value corresponding to the second group; Using the failure counter as the trigger condition in the third group and setting the failure counter value corresponding to the third group.

5. The display method of the ATE device test waveform according to claim 2, wherein The method further includes: Selecting any one of the first group, the second group, and the third group as a trigger condition source; When the trigger condition source in the same group includes multiple trigger conditions, triggering is started when the multiple trigger conditions are simultaneously satisfied.

6. The display method of the test waveform of the ATE device according to claim 1, characterized in that, The sending test data to the device under test and receiving the return data from the device under test includes: Sending test data to the device under test and receiving the corresponding return data after the device under test parses the test data; Parsing the return data to obtain a register address that satisfies the trigger condition and caching the waveform digital information of the corresponding system clock cycle into on-chip memory.

7. The display method of the test waveform of the ATE device according to claim 1, characterized in that, Before obtaining the waveform digital information from the register address corresponding to the logic controller, the method further includes: Detecting the returned trigger completion signal at a preset time interval, and updating the target trigger value of the trigger condition in the case where the trigger completion signal is not detected after exceeding the preset detection threshold; After resetting the trigger condition based on the target trigger value, starting a new round of triggering.

8. The display method of the test waveform of the ATE device according to claim 1, characterized in that, The forwarding the waveform digital information to the host computer for waveform analog signal display after parsing and conversion includes: Parsing the waveform digital information, converting and simulating the waveform analog signal of the transmitted signal group in combination with the timing information, and sending the waveform analog signal to the host computer for waveform display; Comparing the actual value and the expected value returned by the sampling signal group to determine whether the operation on the device under test is correctly completed.

9. A display system for test waveforms of an ATE device, characterized in that, Including: A host computer for sending a waveform display request to a slave computer, wherein the waveform display request includes a trigger condition for triggering the logic controller to save waveform digital information; The slave computer for setting the trigger condition in the waveform conversion request sent by the host computer received to the register address corresponding to the logic controller and executing the pattern program; The logic controller for sending test data to the device under test and receiving the returned data from the device under test, and after the pattern program is executed, transmitting the waveform digital information obtained from the register address corresponding to the logic controller to the slave computer, wherein the waveform digital information is all the test data and returned data saved by the logic controller after reaching the trigger condition; The slave computer is further configured to forward the waveform digital information saved by the logic controller received after parsing and conversion to the host computer for waveform analog signal display.

10. The display system for the test waveform of the ATE device according to claim 9, wherein, The host computer further includes a display main interface, and the display main interface includes a display status information interface, a condition setting interface, and a waveform display interface; the slave computer includes a communication protocol module, a control module, and a first data processing module; the logic controller includes a second data processing module.

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