Memory system performing failover

Abstract

A memory system includes a plurality of memory devices, each of the plurality of memory devices including a plurality of memory cells, and at least one of the plurality of memory devices including a backup area; and a memory controller configured to, in response to a correctable error correction code (CECC) occurring in at least one selected memory cell of a plurality of selected memory cells, store data to be stored in the plurality of selected memory cells in the plurality of selected memory cells and the backup area, the plurality of selected memory cells connected to a selected word line of a selected memory device among the plurality of memory devices, and replace the selected word line with a redundant word line connected to a plurality of redundant memory cells among the plurality of memory cells.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0089434, filed on July 24, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to memory systems. Background Technology

[0004] Even when external power is interrupted, non-volatile memory devices can retain the data stored in them. For example, flash memory devices are non-volatile memory devices that can be electrically programmed and erased. Flash memory devices can be classified as NAND flash memory or NOR flash memory.

[0005] Volatile memory uses a constant power supply to retain the stored information. Most general-purpose random access memory (RAM) (including dynamic RAM (DRAM) and static RAM (SRAM)) is volatile memory.

[0006] Due to the microfabrication processes used in memory devices such as DRAM, SRAM, and flash memory, the number of defective memory cells included in memory devices is growing exponentially. Summary of the Invention

[0007] One aspect of the present invention is to provide a memory system capable of performing failover functionality before the occurrence of an uncorrectable error correction code (UECC).

[0008] According to one aspect of the present invention, a memory system includes: a plurality of memory devices, each of the plurality of memory devices including a plurality of memory cells, and at least one of the plurality of memory devices including a backup region; and a memory controller configured to: in response to the occurrence of a correctable error-correcting code (CECC) in at least one of the plurality of selected memory cells, store data to be stored in the plurality of selected memory cells in the plurality of selected memory cells and the backup region, the plurality of selected memory cells being connected to selected word lines of the selected memory devices among the plurality of memory devices, and replacing the selected word lines with redundant word lines connected to a plurality of redundant memory cells among the plurality of memory cells.

[0009] According to an aspect of the inventive concept, a memory system includes: a plurality of memory devices, each of the plurality of memory devices including a plurality of memory cells, and at least one of the plurality of memory devices including a backup area; and a memory controller configured to, in response to a first area of a selected memory device among the plurality of memory devices having a high access count, store data to be stored in a plurality of selected memory cells in each of a selected word line and the backup area, the plurality of selected memory cells being connected to the selected word line, the selected word line being included in the first area, and replace the selected word line with a redundant word line connected to a plurality of redundant memory cells among the plurality of memory cells.

[0010] According to an aspect of the inventive concept, a memory system includes: a memory module including: a plurality of first memory devices classified as a first rank of memory devices; and a plurality of second memory devices classified as a second rank of memory devices; and a memory controller configured to: activate a first chip select signal and a second chip select signal simultaneously to write data to the memory module, the first chip select signal being configured to select and control the first rank of memory devices, and the second chip select signal being configured to select and control the second rank of memory devices. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic block diagram illustrating a memory system according to an example embodiment of the present disclosure;

[0013] Figure 2 is a schematic block diagram illustrating a memory system including a first memory module 110 and a memory controller 130 according to an example embodiment of the present disclosure;

[0014] Figure 3 is a schematic diagram illustrating a structure of a memory device according to an example embodiment of the present disclosure;

[0015] Figure 4 is a schematic block diagram illustrating a memory bank according to an example embodiment of the present disclosure;

[0016] Figure 5 is a diagram illustrating a memory bank array included in a memory device according to an example embodiment of the present disclosure;

[0017] Figure 6 is a flowchart illustrating an operation of a memory system storing data in a backup area BR based on a hit count according to an example embodiment of the present disclosure;

[0018] Figures 7A-7C is a schematic diagram of a memory system performing operations in accordance with example embodiments of the present disclosure, the memory system having active regions AR and backup regions BR in a single memory bank; Figure 6

[0019] Figures 8A-8C is a schematic diagram of a memory system performing operations in accordance with example embodiments of the present disclosure, the memory system having active regions AR and backup regions BR in different memory banks; Figure 6

[0020] Figure 9 is a flowchart illustrating operations of a memory system storing data in a backup region BR based on a CECC occurrence count in accordance with example embodiments of the present disclosure;

[0021] Figures 10A-10C is a schematic diagram of a memory system performing operations in accordance with example embodiments of the present disclosure, the memory system having word lines EWL connected to defective memory cells and backup regions BR in a single memory bank; Figure 9

[0022] Figures 11A-11C is a schematic diagram of a memory system performing operations in accordance with example embodiments of the present disclosure, the memory system having word lines EWL connected to defective memory cells and backup regions BR in different memory banks; Figure 9

[0023] Figure 12 is a flowchart illustrating operations of a memory system having memory devices of different ranks in accordance with example embodiments of the present disclosure;

[0024] Figures 13A-13C is a schematic diagram of a memory system performing operations in accordance with example embodiments of the present disclosure; and Figure 12

[0025] Figure 14 is a schematic block diagram illustrating an electronic device including a memory device in accordance with example embodiments. DETAILED DESCRIPTION

[0026] Hereinafter, some example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 is a schematic block diagram of a memory system in accordance with example embodiments of the present disclosure.

[0028] Reference will now be made to Figure 1 ​​​​​The memory system 100 includes a first memory module 110, a memory controller 200, and / or a second memory module 300. The first memory module 110, the memory controller 200, and the second memory module 300 can be integrated into a single semiconductor device. For example, the first memory module 110, the memory controller 200, and the second memory module 300 can be integrated into a single semiconductor device to form a solid-state drive (SSD).

[0029] The first memory module 110 may include volatile memory (e.g., dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, low power DDR (LPDDR) SDRAM, SRAM, etc.) and / or non-volatile memory (e.g., FRAM, ReRAM, STT-MRAM, PRAM, etc.). The first memory module 110 may serve as a buffer memory for temporarily storing data received from the host and / or data received from the second memory module 300. According to an embodiment, the first memory module 110 may be used to store a mapping table that translates logical addresses viewed by the host into physical addresses in the flash memory.

[0030] The second memory module 300 can be implemented as a non-volatile memory, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), spin torque magnetic RAM (STT-MRAM), etc.

[0031] The memory controller 200 may include a DRAM controller 210, a host controller 220, a non-volatile memory (NVM) controller 230, an error correction code (ECC) engine 240, a central processing unit (CPU) 250, and / or an SRAM 260. According to some example embodiments, the DRAM controller 210, host controller 220, non-volatile memory controller 230, ECC engine 240, and / or CPU 250 may communicate with each other and / or with the SRAM 260 (e.g., via a bus).

[0032] The DRAM controller 210 can control the read and / or write operations of the first memory module 110. For example, the DRAM controller 210 can temporarily store write data and / or read data in the first memory module 110.

[0033] The host controller 220 can process read and / or write commands received from the host. The host controller 220 can provide an interface for communication between the host and the CPU 250 under the control of the CPU 250. For example, this interface can be an Advanced Technology Attachment (ATA) interface, a Serial ATA interface, a Parallel ATA interface, and / or a Small Computer System Interface (SCSI) interface.

[0034] The non-volatile memory controller 230 can control the read and write operations of the second memory module 300.

[0035] ECC engine 240 may include an ECC encoder and / or an ECC decoder. The ECC encoder can perform error correction encoding on data to be programmed in the second memory module 300 and can form data with added parity bits. The parity bits can be stored in the second memory module 300. Furthermore, the ECC decoder can perform error correction decoding on data read from the second memory module 300. The ECC decoder can determine whether the error correction decoding was successful and can output an indication signal based on the determination result. The ECC decoder can use the parity bits generated during ECC encoding to correct erroneous bits in the data.

[0036] CPU 250 can interpret multiple host commands entering the command queue to read data from and / or write data to the second memory module 300 via the non-volatile memory controller 230.

[0037] SRAM 260 can be used to store code and data for firmware execution on a CPU. According to some example embodiments, operations described herein as being performed by memory system 100, memory controller 200, DRAM controller 210, host controller 220, non-volatile memory controller 230, error correction code (ECC) engine 240, ECC encoder, and / or ECC decoder can be performed by processing circuitry. As used herein, the term "processing circuitry" can refer to, for example, hardware, including logic circuitry; hardware / software combinations, such as a processor executing software (e.g., software stored in SRAM 260); or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU) (e.g., CPU 250), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0038] According to embodiments of this disclosure, the ECC engine 240 can detect the presence of correctable error-correcting codes (CECCs) in a memory region included in the first memory module 110. A CECC can refer to a single bit error. The memory controller 200 can correct data in which a CECC has occurred.

[0039] However, due to the microfabrication process used in DRAM, uncorrectable error correction codes (UECCs) can appear in memory regions included in the first memory module 110. Alternatively, in the first memory module 110, a memory region where a UECC has occurred can affect the peripheral memory region that caused the UECC. UECC can refer to a multi-bit error. Conventional memory controllers cannot recover data containing UECCs, resulting in insufficient reliability in the corresponding conventional memory system.

[0040] However, according to embodiments of this disclosure, at least one of the plurality of memory devices included in the first memory module 110 may include a backup region. The memory controller 200 can determine memory regions where an uncorrectable error (e.g., UECC) is highly likely to occur. The memory controller 200 can store data to be stored in each of the determined memory regions and the backup region. Therefore, even when UECC occurs in a memory region, the memory controller 200 can use the data stored in the backup region to perform a failover function, thereby mitigating or reducing data loss due to UECC and improving the reliability of the memory system.

[0041] Furthermore, when data is written to the designated memory area, it is also written to the backup area, thereby enabling timely failover. That is, failover can be performed without halting the operation of the memory system 100. Therefore, the mean time between failures (MTBF) can be increased, and the reliability of the memory system 100 can be improved.

[0042] Figure 2 This is a schematic block diagram illustrating a memory system 400 including a first memory module 110 and a memory controller 130 according to an exemplary embodiment of the present disclosure.

[0043] refer to Figure 2The memory system 400 includes a first memory module 110 and / or a memory controller 130. The first memory module 110 may include first memory devices 110-1 to 110-4 (e.g., first memory devices 110-1, 110-2, 110-3, and 110-4) configured in multiple levels, and second memory devices 120-1 to 120-4 (e.g., second memory devices 120-1, 120-2, 120-3, and 120-4). According to some example embodiments, operations described herein as being performed by the memory controller 130 may be performed by processing circuitry. According to some example embodiments, the memory controller 130 may be the same as or similar to the memory controller 200.

[0044] Memory devices 110-1 to 110-4 and 120-1 to 120-4 may include a first memory device 110-1 to 110-4 classified as a first rank 0 and a second memory device 120-1 to 120-4 classified as a second rank 1. Each of memory devices 110-1 to 110-4 and 120-1 to 120-4 may include at least one memory bank.

[0045] According to an embodiment, at least one memory device among the first memory devices 110-1 to 110-4 and at least one memory device among the second memory devices 120-1 to 120-4 may be included in a single memory package. For example, the first memory device 110-1 among the first memory devices 110-1 to 110-4 and the second memory device 120-1 among the second memory devices 120-1 to 120-4 may be included in the first memory package.

[0046] Following the same principle, the first memory device 110-2 and the second memory device 120-2 may be included in the second memory package, the first memory device 110-3 and the second memory device 120-3 may be included in the third memory device, and the first memory device 110-4 and the second memory device 120-4 may be included in the fourth memory package.

[0047] The memory controller 130 may output a first chip select signal CS0 and / or a second chip select signal CS1. The memory controller 130 may activate the first chip select signal CS0 to select first memory devices 110-1 to 110-4. The memory controller 130 may activate the second chip select signal CS1 to select second memory devices 120-1 to 120-4. According to some example embodiments, the memory controller 130 may generate the first chip select signal CS0 and / or the second chip select signal CS1.

[0048] In some embodiments, the memory controller 130 may write data to the first memory devices 110-1 to 110-4. The memory controller 130 may activate a first chip select signal CS0 to select the first memory devices 110-1 to 110-4. In this case, the second chip select signal CS1 may not be activated. For example, the first chip select signal CS0 may be activated when it is in a low state (e.g., logic low), while the second chip select signal CS1 may not be activated when it is in a high state (e.g., logic high).

[0049] In some embodiments, the memory controller 130 may write data to the second memory devices 120-1 to 120-4. The memory controller 130 may activate a second chip select signal CS1 to select the second memory devices 120-1 to 120-4. In this case, the first chip select signal CS0 may not be activated. For example, the second chip select signal CS1 may be activated when it is low, while the first chip select signal CS0 may not be activated when it is high.

[0050] According to embodiments of this disclosure, at least one of the memory devices 110-1 to 110-4 and / or memory devices 120-1 to 120-4 may include a backup region. The memory system 400 (e.g., memory controller 130) may identify memory regions in memory devices 110-1 to 110-4 and memory devices 120-1 to 120-4 that have a high probability of experiencing uncorrectable errors.

[0051] When data needs to be written to a memory region, the memory system 400 (e.g., memory controller 130) can write the data to each of the memory region and the backup region. Therefore, the memory system 400 (e.g., memory controller 130) can use data stored in the backup region before the UECC occurs in the memory region to perform failover functionality.

[0052] Figure 3 This is a schematic diagram illustrating the structure of a memory device according to an exemplary embodiment of the present disclosure. Reference Figure 3Memory device 110-1 according to an example embodiment of the present disclosure includes memory banks 60 and / or logic circuitry 70. Memory banks 60 may include a memory bank array 61 (e.g., a first memory bank array) having a plurality of memory cells, a row decoder 62, a column decoder 63, and / or a sense amplifier (SA) 64. In embodiments, the first memory device 110-1 may include a plurality of memory banks 60. According to some example embodiments, each of the plurality of memory banks 60 may include a corresponding memory bank array (e.g., a second memory bank array, a third memory bank array, a fourth memory bank array, a fifth memory bank array, a sixth memory bank array, a seventh memory bank array, and / or an eighth memory bank array) that may be the same as or similar to the memory bank array 61.

[0053] The plurality of memory banks 60 included in the first memory device 110-1 can share a single logic circuit 70. The logic circuit 70 can read data from the memory bank array 61, store data in the memory bank array 61, and / or delete data stored in the memory bank array 61. Furthermore, in addition to receivers and / or transmitters connected to input and / or output pins for sending and / or receiving data, the logic circuit 70 may also include control logic for controlling the row decoder 62, column decoder 63, and / or sense amplifier 64. According to some example embodiments, the operations described herein as being performed by the row decoder 62, column decoder 63, sense amplifier, and / or logic circuit 70 can be performed by processing circuitry. According to some example embodiments, each of the first memory devices 110-1 to 110-4 and / or the second memory devices 120-1 to 120-4 may be similar to or identical to the first memory device 110-1.

[0054] Figure 4 This is a schematic block diagram illustrating a storage medium according to an exemplary embodiment of the present disclosure. (Reference) Figure 4 The memory bank 60 according to an exemplary embodiment of this disclosure may include a memory controller 20 and / or a memory bank array 30. In an embodiment, the memory controller 20 may include control logic 21, a row driver 22, and / or a column driver 23. The memory bank array 30 may include a plurality of memory cells 40 and a plurality of redundant memory cells.

[0055] In one embodiment, row driver 22 can be connected to memory cell 40 via word line WL, while column driver 23 can be connected to memory cell 40 via bit line BL. In another embodiment, row driver 22 may include an address decoder for selecting memory cells to which data is written and / or from which data is read, while column driver 23 may include a sense amplifier and a column decoder for writing data to and / or reading data from memory cells. The operation of row driver 22 and column driver 23 may be controlled by control logic 21. According to some example embodiments, the operations described herein as being performed by memory controller 20, control logic 21, row driver 22, address decoder, column driver 23, sense amplifier, and / or column decoder may be performed by processing circuitry.

[0056] According to embodiments of this disclosure, at least a portion of the memory cells 40 included in the memory array 30 may be a backup region. When the memory system 100 (e.g., memory controller 200) writes data to a memory region determined to have a high probability of uncorrectable errors, the memory system 100 (e.g., memory controller 200) may synchronously or simultaneously write data to the backup region. Therefore, the memory system can have the effect of performing failover functionality.

[0057] Figure 5 This is a diagram illustrating a memory bank array included in a memory device according to an example embodiment of the present disclosure.

[0058] refer to Figure 5 The memory array 30 according to an exemplary embodiment of this disclosure may include a plurality of memory cells 40. The memory cells 40 may be located at the intersection of a plurality of word lines WL and a plurality of bit lines BL. That is, each memory cell in the memory cells 40 may be connected to a single word line WL and a single bit line BL.

[0059] Each memory cell in memory cell 40 may include a switching device SW and / or an information storage capacitor CC. In an embodiment, the switching device SW may include a transistor. The gate terminal of the transistor may be connected to the word line WL, and the drain / source terminals of the transistor may be connected to the bit line BL and the information storage capacitor CC, respectively.

[0060] The memory controller can write or delete data by charging or releasing the charge charged in the information storage capacitor CC included in each of the plurality of memory cells 40 via multiple word lines WL and multiple bit lines BL. Furthermore, the memory controller can read the voltage of the information storage capacitor CC to read data from each of the plurality of memory cells 40. In an embodiment, the memory controller can perform a refresh operation to write data to the plurality of memory cells 40 again so that the data is not lost through the natural release of the charge charged in the information storage capacitor CC.

[0061] Figure 6 This is a flowchart illustrating the operation of a memory system according to an example embodiment of the present disclosure, and Figures 7A-7C This is a schematic diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

[0062] exist Figures 7A-7C In memory system 100A, a single memory bank and a memory controller MC are shown in each of a plurality of memory devices. A single memory bank may include multiple memory cells MA, some of which may be considered redundant memory cells. Furthermore, a single memory bank may include a backup region BR. According to some example embodiments, memory system 100A may be the same as or similar to memory system 100, and / or memory controller MC may be the same as or similar to memory controller 200.

[0063] refer to Figure 6 and Figure 7AThe memory controller MC can periodically read the address (hereinafter referred to as the hit address) and access count (hereinafter referred to as the hit count) of a first region AR with the highest access count in each of the plurality of memory devices (S110). For example, the memory controller MC can read the hit address and hit count via a mode register read (MRR). The mode register read (MRR) can refer to a user-readable mode register. According to some example embodiments, the first region AR can be a region comprising a defined number of consecutive memory cells (e.g., it can include a defined number of consecutive word lines within a single memory bank). According to some example embodiments, the first region AR can have the highest access count among regions within a single memory bank, among regions within a single memory device among the plurality of memory devices, and / or among regions within a single memory module (e.g., the first memory module 110). According to some example embodiments, the hit count can be a count of accesses to memory cells, word lines, and / or regions (e.g., write accesses and / or read accesses).

[0064] The memory controller (MC) can count the access counts of each of a plurality of memory devices. Based on the counting results, the memory controller (MC) can determine the most frequently accessed region of the plurality of memory devices as a first region (AR). The memory controller (MC) can store the address and access count corresponding to the first region (AR) as the hit address and hit count, respectively, in the memory device (e.g., SRAM 260).

[0065] The memory controller MC can compare the hit count corresponding to the first region AR with a reference count (S120). As a result of the comparison, if the hit count corresponding to the first region AR is greater than the reference count, the memory controller MC can store (e.g., in a memory such as SRAM 260) the hit address corresponding to the first region AR. According to some example embodiments, operation S120 may additionally or alternatively include determining whether the hit count corresponding to the first region AR is greater than the reference count. According to some example embodiments, the reference count may be a design parameter determined through empirical studies.

[0066] The likelihood of the first region AR failing is higher when the hit count corresponding to it is greater than the reference count. Therefore, the probability of UECC occurring is higher when data is stored in the first region AR.

[0067] Subsequently, the memory controller MC can receive from the host the address in which data is to be stored, as well as a command for storing the data. The address sent from the host may correspond to a selected memory cell connected to a selected word line of a first region AR included in a selected memory device among a plurality of memory devices.

[0068] The memory controller MC can store data to be stored in selected memory cells (e.g., selected memory cells corresponding to addresses received from the host) into each of a selected word line and a backup region BR (e.g., word line BWL of the backup region BR) (S130). The hit count corresponding to the first region AR can be greater than the reference count. In this case, when data is stored in the first region AR, it can be stored not only in the selected memory cells connected to the selected word line, but also in the backup region. Therefore, the memory system 100A can write data twice in the region where a UECC may occur (e.g., once to the selected word line and once to the backup region BR) before a UECC occurs. The memory system 100A can perform a failover function by writing data to the backup region in advance before a UECC occurs.

[0069] When the hit count corresponding to the first region AR is less than the reference count, the memory controller MC can continuously monitor the hit address and hit count of the first region AR with the highest access count in the memory bank included in each of the multiple memory devices (S110).

[0070] refer to Figure 6 and Figure 7B The memory controller MC can replace a selected word line SWL included in the first region AR with a redundant word line RWL connected to multiple redundant memory cells (S140). That is, a repair operation can be performed to replace the selected word line SWL connected to the defective memory cell with a redundant word line RWL. The above repair operation can be defined as post-packaging repair (PPR). For example, even when the address of the selected word line SWL is used after the memory controller MC performs PPR, the redundant word line can be accessed due to the decoding operation inside the DRAM. According to some example embodiments, as described herein, replacing the selected word line SWL with a redundant word line RWL may include associating the redundant word line RWL instead of the selected word line SWL with an address received from the host; and / or, when a corresponding command associated with the address is received from the host, writing data to and / or reading data from the redundant word line RWL.

[0071] refer to Figure 6 and Figure 7CThe memory controller MC can store data in memory cells connected to word lines BWL of the backup region BR into multiple redundant memory cells connected to redundant word lines RWL (S150). Therefore, the memory system 100A (e.g., the memory controller MC) can read data from the redundant word lines RWL instead of from selected word lines SWL included in the first region AR, and / or can write data to the redundant word lines RWL instead of writing data to selected word lines SWL included in the first region AR.

[0072] According to embodiments of this disclosure, a single memory bank may include a backup region BR, and a memory controller MC may identify memory regions within the memory bank that are determined to have high access counts. The memory controller MC may store data to be stored in the memory regions identified as having high access counts in each of the memory regions and the backup region BR. That is, for memory regions with a high probability of UECC occurrence, data to be stored in that memory region may be stored synchronously or simultaneously in the backup region. Data can be backed up in advance before UECC occurs, by replacing word lines SWL connected to defective memory cells with redundant word lines RWL via PPR, and the backed-up data can be stored in the redundant word lines RWL. The memory system 100A (e.g., the memory controller MC) can provide services using the redundant word lines RWL instead of the word lines SWL connected to defective memory cells. Therefore, the memory system 100A can perform failover functionality.

[0073] Figures 8A-8C This is a schematic diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

[0074] exist Figures 8A-8C In the memory system 100B, to be compatible with Figures 7A-7C In different ways, the first region AR and the backup region BR of the memory system 100A may be included in different memory banks. For example, the first region AR may be included in the first memory bank BANK1, while the backup region BR may be included in the second memory bank BANK2. The first memory bank BANK1 may include a plurality of memory cells MA1, some of which may be considered redundant memory cells MA1. The second memory bank BANK2 may include a plurality of memory cells MA2, some of which may be considered redundant memory cells MA2. According to some example embodiments, the memory system 100B may be the same as or similar to the memory system 100, and / or the memory controller MC may be the same as or similar to the memory controller 200.

[0075] refer toFigure 6 and Figure 8A The memory controller MC can periodically read the hit address and hit count of the first region AR with the highest access count in each of the plurality of memory devices (S110). The first region AR can be included in the first memory bank BANK1. According to some example embodiments, the first region AR can be a region including a defined number of consecutive memory cells (e.g., it can include a defined number of consecutive word lines within the first memory bank BANK1). According to some example embodiments, the first region AR can have the highest access count among regions within a single memory bank BANK, among regions within a single memory device among the plurality of memory devices, and / or among regions within a single memory module (e.g., the first memory module 110). According to some example embodiments, the hit count can be a count of accesses to memory cells, word lines, and / or regions (e.g., write accesses and / or read accesses).

[0076] The memory controller MC can compare the hit count corresponding to the first region AR with a reference count (S120). As a result of the comparison, if the hit count corresponding to the first region AR is greater than the reference count, the memory controller MC can store the hit address corresponding to the first region AR in a memory device (e.g., SRAM 260).

[0077] Subsequently, the memory controller MC can receive from the host the address in which data is to be stored, as well as a command for storing the data. The address sent from the host may correspond to a selected memory cell connected to a selected word line of a first region AR included in a selected memory device among a plurality of memory devices.

[0078] The memory controller MC can store data to be stored in selected memory cells in each of selected word lines and backup regions BR (S130). The backup region BR can be included in the second memory bank BANK2. Therefore, the backup region BR and the first region AR can be included in different memory banks.

[0079] refer to Figure 6 and Figure 8B The memory controller MC can (e.g., via PPR) replace selected word lines SWL included in the first region AR with redundant word lines RWL connected to a plurality of redundant memory cells (S140). The plurality of redundant memory cells can be included in the first memory bank BANK1. Therefore, the redundant word lines RWL and the first region AR can be included in the same or similar memory bank.

[0080] refer toFigure 6 and Figure 8C The memory controller MC can store data stored in the backup area BR of the second memory bank BANK2 to the redundant word line RWL of the first memory bank BANK1 (S150). Therefore, the memory system 100B (e.g., the memory controller MC) can read data from the redundant word line RWL instead of from the selected word line SWL included in the first area AR, and / or can write data to the redundant word line RWL instead of writing data to the selected word line SWL included in the first area AR.

[0081] According to embodiments of this disclosure, the second memory bank BANK2 may include a backup region BR, and the memory controller may identify memory regions AR in the first memory bank BANK1 that are determined to have high access counts. The memory controller MC may store data to be stored in the memory regions AR determined to have high access counts in each of the memory regions AR and the backup region BR. That is, for memory regions AR with a high probability of UECC, data to be stored in those memory regions AR may be synchronously or simultaneously stored in the backup region BR. The memory system 100B (e.g., the memory controller MC) may back up the data in advance before UECC occurs by replacing word lines SWL connected to defective memory cells with redundant word lines RWL via PPR, and storing the backed-up data in the redundant word lines RWL. The memory system 100B can use the redundant word lines RWL instead of the word lines SWL connected to defective memory cells to provide services. Therefore, the memory system 100B can perform failover functionality.

[0082] Figure 9 This is a flowchart illustrating the operation of a memory system according to an example embodiment of the present disclosure, and Figures 10A-10C This is a schematic diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

[0083] exist Figures 10A-10C In the memory system 100C, a single memory bank and a memory controller MC are shown among the memory banks included in each of a plurality of memory devices. A single memory bank may include multiple memory cells MA, some of which may be considered redundant memory cells. Furthermore, a single memory bank may include a backup region BR. According to some example embodiments, the memory system 100C may be the same as or similar to the memory system 100, and / or the memory controller MC may be the same as or similar to the memory controller 200.

[0084] refer to Figure 9 and Figure 10AThe memory controller MC can periodically read the address (hereinafter referred to as the ECC address) and ECC count of the memory cell with the highest CECC occurrence count in the memory bank included in each of the multiple memory devices (S210). For example, the memory controller MC can store the ECC address and ECC count of the memory cell with the highest CECC occurrence count in advance in the memory controller MC (e.g., in SRAM 260).

[0085] The memory controller (MC) can identify (e.g., determine) the location of the word line of the defective memory cell with the highest CECC occurrence count among multiple memory cells comprising a memory region by referring to the ECC address. For example, the ECC address can include a bank address, a row address, and / or a column address. Therefore, the memory controller (MC) can identify the address, i.e., the ECC address of the word line (EWL) connected to the defective memory cell.

[0086] The memory controller MC can count the occurrence counts of CECCs across multiple memory devices. Based on the counting results, the memory controller MC can determine the defective memory cell among the multiple memory devices that most frequently exhibits CECC. The memory controller MC can store the ECC address and ECC count corresponding to the word line EWL connected to the defective memory cell in the memory controller MC (e.g., in SRAM 260). According to some example embodiments, the memory controller MC can determine the defective memory cell among the memory cells within a word line, among the memory cells within a memory body, among the memory cells within a single memory device, and / or among the memory cells within a single memory module (e.g., the first memory module 110) that most frequently exhibits CECC.

[0087] The memory controller MC can compare the ECC count corresponding to the word line EWL with a reference count (S220). As a result of the comparison, if the ECC count corresponding to the word line EWL is greater than the reference count, the memory controller MC can store the ECC address corresponding to the word line EWL (the word line EWL may also be referred to herein as a "region"). The ECC count corresponding to the word line EWL may be greater than the reference count. In this case, the probability of UECC occurring is higher when data is stored in the word line EWL. According to some example embodiments, operation S220 may additionally or alternatively include determining whether the ECC count corresponding to the word line EWL is greater than the reference count. According to some example embodiments, the reference count may be a design parameter determined through empirical studies.

[0088] Subsequently, the memory controller MC can receive from the host the address in which data is to be stored, as well as the command for storing the data. The address sent from the host can correspond to a selected memory cell connected to a selected word line SWL, which corresponds to (e.g., the same or similar to) the word line of a selected memory device among a plurality of memory devices.

[0089] The memory controller MC can store data to be stored in selected memory cells (e.g., selected memory cells corresponding to addresses received from the host) in each of a selected word line SWL and a backup region BR (e.g., word line BWL of the backup region BR) (S230). That is, the ECC count corresponding to the selected word line SWL can be greater than the reference count. In this case, when data is stored in the selected word line SWL, it can be stored synchronously or simultaneously in the backup region BR. Therefore, data can be backed up before UECC occurs.

[0090] When the ECC count corresponding to the word line SWL is less than the reference count, the memory controller MC can continuously monitor the ECC address and ECC count of the memory cell with the highest CECC occurrence count in the memory bank included in each of the multiple memory devices (S210).

[0091] refer to Figure 9 and Figure 10B The memory controller MC can replace a selected word line SWL with a redundant word line RWL connected to multiple redundant memory cells (e.g., perform PPR) (S240). That is, a repair operation can be performed to replace a selected word line SWL connected to a defective memory cell with a redundant word line RWL (e.g., replace the selected word line SWL with a redundant word line RWL as the word line referred to by the address received from the host).

[0092] refer to Figure 9 and Figure 10C The memory controller MC can store data stored in the backup region BR to the redundant word line RWL (S250). Therefore, the memory system 100C (e.g., the memory controller MC) can read data from the redundant word line RWL instead of from the selected word line SWL corresponding to the word line EWL, and / or can write data to the redundant word line RWL instead of writing data to the selected word line corresponding to the word line EWL.

[0093] According to embodiments of this disclosure, a single memory bank may include a backup region BR, and a memory controller MC may identify word lines EWLs in the memory bank connected to defective memory cells determined to have a high UECC occurrence count. The memory controller MC may store data to be written to the word line EWL connected to the defective memory cell in each of the word line EWL (e.g., a selected word line SWL) and the backup region BR. That is, for memory cells with a high probability of UECC occurrence, data to be stored in that memory cell may be synchronously or simultaneously stored in the backup region BR. Data can be backed up in advance before the UECC occurs, thus enabling the memory system 100C to perform failover functionality.

[0094] Figures 11A-11C This is a schematic diagram of a memory system according to an exemplary embodiment of the present disclosure.

[0095] about Figures 11A-11C The structure of the memory system 100D is designed to be compatible with... Figures 10A-10C In different ways than memory system 100C, word lines EWL connected to defective memory cells and backup regions BR can be included in different memory banks. For example, word lines EWL connected to defective memory cells can be included in a first memory bank BANK1, while backup regions BR can be included in a second memory bank BANK2. The first memory bank BANK1 can include multiple memory cells MA1, some of which can be considered redundant memory cells. The second memory bank BANK2 can include multiple memory cells MA2, some of which can be considered redundant memory cells. According to some example embodiments, memory system 100D can be the same as or similar to memory system 100, and / or memory controller MC can be the same as or similar to memory controller 200.

[0096] refer to Figure 9 and Figure 11A The memory controller MC can periodically read the ECC address and ECC count of the word line EWL connected to the memory cell with the highest CECC occurrence count in the memory bank included in each of the plurality of memory devices (S210). The word line EWL connected to the memory cell with the highest CECC occurrence count can be included in the first memory bank BANK1.

[0097] The memory controller MC can compare the ECC count corresponding to the word line EWL with a reference count (S220). As a result of the comparison, if the ECC count corresponding to the word line EWL is greater than the reference count, the memory controller MC can store (e.g., in a memory such as SRAM 260) the ECC address corresponding to the word line EWL. According to some example embodiments, the memory controller MC can determine the defective memory cell in which CECC occurs most frequently among the memory cells within the word line, among the memory cells within the memory body, among the memory cells within a single memory device, and / or among the memory cells within a single memory module (e.g., the first memory module 110).

[0098] Subsequently, the memory controller MC can receive from the host the address in which data is to be stored, as well as the command for storing the data. The address sent from the host can correspond to a selected memory cell connected to a selected word line SWL, which corresponds to (e.g., the same or similar to) the word line of a selected memory device among a plurality of memory devices.

[0099] The memory controller MC can store data to be stored in selected memory cells (e.g., selected memory cells corresponding to addresses received from the host) in each of a selected word line SWL and a backup region BR (e.g., in the word line BWL of the backup region BR) (S230). The backup region BR can be included in a second memory bank BANK2, which is different from the first memory bank BANK1 that includes the selected word line SWL.

[0100] refer to Figure 9 and Figure 11B The memory controller MC can replace a selected word line SWL (S240) with a redundant word line RWL connected to multiple redundant memory cells. The redundant word line RWL can be included in the first memory bank BANK1. Therefore, the redundant word line RWL and the backup area BR can be included in different memory banks.

[0101] refer to Figure 9 and Figure 11C The memory controller MC can store data stored in the backup area BR of the second memory bank BANK2 to the redundant word line RWL of the first memory bank BANK1 (S250). Therefore, the memory system 100D (e.g., the memory controller MC) can read data from the redundant word line RWL instead of the selected word line SWL, and / or can write data to the redundant word line RWL instead of the selected word line SWL.

[0102] According to embodiments of this disclosure, the second memory bank BANK2 may include a backup region BR, and the memory controller MC may identify defective memory cells in the first memory bank BANK1 that are determined to have a high CECC occurrence count. The memory bank including the defective memory cells may differ from the memory bank including the backup region. The memory controller MC may store data to be stored in word lines SWL connected to the defective memory cells determined to have a high CECC occurrence count in each of the word lines SWL and the backup region BR. That is, for memory regions with a high probability of UECC occurrence, data to be stored in word lines SWL may be synchronously or simultaneously stored in the backup region BR. The memory system 100D (e.g., the memory controller MC) may back up the data in advance before the UECC occurs by replacing the word lines SWL connected to the defective memory cells with redundant word lines RWL via PPR, and storing the backed-up data in the redundant word lines RWL. The memory system 100D (e.g., the memory controller MC) may use the redundant word lines RWL instead of the word lines SWL connected to the defective memory cells to provide service. Therefore, the memory system 100D (e.g., the memory controller MC) can perform failover functions.

[0103] Figure 12 This is a flowchart illustrating the operation of a memory system according to an example embodiment of the present disclosure, and Figures 13A-13C This is a schematic diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

[0104] exist Figures 13A-13C In this context, memory systems 400A, 400B, and 400C may include memory devices 410-1 to 410-4 (e.g., memory devices 410-1, 410-2, 410-3, and 410-4) and memory devices 420-1 to 420-4 (e.g., memory devices 420-1, 420-2, 420-3, and 420-4) configured as multiple levels, and / or a memory controller 430. According to some example embodiments, memory systems 400A, 400B, and / or 400C may be the same as or similar to memory system 400. According to some example embodiments, memory controller 430 may be the same as or similar to memory controller 130 and / or memory controller 200. According to some example embodiments, memory devices 410-1 to 410-4 and / or memory devices 420-1 to 420-4 may be the same as or similar to memory devices 110-1 to 110-4 and / or memory devices 120-1 to 120-4.

[0105] Memory devices 410-1 to 410-4 and memory devices 420-1 to 420-4 may be referred to as first memory devices 410-1 to 410-4 classified as first-level RANK0, and second memory devices 420-1 to 420-4 classified as second-level RANK1. Each of memory devices 410-1 to 410-4 and memory devices 420-1 to 420-4 may include at least one memory bank.

[0106] According to an embodiment, at least one memory device among the first memory devices 410-1 to 410-4 and at least one memory device among the second memory devices 420-1 to 420-4 may be included in a single memory package. For example, the first memory device 410-1 among the first memory devices 410-1 to 410-4 and the second memory device 420-1 among the second memory devices 420-1 to 420-4 may be included in the first memory package.

[0107] Following the same principle, the first memory device 410-2 and the second memory device 420-2 may be included in the second memory package, the first memory device 410-3 and the second memory device 420-3 may be included in the third memory device, and the first memory device 410-4 and the second memory device 420-4 may be included in the fourth memory package.

[0108] The memory controller 430 can output a first chip select signal CS0 and a second chip select signal CS1. The memory controller 430 can activate the first chip select signal CS0 to select first memory devices 410-1 to 410-4. The memory controller 430 can activate the second chip select signal CS1 to select second memory devices 420-1 to 420-4.

[0109] According to exemplary embodiments of this disclosure, in memory systems 400A, 400B, and 400C, memory devices 410-1 to 410-4 and memory devices 420-1 to 420-4 can have a capacity more than twice the capacity desired by a memory module (e.g., DRAM) for data storage execution under host instructions, and can be configured in multiple tiers. For example, the desired capacity for memory devices 410-1 to 410-4 and memory devices 420-1 to 420-4 could be 8 Gbit. In this case, according to related technologies, the first memory devices 410-1 to 410-4, classified as RANK0, are configured with 4 Gbit, while the second memory devices 420-1 to 420-4, classified as RANK1, are configured with 4 Gbit.

[0110] However, according to the example embodiment, the memory devices 410-1 to 410-4 and 420-1 to 420-4 may be intended to use a capacity of 8 Gbit. In this case, the first memory devices 410-1 to 410-4, classified as RANK0, can be configured to 8 Gbit, while the second memory devices 420-1 to 420-4, classified as RANK1, can also be configured to 8 Gbit.

[0111] Therefore, among the first memory devices 410-1 to 410-4 classified as first-level RANK0 and the second memory devices 420-1 to 420-4 classified as second-level RANK1, the second memory devices 420-1 to 420-4 classified as second-level RANK1 can be used as backup areas.

[0112] Memory controller 130 may activate a first chip select signal CS0 to select first memory devices 410-1 to 410-4. Synchronously or simultaneously, memory controller 130 may activate a second chip select signal CS1 to select second memory devices 420-1 to 420-4. According to some example embodiments, memory controller 130 may generate and / or output the first chip select signal CS0 and / or the second chip select signal CS1. According to some example embodiments, as used herein, activating the chip select signal may refer to outputting the chip select signal in a first logic state (e.g., logic low), and not activating and / or deactivating the chip select signal may refer to outputting the chip select signal in a second logic state (e.g., logic high) different from the first logic state.

[0113] refer to Figure 12 and Figure 13A The memory controller 430 can write data to memory devices 410-1 to 410-4 and memory devices 420-1 to 420-4 (S310). The memory controller 430 can activate a first chip selection signal CS0 to select the first memory devices 410-1 to 410-4. Synchronously or simultaneously, the memory controller 430 can activate a second chip selection signal CS1 to select the second memory devices 420-1 to 420-4. Therefore, write operations on the first memory devices 410-1 to 410-4 classified as first-level RANK0 and write operations on the second memory devices 420-1 to 420-4 classified as second-level RANK1 can be performed synchronously or simultaneously.

[0114] For example, when receiving a command from the host to write first to fourth data, the memory controller 430 can write the first data to each of the first memory device 410-1 and the second memory device 420-1. Following the same principle, the memory controller 430 can write second data to each of the first memory device 410-2 and the second memory device 420-2, write third data to each of the first memory device 410-3 and the second memory device 420-3, and write fourth data to each of the first memory device 410-4 and the second memory device 420-4.

[0115] refer to Figure 12 and Figure 13B The memory controller 430 can read data from the first memory devices 410-1 to 410-4, which are classified as first-level RANK0 (S320). The memory controller 430 can activate the first chip select signal CS0 to select the first memory devices 410-1 to 410-4. Synchronously or simultaneously, the memory controller 430 can deactivate the second chip select signal CS1, thereby not selecting the second memory devices 420-1 to 420-4.

[0116] Therefore, read operations can be performed on the first memory devices 410-1 to 410-4 that are classified as first-level RANK0, while read operations can be omitted on the second memory devices 420-1 to 420-4 that are classified as second-level RANK1.

[0117] refer to Figure 12 and Figure 13C The memory controller 430 can detect whether a UECC has occurred in the first memory devices 410-1 to 410-4 (S330). For example, the method by which the memory controller 130 confirms whether a UECC has occurred in the first memory devices 410-1 to 410-4 can be a single-bit error correction and double-bit error detection (SEDEC) method.

[0118] In the case of SECE, when a single-bit error is detected, the memory controller 430 can directly correct the error. However, when a 2-bit error is detected, the memory controller 430 can notify the user of the 2-bit error and stop the operation of the memory system 100D. Furthermore, when 3-bit or more bit errors are detected, the firmware of the memory controller 430 can check for abnormal signals.

[0119] When a UECC has been present in the first memory devices 410-1 to 410-4, the memory controller 430 can use the second memory devices 420-1 to 420-4 to read and / or write data (S340).

[0120] When no UECC appears in the first memory devices 410-1 to 410-4, the memory controller 430 can synchronously or simultaneously write data to the first memory devices 410-1 to 410-4 classified as the first level RANK0 and the second memory devices 420-1 to 420-4 classified as the second level RANK1 (S310). Furthermore, the memory controller 430 can read data from the first memory devices 410-1 to 410-4 classified as the first level RANK0.

[0121] According to embodiments of this disclosure, memory systems 400A, 400B, and 400C may include memory devices 410-1 to 410-4 and memory devices 420-1 to 420-4 configured as multiple levels. Among memory devices 410-1 to 410-4 and memory devices 420-1 to 420-4, second memory devices 420-1 to 420-4 may be used as backup areas.

[0122] The memory controller 430 can synchronously or simultaneously write data to be written to the first memory devices 410-1 to 410-4 to the second memory devices 420-1 to 420-4. Therefore, even when a UECC has occurred in the memory area of ​​the first memory devices 410-1 to 410-4, the memory systems 400A, 400B, and / or 400C can use the data stored in the second memory devices 420-1 to 420-4 to perform failover functionality.

[0123] Furthermore, when the second memory devices 420-1 to 420-4 are used as a backup area, the MTBF can be doubled compared to using only the first memory devices 410-1 to 410-4. Therefore, the reliability of the memory system can be doubled. For example, when only the first memory devices 410-1 to 410-4 are used, the MTBF can be 200 million hours. Meanwhile, when the second memory devices 420-1 to 420-4 are used together with the first memory devices 410-1 to 410-4 as a backup area, the MTBF can be 400 million hours.

[0124] Figure 14 This is a schematic block diagram illustrating an electronic device including a memory device according to an example embodiment.

[0125] Figure 14 The electronic device 1000 shown according to an example embodiment includes a display 1010, a sensor unit 1020, a memory 1030, a communication unit 1040, a processing circuit 1050 (e.g., at least one processor), and / or a port 1060. The electronic device 1000 may also include a power supply, input and / or output devices, etc.Figure 14 Among the components shown, port 1060 can be provided for electronic device 1000 to communicate with video cards, sound cards, memory cards, Universal Serial Bus (USB) devices, etc. Electronic device 1000 can be a concept including smartphones, tablet PCs, smart wearable devices, etc., as well as desktop computers and laptop computers according to related technologies.

[0126] The processing circuit 1050 can perform specific operations, commands, tasks, etc. The processing circuit 1050 can be a central processing unit (CPU), a microprocessor unit (MCU), a system-on-a-chip (SoC), etc., and can communicate with the display 1010, sensor unit 1020, memory 1030, communication unit 1040 and / or other devices connected to port 1060 via bus 1070.

[0127] Memory 1030 may be a storage medium for storing data and / or multimedia data used in the operation of electronic device 1000. Memory 1030 may include volatile memory such as random access memory (RAM) and / or non-volatile memory such as flash memory. Additionally or alternatively, memory 1030 may include at least one of a solid-state drive (SSD), a hard disk drive (HDD), and / or an optical disk drive (ODD) as a storage device. Figure 14 In the illustrated embodiment, the memory 1030 can be implemented according to the previous information regarding Figures 1-13C The memory devices or memory packages described are various example embodiments.

[0128] As described above, according to an exemplary embodiment of the present invention, at least one memory device in the memory device may include a backup region, and the memory controller may determine a memory region with a high probability of UECC occurring. When data is written to a memory region, the memory controller may store the data in each of the memory region and the backup region. Therefore, the memory system may have the effect of performing failover functionality.

[0129] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A memory system comprising: a plurality of memory devices, each of the plurality of memory devices including a plurality of memory cells, and at least one of the plurality of memory devices including a backup area; and a memory controller configured to, in response to a correctable error correcting code (CECC) occurring in at least one selected memory cell of a plurality of selected memory cells, perform the following operations: storing data in both the plurality of selected memory cells and the backup area, the plurality of selected memory cells connected to a selected word line of a selected memory device among the plurality of memory devices; and replacing the selected word line with a redundant word line connected to a plurality of redundant memory cells among the plurality of memory cells.

2. The memory system of claim 1, wherein, The memory controller is configured to store data stored in the backup area in the plurality of redundant memory cells.

3. The memory system of claim 1, wherein, The backup area and the selected word line are included in a same memory bank.

4. The memory system of claim 1, wherein, The backup area and the selected word line are included in different memory banks.

5. The memory system of claim 1, wherein, The memory controller is configured to: store an address of an area in which the CECC has occurred and an access count of the area; and in response to determining that the access count is greater than a reference count, store data in both the plurality of selected memory cells and the backup area. The address includes a bank address, a row address, and a column address.

6. The memory system of claim 5, wherein, The address indicates a defective memory cell among the plurality of selected memory cells in which the CECC has occurred, and the selected word line is connected to the defective memory cell.

7. The memory system of claim 5, wherein, 8. A memory system comprising: a plurality of memory devices, each of the plurality of memory devices including a plurality of memory cells, and at least one of the plurality of memory devices including a backup area; and a memory controller configured to, in response to a first area of a selected memory device among the plurality of memory devices having a high access count, perform the following operations: storing data to be stored in a plurality of selected memory cells in each of a selected word line and the backup area, the plurality of selected memory cells connected to the selected word line, the selected word line included in the first area; and replacing the selected word line with a redundant word line connected to a plurality of redundant memory cells among the plurality of memory cells. The memory controller is configured to store data stored in the backup area in the redundant word line.

9. The memory system of claim 8, wherein, The backup area and the first area are included in a same memory bank.

10. The memory system of claim 8, wherein, The backup area and the first area are included in different memory banks.

11. The memory system of claim 8, wherein, The memory controller is configured to:

12. The memory system of claim 8, wherein, read an address of an area having a highest access count among a plurality of memory areas in each of the plurality of memory devices and an access count of the area having the highest access count; and in response to determining that the access count is greater than a reference count, store data in both the plurality of selected memory cells and the backup area. ​ in response to the access count being greater than a reference count, storing data to be stored in the plurality of selected memory cells in each of the selected word line and the backup area.

13. The memory system of claim 12, wherein, the memory controller is configured to read the address and the access count through a mode register read (MRR).

14. A memory system comprising: a memory module comprising a plurality of first memory devices classified as a first rank of memory devices and a plurality of second memory devices classified as a second rank of memory devices; and a memory controller configured to activate a first chip select signal and a second chip select signal simultaneously to write data to the memory module, the first chip select signal configured to select and control the first rank of memory devices and the second chip select signal configured to select and control the second rank of memory devices.

15. The memory system of claim 14, wherein, at least one first memory device of the plurality of first memory devices and at least one second memory device of the plurality of second memory devices are included in a single memory package.

16. The memory system of claim 14, wherein, the memory controller is configured to perform a first write operation to the plurality of first memory devices and a second write operation to the plurality of second memory devices based on the first chip select signal and the second chip select signal being activated simultaneously to write data to the memory module.

17. The memory system of claim 16, wherein, the memory controller is configured to activate the first chip select signal and deactivate the second chip select signal to perform a read operation to the plurality of first memory devices.

18. The memory system of claim 17, wherein, the memory controller is configured to deactivate the first chip select signal and activate the second chip select signal to perform a read operation and a write operation to the plurality of second memory devices in response to an uncorrectable error correction code (UECC) occurring in at least one first memory device of the plurality of first memory devices.

19. The memory system of claim 14, wherein, the memory system is a solid state drive (SSD).

20. The memory system of claim 14, wherein, the memory module is a dynamic random access memory (DRAM). the memory module is a dynamic random access memory (DRAM).

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