Storage device, storage system including the same, and storage device operation method

Abstract

A storage device, a storage system including the same, and an operation method of the storage device are provided. The storage system includes a storage device and a host accessing the storage device, and the storage device includes a non-volatile memory device and a storage controller configured to control the non-volatile memory device. The storage device transmits mapping data to the host according to a request of the host, in which the physical address of the non-volatile memory device is mapped with the logical address provided by the host. The host stores and manages the transmitted mapping data as mapping cache data. The mapping cache data is managed according to a priority determined based on a corresponding area of ​​the non-volatile memory device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0093997 filed on August 1, 2019, in the Korean Intellectual Property Office, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concepts described herein relate to a semiconductor memory device, and more particularly, to a memory device using a memory of a host and an operating method thereof. Background Art

[0004] Semiconductor memory devices can be classified as volatile memory devices or non-volatile memory devices. Volatile memory devices are memory devices that lose stored data when power is off. Examples of volatile memory devices include static random access memory (SRAM) or dynamic random access memory (DRAM). Non-volatile memory devices are memory devices that retain stored data even when power is off. Examples of non-volatile memory devices include flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM) or ferroelectric RAM (FRAM).

[0005] Currently, flash memory devices are widely used as high-capacity storage media in computing devices, and various technologies are being developed to support high-speed operation of flash memory devices. For example, the Universal Flash Storage (UFS) interface defined by the JEDEC standard can support higher operating speeds than conventional flash memory-based storage devices. Summary of the invention

[0006] Exemplary embodiments of the inventive concept provide a storage system and a metadata management method thereof which stores and manages metadata of a storage device using a turbo write buffer at a host.

[0007] According to an exemplary embodiment, a storage system includes: a storage device and a host accessing the storage device, the storage device including a non-volatile memory device and a storage controller configured to control the non-volatile memory device. The storage device transmits mapping data to the host according to a request of the host, in which a physical address of the non-volatile memory device is mapped with a logical address provided from the host. The host stores and manages the transmitted mapping data as mapping cache data. The mapping cache data is managed according to a priority determined based on a corresponding area of ​​the non-volatile memory device.

[0008] According to an exemplary embodiment, a method for operating a storage device, the storage device includes a nonvolatile memory device, the nonvolatile memory device includes a user storage area and an accelerated write buffer area providing a higher access speed than the user storage area, the method includes: receiving an access request from a host; transmitting mapping data and an identifier to the host, the mapping data being configured according to the execution of the access request, the identifier indicating whether the mapping data corresponds to the accelerated write buffer area or the user storage area; and configuring and managing mapping cache data by using the mapping data. Managing the mapping cache data includes: determining a priority of the mapping cache data according to the identifier, and when updating or deleting the mapping cache data, updating or deleting the mapping cache data according to the priority.

[0009] According to an exemplary embodiment, a storage device that communicates with a host by using a universal flash storage (UFS) interface includes: a non-volatile memory device, the non-volatile memory device including a user storage area and an accelerated write buffer area having a higher access speed than the user storage area; and a storage controller that transmits mapping data to the host, in which the physical address of the non-volatile memory device is mapped to the logical address of the host. The storage controller adds an identifier to the mapping data and transmits the mapping data and the identifier to the host, the identifier indicating whether the mapping data corresponds to the user storage area or the accelerated write buffer area. In a cache management operation of the mapping data, an update priority or a deletion priority of the mapping data is determined based on the identifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

[0012] Figure 2 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 An illustration of the physical storage space of a storage device.

[0013] Figure 3A and Figure 3B is used to describe an exemplary embodiment according to the inventive concept Figure 2 Schematic diagram of the accelerated write buffer types.

[0014] Figure 4A and Figure 4Bis a configuration for describing an exemplary embodiment according to the inventive concept Figure 1 Schematic diagram of a mode of accelerating write buffer of a storage device.

[0015] Figure 5 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A flow chart of the operation of a storage system.

[0016] Figure 6 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A flow chart of the operation of a storage system.

[0017] Figure 7 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A flowchart of the operation of a storage device.

[0018] Figure 8 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A block diagram of the physical storage space of a storage device.

[0019] Fig. 9 is a diagram for reference showing an exemplary embodiment according to the inventive concept Figure 8 A diagram of the logical storage space of a storage device depicting the physical storage space.

[0020] Fig. 10A and Fig. 10B is a reference diagram showing an exemplary embodiment according to the inventive concept Figure 8 A diagram describing operations in the physical storage space of a storage device.

[0021] Fig.11 is a block diagram illustrating a computer system according to an exemplary embodiment of the inventive concept.

[0022] Fig.12 is a diagram showing an exemplary embodiment according to the inventive concept Fig.11 A memory map of the host memory allocation structure.

[0023] Fig.13A and Fig. 13B is a diagram showing an exemplary embodiment according to the inventive concept. Fig.11 A flowchart of an example of a memory management operation performed by a host.

[0024] Fig.14 is a block diagram illustrating an example of transferring mapping cache data to a host memory according to an exemplary embodiment of the inventive concept.

[0025] Fig.15is a diagram illustrating a method of transmitting mapping cache data according to an exemplary embodiment of the inventive concept.

[0026] Fig.16 is a diagram illustrating a method of transmitting mapping cache data according to an exemplary embodiment of the inventive concept.

[0027] Fig.17 is a diagram illustrating a method of transmitting mapping cache data according to an exemplary embodiment of the inventive concept.

[0028] Fig.18 is a diagram illustrating a method of transmitting mapping cache data according to an exemplary embodiment of the inventive concept.

[0029] Fig.19 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 Illustration of the hierarchical structure of a storage system.

[0030] Fig. 20 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

[0031] Fig.21 A conceptual diagram showing that an exemplary embodiment of the present inventive concept is applied to a memory system.

[0032] Fig. 22 is a block diagram illustrating a memory card to which a memory system according to an exemplary embodiment of the inventive concept is applied.

[0033] Fig.23 is a block diagram illustrating a portable terminal including a storage device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0034] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings.Like reference numerals may denote like elements throughout the drawings.

[0035] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, a "first" element in one exemplary embodiment may be described as a "second" element in another exemplary embodiment.

[0036] It will be further understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0037] As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0038] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

[0039] Reference Figure 1 , the storage system 1000 may include a host 1100 and a storage device 1200. In an exemplary embodiment of the inventive concept, the storage system 1000 may include one of various computing devices such as a personal computer, a notebook, a tablet computer, a smart phone, and a wearable device.

[0040] The host 1100 may store data in the storage device 1200, or may read data stored in the storage device 1200. For example, the host 1100 may transmit a write command or write data to the storage device 1200 to store the data in the storage device 1200. Alternatively, in order to read data from the storage device 1200, the host 1100 may transmit a read command to the storage device 1200, and may receive data from the storage device 1200.

[0041] The host 1100 may include a main processor such as a central processing unit (CPU) or an application processor (AP). In addition, the host 1100 may include an auxiliary processor that assists the main processor, for example, a graphics processing unit (GPU) or a neural processing unit (NPU).

[0042] The storage device 1200 may operate under the control of the host 1100. For example, the storage device 1200 may include a controller 1210 and a nonvolatile memory device 1220. The controller 1210, which may also be referred to as a memory controller, may operate in response to a command received from the host 1100. For example, the controller 1210 may receive a write command and write data from the host 1100, and may store the received write data in the nonvolatile memory device 1220 in response to the received write command.

[0043] Alternatively, the controller 1210 may receive a read command from the host 1100, and may read data stored in the nonvolatile memory device 1220 in response to the received read command. Thereafter, the controller 1210 may transmit the read data to the host 1100. In an exemplary embodiment of the inventive concept, the nonvolatile memory device 1220 may be a NAND flash memory device, but the inventive concept is not limited thereto.

[0044] In an exemplary embodiment of the inventive concept, the host 1100 may communicate with the storage device 1200 based on a universal flash storage (UFS) interface or protocol defined by the JEDEC standard. For example, the host 1100 and the storage device 1200 may exchange data packets in the form of a UFS protocol information unit (UPIU). The UPIU may include various information defined by an interface (e.g., a UFS interface) between the host 1100 and the storage device 1200. However, the inventive concept is not limited thereto. Below, for ease of description, the terms "command", "UPIU", and "data" may be interchangeable, and the terms may have the same meaning or different meanings according to the embodiments disclosed herein.

[0045] In an exemplary embodiment of the inventive concept, the storage device 1200 may support a turbowrite function or turbowrite feature. The turbowrite function may be enabled or disabled under the control of the host 1100. When the turbowrite function is enabled under the control of the host 1100, the storage device 1200 may perform a turbowrite operation. The turbowrite operation may be performed based on a single level cell (SLC) buffering scheme, but not limited thereto, and may provide improved performance (particularly improved write performance) of the storage device 1200. The turbowrite operation will be described more fully below with reference to the accompanying drawings.

[0046] Figure 2 It is shown Figure 1 1 is a diagram of a physical storage space PS of a storage device 1200. The physical storage space PS of the storage device 1200 may indicate a physical area of ​​the nonvolatile memory device 1220 that actually stores user data. In other words, the physical storage space PS may be a space recognized by the host 1100 as the capacity of the storage device 1200. The host 1100 and the storage device 1200 may be implemented in accordance with a UFS protocol proposed by JEDEC for communicating with each other, but the inventive concept is not limited thereto.

[0047] In an exemplary embodiment of the present inventive concept, the storage device 1200 includes not only Figure 2 The physical storage space PS shown in the figure may also include any other storage space (for example, space that is not recognized by the host 1100 as the capacity of the storage device 1200, such as a reserved area, a meta area for storing metadata, or an overprovisioning area for improving performance). However, for ease of description, additional descriptions associated with other storage spaces will be omitted (or minimized), and the description will focus on the physical storage space PS for storing user data.

[0048] Reference Figure 1 and Figure 2, the physical storage space PS of the storage device 1200 may include a speed-up write buffer area (TWB) (hereinafter referred to as "speed-up write buffer area") and a user storage area (UST) (hereinafter referred to as "user storage area"). The user storage area and the speed-up write buffer area may be referred to as a first area, a second area, a third area, etc.

[0049] The accelerated write buffer TWB may correspond to a portion (e.g., “a”) of the physical storage space PS of the nonvolatile memory device 1220. The user storage area UST may correspond to the rest (e.g., “b”) of the physical storage space PS of the nonvolatile memory device 1220. Alternatively, the user storage area UST may correspond to the entire physical storage space PS of the nonvolatile memory device 1220 (e.g., a+b).

[0050] In an exemplary embodiment of the inventive concept, each storage cell corresponding to the accelerated write buffer TWB may be used as an SLC, and each storage cell corresponding to the user storage area UST may be used as a three-level cell (TLC). Alternatively, each storage cell corresponding to the accelerated write buffer TWB may store n-bit data (n is a positive integer), and each storage cell corresponding to the user storage area UST may store m-bit data (m is a positive integer greater than n). In other words, the accelerated write buffer TWB may be an area that supports a higher write speed than the user storage area UST.

[0051] The inventive concept is not limited to the above description of the accelerated write buffer TWB and the user storage area UST. For example, the number of bits stored in each storage unit corresponding to the accelerated write buffer TWB (e.g., k) may be greater than or equal to the number of bits stored in each storage unit corresponding to the user storage area UST (e.g., i), (e.g., k ≥ i). In an exemplary embodiment of the inventive concept, in the accelerated write buffer TWB and the user storage area UST, the number of bits to be stored in each storage unit may be determined by various factors such as reliability and life of the storage device 1200. Alternatively, the accelerated write buffer TWB and the user storage area UST may be divided according to various factors such as the reliability and life of the storage device 1200 and the number of bits to be stored in each storage unit.

[0052] In an exemplary embodiment of the inventive concept, each of the reference symbols "a" and "b" may be the number of storage blocks in the corresponding storage space. The values ​​of "a" and "b" may be changed differently according to the sizes of the accelerated write buffer TWB and the user storage area UST and the schemes (e.g., SLC, multi-level cell (MLC), TLC, and quad-level cell (QLC)) for implementing the accelerated write buffer TWB and the user storage area UST.

[0053] As reference Figure 1 As described, the storage device 1200 can support a normal write function and an accelerated write function. When the host 1100 enables the accelerated write function, the storage device 1200 can perform an accelerated write operation. When the host 1100 disables the accelerated write function, the storage device 1200 can perform a normal write operation.

[0054] For example, when the accelerated write function is enabled, the storage device 1200 may preferentially write the write data received from the host 1100 in the accelerated write buffer TWB. In this case, because the write data received from the host 1100 is written in the accelerated write buffer TWB (e.g., SLC programming), a fast operation speed can be ensured compared to the case where a normal write operation (e.g., TLC programming) is performed on the user storage area UST. When the accelerated write function is disabled, the storage device 1200 may not first write the write data in the accelerated write buffer TWB. According to an internally allocated policy (e.g., a normal write policy), the storage device 1200 may write the write data directly in the user storage area UST, or may write the write data in the accelerated write buffer TWB. According to the normal write policy, how to write the write data may be determined based on various factors (such as the data share of the accelerated write buffer TWB and the state of the physical storage space PS).

[0055] As another example, the normal write strategy may first write the write data into the user storage area UST. In order to more clearly illustrate the inventive concept, in the following detailed description, the normal write strategy is a strategy that preferentially writes the write data into the user storage area UST. However, the inventive concept is not limited thereto.

[0056] In an exemplary embodiment of the inventive concept, data written in the acceleration write buffer TWB may be flushed or migrated to the user storage area UST according to an explicit command from the host 1100 or an internally assigned policy.

[0057] Figure 3A and Figure 3B Is used to describe Figure 2 Schematic diagram of the accelerated write buffer.

[0058] Reference Figure 1 , Figure 2 , Figure 3A and Figure 3B, the storage device 1200 may include a first logical unit LU1, a second logical unit LU2, a third logical unit LU3, and a fourth logical unit LU4. Each of the first logical unit LU1 to the fourth logical unit LU4 may be an externally addressable, independent processing entity that processes commands from the host 1100. The host 1100 may manage the storage space of the storage device 1200 through the first logical unit LU1 to the fourth logical unit LU4. Each of the first logical unit LU1 to the fourth logical unit LU4 may be used to store data in the storage device 1200.

[0059] Each of the first to fourth logical units LU1 to LU4 may be associated with at least one storage block of the nonvolatile memory device 1220. Various logical units may exist for various purposes. However, the first to fourth logical units LU1 to LU4 may correspond to a physical storage space PS and may be used to store data of the host 1100.

[0060] exist Figure 3A and Figure 3B 1 to 4 logical units LU1 to LU4 are illustrated, but the inventive concept is not limited thereto. For example, the storage device 1200 may include other logical units for storing and managing user data in addition to the first to fourth logical units LU1 to LU4. Alternatively, the storage device 1200 may include other logical units for supporting various functions in addition to the first to fourth logical units LU1 to LU4.

[0061] The acceleration write buffer TWB of the storage device 1200 may be configured as various types. The acceleration write buffer TWB may be configured as one of a logical unit (LU) dedicated buffer type and a shared buffer type.

[0062] In the case of the LU dedicated buffer type, the accelerated write buffer TWB may be configured independently or individually for each logical unit LU. Figure 3A As shown, in the LU dedicated buffer type, a first accelerated write buffer TWB1 can be configured for the first logical unit LU1 among the first logical unit LU1 to the fourth logical unit LU4, and a third accelerated write buffer TWB3 can be configured for the third logical unit LU3 among the first logical unit LU1 to the fourth logical unit LU4.

[0063] exist Figure 3AIn the LU dedicated buffer type, when a write command for the first logical unit LU1 is received after the accelerated write function is enabled, the write data may be preferentially written in the first accelerated write buffer TWB1 corresponding to the first logical unit LU1. When a write command for the third logical unit LU3 is received after the accelerated write function is enabled, the write data may be preferentially written in the third accelerated write buffer TWB3 corresponding to the third logical unit LU3.

[0064] In the case where a write command is received for the second logical unit LU2 and the fourth logical unit LU4 to which the accelerated write buffer TWB is not allocated, the write data may be written in the user storage area UST corresponding to the second logical unit LU2 and the fourth logical unit LU4. In addition, in the case where a write command is received for the first logical unit LU1 or the third logical unit LU3 after the accelerated write function is deactivated, the write data may be written in the user storage area UST of the first logical unit LU1 or the first accelerated write buffer TWB1, or may be written in the user storage area UST of the third logical unit LU3 or the third accelerated write buffer TWB3 according to the normal write strategy.

[0065] In an exemplary embodiment of the inventive concept, the capacity of the first accelerated write buffer TWB1 and the capacity of the third accelerated write buffer TWB3 can be set independently of each other. However, the inventive concept is not limited thereto. For example, the number of logical units LU to which the accelerated write buffers are respectively allocated, the capacity of each accelerated write buffer, etc. can be changed or modified differently.

[0066] In an exemplary embodiment of the inventive concept, the size of the accelerated write buffer TWB of each logical unit may be set to the accelerated write buffer size field of each unit in the unit descriptor (e.g., "dLUNumTurboWriteBufferAllocUnits"). In an exemplary embodiment of the inventive concept, the accelerated write buffer size field of each unit (e.g., "dLUNumTurboWriteBufferAllocUnits") may be a configurable parameter.

[0067] In the case of a shared buffer type, one accelerated write buffer can be configured for all logical units. Figure 3B As shown, in the shared buffer type, one accelerated write buffer TWB0 shared by all the first to fourth logical units LU1 to LU4 may be configured.

[0068] In this case, when a write command for each of the first to fourth logical units LU1 to LU4 is received after the accelerated write function is enabled, the write data may be first written in the shared accelerated write buffer TWB0. In the case where a write command for each of the first to fourth logical units LU1 to LU4 is received after the accelerated write function is disabled, the write data may be written in the user storage area UST corresponding to each of the first to fourth logical units LU1 to LU4 according to the normal write strategy, or in the shared accelerated write buffer TWB0.

[0069] As described above, the storage device 1200 may include an accelerated write buffer TWB for supporting an accelerated write function. Depending on the buffer type (e.g., LU dedicated buffer type or shared buffer type), the accelerated write buffer TWB may be configured for each of a plurality of logical units, or one accelerated write buffer TWB may be configured to be shared by all logical units.

[0070] Figure 4A and Figure 4B It is used to describe the configuration Figure 1 Schematic diagram of a mode of accelerating write buffer of a storage device.

[0071] For ease of description, it is assumed that the physical storage space PS of the storage device 1200 is 32 GB based on TLC. In other words, if each storage unit in the storage device 1200 stores 3 bits of data, the storage device 1200 can store 32 GB of user data.

[0072] However, the inventive concept is not limited thereto. For example, the physical storage space PS of the storage device 1200 may be changed differently according to a scheme for implementing the storage device 1200 or the nonvolatile memory device 1220 (e.g., according to a storage cell type (e.g., SLC, MLC, TLC, or QLC), the number of storage cells, a storage cell structure, a reserved ratio, etc.).

[0073] Reference Figure 1 , Figure 4A and Figure 4B The storage device 1200 may configure the physical storage space of the accelerated write buffer TWB according to various modes. For example, the storage device 1200 may configure the physical storage space of the accelerated write buffer based on one of a user capacity reduction mode and a non-user capacity reduction mode.

[0074] The user capacity reduction mode may be a mode for reducing the user capacity of the user storage area USTa for the purpose of configuring the accelerated write buffer TWBa. Figure 4AAs shown, the physical storage space PS of the storage device 1200 may be 32 GB based on TLC.

[0075] Before configuring the accelerated write buffer TWB, 32GB of capacity (eg, the entire capacity of the physical storage space PS) may be allocated to or used for the user storage area UST. In this case, from the perspective of the host 1100, the user storage area UST may be identified as 32GB.

[0076] The acceleration write buffer TWB may be configured according to the user capacity reduction mode. In this case, the second physical storage space PS2a as a part of the physical storage space PS may be allocated to the acceleration write buffer TWBa or may be used for the acceleration write buffer TWBa.

[0077] In addition, the first physical storage space PS1a as part of the physical storage space PS can be allocated to the user storage area USTa, or can be used for the user storage area USTa. In this case, compared with the case where the accelerated write buffer TWBa is not configured, from the perspective of the host 1100, the capacity of the user storage area USTa is reduced (for example, from 32GB to 26GB).

[0078] In an exemplary embodiment of the inventive concept, the first physical storage space PS1a corresponding to the user storage area USTa can be implemented by TLC, and the second physical storage space PS2a corresponding to the acceleration write buffer TWBa can be implemented by SLC. The capacity ratio of the same storage space used as TLC and SLC can be 3:1.

[0079] In other words, when the size of the accelerated write buffer TWBa increases by up to 1 GB, the size of the logical storage space of the user storage area USTa can be reduced by up to 3 GB. As described above, in the case where the accelerated write buffer TWBa is configured in the user capacity reduction mode, a portion of the physical storage space PS of the storage device 1200 can be allocated to the accelerated write buffer TWBa, so that the capacity of the user storage area USTa recognized by the host 1100 can be reduced.

[0080] In an exemplary embodiment of the inventive concept, the first physical storage space PS1a corresponding to the user storage area USTa and the second physical storage space PS2a corresponding to the acceleration write buffer area TWBa may be physically adjacent to each other, or may be physically spaced apart from each other.

[0081] The no user capacity reduction mode may be a mode in which the logical storage capacity of the user storage area USTb identified by the host 1100 is not reduced even if the accelerated write buffer TWBb is configured. Figure 4B As shown, before configuring the accelerated write buffer TWB, the user storage area UST may have a capacity of 32 GB. In other words, the physical storage space PS of the storage device 1200 may be allocated to the user storage area UST or may be used for the user storage area UST.

[0082] In the case of configuring the accelerated write buffer TWB based on the no user capacity reduction mode, an accelerated write buffer TWBb with a specific capacity (e.g., 2GB) can be configured. The second physical storage space PS2b as part of the physical storage space PS can be allocated to the accelerated write buffer TWBb or can be used for the accelerated write buffer TWBb.

[0083] Unlike the user capacity reduction mode, the user storage area USTb in the non-user capacity reduction mode can maintain a capacity of 32 GB. In other words, in the non-user capacity reduction mode, even if the accelerated write buffer TWBb is configured, the capacity of the user storage area UST identified from the perspective of the host 1100 can be the same as the capacity before the accelerated write buffer TWBb is configured.

[0084] In an exemplary embodiment of the inventive concept, in the non-user capacity reduction mode, the size or configuration of the accelerated write buffer TWBb may be changed by an internal policy of the storage device 1200 or an explicit request from the host 1100. For example, because the second physical storage space PS2b as a part of the physical storage space PS is used to configure the accelerated write buffer TWBb, the first physical storage space PS1b to be used for the user storage area USTb may be smaller than the capacity of the user storage area USTb.

[0085] In other words, when the entire first physical storage space PS1b is used to store user data or the available free capacity of the first physical storage space PS1b is equal to or less than a reference value, all or part of the second physical storage space PS2b used to accelerate the write buffer TWBb can be returned to the user storage area USTb.

[0086] In other words, in the physical storage space PS, when the accelerated write buffer TWBb cannot be maintained due to lack of available space for the user storage area USTb, the second physical storage space PS2b allocated to the accelerated write buffer TWBb can be returned to the user storage area USTb. For example, the above-mentioned return operation can be performed through a user data dump operation and an operation of setting the size of the accelerated write buffer.

[0087] In an exemplary embodiment of the inventive concept, the host 1100 may check the current available size of the accelerated write buffer TWB of the storage device 1200. For example, the storage device 1200 may set information about the current size of the accelerated write buffer TWB in the current accelerated write buffer size field (e.g., "dCurrentTurboWriteBufferSzie") of the attribute. In addition, the storage device 1200 may set information about the ratio of the current available capacity of the accelerated write buffer TWB in the available accelerated write buffer size field (e.g., "dAvailableTurboWriteBufferSize") of the attribute.

[0088] The host 1100 can check the current available size of the accelerated write buffer TWB by checking the current accelerated write buffer size field and the available accelerated write buffer size field of the attribute. Based on the checked information, the host 1100 can change the strategy to use accelerated write, or can return the physical storage space used for the accelerated write buffer TWB to the user storage area UST.

[0089] As another example, the storage device 1200 can autonomously return the physical storage space used for accelerating the write buffer TWB to the user storage area UST. For example, the storage device 1200 can periodically compare the available space of the user storage area UST with a reference value to determine whether the physical storage space used for accelerating the write buffer TWB needs to be returned to the user storage area UST. When the storage device 1200 has returned the physical storage space used for accelerating the write buffer TWB to the user storage area UST, the storage device 1200 can set a status flag to indicate that the accelerated write buffer TWB is no longer available. The status flag can be stored in a register in the storage device 1200. The host 1100 can check the changed state of the accelerated write buffer TWB through the current accelerated write buffer size field. When the physical storage space used for accelerating the write buffer TWB is returned to the user storage area UST, the storage device 1200 can set the current accelerated write buffer size field to 0.

[0090] In an exemplary embodiment of the inventive concept, the storage device 1200 may provide information about the life of the accelerated write buffer TWB based on the number of program / erase (P / E) cycles of the physical storage space (or storage block) allocated to or used for the accelerated write buffer TWB. For example, the storage device 1200 may set the information about the life of the accelerated write buffer TWB in the accelerated write buffer life estimation field (e.g., "dTurboWriteBufferLifeTimeEst") of the attribute.

[0091] The host 1100 may estimate the life of the accelerated write buffer TWB by checking the accelerated write buffer life estimation field of the properties of the storage device 1200 via a query request. In an exemplary embodiment of the inventive concept, in a non-user capacity reduction mode, because the user storage area UST and the accelerated write buffer TWB share the physical storage space PS, the life of the accelerated write buffer TWB may be reduced in the case where a write operation is performed on the user storage area UST.

[0092] Figure 5 It is shown Figure 1 A flowchart of the operation of the storage system. Figure 5 Describe the initialization operation of the storage system 1000. Figure 1 , Figure 2 and Figure 5 In operation S11, the host 1100 and the storage device 1200 may perform an operation such as a power-on reset (POR) operation, a hardware reset operation, or an endpoint reset operation.

[0093] In operation S12, the host 1100 and the storage device 1200 may perform hardware initialization and startup. For example, a hardware layer of each of the host 1100 and the storage device 1200 may be initialized and started.

[0094] In operation S13, the host 1100 and the storage device 1200 may perform initialization on a specific layer (eg, a UFS transport (UTP) layer). For example, the host 1100 may transmit a NOP OUT UPIU to the storage device 1200. The storage device 1200 may transmit a NOP IN UPIU to the host 1100 in response to the NOP OUT UPIU.

[0095] In operation S14, the host 1100 may check the device descriptor from the storage device 1200. For example, the host 1100 may transmit a query request for reading the descriptor to the storage device 1200. The storage device 1200 may transmit a query response including the device descriptor to the host 1100 in response to the query request. The query request may include a read descriptor. For example, the read descriptor may indicate to the storage device 1200 that the external device requires a device descriptor.

[0096] In an exemplary embodiment of the inventive concept, the host 1100 may check the configuration and function of the storage device 1200 through the device descriptor. For example, the device descriptor may include an extended UFS function support field (e.g., "dExtendedUFSFeaturesSupport"), which includes information about whether the accelerated write function is supported. In an exemplary embodiment of the inventive concept, the information about whether the accelerated write function is supported may be set in a specific bit (e.g., bit [8]) of the extended UFS function support field.

[0097] The device descriptor may also include a turbo write buffer no user space reduction enable field (e.g., "bTurboWriteBufferNoUserSpaceReductionEn") that includes information about the turbo write buffer mode. In the case where the value of the turbo write buffer no user space reduction enable field is "00h", the device descriptor may be configured to use the turbo write buffer mode. Figure 4A In the case where the value of the TWB No User Space Reduction Enable field is "01h", the TWB can be configured in accordance with the user space reduction mode described in the TWB. Figure 4B The described no user capacity reduction mode is used to configure the accelerated write buffer TWB.

[0098] The device descriptor may also include a turbo write buffer type field (eg, "bTurbowriteBufferType") that includes information about the turbo write buffer type. In the case where the value of the turbo write buffer type field is "00h", the device descriptor may be configured to read the turbo write buffer type field according to the reference. Figure 3A The LU dedicated buffer type described in the description is used to configure the accelerated write buffer TWB. In the case where the value of the accelerated write buffer type field is "01h", the reference Figure 3B Describes the shared buffer type used to configure the accelerated write buffer TWB.

[0099] The device descriptor may also include a shared turbo write buffer allocation number field (e.g., "dNumSharedTurboWriteBufferAllocUnits") that includes information about the size of the turbo write buffer. In the case where the number of units allocated to the shared turbo write buffer is set to "0," a turbo write buffer of the shared buffer type may not be configured.

[0100] The above fields are exemplary only, and the inventive concept is not limited thereto. For example, in addition to the above fields, the device descriptor may also include other fields containing information about the configuration, structure, function, etc. of the storage device 1200. The various fields of the device descriptor may indicate the values ​​set before the initialization operation. The host 1100 may identify the current state of the storage device 1200 by reading the various fields of the device descriptor.

[0101] In an exemplary embodiment of the inventive concept, the above-mentioned fields of the device descriptor, such as "bTurboWriteBufferNoUserSpaceReductionEn", "bTurboWriteBufferType", and "dNumSharedTurboWriteBufferAllocUnits", can be changed by writing the values ​​of the corresponding fields of the configuration descriptor. In other words, the host 1100 can change information such as the accelerated write buffer type, the accelerated write buffer no user space reduction enabled, and the number of units allocated to the accelerated write buffer by writing the values ​​of the various fields of the configuration descriptor. In an exemplary embodiment of the inventive concept, the geometry descriptor of the storage device 1200 may include information such as an accelerated write buffer maximum size field, an accelerated write buffer maximum number field, an accelerated write buffer capacity adjustment factor field, a supported accelerated write buffer no user capacity reduction type field, a supported accelerated write buffer type field, and the like.

[0102] For example, the accelerated write buffer maximum size field (e.g., "dTurboWriteBufferMaxNAllocUnits") may include information about the maximum size of the accelerated write buffer TWB supported by the storage device 1200. The accelerated write buffer maximum number field (e.g., "bDeviceMaxTurboWriteLUs") may include information about the maximum number of accelerated write buffers supported by the storage device 1200.

[0103] The accelerated write buffer capacity adjustment factor field (e.g., "bTurboWriteBufferCapAdjFac") may include information about a capacity reduction factor according to the type of the accelerated write buffer memory. For example, in the case where the accelerated write buffer TWB is implemented with SLC and the user storage area UST is implemented with TLC, the value of the accelerated write buffer capacity adjustment factor field may be "3". In the case where the accelerated write buffer TWB is implemented with SLC and the user storage area UST is implemented with MLC, the value of the accelerated write buffer capacity adjustment factor field may be "2".

[0104] The supported turbo write buffer no user space reduction types field (eg, “bSupportedTurboWriteBufferNoUserSpaceReductionTypes”) may include information about whether the storage device 1200 supports any turbo write buffer modes (eg, user space reduction mode, no user space reduction mode, or both).

[0105] The supported turbo write buffer types field (eg, “bSupportedTurboWriteBufferTypes”) may include information about whether the storage device 1200 supports any turbo write buffer types (eg, LU-dedicated buffer types, shared buffer types, or both).

[0106] The above-mentioned fields are merely exemplary, and the present inventive concept is not limited thereto.

[0107] In operation S15, the host 1100 may download the boot code from the storage device 1200. For example, the host 1100 may transmit a TEST UNIT READY UPIU to the storage device 1200. The storage device 1200 may transmit status information in response to the received TEST UNIT READY UPIU. The host 1100 may determine whether a boot logical unit (or known boot LU) of the storage device 1200 is accessible based on the received status information.

[0108] In the case where the boot logic unit is accessible, the host 1100 may transmit a SCSI read (SCSI READ) command to the storage device 1200. In an exemplary embodiment of the inventive concept, the SCSI READ command may correspond to the boot logic unit. The storage device 1200 may transmit data "DATA" and status information to the host 1100 in response to the received command.

[0109] In operation S16, the host 1100 may complete the initialization operation by setting the flag of the storage device 1200. For example, the host 1100 may transmit a query request to the storage device 1200. The query request may be a request to set a device initialization field (e.g., "fDeviceInit") included in the flag of the storage device 1200. In response to the query request, the device initialization field included in the flag of the storage device 1200 may be set to a specific value (e.g., "01h"). Thereafter, the storage device 1200 may transmit a query response.

[0110] In operation S17, the host 1100 may poll a device initialization field (e.g., “fDeviceInit”) in the flag of the storage device 1200. For example, the host 1100 may transmit a query request for reading the device initialization field in the flag to the storage device 1200, and the storage device 1200 may transmit a query response including the device initialization field to the host 1100.

[0111] In an exemplary embodiment of the inventive concept, after operation S16, in order to complete the initialization operation of the storage device 1200, the device initialization field may be reset to a different value (e.g., "00h"). For example, the host 1100 may repeatedly perform operation S17 to check whether the device initialization field is reset. In the case where the device initialization field is reset, the initialization operation of the storage device 1200 may be completed.

[0112] Figure 6 It is shown Figure 1 A flowchart of the operation of the storage system. Figure 6 The write operation of the storage system 1000 is described. Figure 1 and Figure 6 In operation S21 , the host 1100 may transmit a CMD UPIU including a write command WR CMD to the storage device 1200 .

[0113] In operation S22, the host 1100 and the storage device 1200 may perform a data transaction. For example, the storage device 1200 may transmit a "Ready to Transfer UPIU (RTT UPIU)" to the host 1100. The RTT UPIU may include information about the data range in which the storage device 1200 can receive data. The host 1100 may transmit a DATAOUT UPIU including write data to the storage device 1200 in response to the RTT UPIU. As the above operations are repeatedly performed, the write data may be transmitted from the host 1100 to the storage device 1200.

[0114] After receiving all write data, the storage device 1200 may transmit a "RESPONSE UPIU" to the host 1100 in operation S23. The RESPONSE UPIU may include information indicating that an operation corresponding to the write command received in operation S21 is completed.

[0115] In an exemplary embodiment of the inventive concept, the storage device 1200 may perform a normal write operation on the write data received in operation S22. For example, in operation S21, the storage device 1200 may determine whether to enable the accelerated write function. More specifically, the storage device 1200 may determine whether to enable the accelerated write function based on the value of the accelerated write enable field (e.g., "fTurboWriteEn") in the flag.

[0116] In the case where the value of the accelerated write enable field is "0b", the accelerated write function may be in a disabled state. In the case where the value of the accelerated write enable field is "1b", the accelerated write function may be in an enabled state. In an exemplary embodiment of the inventive concept, the value of the accelerated write enable field in the flag may be set by a query request to set the flag of the host 1100.

[0117] The host 1100 may not set the value of the accelerated write enable field. In this case, the write data received in operation S22 may be written in the accelerated write buffer TWB or the user storage area UST according to the normal write policy.

[0118] In operation S30, the host 1100 may set the value of the accelerated write enable field to a specific value (e.g., “1b”). For example, the host 1100 may transmit a query request for setting the value of the accelerated write enable field to a specific value (e.g., “1b”) to the storage device 1200. In response to the query request from the host 1100, the value of the accelerated write enable field may be set to a specific value (e.g., “1b”), and the storage device 1200 may transmit a query response to the host 1100.

[0119] Thereafter, the host 1100 may perform operations S31 to S33. Operations S31 to S33 may be similar to operations S21 to S23 except that accelerated writing is performed according to the accelerated write enable field, and thus additional description will be omitted to avoid repetition.

[0120] In an exemplary embodiment of the inventive concept, the write data received in operation S32 may be written in the accelerated write buffer TWB. For example, in operation S30, since the value of the accelerated write enable field is set to a specific value (e.g., "1b"), the accelerated write function may be enabled. In this case, the write data received from the host 1100 may be written in the accelerated write buffer TWB. For example, in operation S31, the data received from the host 1100 may be stored in the fixed accelerated write buffer TWB-p or the non-fixed accelerated write buffer TWB-np according to the specific factor value of the command UPIU. Figure 8How to configure the acceleration write buffer divided into the fixed acceleration write buffer TWB-p and the non-fixed acceleration write buffer TWB-np is described more comprehensively.

[0121] In an exemplary embodiment of the inventive concept, even if the accelerated write function is enabled, in the case where the space of the accelerated write buffer TWB is insufficient, the storage device 1200 may write the received write data in the user storage area UST.

[0122] Figure 7 It is shown Figure 1 A flowchart of the operation of a storage device. Figure 7 Describe the dump operation of the storage device 1200. Figure 1 , Figure 2 and Figure 7 In operation S41, the storage device 1200 may determine whether the current state is an idle state, a sleep state, or a runtime state. When the storage device 1200 is in the runtime state, a separate dump operation may not be performed.

[0123] For example, when the storage device 1200 is processing a command received from the host 1100, the storage device 1200 may be in a runtime state. When there is no command received from the host 1100 and being processed or to be processed (e.g., a pending command), the storage device 1200 may be in an idle state. When the storage device 1200 enters a low power mode called "sleep" by the storage device 1200 or the host 1100 booting, the storage device 1200 may be in a sleep state.

[0124] When the storage device 1200 is in an idle state, in operation S42, it may be determined whether the first dump operation is enabled. The host 1100 may allow or disable the first dump operation at the storage device 1200 by setting the value of the accelerated write buffer dump enable field (e.g., "fTurboWriteBufferFlushEn") in the flag. The storage device 1200 may determine whether the first dump operation is enabled by checking the value of the accelerated write buffer dump enable field in the flag.

[0125] In an exemplary embodiment of the inventive concept, when the value of the accelerated write buffer dump enable field in the flags is "0b", the first dump operation may be disabled or prohibited. When the value of the accelerated write buffer dump enable field in the flags is "1b", the first dump operation may be enabled. In the case where the first dump operation is disabled, the storage device 1200 may not perform a separate dump operation.

[0126] In the case where the first dump operation is enabled, in operation S43, the storage device 1200 may perform the first dump operation during the idle state. The first dump operation may be a dump operation performed by the storage device 1200 in the idle state. The dump operation may be an operation of dumping or migrating user data written in the accelerated write buffer TWB to the user storage area UST according to an internal policy or an explicit command from the host 1100.

[0127] In an exemplary embodiment of the inventive concept, when the user data written in the accelerated write buffer TWB is dumped to the user storage area UST, the logical address of the dumped user data can be maintained, and the physical address can be changed. In this case, the storage device 1200 can update the mapping information of the logical address and the physical address of the dumped user data. For example, the physical address can be changed from the address of the accelerated write buffer TWB to the address of the user storage area UST.

[0128] When the determination result of operation S41 indicates that the storage device 1200 is in a dormant state, in operation S44, the storage device 1200 may determine whether to enable the second dump operation. As described above, for example, the host 1100 may allow or disable the second dump operation at the storage device 1200 by setting the value of the dormant period acceleration write buffer dump enable field (e.g., "fTurboWriteBufferFlushDuringHibernat") in the flag.

[0129] The storage device 1200 can determine whether to enable the second dump operation by checking the value of the accelerated write buffer dump enable field during sleep in the flag. In an exemplary embodiment of the inventive concept, when the value of the accelerated write buffer dump enable field during sleep in the flag is "0b", the second dump operation can be disabled or prohibited. When the value of the accelerated write buffer dump enable field during sleep in the flag is "1b", the second dump operation can be enabled. In the case where the second dump operation is disabled, the storage device 1200 may not perform a separate dump operation.

[0130] In case the second dump operation is enabled, the storage device 1200 may perform the second dump operation during the hibernation state in operation S45. The second dump operation may indicate a dump operation performed by the storage device 1200 in the hibernation state.

[0131] According to the above dump operation, the user data written in the acceleration write buffer TWB can be dumped or migrated to the user storage area UST. In this way, the available buffer size of the acceleration write buffer TWB can be ensured.

[0132] In an exemplary embodiment of the inventive concept, the above dump operation may be suspended under certain conditions. For example, the first dump operation performed in the idle state may be performed only when the command queue of the storage device 1200 is empty. In the case where a command is issued from the host 1100 while the first dump operation is being performed, the storage device 1200 may suspend the first dump operation being performed, and may first process the command issued from the host 1100. In an exemplary embodiment of the inventive concept, in the case where the sleep mode is terminated, the second dump operation performed in the sleep state may be stopped.

[0133] As mentioned above, according to certain conditions, the dump operation being performed can be suspended. In this case, the storage device 1200 can set the current state of the suspension information (or the information of the progress degree) or the dump operation in the accelerated write buffer dump status field (e.g., "bTurboWriteBufferFlushStatus") of the attribute.

[0134] In an exemplary embodiment of the inventive concept, the storage device 1200 may set information indicating that a flush operation is required for the accelerated write buffer TWB as a specific value (e.g., bit [5]) of an exception event status of an attribute (e.g., “dExceptionEventStatus”). The host 1100 may check the specific value (e.g., bit [5]) of the exception event status of the attribute, may determine that a flush operation is required at the storage device 1200, and may set specific fields (e.g., “fTurboWriteBufferFlushEn” and “fTurboWriteBufferFlushDuringHibernate”) in the flags of the storage device 1200 according to a policy.

[0135] refer to Figure 7 The description given is that the storage device 1200 performs a dump operation based on the value of the dump enable field (i.e., the value of the accelerated write buffer dump enable field or the value of the accelerated write buffer dump enable field during sleep), but the inventive concept is not limited to this. In an exemplary embodiment, the storage device 1200 performs a dump or migration operation based on an internal policy without considering the value of the dump enable field (i.e., the value of the accelerated write buffer dump enable field or the value of the accelerated write buffer dump enable field during sleep). In this case, the storage device 1200 can perform a dump or migration operation based on a determination result automatically made by the storage device 1200 (without external intervention, or based on its own determination result).

[0136] Figure 8 It is shown Figure 1 A block diagram of the physical storage space of the storage device 1200. Figure 1 and Figure 8 , the physical storage space PS of the storage device 1200 may include an accelerated write buffer TWB and a user storage area UST. The physical storage space PS, the accelerated write buffer TWB, and the user storage area UST of the storage device 1200 are described above, and therefore, additional description will be omitted to avoid repetition.

[0137] The accelerated write buffer TWB can be divided into a pinned accelerated write buffer TWB-p and a non-pinned accelerated write buffer TWB-np. As described above, when the accelerated write function of the storage device 1200 is enabled, the write data can be stored in one of the pinned accelerated write buffer TWB-p and the non-pinned accelerated write buffer TWB-np.

[0138] In an embodiment, data stored in the fixed acceleration write buffer TWB-p is not a target for movement (e.g., migration or dumping) to the user storage area UST, and data stored in the non-fixed acceleration write buffer TWB-np may be a target for movement to the user storage area UST. That is, the priority of data stored in the fixed acceleration write buffer TWB-p may be higher than the priority of data stored in the non-fixed acceleration write buffer TWB-np. However, the inventive concept is not limited thereto, because data stored in the fixed acceleration write buffer TWB-p may be a target for movement to the non-fixed acceleration write buffer TWB-np or the user storage area UST, depending on system resources or policies. In an exemplary embodiment, a migration or dump operation is periodically performed to move data from the acceleration write buffer TWB to the user storage area UST. In this embodiment, before any data in the fixed acceleration write buffer TWB-p is migrated or dumped to the user storage area UST, all data present in the non-fixed acceleration write buffer TWB-np is first migrated or dumped to the user storage area UST. In another embodiment, during a given migration, first data in the non-fixed acceleration write buffer TWB-np is migrated to the user storage area UST during a first period of migration, and second data in the fixed acceleration write buffer TWB-p is migrated to the user storage area UST during a second period after the first period.

[0139] The acceleration write buffer to store write data may be determined from among the fixed acceleration write buffer TWB-p and the non-fixed acceleration write buffer TWB-np through various schemes (eg, internal policy, change of internal policy according to a request of the host, explicit request of the host).

[0140] In an exemplary embodiment of the inventive concept, as described above, the size of the acceleration write buffer TWB may be determined under the control of the host 1100 or according to the internal policy of the storage device 1200. In this case, the ratio of the fixed acceleration write buffer TWB-p and the non-fixed acceleration write buffer TWB-np in the acceleration write buffer TWB may be determined or changed through various schemes (e.g., internal policy, change of internal policy according to a request of the host, explicit request of the host).

[0141] In an exemplary embodiment of the inventive concept, user data may be transferred, migrated or moved between the fixed acceleration write buffer TWB-p, the non-fixed acceleration write buffer TWB-np and the user storage area UST. For example, according to an explicit request of the host 1100, an internal policy of the storage device 1200 or a change of the internal policy according to a request of the host 1100, the user data may be migrated or moved between the fixed acceleration write buffer TWB-p and the non-fixed acceleration write buffer TWB-np.

[0142] Alternatively, according to an explicit request of the host 1100, an internal policy of the storage device 1200, or a change in the internal policy according to the request of the host 1100, the user data may be migrated or moved between the non-fixed acceleration write buffer TWB-np and the user storage area UST. For example, the user data may be dumped from the non-fixed acceleration write buffer TWB-np to the user storage area UST. Alternatively, according to an explicit request of the host 1100, an internal policy of the storage device 1200, or a change in the internal policy according to the request of the host 1100, the user data may be migrated or moved between the fixed acceleration write buffer TWB-p and the user storage area UST.

[0143] In an exemplary embodiment of the inventive concept, as shown in FIG. Figure 7 As described, the storage device 1200 may perform a dump operation during an idle state or a dormant state. In this case, the storage device 1200 may perform a dump operation on the non-fixed accelerated write buffer TWB-np in the accelerated write buffer TWB. In other words, the storage device 1200 may dump the user data in the non-fixed accelerated write buffer TWB-np stored in the accelerated write buffer TWB to the user storage area UST.

[0144] In this case, in an exemplary embodiment, the user data written in the fixed acceleration write buffer TWB-p may not be dumped to the user storage area UST. In other words, even if the storage device 1200 performs a dump operation, the user data written in the fixed acceleration write buffer TWB-p may be maintained.

[0145] As another example, data to be stored in the non-fixed acceleration write buffer TWB-np may be written in the fixed acceleration write buffer TWB-p according to the internal policy of the storage device 1200. The data may be dumped from the fixed acceleration write buffer TWB-p to the user storage area UST. In other words, the data stored in the fixed acceleration write buffer TWB-p may not be dumped by an explicit dump request from the host 1100, but may be selectively dumped to the user storage area UST according to the internal dump policy of the storage device 1200.

[0146] In an exemplary embodiment of the present inventive concept, in the case of dumping, migrating or moving data between the fixed acceleration write buffer TWB-p, the non-fixed acceleration write buffer TWB-np and the user storage area UST, the controller 1210 may be configured to update the mapping relationship of the moved data. For example, in the case where data corresponding to the first logical block address is dumped or migrated from the fixed acceleration write buffer TWB-p to the user storage area UST, the controller 1210 may release the mapping relationship between the first logical block address and the physical address of the fixed acceleration write buffer TWB-p, and may update the mapping relationship between the first logical block address and the physical address of the user storage area UST. The release or update of the mapping relationship may be performed in a similar scheme to the above-mentioned scheme for moving between other areas, and therefore, additional description will be omitted to avoid repetition.

[0147] In order to more clearly explain the inventive concept, a description will be given below on the assumption that data to be stored in the fixed acceleration write buffer TWB-p needs to be stored in the fixed acceleration write buffer TWB-p. However, the inventive concept is not limited thereto.

[0148] Accordingly, when the host 1100 issues a read command for the first user data written in the fixed acceleration write buffer TWB-p, the first user data can be read from the fixed acceleration write buffer TWB-p. In this case, the first user data can be read at a high speed.

[0149] For example, as described above, the fixed acceleration write buffer TWB-p can store user data based on the SLC scheme, and the user storage area UST can store user data based on the TLC scheme. The time required to read user data stored based on the SLC scheme is shorter than the time required to read user data stored based on the TLC scheme.

[0150] In other words, since the specific user data is retained in the fixed acceleration write buffer TWB-p, the speed of reading the specific user data can be increased. This function of the storage device 1200 can be called "accelerated reading".

[0151] In an exemplary embodiment of the inventive concept, the physical storage space PS of the storage device 1200 may indicate a storage space of the nonvolatile memory device 1220. In other words, the nonvolatile memory device 1220 may include a fixed acceleration write buffer TWB-p, a non-fixed acceleration write buffer TWB-np, or a user storage area UST.

[0152] Fig. 9 is shown for reference Figure 8 A diagram of a logical storage space of a physical storage space PS of a storage device 1200 is described.

[0153] For ease of description, reference will be made to a logical unit description. Fig. 9 However, the inventive concept may be equally applied to two or more logical units corresponding to the acceleration write buffer TWB, or equally applied to the relationship between a logical unit and a shared acceleration write buffer (eg, TWB0).

[0154] Reference Figure 1 and Fig. 9 The logical storage space LS of the storage device 1200 identified by the host 1100 may include a user storage area UST and an accelerated write buffer TWB. The accelerated write buffer TWB may include a fixed accelerated write buffer TWB-p and a non-fixed accelerated write buffer TWB-np.

[0155] The first logical block address range (e.g., LBA0 to LBAa, LBAb+1 to LBAc, and LBAe+1 to LBAn) may correspond to the logical storage space of the user storage area UST. In this case, user data stored in the first logical block address range (e.g., LBA0 to LBAa, LBAb+1 to LBAc, and LBAe+1 to LBAn) may be stored in the physical storage space of the user storage area UST.

[0156] The second logical block address range (e.g., LBAa+1 to LBAb and LBAd+1 to LBAe) may correspond to the logical storage space of the non-fixed accelerated write buffer TWB-np. In this case, user data stored in the second logical block address range (e.g., LBAa+1 to LBAb and LBAd+1 to LBAe) may be stored in the physical storage space of the non-fixed accelerated write buffer TWB-np.

[0157] The third logical block address range (e.g., LBAc+1 to LBAd) may correspond to the logical storage space of the fixed acceleration write buffer TWB-p. In this case, user data stored in the third logical block address range (e.g., LBAc+1 to LBAd) may be stored in the physical storage space of the fixed acceleration write buffer TWB-p.

[0158] As described above, the user storage area UST, the non-fixed accelerated write buffer TWB-np, and the fixed accelerated write buffer TWB-p may be distributed in various forms on the logical storage space LS identified by the host 1100. However, the inventive concept is not limited thereto, and the third logical block address range may correspond to the logical storage space of the non-fixed accelerated write buffer TWB-np, and the second logical block address range may correspond to the logical storage space of the fixed accelerated write buffer TWB-p. In an exemplary embodiment of the inventive concept, according to an explicit request of the host 1100 or an internal policy of the storage device 1200, user data may be moved / dumped / migrated between the user storage area UST, the non-fixed accelerated write buffer TWB-np, and the fixed accelerated write buffer TWB-p.

[0159] For example, the host 1100 may specify one of the fixed accelerated write buffer TWB-p and the non-fixed accelerated write buffer TWB-np when accelerating writing. As another example, the host 1100 may specify one of the fixed accelerated write buffer TWB-p and the non-fixed accelerated write buffer TWB-np as the accelerated write target before accelerating writing. As another example, the host 1100 may not specify the fixed accelerated write buffer TWB-p or the non-fixed accelerated write buffer TWB-np when accelerating writing.

[0160] The host 1100 may check the distribution status of data changed by the storage device 1200 by periodically or on demand requesting (eg, using a query UPIU) information of the fixed acceleration write buffer TWB-p and the non-fixed acceleration write buffer TWB-np from the storage device 1200 .

[0161] Fig. 10A and Fig. 10B is shown in reference Figure 8 Schematic diagram of the operation in the physical storage space of the storage device described. For the sake of simplicity and convenience of description, it is assumed that the fixed acceleration write buffer TWB-p includes a first storage block BLK1, the non-fixed acceleration write buffer TWB-np includes a second storage block BLK2, and the user storage area UST may include a third storage block BLK3. However, the inventive concept is not limited thereto.

[0162] Reference Figure 1 , Figure 8 and Fig. 10A , the storage device 1200 may receive the first data DT1 corresponding to the first logical block address LBA1 from the host 1100. In an exemplary embodiment of the inventive concept, the accelerated write function of the storage device 1200 may be in an enabled state. In this case, the storage device 1200 may write the received first data DT1 in the accelerated write buffer TWB (e.g., the non-fixed accelerated write buffer TWB-np).

[0163] In other words, the storage device 1200 may perform accelerated writing on the first data DT1. In an exemplary embodiment of the inventive concept, when the accelerated writing function is enabled, it may be determined through various schemes whether to store data in any one of the fixed accelerated writing buffer TWB-p and the non-fixed accelerated writing buffer TWB-np.

[0164] In an exemplary embodiment of the inventive concept, Fig. 10A As shown, the fixed accelerated write buffer TWB-p and the non-fixed accelerated write buffer TWB-np may be filled with user data DTa, DTb, DT0, and DT1. In this case, the storage device 1200 may notify the host 1100 that a dump operation is required by setting a specific bit (e.g., bit [5]) of the exception event status field (e.g., "wExceptionEventStatus") of the attribute.

[0165] The host 1100 can check the abnormal event status field of the attribute through the query request, and can check whether a dump operation is required at the storage device 1200. ... Figure 7 The accelerated write buffer dump enable field or the accelerated write buffer dump enable field during hibernation in the flag of the storage device 1200 is set as described to allow the dump operation of the storage device 1200.

[0166] When the dump function is allowed (or enabled) under the control of the host 1100, the storage device 1200 may perform a dump operation. For example, in an idle state or a sleep state, the storage device 1200 may dump the user data DT0 and DT1 stored in the non-fixed acceleration write buffer TWB-np to the third storage block BLK3 of the user storage area UST. In an exemplary embodiment of the inventive concept, even if the dump operation is allowed under the control of the host 1100, the user data DTa and DTb stored in the fixed acceleration write buffer TWB-p may not be dumped to the user storage area UST. In other words, the user data DTa and DTb stored in the fixed acceleration write buffer TWB-p are retained, while the user data DT0 and DT1 stored in the non-fixed acceleration write buffer TWB-np are dumped.

[0167] Thereafter, the storage device 1200 may receive a read command for the first logical block address LBA1 from the host 1100. In this case, the storage device 1200 may read the first data DT1 stored in the third storage block BLK3 of the user storage area UST and may output the read first data DT1 to the host 1100.

[0168] In an exemplary embodiment of the inventive concept, since the first data DT1 is written (e.g., programmed by SLC) in the non-fixed acceleration write buffer TWB-np, but the first data DT1 is dumped to the user storage area UST due to the dump operation, the first data DT1 can be read by a normal read operation (e.g., a TLC read operation). In other words, the first data DT1 can be programmed by SLC but read by TLC.

[0169] Reference Figure 1 , Figure 8 and Fig. 10B , the zeroth data DT0 and the first data DT1 may be stored in the second storage block BLK2 of the non-fixed acceleration write buffer TWB-np, and the ath data DTa may be stored in the third storage block BLK3 of the user storage area UST.

[0170] Afterwards, according to an explicit request of the host 1100 or an internal policy of the storage device 1200, the ath data DTa of the user storage area UST may be moved to the first storage block BLK1 of the fixed acceleration write buffer TWB-p. For example, the storage device 1200 may read the ath data DTa from the third storage block BLK3 of the user storage area UST, and may store the read ath data DTa in the first storage block BLK1 of the fixed acceleration write buffer TWB-p. Afterwards, the ath data DTa stored in the third storage block BLK3 of the user storage area UST may be invalidated, deleted, or unmapped. In an exemplary embodiment of the inventive concept, even if the ath data DTa is invalidated, deleted, or unmapped, the ath logical block address LBAa corresponding to the ath data DTa may maintain mapping with the first storage block BLK1 of the fixed acceleration write buffer TWB-p.

[0171] Afterwards, the storage device 1200 may receive a read command for the ath logical block address LBAa corresponding to the ath data DTa from the host 1100. In this case, the storage device 1200 may read the ath data DTa stored in the first storage block BLK1 of the fixed acceleration write buffer TWB-p, and may transmit the read ath data DTa to the host 1100.

[0172] In an exemplary embodiment of the inventive concept, an operation of reading the ath data DTa stored in the first storage block BLK1 of the fixed acceleration write buffer TWB-p may be faster than an operation of reading data stored in the third storage block BLK3 of the user storage area UST. In other words, the storage device 1200 according to an exemplary embodiment of the inventive concept may support a fast read operation (e.g., an accelerated read operation) for specific data by storing and retaining the specific data in the acceleration write buffer TWB (or, the fixed acceleration write buffer TWB-p).

[0173] In an exemplary embodiment of the inventive concept, the storage device 1200 may notify the host 1100 of the remaining (or free) capacity of the accelerated write buffer TWB in response to a request of the host 1100. The storage device 1200 may write information about the remaining free capacity of the accelerated write buffer TWB to an available accelerated write buffer size field (e.g., "dAvailableTurboWriteBufferSize") of the attribute. The host 1100 may obtain the capacity information of the accelerated write buffer TWB by reading (e.g., by using a query UPIU) the available accelerated write buffer size field.

[0174] For example, the storage device 1200 may separately record the remaining capacity of the fixed accelerated write buffer TWB-p and the remaining capacity of the non-fixed accelerated write buffer TWB-np in the available accelerated write buffer size field. As another example, the storage device 1200 may record the sum of the remaining capacity of the accelerated write buffer TWB in the available accelerated write buffer size field. Whether the storage device 1200 records the remaining capacity of the accelerated write buffer TWB as a whole or individually may be specified by setting a flag of the host 1100.

[0175] For example, the storage device 1200 may record a capacity smaller than the actual free capacity of the acceleration write buffer TWB in the available acceleration write buffer size field. In a nonvolatile memory device 1220 such as a flash memory, when the time between consecutive erase operations is less than a threshold time, data reliability may be reduced.

[0176] Because the capacity of the accelerated write buffer TWB is smaller than that of the user storage area UST, and the accelerated write buffer TWB is used in the SLC scheme, the accelerated write buffer TWB can be filled with data faster than the user storage area UST. In addition, in the case where the host 1100 prefers high-speed accelerated writing, the accelerated write buffer TWB can be filled with data faster.

[0177] In the case where data is written intensively in the accelerated write buffer TWB, during a short time window, the following series of operations are performed: a first erase operation is performed on the accelerated write buffer TWB, data is written in the accelerated write buffer TWB, data in the accelerated write buffer TWB is dumped, a second erase operation is performed on the accelerated write buffer TWB, and data is written in the accelerated write buffer TWB.

[0178] In this case, when the time between the first erase operation and the second erase operation is less than the threshold time, the reliability of the data written in the accelerated write buffer TWB after the second erase operation may be reduced. In order to improve reliability, even if a specific storage block of the accelerated write buffer TWB does not store valid data and can be reused after the erase operation, when the time elapsed after the last erase operation of the specific storage block is less than the threshold time, the storage device 1200 can record the capacity excluding the capacity of the specific storage block in the available accelerated write buffer size field.

[0179] Fig.11 is a block diagram illustrating a computer system according to an exemplary embodiment of the inventive concept.

[0180] Reference Fig.11 , the computer system 2000 may include a host 2100 and a storage device 2200. The computer system 2000 may be one of electronic devices such as a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a workstation, one or more servers, an electric car, a home appliance, a medical device, etc.

[0181] The host 2100 may access the storage device 2200, for example, for the purpose of reading data. The storage device 2200 stores data in the nonvolatile memory device 2220, or reads data from the nonvolatile memory device 2220 in response to a write or read request of the host 2100. The host 2100 may include, for example, a processor 2110, a host memory 2120, and an interface circuit 2130.

[0182] The processor 2110 executes an application program, an operating system OS, and various driver programs loaded on the host memory 2120 .

[0183] Applications, file systems, device drivers, etc. may be loaded onto the host memory 2120. In addition, data or various software driven at the host 2100 may be loaded onto the host memory 2120. For example, the host 2100 may allocate a portion of the host memory 2120 to a buffer area for storing metadata of the storage device 2200. Here, the metadata of the storage device 2200 may be, for example, mapping data MD or mapping cache data MCD. Hereinafter, a portion of the host memory 2120 allocated to the buffer of the storage device 2200 is referred to as a "storage allocation area (SAA) 2123". The mapping data MD may include first mapping data corresponding to a fixed acceleration write buffer TWB-p, second mapping data corresponding to a non-fixed acceleration write buffer TWB-np, and third mapping data corresponding to a user storage area UST. Such first mapping data may be used to update corresponding first mapping cache data, such second mapping data may be used to update corresponding second mapping cache data, and such third mapping data may be used to update corresponding third mapping cache data.

[0184] The storage allocation area 2123 is allocated to allow the storage device 2200 to use the host memory 2120 as a buffer of the storage device 2200. For example, in an exemplary embodiment, such as mapping cache data (in Fig.11 The metadata of the mapping cache data 2124 and 2126 (respectively marked by "MCD_TWB" and "MCD_UST" in the memory) is stored in the storage allocation area 2123. The mapping cache data 2124 and 2126 may include mapping cache data MCD_TWB and MCD_UST associated with the acceleration write buffers 2222, 2224 and the user storage area 2226 of the storage device 2200, respectively. The acceleration write buffer 2222 may be a fixed acceleration write buffer, and the acceleration write buffer 2224 may be a non-fixed acceleration write buffer. Each of the mapping cache data MCD_TWB and MCD_UST stored in the storage allocation area 2123 is managed according to the priority of each corresponding area. For example, in a page cache operation, the retention time of the mapping cache data 2124 corresponding to the acceleration write buffers 2222, 2224 may be set to be longer than the retention time of the mapping cache data 2126 corresponding to the user storage area 2226. This will be described in further detail below.

[0185] Once the storage allocation area 2123 is allocated in the host memory 2120 for the buffer of the storage device 2200, the storage device 2200 can be used as a master device and the host memory 2120 can be used as a slave device with respect to the storage allocation area 2123. Alternatively, in the case of using virtual memory, the storage allocation area 2123 can be managed on one storage map using the internal buffer 2112 of the storage controller 2210.

[0186] The interface circuit 2130 provides a physical connection between the host 2100 and the storage device 2200. For example, the interface circuit 2130 converts commands, addresses, data, etc. corresponding to various access requests generated from the host 2100 into a format suitable for the interface scheme of the storage device 2200. The access request sent from the host 2100 to the storage device 2200 can cause the storage device 2200 to transmit the mapping data MD to the host 2100 in response to the access request. For example, in response to such an access request, the storage device 2200 can transmit the first mapping data Map_Data1 corresponding to the fixed acceleration write buffer TWB-p to the host (see Fig.14 ), and the second mapping data Map_Data2 corresponding to the non-fixed acceleration write buffer TWB-np (see Fig.14 ), and the third mapping data Map_Data3 corresponding to the user storage area UST (see Fig.14 ). The protocol of the interface circuit 2130 may include at least any one of the following, for example: Universal Serial Bus (USB), Small Computer System Interface (SCSI), PCI Express, ATA, Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), and Universal Flash Storage (UFS). Here, it is assumed that the interface circuit 2130 includes the Universal Flash Storage (UFS) interface protocol.

[0187] The storage device 2200 may be provided as a data storage of the host 2100. The storage device 2200 may include a storage controller 2210 and a nonvolatile memory device 2220. The storage device 2200 may access the nonvolatile memory device 2220 in response to a command CMD from the host 2100, or may perform various operations requested by the host 2100.

[0188] The storage controller 2210 provides an interface between the host 2100 and the storage device 2200. The storage controller 2210 may write data in the nonvolatile memory device 2220 according to a request from the host 2100. In addition, the storage controller 2210 may output data stored in the nonvolatile memory device 2220 to the host 2100 in response to a command from the host 2100. The storage controller 2210 may include an internal buffer 2112.

[0189] The storage controller 2210 may manage various metadata required for managing the nonvolatile memory device 2220. The metadata may be stored in the nonvolatile memory device 2220 and may be read from the nonvolatile memory device 2220 when the storage controller 2210 needs the metadata. For example, the metadata managed by the storage controller 2210 may include mapping data MD. The mapping data MD may include mapping information between a physical address of a storage space of the nonvolatile memory device 2220 and a logical address assigned to the storage device 2200 by the host device.

[0190] The storage controller 2210 may load a portion of the mapping data MD (e.g., a portion required to execute a request from a host device or a background operation) onto the internal buffer 2112 as mapping cache data MCD. The internal buffer 2112 may be, for example, a static random access memory (SRAM). In the case where the mapping cache data MCD is updated when the storage controller 2210 executes an operation corresponding to a request from the host 2100 or performs a background operation, the updated portion may be written in the nonvolatile memory device 2220, so that the updated portion is applied to the mapping data MD of the nonvolatile memory device 2220.

[0191] The capacity of the internal buffer 2112 of the storage controller 2210 may be smaller than the capacity of the mapping data MD. In this case, the entire mapping data MD cannot be loaded onto the storage controller 2210. In the case where a portion of the mapping data MD required for executing a request or background operation of the host 2100 is not loaded onto the storage controller 2210 as the mapping cache data MCD, the storage controller 2210 may delete a portion of the mapping cache data MCD, or may write a portion of the mapping cache data MCD in the nonvolatile memory device 2220, and the storage controller 2210 may read a required portion of the mapping data MD from the nonvolatile memory device 2220. This results in an increase in the time required to execute a request or background operation of the host 2100.

[0192] In order to prevent or reduce the increase in this time, the storage device 2200 is configured to transmit all or part of the mapping data MD to the host 2100. The host 2100 is configured to store all or part of the mapping data MD transmitted from the storage device 2200 as mapping cache data MCD in the storage allocation area 2123. Subsequently, the host 2100 can transmit a read request to the storage device 2200 with reference to the mapping cache data MCD. In this case, the time required for the storage device 2200 to execute the request of the host 2100 can be reduced, and the performance of the storage device 2200 and the computer system 2000 can be improved.

[0193] For example, in an exemplary embodiment, the mapping cache data MCD stored in the storage allocation area 2123 may be divided and managed according to the corresponding area of ​​the storage device 2200. For example, among the mapping cache data MCD stored in the storage allocation area 2123, the mapping cache data TWB_MCD corresponding to the acceleration write buffers 2222 and 2224 may be managed with a higher priority than the mapping cache data UST_MCD corresponding to the user storage area 2226. In addition, the priority assigned to the mapping cache data corresponding to the fixed acceleration write buffer 2222 may be different from the priority assigned to the mapping cache data corresponding to the non-fixed acceleration write buffer 2224. For example, in an exemplary embodiment, the priority assigned to the mapping cache data corresponding to the fixed acceleration write buffer 2222 may be higher than the priority assigned to the mapping cache data corresponding to the non-fixed acceleration write buffer 2224. In an exemplary embodiment, the priority assigned to the mapping cache data corresponding to the fixed acceleration write buffer 2222 and the priority assigned to the mapping cache data corresponding to the non-fixed acceleration write buffer 2224 may both be higher than the priority assigned to the mapping cache data corresponding to the user storage area 2226.

[0194] The nonvolatile memory device 2220 is provided as a storage medium of the storage device 2200. The nonvolatile memory device 2220 may include a reference Figure 8 Described are the fixed acceleration write buffer 2222, the non-fixed acceleration write buffer 2224 and the user storage area 2226.

[0195] According to an exemplary embodiment of the inventive concept, the storage device 2200 may transmit mapping cache data MCD of each region of the nonvolatile memory device 2220 to the host 2100. The storage device 2200 may add an identifier corresponding to the region to the mapping cache data for each region, and may transmit the mapping cache data including the added identifier. The host 2100 may store and manage the mapping cache data MCD of each region provided from the storage device 2200 in the storage allocation area 2123 provided in the host memory 2120. In a read request, the host 2100 may perform access to the nonvolatile memory device 2220 by using the mapping cache data stored in the storage allocation area 2123. In addition, in the case where the mapping data MD is changed by a read or write operation, the changed mapping cache data may be provided to the host 2100 so that the host 2100 updates the mapping cache data MCD.

[0196] Fig.12is a diagram showing an exemplary embodiment according to the inventive concept Fig.11 A memory map of the host memory allocation structure.

[0197] Reference Fig.12 , the host memory 2120 may be divided into a host allocation area (HAA) 2122 and a storage allocation area (SAA) 2123 storing the mapped cache data MCD.

[0198] Data used for various operations of the host 2100 is stored in the host allocation area 2122. For example, an application program, an operating system, or various functions called by the processor 2110 may be loaded into the host allocation area 2122.

[0199] The mapping cache data MCD of each area of ​​the storage allocation area 2123 may be loaded onto the storage allocation area 2123. For example, the mapping cache data MCD_TWB-p 2124a, MCD_TWB-np 2124b, and MCD_UST 2126 associated with the acceleration write buffers 2222, 2224, and the user storage area 2226 are loaded onto the storage allocation area 2123. When providing the mapping cache data MCD_TWB-p 2124a, MCD_TWB-np 2124b, and MCD_UST 2126, the storage device 2200 may mark the identifiers on the respective areas and transmit the identifiers of the respective areas. With regard to the management operation of the host memory 2120, the host 2100 may manage the mapping cache data MCD_TWB-p 2124a, MCD_TWB-np 2124b, and MCD_UST 2126 with different priorities.

[0200] In the page cache operation, the host 2100 may manage the storage allocation area 2123 in a scheme of excluding the mapping cache data from the victim target according to the priorities of the mapping cache data MCD_TWB-p 2124a, MCD_TWB-np 2124b, and MCD_UST 2126. Therefore, the mapping cache data with a high priority may have a long life in the storage allocation area 2123. Alternatively, when a plurality of mapping cache data with different priorities are provided from the storage device 2200, the host 2100 may first update the mapping cache data with a high priority. For example, the mapping cache data MCD_TWB-p 2124a corresponding to the fixed acceleration write buffer TWB-p may have a higher priority than the mapping cache data MCD_UST 2126 of the user storage area UST. In this case, the mapping cache data MCD_TWB-p 2124a corresponding to the fixed acceleration write buffer TWB-p may be updated before the mapping cache data MCD_UST 2126 of the user storage area UST.

[0201] According to the above management scheme, the mapping cache data of the frequently accessed area can exist in the storage allocation area 2123 for a relatively long period of time. Therefore, when the host 2100 accesses the storage device 2200, the hit rate of the mapping cache data stored in the internal buffer 2112 or the host memory 2120 can be improved.

[0202] The nonvolatile memory device 2220 may include accelerated write buffers 2222 and 2224 that can perform high-speed write and read operations. High access speed can be provided by the accelerated write buffers 2222 and 2224. In addition, the read speed can be further improved by managing the mapping cache data MCD of the accelerated write buffers 2222 and 2224 at the host memory 2120.

[0203] Fig.13A and Fig. 13B is a diagram showing an exemplary embodiment according to the inventive concept. Fig.11 A flowchart of an example of a memory management operation performed at a host.

[0204] The host 2100 may manage the mapping cache data MCD stored in the host memory 2120 according to the priority. For example, the mapping cache data MCD having a high priority may have a priority for updating. Alternatively, in a page cache operation, the mapping cache data MCD having a high priority may have a low deletion priority.

[0205] Reference Fig.13A, the host 2100 updates the mapping cache data MCD stored in the host memory 2120 by using the mapping data MD or the mapping cache data MCD provided from the storage device 2200. For example, the mapping cache data MCD may have different update priorities depending on the relevant areas.

[0206] In operation S61, the host 2100 receives mapping data MD or mapping cache data MCD provided from the storage device 2200. The mapping data MD or mapping cache data MCD may be included in a response after a read or write command. Alternatively, the host 2100 may request the mapping data MD or mapping cache data MCD from the storage device 2200 through a separate command.

[0207] In operation S62, the host 2100 determines whether it is necessary to update the mapping cache data MCD managed at the host memory 2120 based on the result of comparing the mapping data MD or the mapping cache data MCD received from the storage device 2200. When it is determined that the mapping cache data MCD does not need to be updated (No), the process proceeds to operation S61 to receive new mapping data MD or new mapping cache data MCD. When it is determined that the mapping cache data MCD needs to be updated (Yes), the process proceeds to operation S63.

[0208] In operation S63, it is determined whether the received mapping data MD or the received mapping cache data MCD corresponds to the fixed acceleration write buffer TWB-p. When it is determined that the received mapping data MD or the received mapping cache data MCD corresponds to the fixed acceleration write buffer TWB-p (Yes), the process proceeds to operation S64. On the contrary, when it is determined that the received mapping data MD or the received mapping cache data MCD does not correspond to the fixed acceleration write buffer TWB-p (No), the process proceeds to operation S65.

[0209] In operation S65, it is determined whether the received mapping data MD or the received mapping cache data MCD corresponds to the non-fixed acceleration write buffer TWB-np. When it is determined that the received mapping data MD or the received mapping cache data MCD corresponds to the non-fixed acceleration write buffer TWB-np (Yes), the process proceeds to operation S66. On the contrary, when it is determined that the received mapping data MD or the received mapping cache data MCD does not correspond to the non-fixed acceleration write buffer TWB-np (No), the process proceeds to operation S67.

[0210] In operation S64, because the received mapping data MD or the received mapping cache data MCD corresponds to the fixed acceleration write buffer TWB-p, the mapping cache data MCD is updated immediately. In operation S66, because the received mapping data MD or the received mapping cache data MCD corresponds to the non-fixed acceleration write buffer TWB-np, the mapping cache data MCD is updated after the elapsed time T1. When new mapping data MD or new mapping cache data MCD is received before the elapsed time T1, the process proceeds to operation S61. In operation S67, because the received mapping data MD or the received mapping cache data MCD does not correspond to the acceleration write buffer TWB, the mapping cache data MCD is updated after the elapsed time T2 which is longer than the elapsed time T1. When new mapping data MD or new mapping cache data MCD is received before the elapsed time T2, the process proceeds to operation S61.

[0211] The method of managing the host memory 2120 according to the update priority of the mapping cache data MCD_TWB-p, MCD_TWB-np, and MCD_UST is described above. However, updating the mapping cache data MCD_TWB-p, MCD_TWB-np, and MCD_UST in consideration of the priority is not limited to the above description. For example, in an exemplary embodiment, the priority may be changed based on various references that conform to the policy for managing the mapping cache data MCD_TWB-p, MCD_TWB-np, and MCD_UST.

[0212] Reference Fig. 13B , the host 2100 manages the host memory 2120. For example, the host 2100 may perform a page cache operation to effectively manage the mapping cache data MCD within a limited memory size.

[0213] In operation S110, the host 2100 detects an update request for the mapping cache data MCD stored in the storage allocation area 2123 of the host memory 2120. For example, when new mapping cache data MCD is transmitted from the storage device 2200, the host 2100 may start a page cache operation to update the mapping cache data MCD in the storage allocation area 2123.

[0214] In operation S120, the host 2100 determines whether the mapping cache data MCD needs to be updated. When it is determined that the mapping cache data MCD does not need to be updated (No), the process proceeds to operation S110 to continue detecting an update request for the mapping cache data MCD. When it is determined that the mapping cache data MCD needs to be updated (Yes), the process proceeds to operation S130.

[0215] In operation S130, the host 2100 determines whether the mapping cache data MCD_UST associated with the user storage area 2226 having the lowest priority exists in the storage allocation area 2123. Alternatively, the host 2100 may determine whether the size of the mapping cache data MCD_UST occupying the storage allocation area 2123 is equal to or greater than the reference size. When it is determined that the mapping cache data MCD_UST exists in the storage allocation area 2123 (Yes), the process proceeds to operation S135. When it is determined that the mapping cache data MCD_UST does not exist in the storage allocation area 2123 (No), the process proceeds to operation S140.

[0216] In operation S135, the host 2100 selects the mapping cache data MCD_UST associated with the user storage area 2226 as a victim and deletes the selected mapping cache data MCD_UST. Here, when data is called a victim, it means that the data will be deleted. The storage area obtained by deleting the mapping cache data MCD_UST can be provided as an area for storing mapping cache data MCD updated later.

[0217] In operation S140, the host 2100 determines whether the mapping cache data MCD_TWB-np associated with the non-fixed acceleration write buffer 2224 exists in the storage allocation area 2123. When it is determined that the mapping cache data MCD_TWB-np exists in the storage allocation area 2123 (Yes), the process proceeds to operation S145. On the contrary, when it is determined that the mapping cache data MCD_TWB-np does not exist in the storage allocation area 2123 (No), the process proceeds to operation S150.

[0218] In operation S145, the host 2100 selects the mapping cache data MCD_TWB-np associated with the non-fixed acceleration write buffer 2224 as a victim and deletes the selected mapping cache data MCD_TWB-np. The storage area obtained by deleting the mapping cache data MCD_TWB-np can be provided as an area for storing mapping cache data MCD updated later.

[0219] In operation S150 , the host 2100 selects mapping cache data MCD_TWB-p associated with the fixed acceleration write buffer 2222 as a victim and deletes the selected mapping cache data MCD_TWB-p.

[0220] In operation S160, the host 2100 determines whether a sufficient storage area is ensured in the storage allocation area 2123 of the host memory 2120. When an additional storage area for the page cache operation is still required (No), the process proceeds to operation S130 to delete the mapping cache data for the page cache operation. However, when it is determined that a sufficient storage area is ensured for the page cache operation, the memory management operation is terminated.

[0221] In an exemplary embodiment, in a page cache operation, the deletion priority of the mapping cache data MCD_UST is higher than each of the deletion priority of the mapping cache data MCD_TWB-p and the deletion priority of the mapping cache data MCD_TWB-np. In an exemplary embodiment, in a page cache operation, the deletion priority of the mapping cache data MCD_TWB-np is higher than the deletion priority of the mapping cache data MCD_TWB-p.

[0222] It is described above that management operations are performed based on the priorities of the mapping cache data MCD_TWB-p, MCD_TWB-np, and MCD_UST. However, updating the mapping cache data MCD_TWB-p, MCD_TWB-np, and MCD_UST in consideration of the priorities is not limited to the above description. For example, in an exemplary embodiment, the priorities may be changed based on various references that conform to the policy for managing the mapping cache data MCD_TWB-p, MCD_TWB-np, and MCD_UST. For example, the order of the priorities may be the same as that of the above reference. Fig.13A and Fig. 13B There are different levels of description.

[0223] Fig.14 is a block diagram illustrating an example of transferring mapping cache data MCD to a host memory according to an exemplary embodiment of the inventive concept.

[0224] Reference Fig.14 , the storage device 2200 may transmit the mapping cache data MCD to the host 2100 in response to an access command or a buffer read command of the host 2100 .

[0225] The storage device 2200 may load and transmit the mapping cache data MCD corresponding to the data requested for access to a response data packet (e.g., a response UPIU) in response to a read command or a write command of the host 2100. In this case, the mapping cache data MCD of the data requested for access may be transmitted by using a reserved field of the response data packet.

[0226] When a command to access the fixed acceleration write buffer 2222 is received from the host 2100, the storage device 2200 may perform a read or write operation on a selected area of ​​the fixed acceleration write buffer 2222. Subsequently, the storage device 2200 may write the mapping cache data MCD corresponding to the accessed area in a response data packet, and may transmit the response data packet to the host 2100. Such transmission of the mapping cache data MCD may be equally applied to operations of accessing the non-fixed acceleration write buffer 2224 and the user storage area 2226.

[0227] In an exemplary embodiment, when an event occurs in which data is moved from the accelerated write buffer 2222, 2224 to the user storage area 2226, the storage device 2200 may request a buffer read command from the host 2100. Fig.11 ) can be transmitted to the host 2100 through a buffer read command.

[0228] Fig.15 is a diagram illustrating a method of transmitting mapping cache data according to an exemplary embodiment of the inventive concept.

[0229] Reference Fig.15 , in the computer system 2000 (refer to Fig.11 ) in the initialization operation, the host 2100 may request mapping cache data MCD from the storage device 2200.

[0230] In operation S210 , the host 2100 and the storage device 2200 may perform an operation such as a power-on reset (POR) operation, a hardware reset operation, or an endpoint reset operation.

[0231] In operation S220, the host 2100 and the storage device 2200 may perform hardware initialization and startup. For example, a hardware layer of each of the host 2100 and the storage device 2200 may be initialized and started.

[0232] In operation S230, the host 2100 may request the mapping cache data MCD from the storage device 2200. After startup, the initial state of the storage allocation area 2123 of the host memory 2120 may be a blank state. Therefore, the host 2100 may perform a read request on the storage device 2200 to restore the mapping cache data MCD at the storage allocation area 2123.

[0233] In operation S240 , the memory controller 2210 transmits a read request for mapping data MD stored in a specific area of ​​the nonvolatile memory device 2220 in response to a request of the host 2100 .

[0234] In operation S245 , the nonvolatile memory device 2220 may read the mapping data MD stored in the specific area, and may output the read mapping data MD to the memory controller 2210 .

[0235] In operation S250, the storage controller 2210 may transmit all or part of the mapping data MD read from a specific area of ​​the nonvolatile memory device 2220 as mapping cache data MCD to the host 2100. In this case, the storage controller 2210 may add an identifier or a tag of the relevant area to the mapping cache data MCD, and may transmit the mapping cache data MCD to the host 2100. For example, the storage controller 2210 may mark the mapping cache data MCD to indicate whether it corresponds to any one of the fixed acceleration write buffer 2222, the non-fixed acceleration write buffer 2224, and the user storage area 2226, and may transmit the marked mapping cache data MCD.

[0236] In operation S260 , the host 2100 may load the mapping cache data MCD allocated in the storage allocation area 2123 in the host memory 2120 by using the mapping cache data MCD provided from the storage controller 2210 .

[0237] Fig.16 is a diagram illustrating a method of transmitting mapping cache data according to an exemplary embodiment of the inventive concept.

[0238] Reference Fig.16 , the storage device 2200 according to an exemplary embodiment of the inventive concept may transmit the mapping cache data MCD to the host 2100 through a response in a read operation.

[0239] In operation S310, the host 2100 may transmit a read command to the storage device 2200. A read address, which is a logical block address of target data to be read, may be included in the read command.

[0240] In operation S320, the storage controller 2210 detects whether the read address exists in the mapping cache data MCD (hit). When the read address exists in the mapping cache data MCD (or a hit occurs) (yes), the process proceeds to operation S330. On the contrary, when the read address does not exist in the mapping cache data MCD (or a miss occurs) (no), the process proceeds to operation S322.

[0241] In operation S322 , the memory controller 2210 transmits a read request for mapping data MD stored in a specific area of ​​the nonvolatile memory device 2220 to the nonvolatile memory device 2220 .

[0242] In operation S324 , the nonvolatile memory device 2220 reads the mapping data MD and transmits the read mapping data MD to the memory controller 2210 .

[0243] In operation S330, the memory controller 2210 transmits a read request to the nonvolatile memory device 2220 by using the mapping data MD read from the nonvolatile memory device 2220. For example, the memory controller 2210 may obtain a physical address mapped to a logical block address based on the mapping data MD read from the nonvolatile memory device 2220.

[0244] In operation S335 , the memory controller 2210 receives data from the nonvolatile memory device 2220 using the obtained physical address.

[0245] In operation S340, the storage controller 2210 transmits the read data to the host 2100. For example, the read data may be transmitted to the host 2100 by using DATA IN UPIU of the UFS interface.

[0246] When the read data is completely transmitted, in operation S350, the storage controller 2210 transmits a response including the mapping cache data MCD to the host 2100. For example, in the case of a UFS interface, the response may be provided by using a response UPIU. In this case, the mapping cache data MCD may be transmitted by utilizing a designated field or a reserved field of the response UPIU.

[0247] In operation S360 , the host 2100 may update the mapping cache data MCD stored in the storage allocation area 2123 of the host memory 2120 by using the mapping cache data MCD provided from the storage controller 2210 .

[0248] Fig.17 is a diagram illustrating a method of transmitting mapping cache data MCD according to an exemplary embodiment of the inventive concept.

[0249] Reference Fig.17 In a write operation, the storage device 2200 according to an exemplary embodiment of the inventive concept may load mapping cache data MCD or mapping data MD onto a response to be transmitted to the host 2100 and may transmit the response to the host 2100 .

[0250] In operation S410, the host 2100 may transmit a write command to the storage device 2200. For example, the host 2100 may transmit a command UPIU including the write command to the storage device 2200.

[0251] In operation S420, the storage device 2200 may transmit 'Ready to Transfer UPIU (RTT UPIU)' to the host 2100. The RTT UPIU may include information on a data range in which the storage device 2200 can receive data.

[0252] In operation S430, the host 2100 may transmit a DATA OUT UPIU including write data to the storage device 2200 in response to the RTT UPIU. As operations S420 and S430 are repeatedly performed, write data to be written in the storage device 2200 may be transmitted from the host 2100 to the storage device 2200.

[0253] In operation S440, the memory controller 2210 may program the received write data in the nonvolatile memory device 2220. The write data may be written in at least one of the fixed acceleration write buffer 2222, the non-fixed acceleration write buffer 2224, and the user storage area 2226.

[0254] In operation S450, the memory controller 2210 may transmit a response to the host 2100. The memory controller 2210 may transmit a response UPIU including the mapping cache data MCD or the mapping data MD to the host 2100. In this case, the mapping cache data MCD or the mapping data MD may be transmitted by using a designated field or a reserved field of the response UPIU.

[0255] In operation S460 , the host 2100 may update the mapping cache data MCD stored in the storage allocation area 2123 of the host memory 2120 by using the mapping cache data MCD provided from the memory controller 2210 .

[0256] Fig.18 is a diagram illustrating a method of transmitting mapping cache data MCD according to an exemplary embodiment of the inventive concept.

[0257] Reference Fig.18, the storage device 2200 according to an exemplary embodiment of the inventive concept may transmit the accumulated mapping cache data MCD to the host 2100 in response to a command from the host 2100. For example, such a scheme of transmitting the mapping cache data MCD may be utilized in a case where data is moved in the nonvolatile memory device 220.

[0258] In operation S510, the host 2100 may transmit a write command to the storage device 2200. For example, the host 2100 may transmit a command UPIU including the write command to the storage device 2200.

[0259] In operation S520, the storage device 2200 may transmit the RTT UPIU to the host 2100. The RTT UPIU may include information on a data range in which the storage device 2200 can receive data.

[0260] In operation S530, the host 2100 may transmit a DATA OUT UPIU including write data to the storage device 2200 in response to the RTT UPIU. As operations S520 and S530 are repeatedly performed, write data to be written in the storage device 2200 may be transmitted from the host 2100 to the storage device 2200.

[0261] In operation S540, the memory controller 2210 may program the received write data into the nonvolatile memory device 2220. The write data may be written in at least one of the fixed acceleration write buffer 2222, the non-fixed acceleration write buffer 2224, and the user storage area 2226.

[0262] In operation S550, the storage controller 2210 may detect whether data movement occurs in a write operation. For example, when data movement occurs between the accelerated write buffer and the user storage area 2226 when executing a write request, the storage controller 2210 may store the changed mapping data according to the data movement in the internal buffer 2112 of the storage device 2200. In this case, the number of changes in the physical address mapped to the logical block address LBA is greater than the number of changes in the physical address in a simple write operation. Therefore, the amount of mapping cache data MCD loaded onto the internal buffer 2112 may become larger. The size of this mapping cache data MCD may be so large that it cannot be transmitted through the response UPIU.

[0263] In operation S560, the memory controller 2210 transmits a request to the host memory 2120 to allow the host 2100 to extract the mapping cache data MCD stored in the internal buffer 2112. For example, the memory controller 2210 may request a buffer read command from the host 2100.

[0264] In operation S570, the host 2100 may transmit the buffer read command to the memory controller 2210. In operation S580, the memory controller 2210 transmits the mapping cache data MCD stored in the internal buffer 2112 to the host 2100. In example embodiments, the memory controller 2210 transmits the changed mapping data stored in the internal buffer and an identifier corresponding to the changed mapping data to the host 2100. In addition, in operation S585, the memory controller 2210 may dump the mapping cache data MCD stored in the internal buffer 2112 to a specific area of ​​the nonvolatile memory device 2220.

[0265] In operation S590 , the host 2100 may update the mapping cache data MCD stored in the storage allocation area 2123 of the host memory 2120 by using the mapping cache data MCD provided from the memory controller 2210 .

[0266] Fig.19 It is shown Figure 1 Illustration of the hierarchical structure of a storage system.

[0267] Reference Fig.19 , the storage system 3000 may include a host 3100 and a storage device 3200. The host 3100 may include an application AP-h, a file system FS-h, a device manager DM-h, a UFS application layer UAP-h, a UFS transport protocol layer UTP-h, and a UFS interconnect layer UIC-h.

[0268] The application AP-h may include various application programs, processes, etc. driven at the host 3100. The file system FS-h may be configured to organize and manage various data generated by the application AP-h. In an exemplary embodiment of the inventive concept, the application AP-h or the file system FS-h may be configured to determine a logical block address range to specify a logical block address range for a specific area, such as referring to Figures 11 to 18 Information about the determined logical block address range may be provided to a lower layer (eg, a device manager DM-h or a UFS application layer UAP-h).

[0269] The UFS application layer UAP-h is configured to support various commands between the host 3100 and the storage device 3200. For example, the UFS application layer UAP-h may include an input / output (I / O) stream manager IOSM-h and a UFS command set UCS-h. The I / O stream manager IOSM-h is configured to manage requests from an application AP-h or a file system FS-h.

[0270] In an exemplary embodiment of the inventive concept, the I / O stream manager IOSM-h may be configured to recognize a specific value of input / output from an application AP-h or a file system FS-h. The I / O stream manager IOSM-h may be configured to manage the priority of a request from an application AP-h or a file system FS-h, or to support various functions according to a request from an application AP-h or a file system FS-h. In an exemplary embodiment of the inventive concept, the I / O stream manager IOSM-h may be configured to support an accelerated write function or an accelerated read function.

[0271] In an exemplary embodiment of the inventive concept, a specific application or process specified by the host 3100 or a user of the host 3100 may use accelerated writing or accelerated reading. The I / O stream manager IOSM-h may determine whether to perform accelerated writing or accelerated reading in response to a write or read request made by a specific application or process to the storage device 3200.

[0272] In addition, specific data managed by the file system FS-h can use accelerated writing or accelerated reading. The I / O stream manager IOSM-h can determine whether to perform accelerated writing or accelerated reading in response to a write or read request to the storage device 3200 for specific data (e.g., metadata).

[0273] In addition, the I / O flow manager IOSM-h can guide the movement of data written in the storage device 3200. The I / O flow manager IOSM-h can adjust the reading speed of data written in the storage device 3200 by moving the data to the fixed acceleration write buffer TWB-p, the non-fixed acceleration write buffer TWB-np, or the user storage area UST.

[0274] In an exemplary embodiment of the present invention, the I / O flow manager IOSM-h can determine the area (e.g., a fixed accelerated write buffer TWB-p, a non-fixed accelerated write buffer TWB-np, or a user storage area UST) in which specific data will be stored based on the attributes of the specific data, and can provide information about the determination result (e.g., area information ARI) to the UFS command set UCS-h.

[0275] In an exemplary embodiment of the present invention, the I / O stream manager IOSM-h may determine a logical block address at which specific data is to be stored based on properties of the specific data and a predetermined logical block address range, and may provide information about the determined logical block address range to a UFS command set UCS-h.

[0276] The UFS command set UCS-h may support various command sets supported between the host 3100 and the storage device 3200. In an exemplary embodiment of the inventive concept, the UFS command set UCS-h may include a UFS native command set and a UFS SCSI command set. The UFS command set UCS-h may configure a command to be transmitted to the storage device 3200 according to a request from an application AP-h or a file system FS-h.

[0277] In an exemplary embodiment of the inventive concept, the UFS command set UCS-h may be configured to receive various information (e.g., logical block address, region information, logical block address range, or range region information) from the I / O stream manager IOSM-h, and generate a logical block address range or a range region information according to the reference. Figures 11 to 18 Describes methods to generate various commands.

[0278] The UFS application layer UAP-h may further include a task manager that processes commands for controlling the command queue.

[0279] The device manager DM-h may manage device-level operations and device-level configurations. In an exemplary embodiment of the inventive concept, the device manager DM-h may manage a query request for setting or checking various information of the storage device 3200.

[0280] The UFS transport protocol layer UTP-h can provide services to the upper layer. The UFS transport protocol layer UTP-h can generate commands or information provided from the UFS application layer UAP-h, or query requests provided from the device manager DM-h in the form of UPIU (UFS Protocol Information Unit) packets.

[0281] In an exemplary embodiment of the inventive concept, the UFS transport protocol layer UTP-h and the device manager DM-h can communicate with each other through UDM-SAP (UDM-Service Access Point). The UFS transport protocol layer UTP-h and the UFS application layer UAP-h can communicate with each other through UTP_CMD_SAP or UTP_TM_SAP.

[0282] The UFS interconnect layer UIC-h may manage the connection with the storage device 3200. In an exemplary embodiment of the inventive concept, the UFS interconnect layer UIC-h may include a hardware configuration physically connected to the UFS interconnect layer UIC-d of the storage device 3200, such as MIPI Unipro or MIPI M-PHY. In this way, the host 3100 and the storage device 3200 may establish a communication channel with each other. In an exemplary embodiment of the inventive concept, the UFS interconnect layer UIC-h and the UFS transport protocol layer UTP-h may communicate through UIC-SAP, and the UFS interconnect layer UIC-h and the device manager DM-h may communicate through UIO-SAP.

[0283] The storage device 3200 may include a storage area manager MAM-d, a storage area attribute manager MAPM-d, a device manager DM-d, a UFS application layer UAP-d, a UFS transport protocol layer UTP-d, and a UFS interconnect layer UIC-d. In an exemplary embodiment of the inventive concept, the configuration of the UFS application layer UAP-d, the UFS transport protocol layer UTP-d, and the UFS interconnect layer UIC-d may be similar to the configuration of the UFS application layer UAP-h, the UFS transport protocol layer UTP-h, and the UFS interconnect layer UIC-h of the host 3100, and allow the corresponding layers to logically communicate with each other, and therefore, additional description will be omitted to avoid repetition.

[0284] The storage area attribute manager MAPM-d of the storage device 3200 may specify and manage an area where write data received from the host 3100 is to be stored. For example, as described above, write data received from the host 3100 may be written in a space of at least one of the fixed acceleration write buffer TWB-p, the non-fixed acceleration write buffer TWB-np, and the user storage area UST according to an explicit request or an internal policy of the host 3100. The storage area attribute manager MAPM-d may select a space where write data received from the host 3100 is to be stored based on the above-described various schemes, and may store the write data in the selected space.

[0285] As described above, according to the explicit request or internal policy of the host 3100, the storage area manager MAM-d of the storage device 3200 can control data movement / dump / migration between the fixed acceleration write buffer TWB-p, the non-fixed acceleration write buffer TWB-np and the user storage area UST.

[0286] The above-described hierarchical structure and functions of each of the host 3100 and the storage device 3200 are merely exemplary, and the inventive concept is not limited thereto.

[0287] Fig. 20 is a block diagram illustrating in detail a memory system 4000 according to an exemplary embodiment of the inventive concept.

[0288] Reference Fig.19 and Fig. 20 , the storage system 4000 may include a host 4100 and a storage device 4200. The host 4100 and the storage device 4200 may be as described in Figures 1 to 19 Operate as described.

[0289] The host 4100 may include an application processor 4110 , a random access memory (RAM) 4120 , a modem 4130 , a device driver 4140 , a speaker 4150 , a display 4160 , a touch panel 4170 , a microphone 4180 , and an image sensor 4190 .

[0290] The application processor 4110 may communicate with peripheral devices through the device driver 4140. For example, the application processor 4110 may communicate with a speaker 4150, a display 4160, a touch panel 4170, a microphone 4180, an image sensor 4190, and a storage device 4200 through the device driver 4140.

[0291] The device driver 4140 may include a device manager DM-h, a UFS application layer UAP-h, a UFS transport protocol layer UTP-h, and a UFS interconnect layer UIC-h. For example, the device driver 4140 may be included in the application processor 4110.

[0292] The speaker 4150 and the display 4160 may be user output interfaces that transmit information to the user. The touch panel 4170, the microphone 4180, and the image sensor 4190 may be user input interfaces that receive information from the user.

[0293] In an exemplary embodiment of the inventive concept, the storage device 4200 may be used as a high-capacity storage medium of the host 4100. The storage device 4200 may be an embedded type UFS device or a memory card type UFS device. The memory card type UFS device may be inserted into a UFS slot included in the host 4100 or may be detached from the UFS slot.

[0294] Fig.21 A diagram showing that an exemplary embodiment of the inventive concept is applied to a memory system 1000 .

[0295] Reference Fig. 20 and Fig.21 , the storage system 4000 may provide setting screens through the display 4160. One of the setting screens may provide information of the acceleration mode to the user.

[0296] The storage system 4000 may display a list of first to nth applications APP1 to APPn to which acceleration modes are applicable through the display 4160. In addition, the storage system 4000 may display a switch through the display 4160 that allows the user to adjust the acceleration modes of the first to nth applications APP1 to APPn.

[0297] In operation S610, the user may touch the activation position of the acceleration mode of the third application APP3. The storage system 4000 may sense the user's touch through the touch panel 4170, in other words, an indication of activating the third application APP3. In operation S620, information of the third application APP3 or a process of the third application APP3 may be transmitted to the I / O stream manager IOSM-h.

[0298] When receiving the information of the third application APP3 or the process of the third application APP3, in operation S630, the I / O flow manager IOSM-h can reserve the subsequent read movement operation of the third application APP3 or the process selected thereby. For example, the I / O flow manager IOSM-h can set the movement attribute MA for the data associated with the third application APP3 by querying the request UPIU, and when the read operation associated with the third application APP3 is required, the I / O flow manager IOSM-h can include the movement flag as the movement information MV in the CMD UPIU.

[0299] As another example, when a read operation associated with the third application APP3 is required, the I / O flow manager IOSM-h may include the mobile flag and the mobile attribute MA as the mobile information MV in the CMD UPIU. For example, the I / O flow manager IOSM-h may specify the fixed acceleration write buffer TWB-p or the non-fixed acceleration write buffer TWB-np as the destination information DST of the mobile attribute MA.

[0300] When the data associated with the third application APP3 is moved to the fixed acceleration write buffer TWB-p or the non-fixed acceleration write buffer TWB-np, the operation of reading the data associated with the third application APP3 is accelerated. Therefore, the performance of the third application APP3 can be improved.

[0301] Fig. 22 is a block diagram illustrating a memory card to which a memory system according to an exemplary embodiment of the inventive concept is applied.

[0302] Reference Fig. 22 , a memory card 5200 connected to a host 5100 includes a memory controller 5210 and a nonvolatile memory 5220. The memory controller 5210 is connected to the nonvolatile memory 5220. The memory controller 5210 is configured to access the nonvolatile memory 5220. For example, the memory controller 5210 is configured to control a read operation, a write operation, an erase operation, and a background operation of the nonvolatile memory 5220. The background operation includes operations such as a wear leveling operation and a garbage collection operation.

[0303] For example, the memory controller 5210 may include an SRAM 5212, a CPU 5213, a host interface 5215, an error correction engine (ECC) 5217, and a memory interface 5219. Figures 1 to 18 The memory controller 1210 or the memory controller 2210 described above, the memory controller 5210 provides the mapping data MD or the mapping cache data MCD to the host 5100. The host 5100 may manage the mapping cache data MCD according to priority.

[0304] The memory controller 5210 may communicate with an external device through a host interface 5215. The memory controller 5210 may communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the memory controller 2215 may be configured to communicate with an external device according to at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), eMMC (embedded MMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), and Non-Volatile Memory Express (NVMe).

[0305] The nonvolatile memory 5220 can be implemented using various nonvolatile memory devices such as: electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM) and spin torque magnetic RAM (STT-MRAM).

[0306] For example, the memory controller 5210 and the non-volatile memory 5220 may be integrated in a single semiconductor device. The memory controller 5210 and the non-volatile memory 5220 may be integrated in a single semiconductor device constituting a memory card. For example, the memory controller 5210 and the non-volatile memory 5220 may be integrated in a single semiconductor device to constitute a memory card such as a PC card (or a Personal Computer Memory Card International Association (PCMCIA) card), a Compact Flash card (CF), a Smart Media Card (SM, SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a Universal Flash Memory (UFS).

[0307] Fig.23 is a block diagram illustrating a portable terminal including a storage device according to an exemplary embodiment of the inventive concept.

[0308] Reference Fig.23 , a portable terminal 6000 according to an exemplary embodiment of the inventive concept includes an image processing unit 6100 , a wireless transceiver unit 6200 , an audio processing unit 6300 , an image file generating unit 6400 , an embedded memory 6500 , a user interface 6600 , and a controller 6700 .

[0309] The image processing unit 6100 may include an image sensor 6120 that senses light incident through the lens 6110, an image processor 6130, and a display unit 6140. The wireless transceiver unit 6200 includes an antenna 6210, a transceiver 6220, and a modulator / demodulator (modem) 6230. The audio processing unit 6300 includes an audio processor 6310, a microphone 6320, and a speaker 6330. The image file generation unit 6400 may be a component for generating an image file within the portable terminal 6000. In addition, the embedded memory 6500 may be used as a memory of the portable terminal 6000. In addition, the embedded memory 6500 may include a memory corresponding to the reference image file. Figures 1 to 18 The described storage devices 1200 or 2200 have substantially the same functions and configurations.

[0310] Here, the embedded memory 6500 may transfer the mapping data MD or the mapping cache data MCD to the controller 6700 corresponding to the host. The controller 6700 may manage the mapping cache data MCD according to the priority of each region.

[0311] As is conventional in the field of the present invention, exemplary embodiments are described and shown in the accompanying drawings from the perspective of functional blocks, units and / or modules. Those skilled in the art will recognize that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and associated circuits).

[0312] According to an exemplary embodiment of the present inventive concept, metadata from a storage device using an accelerated write buffer may be provided to a host, and the host may store and manage the provided metadata. Therefore, a storage device in which a memory for managing metadata such as mapping data is insufficient may provide a relatively large amount of metadata, thereby improving a hit rate. Therefore, the performance of the storage device may be improved.

[0313] While the inventive concepts have been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concepts as set forth in the following claims.

Claims

1. A storage system, comprising: A storage device, the storage device comprising a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device; as well as a host configured to access the storage device, wherein the storage device transmits mapping data to the host according to a request of the host, in which the physical address of the nonvolatile storage device is mapped with the logical address provided by the host, The host stores and manages the transmitted mapping data as mapping cache data in a storage allocation area of ​​the host. wherein the mapping cache data is managed according to a priority determined based on a corresponding area of ​​the non-volatile memory device, The non-volatile memory device includes a user storage area and an accelerated write buffer area that can be accessed at a higher speed than the user storage area, and Among them, among the mapping cache data stored in the storage allocation area of ​​the host, the mapping cache data corresponding to the accelerated write buffer area of ​​the non-volatile memory device is managed with a higher priority than the mapping cache data corresponding to the user storage area of ​​the non-volatile memory device.

2. The storage system according to claim 1, wherein: The accelerated write buffer area includes: a first buffer area, first stored data in the first buffer area being prohibited from being moved to the user storage area; and A second buffer area, wherein second stored data in the second buffer area is allowed to be moved to the user storage area.

3. The storage system according to claim 2, wherein: The request from the host comprises an access request, and The storage device transmits first mapping data corresponding to the first buffer area, second mapping data corresponding to the second buffer area, and third mapping data corresponding to the user storage area to the host in response to the access request of the host.

4. The storage system according to claim 3, wherein: The host updates first mapping cache data by using the first mapping data, updates second mapping cache data by using the second mapping data, and updates third mapping cache data by using the third mapping data.

5. The storage system according to claim 4, wherein: An update priority of the first mapping cache data and an update priority of the second mapping cache data are both higher than an update priority of the third mapping cache data.

6. The storage system according to claim 4, wherein: An update priority of the first mapping cache data is higher than an update priority of the second mapping cache data.

7. The storage system according to claim 4, wherein: In a page cache operation, a deletion priority of the third mapping cache data is higher than each of a deletion priority of the first mapping cache data and a deletion priority of the second mapping cache data.

8. The storage system according to claim 7, wherein: In the page cache operation, a deletion priority of the second mapping cache data is higher than a deletion priority of the first mapping cache data.

9. The storage system according to claim 3, wherein: The storage device marks an identifier of a corresponding area on the first mapping data to the third mapping data, and transmits the marked first mapping data to the third mapping data to the host.

10. A method for operating a storage device, comprising: Receive access request from host, Wherein, the storage device comprises a non-volatile memory device, the non-volatile memory device comprises a user storage area and an accelerated write buffer area providing a higher access speed than the user storage area; transmitting mapping data and an identifier to the host, the mapping data being configured according to the execution of the access request, the identifier indicating whether the mapping data corresponds to the accelerated write buffer area or the user storage area; and configuring and managing mapping cache data in a storage allocation area of ​​the host by using the mapping data, Wherein, managing the mapping cache data comprises: determining a priority of the mapping cache data according to the identifier, and when updating or deleting the mapping cache data, updating or deleting the mapping cache data according to the priority, and Among them, among the mapping cache data stored in the storage allocation area of ​​the host, the mapping cache data corresponding to the accelerated write buffer area of ​​the non-volatile memory device is managed with a higher priority than the mapping cache data corresponding to the user storage area of ​​the non-volatile memory device.

11. The operating method according to claim 10, wherein: The access request corresponds to a write request, and The transmitting of the mapping data comprises: loading the mapping data and the identifier on a response data packet in response to the write request, and transmitting the response data packet to the host.

12. The operating method according to claim 10, wherein: The access request corresponds to a write request, and the operation method further includes: When data movement between the accelerated write buffer area and the user storage area occurs when the write request is executed, changed mapping data changed according to the data movement is stored in an internal buffer of the storage device.

13. The operating method according to claim 12, wherein: When the data movement occurs, transmitting the mapping data includes: transmitting a request for a buffer read command to the host; The host transmits the buffer read command to the storage device to request the changed mapping data stored in the internal buffer; and The changed mapping data stored in the internal buffer and an identifier corresponding to the changed mapping data are transmitted to the host.

14. The operating method according to claim 10, wherein: The accelerated write buffer area includes a first buffer area and a second buffer area, first stored data in the first buffer area is prohibited from being moved to the user storage area, second stored data in the second buffer area is allowed to be moved to the user storage area, and Among them, the update priority of the first mapping cache data corresponding to the first buffer area is higher than the update priority of the second mapping cache data corresponding to the second buffer area, and the update priority of the second mapping cache data is higher than the update priority of the third mapping cache data corresponding to the user storage area.

15. The operating method according to claim 14, wherein: The deletion priority of the third mapping cache data is higher than the deletion priority of the second mapping cache data, and the deletion priority of the second mapping cache data is higher than the deletion priority of the first mapping cache data.

16. A storage device for communicating with a host by using a universal flash storage interface, the storage device comprising: A nonvolatile memory device comprising a user storage area and an accelerated write buffer area having a higher access speed than the user storage area; as well as a storage controller configured to transmit mapping data to the host, in which a physical address of the nonvolatile memory device is mapped with a logical address of the host, wherein the storage controller adds an identifier to the mapping data and transmits the mapping data and the identifier to the host, the identifier indicating whether the mapping data corresponds to the user storage area or the accelerated write buffer area, wherein, in the cache management operation of the mapping data, an update priority or a deletion priority of the mapping data is determined based on the identifier, and Wherein, based on the identifier, an update priority or a deletion priority of the mapping data corresponding to the accelerated write buffer area is determined to be higher than an update priority or a deletion priority of the mapping data corresponding to the user storage area.

17. The storage device according to claim 16, wherein: The accelerated write buffer area includes: a first buffer area, first stored data in the first buffer area being prohibited from being moved to the user storage area; and A second buffer area, wherein second stored data in the second buffer area is allowed to be moved to the user storage area.

18. The storage device according to claim 16, wherein: The mapping data or the identifier is loaded on a response data packet in response to an access request provided from the host, and the response data packet is transmitted to the host.

19. The storage device according to claim 16, wherein: The memory controller includes an internal buffer storing the mapping data, and The mapping data or the identifier is transmitted to the host in response to a read command of the host to the internal buffer.

20. The storage device according to claim 16, wherein: The cache management operations are performed at the host.

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