Cross-board homologous clock system

Abstract

The present invention discloses a cross-board homologous clock system. When multiple boards are stacked for use, a single board is defined as a main board, and other single boards are defined as slave boards. The control module of the main board collects the frequency and phase of the clock signal fed back by the slave board, compares the collected frequency with the preset frequency, and controls the clock generation module of the main board to compensate and correct the frequency of the clock signal according to the comparison result. The present invention processes and analyzes the clock frequency and phase detected by each slave board through the control module of the main board, and compensates and corrects the clock frequency and phase of each single board according to the analysis result, thereby solving the cross-board system clock synchronization problem, realizing the coordinated work of multiple FPGAs, realizing cross-board homologous clock configuration and detection, and can flexibly stack and use multiple single boards according to the required number of logic gates. The clock signal is modulated, pulled off, frequency modulated, multiplied, etc., synthesized with low jitter and high-precision clock frequency, and the stability of the system is improved.

Description

Technical Field

[0001] The invention relates to the field of simulation testing, and in particular to a cross-board homologous clock system. Background Art

[0002] With the high integration of ICs, more and more internal resources of FPGAs are needed for verification. However, the resources of a single FPGA are limited and can no longer meet the needs of IC simulation verification. Therefore, there is a strong demand for coordinated work of multiple FPGAs. Due to the limitations of board manufacturing technology, a single board can only hold 4-6 FPGAs at most, which cannot meet the simulation needs of tens of millions or even hundreds of millions of logic gate designs. The system built by interconnecting multiple boards has high requirements for clock synchronization. Summary of the invention

[0003] In order to solve the technical problem that clock frequencies cannot be synchronized in the above-mentioned prior art, the present invention proposes a cross-board homologous clock system.

[0004] The technical solution adopted by the present invention is:

[0005] The present invention proposes a cross-board homologous clock system, comprising: multiple single boards, each of which is provided with: a clock source that outputs a pulse signal, a clock generation module that receives the pulse signal, and a control module that controls the clock generation module to modulate the pulse signal and output the clock signal; when multiple boards are stacked for use, one single board is defined as a main board, and the other single boards are defined as slave boards, the control module of the main board collects the frequency and phase of the clock signal fed back by the control module of each slave board, compares the collected frequency with the preset frequency, and controls the clock generation module of the main board to compensate and correct the frequency of the clock signal according to the comparison result.

[0006] Furthermore, each of the single boards is provided with a clock multiplexing module for dividing the clock signal into multiple clock signals, connecting the input interface of the input end of the clock multiplexing module and multiple DUT units for receiving the clock signal at the output end, and the impedance and length of the connection line connecting each of the DUT units to the clock multiplexing module are the same, so that the delay of the clock signal from the clock multiplexing module to all DUT units on a single board is consistent.

[0007] Furthermore, each of the single boards is also provided with a plurality of output interfaces connected to the output end of the clock multiplexing module, and the impedance and length of the connection line connecting each of the output interfaces to the clock multiplexing module are the same, so that the delay of the clock signal from the clock multiplexing module to all output interfaces on a single board is consistent.

[0008] Furthermore, the single board is provided with a clock detection module for detecting the frequency and phase of the clock signal output by the clock multiplexing module.

[0009] The control module can switch one of the input interface and the clock generation module as the input source of the clock multiplexing module.

[0010] When the single board is in use, the control module switches the clock generation module as the input source of the clock multiplexing module.

[0011] When multiple boards are stacked for use, the output interface of the main board is connected to the input interface of the slave board via a connecting line to output a clock signal. The control module of the main board switches the clock generation module as the input source of the clock multiplexing module, and switches the input interface of the slave board as the input source of the clock multiplexing module.

[0012] Compared with the prior art, the present invention processes and analyzes the clock frequency and phase information detected by each slave board through the control module of the main board, and compensates and corrects the clock frequency and phase of each single board according to the analysis results, thereby solving the problem of cross-board system clock synchronization, realizing the coordinated work of multiple FPGAs, realizing cross-board homologous clock configuration and detection, and can flexibly stack and use multiple single boards according to the required number of logic gates. In addition, a clock generation module is provided on each single board to perform operations such as modulation, deviation, frequency modulation, and frequency multiplication, synthesizing low-jitter, high-precision clock frequency, avoiding the clock source directly outputting the clock signal to the DUT unit, and improving the stability of the system. At the same time, the impedance and length of the connection line connecting each DUT unit to the clock multiplexing module are the same, so that the delay of the clock signal on a single board from the clock multiplexing module to all DUT units is consistent, and the impedance and length of the connection line connecting each output interface to the clock multiplexing module are the same, so that the delay of the clock signal on a single board from the clock multiplexing module to all output interfaces is consistent. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0014] Figure 1 It is a module block diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0015] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0016] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0017] In the description of the present invention, it should be understood that the terms "center", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0018] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0019] The principle and structure of the present invention are described in detail below with reference to the accompanying drawings and embodiments.

[0020] like Figure 1As shown, the present invention proposes a cross-board homologous clock system, including multiple single boards, each of which is provided with a clock multiplexing module, an input interface and multiple DUT units. The clock multiplexing unit can receive a clock signal and divide the clock signal into multiple clock signals. The input input end is connected to the input end of the multiplexing module. Multiple DUT units are simultaneously connected to the output end of the clock multiplexing module. The DUT units are located in the FPGA. Each DUT unit receives one clock signal correspondingly, and the impedance and length of the connection line of each DUT unit connected to the clock multiplexing module are the same, so that the delay of the clock signal on a single board from the clock multiplexing module to all DUT units is consistent. Thereby, the clock signals of all DUT units in the single board are controlled to be homologous and in phase. Each single board is also provided with multiple output interfaces connected to the output end of the clock multiplexing module, and the impedance and length of the connection line of each output interface connected to the clock multiplexing module are the same, so that the delay of the clock signal on a single board from the clock multiplexing module to all output interfaces is consistent. This solves the problem of cross-board system clock synchronization, enables coordinated work of multiple FPGAs, realizes cross-board homologous clock configuration and detection, and can flexibly stack and use multiple boards according to the required number of logic gates.

[0021] Each board is also equipped with: clock source, clock generation module and control module. The clock source is used to output a clock pulse signal with matching level. The clock generation module is connected to the output end of the clock source. The control module modulates, deflects, modulates, multiplies the clock signal input by the clock generation module, and synthesizes a low-jitter, high-precision clock frequency, i.e., a clock signal, to avoid the clock source directly outputting the clock signal to the DUT unit. Clock sources, such as crystal oscillators, are prone to introduce instability problems in the system due to their temperature drift characteristics. Use a clock generation module to improve the stability of the system.

[0022] The single board is also provided with a clock detection module, which receives a clock signal from the output end of the clock multiplexing module and is used to detect the frequency and phase of the clock signal output by the clock multiplexing module. The control module compares the frequency detected by the clock detection module with the preset frequency, and controls the clock generation module to correct the frequency of the clock signal according to the comparison result, thereby adjusting the clock configuration parameters of the clock generation module and outputting an accurate clock signal.

[0023] At the same time, the control module can switch the input interface and the clock generation module as the input source of the clock multiplexing module, so that the single board can be used alone or in a stacked manner.

[0024] When the single board is in use, the control module switches the clock generation module as the input source of the clock multiplexing module, that is, the clock signal is generated by the clock source, and the control module controls the clock generation module to adjust and output it to the clock multiplexing module, and then the multiplexing module is used to transmit the multiple clock signals to the DUT unit respectively.

[0025] When multiple boards are stacked for use, one board is defined as the main board, and the other boards are defined as slave boards. The output interface of the main board is connected to the input interface of the slave board through a connecting line to output the clock signal, that is, the control module of the main board switches the clock generation module as the input source of the clock multiplexing module, and the control module of the slave board switches the input interface as the input source of the clock multiplexing module, so that the clock signal of the main board is generated by the clock source of the main board and output through the output interface. The output interface of the main board is connected to the input interface of the slave board through a connecting line to output the clock signal, and the clock signal of the slave board is input to the clock multiplexing module through its input interface, and then transmitted to each DUT unit on the slave board.

[0026] Each single board has a clock detection module. The detected clock frequency and phase information are processed by the control module and transmitted to the control module of the main board for analysis. The control module of the main board collects the frequency and phase information of the clock signal fed back by the control module of each slave board, compares the collected frequency with the preset frequency, and controls the clock generation module of the main board to compensate and correct the frequency and phase of the clock signal according to the comparison result; that is, when the frequency of the clock signal detected by the slave board is inconsistent with the frequency of the clock signal detected by the main board, the clock generation module of the main board can be controlled to adjust the frequency of the clock signal to make the frequencies of the two clock signals consistent, thereby achieving consistency in the frequency and phase of the clock signal of each single board, and realizing homologous control of the DUT unit when multiple single boards are interconnected.

[0027] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A cross-board homologous clock system, comprising a plurality of single boards, each of which is provided with a clock source for outputting pulse signals and a clock generation module for receiving pulse signals; characterized in that: Each of the single boards is provided with a clock multiplexing module for dividing the clock signal into multiple clock signals, an input interface at the input end of the clock multiplexing module is connected to multiple DUT units at the output end receiving the clock signal, and each single board is also provided with a control module for controlling the clock generation module to modulate the pulse signal to output the clock signal; when multiple boards are stacked for use, one single board is defined as the main board, and the other single boards are defined as slave boards, the control module of the main board switches the clock generation module as the input source of the clock multiplexing module, and the control module of the slave board switches the input interface as the input source of the clock multiplexing module, so that the clock signal of the main board is generated by the clock source of the main board; The control module of the main board collects the frequency and phase of the clock signal fed back by the control module of each slave board, compares the collected frequency with the preset frequency, and controls the clock generation module of the main board to compensate and correct the frequency of the clock signal according to the comparison result.

2. The cross-board homologous clock system according to claim 1, characterized in that: The impedance and length of the connection line connecting each DUT unit to the clock multiplexing module are the same, so that the delay of the clock signal from the clock multiplexing module to all DUT units on a single board is consistent.

3. The cross-board homologous clock system according to claim 2, characterized in that: Each of the single boards is also provided with a plurality of output interfaces connected to the output end of the clock multiplexing module. The impedance and length of the connection line connecting each of the output interfaces to the clock multiplexing module are the same, so that the delay of the clock signal from the clock multiplexing module to all the output interfaces on a single board is consistent.

4. The cross-board homologous clock system according to claim 1, characterized in that: The single board is provided with a clock detection module for detecting the frequency and phase of the clock signal output by the clock multiplexing module.

5. The cross-board homologous clock system according to claim 2, characterized in that: The control module can switch one of the input interface and the clock generation module as the input source of the clock multiplexing module.

6. The cross-board homologous clock system according to claim 5, characterized in that: When the single board is in use, the control module switches the clock generation module as the input source of the clock multiplexing module.

7. The cross-board homologous clock system according to claim 6, characterized in that: When multiple boards are stacked for use, the output interface of the main board is connected to the input interface of the slave board via a connecting line to output a clock signal.

8. The cross-board homologous clock system according to claim 7, characterized in that: The control module of the main board switches the clock generation module as the input source of the clock multiplexing module, and the slave board switches the input interface as the input source of the clock multiplexing module.

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