Display device

Abstract

The present disclosure relates to a display device, comprising: a controller, the controller comprising: a region splitting block, configured to divide input image data into a plurality of partial image data respectively corresponding to a plurality of partial panel regions of a display panel; a plurality of panel region frequency determination blocks, configured to determine a plurality of driving frequencies for a plurality of partial panel regions by respectively analyzing the plurality of partial image data; a non-driving period setting block, configured to classify a plurality of frame periods into driving frame periods and non-driving frame periods based on a maximum driving frequency among the plurality of driving frequencies; and a scanning driver control block, configured to provide a scanning driver input signal to a scanning driver in a driving frame period, and not provide a scanning driver input signal to the scanning driver in a non-driving frame period.

Description

Technical Field

[0001] Aspects of some example embodiments of the inventive concepts relate to display devices. Background Art

[0002] In display devices employed in portable devices such as smart phones, tablet computers, etc., high efficiency or low power consumption is generally desired. For example, in order to reduce the power consumption of the display device, a low-frequency driving technology may be utilized, which drives or refreshes the display panel at a frequency lower than the input frame frequency of the input image data.

[0003] However, in a display device of the related art to which the low-frequency driving technology is applied, when a still image is not displayed in the entire area of ​​the display panel, or when a still image is displayed only in a partial area of ​​the display panel, the entire area of ​​the display panel may be driven at a driving frequency substantially the same as the input frame frequency. Therefore, in this case, the low-frequency driving may not be performed, and the power consumption may not be reduced.

[0004] The above information disclosed in this background section is only for enhancement of understanding of the background technology and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some example embodiments of the inventive concepts relate to a display device, and, for example, to a display device that performs multi-frequency driving (MFD).

[0006] Some example embodiments include a display device capable of reducing power consumption by performing multi-frequency driving (MFD).

[0007] According to some example embodiments, a display device includes: a display panel including a plurality of pixels; a data driver configured to provide a data signal to the plurality of pixels; a scan driver configured to provide a scan signal to the plurality of pixels based on a scan driver input signal; and a controller configured to control the data driver and the scan driver. The controller includes: a region division block configured to divide input image data into a plurality of partial image data corresponding to a plurality of partial panel regions of the display panel, respectively; a plurality of panel region frequency determination blocks configured to determine a plurality of driving frequencies for the plurality of partial panel regions by respectively analyzing the plurality of partial image data; a non-driving period setting block configured to classify a plurality of frame periods into driving frame periods and non-driving frame periods based on a maximum driving frequency among the plurality of driving frequencies; and a scan driver control block configured to provide the scan driver input signal to the scan driver in the driving frame period, and not to provide the scan driver input signal to the scan driver in the non-driving frame period.

[0008] According to some example embodiments, the scan driver control block may not provide a scan start signal and a scan clock signal as the scan driver input signal to the scan driver in the non-driving frame period.

[0009] According to some example embodiments, the controller may further include: a power supply block configured to generate a high gate voltage and a low gate voltage. The scan driver control block may include: a scan driver input signal generating unit configured to generate an initial scan start signal and an initial scan clock signal; and a level shifting unit configured to generate a scan start signal and a scan clock signal as the scan driver input signal by changing the voltage levels of the initial scan start signal and the initial scan clock signal based on at least one of the high gate voltage and the low gate voltage. In the non-driving frame period, the power supply block may change the at least one of the high gate voltage and the low gate voltage to a cut-off level.

[0010] According to some example embodiments, the scan driver control block may provide a scan output mask signal to the scan driver in a partial period of the driving frame period allocated to a portion of the multiple partial panel areas, so that the scan signal is not provided to the portion of the multiple partial panel areas within the driving frame period.

[0011] According to some example embodiments, the scan driver may include: a plurality of stages configured to generate the scan signals for the plurality of scan lines included in the display panel; and a plurality of logic gates respectively connected to the plurality of stages and configured to selectively output the scan signals generated by the plurality of stages in response to the scan output mask signals, respectively.

[0012] According to some example embodiments, the display device may be a foldable display device. The plurality of partial panel areas may include a first partial panel area located in a first direction from a folding line of the foldable display device and a second partial panel area located in a second direction opposite to the first direction from the folding line. The area splitting block may divide the input image data into first partial image data for the first partial panel area and second partial image data for the second partial panel area as the plurality of partial image data.

[0013] According to some example embodiments, each of the plurality of panel area frequency determination blocks may include: a still image detection unit configured to receive corresponding partial image data among the plurality of partial image data at an input frame rate and determine whether the corresponding partial image data represents a still image; and a driving frequency determination unit configured to determine, when the corresponding partial image data does not represent the still image, a corresponding driving frequency among the plurality of driving frequencies as the input frame rate, and to determine, when the corresponding partial image data represents the still image, the corresponding driving frequency as a frequency lower than the input frame rate.

[0014] According to some example embodiments, each of the plurality of panel area frequency decision blocks may further include: a representative value memory configured to store a representative value of the corresponding partial image data in a previous frame period. The still image detection unit may calculate a representative value of the corresponding partial image data in a current frame period, and may determine whether the corresponding partial image data represents the still image by comparing the calculated representative value of the corresponding partial image data with the representative value of the corresponding partial image data stored in the representative value memory.

[0015] According to some example embodiments, each of the plurality of panel area frequency decision blocks may further include: a flicker lookup table configured to store flicker values ​​corresponding to gray levels of respective image data. When the corresponding portion of image data represents the still image, the driving frequency decision unit may determine the flicker value corresponding to the gray level of the corresponding portion of image data by using the flicker lookup table, and may determine the corresponding driving frequency according to the determined flicker value.

[0016] According to some example embodiments, each of the multiple panel area frequency decision blocks may also include: a driving frequency mixing unit configured to gradually change a corresponding one of the multiple driving frequencies used for a corresponding partial panel area among the multiple partial panel areas from the previous driving frequency used for the partial panel area to the corresponding driving frequency determined by the driving frequency decision unit when the corresponding driving frequency determined by the driving frequency decision unit changes from a previous driving frequency.

[0017] According to some example embodiments, each of the plurality of pixels may include: a driving transistor configured to generate a driving current; a switching transistor configured to transmit a corresponding one of the data signals to a source of the driving transistor; a compensation transistor configured to diode-connect the driving transistor; a storage capacitor configured to store the corresponding one of the data signals transmitted through the switching transistor and the diode-connected driving transistor; a first initialization transistor configured to provide an initialization voltage to the storage capacitor and a gate of the driving transistor; a first emission control transistor configured to connect a line of a power supply voltage to the source of the driving transistor; a second emission control transistor configured to connect a drain of the driving transistor to an organic light emitting diode; a second initialization transistor configured to provide the initialization voltage to the organic light emitting diode; and the organic light emitting diode configured to emit light based on the driving current. At least the first one of the driving transistor, the switching transistor, the compensation transistor, the first initialization transistor, the first emission control transistor, the second emission control transistor and the second initialization transistor can be implemented by a PMOS transistor, and at least the second one of the driving transistor, the switching transistor, the compensation transistor, the first initialization transistor, the first emission control transistor, the second emission control transistor and the second initialization transistor can be implemented by an NMOS transistor.

[0018] According to some example embodiments, the non-driving period setting block may set a partial period of the driving frame period as a non-driving partial frame period based on a driving frequency lower than the maximum driving frequency among the multiple driving frequencies, and the scan driver control block may not provide the scan driver input signal to the scan driver in the non-driving frame period and the non-driving partial frame period.

[0019] According to some example embodiments, the controller may further include: a power supply block configured to generate a high gate voltage and a low gate voltage. The scan driver control block may include: a scan driver input signal generating unit configured to generate an initial scan start signal and an initial scan clock signal; and a level shifting unit configured to generate a scan start signal and a scan clock signal as the scan driver input signal by changing the voltage levels of the initial scan start signal and the initial scan clock signal based on at least one of the high gate voltage and the low gate voltage. In the non-driving frame period and the non-driving partial frame period, the power supply block may change the at least one of the high gate voltage and the low gate voltage to a cut-off level.

[0020] According to some example embodiments, a display device includes: a display panel including a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a scan driver configured to provide scan signals to the plurality of pixels based on a scan driver input signal; and a controller configured to control the data driver and the scan driver. The controller includes: a region splitting and still image detection block, configured to receive input image data at an input frame rate, and configured to divide the input image data into motion image portion data representing a motion image and still image portion data representing a still image; a region splitting and panel area frequency determination block, configured to determine a first driving frequency for a first partial panel area of ​​the display panel corresponding to the motion image portion data as the input frame rate, and determine a plurality of second driving frequencies for a plurality of second partial panel areas of the display panel by analyzing the still image portion data; a non-driving period setting block, configured to classify a plurality of frame periods into driving frame periods and non-driving frame periods based on the maximum driving frequency among the first driving frequency and the plurality of second driving frequencies; and a scan driver control block, configured to provide the scan driver input signal to the scan driver in the driving frame period, and not provide the scan driver input signal to the scan driver in the non-driving frame period.

[0021] According to some example embodiments, the scan driver control block may not provide a scan start signal and a scan clock signal as the scan driver input signal to the scan driver in the non-driving frame period.

[0022] According to some example embodiments, the controller may further include: a power supply block configured to generate a high gate voltage and a low gate voltage. The scan driver control block may include: a scan driver input signal generating unit configured to generate an initial scan start signal and an initial scan clock signal; and a level shifting unit configured to generate a scan start signal and a scan clock signal as the scan driver input signal by changing the voltage levels of the initial scan start signal and the initial scan clock signal based on at least one of the high gate voltage and the low gate voltage. In the non-driving frame period, the power supply block may change the at least one of the high gate voltage and the low gate voltage to a cut-off level.

[0023] According to some example embodiments, the region splitting and still image detection block may include: a plurality of representative value memories configured to store a plurality of representative values ​​of a plurality of input partial image data in a previous frame period; and a region still image detection unit configured to: receive the input image data in a current frame period; divide the input image data in the current frame period into the plurality of input partial image data; calculate a plurality of representative values ​​of the plurality of input partial image data in the current frame period; determine whether each of the plurality of input partial image data represents the moving image or the still image by comparing the calculated plurality of representative values ​​with the plurality of representative values ​​stored in the plurality of representative value memories; output the input partial image data representing the moving image among the plurality of input partial image data as the moving image partial data; and output the input partial image data representing the still image among the plurality of input partial image data as the still image partial data.

[0024] According to some example embodiments, the zone splitting and panel zone frequency determination block may include: a flicker lookup table configured to store flicker values ​​corresponding to the grayscale levels of each image data; and a zone driving frequency determination unit configured to: determine the first driving frequency for the first partial panel zone corresponding to the motion image portion data as the input frame rate; divide the still image portion data into a plurality of segmented data for a plurality of segments; determine a plurality of segmented flicker values ​​corresponding to the grayscale levels of the plurality of segmented data by using the flicker lookup table; determine the plurality of second partial panel zones by grouping the plurality of segments based on the plurality of segmented driving frequencies corresponding to the plurality of segmented flicker values; and determine the plurality of second driving frequencies for the plurality of second partial panel zones respectively based on the plurality of segmented driving frequencies of the plurality of second partial panel zones.

[0025] According to some example embodiments, the non-driving period setting block may set a partial period of the driving frame period as a non-driving partial frame period based on the first driving frequency and a driving frequency lower than the maximum driving frequency among the multiple second driving frequencies, and the scan driver control block may not provide the scan driver input signal to the scan driver in the non-driving frame period and the non-driving partial frame period.

[0026] According to some example embodiments, the controller may further include: a power supply block configured to generate a high gate voltage and a low gate voltage. The scan driver control block may include: a scan driver input signal generating unit configured to generate an initial scan start signal and an initial scan clock signal; and a level shifting unit configured to generate a scan start signal and a scan clock signal as the scan driver input signal by changing the voltage levels of the initial scan start signal and the initial scan clock signal based on at least one of the high gate voltage and the low gate voltage. In the non-driving frame period and the non-driving partial frame period, the power supply block may change the at least one of the high gate voltage and the low gate voltage to a cut-off level.

[0027] As described above, the display device according to some example embodiments may set a non-driving frame period based on the maximum driving frequency among the plurality of driving frequencies for the plurality of partial panel areas, and may not provide a scan driver input signal to the scan driver during the non-driving frame period. Therefore, the display device according to some example embodiments may further reduce power consumption when performing the multi-frequency driving (MFD). BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a block diagram illustrating a display device according to some example embodiments.

[0030] Figure 2 is a circuit diagram illustrating an example of a pixel included in a display device according to some example embodiments.

[0031] Figure 3A It shows that Figure 1 The display device is an example of an inward-folding display device, and Figure 3B It shows that Figure 1 The display device is a diagram of an example of an outward-folding display device.

[0032] Figure 4 is a block diagram illustrating an example of a frequency decision block for each panel area included in a display device according to some example embodiments.

[0033] Figure 5 It is shown Figure 4 0047] Figure 2 is a diagram of an example of a flicker lookup table (LUT) shown in FIG.

[0034] Figure 6 is a block diagram illustrating an example of a scan driver control block included in a display device according to some example embodiments.

[0035] Figure 7 is a block diagram illustrating an example of a scan driver included in a display device according to some example embodiments.

[0036] Figure 8 is a diagram for describing an example of first driving frequencies and second driving frequencies determined for a first partial panel area and a second partial panel area of ​​a display panel.

[0037] Fig. 9 is a timing diagram for describing an example of an operation of a display device according to some example embodiments.

[0038] Fig.10 is a block diagram illustrating a display device according to some example embodiments.

[0039] Fig.11 It is shown that the Fig.10 A block diagram of an example of a scan driver in a display device.

[0040] Fig.12 is a timing diagram for describing an example of an operation of a display device according to some example embodiments.

[0041] Fig.13 is a block diagram illustrating a display device according to some example embodiments.

[0042] Fig.14 is a diagram for describing an example of first to fourth driving frequencies determined with respect to first to fourth partial panel areas of a display panel.

[0043] Fig.15 is a timing diagram for describing an example of an operation of a display device according to some example embodiments.

[0044] Fig.16 is a block diagram illustrating a display device according to some example embodiments.

[0045] Fig.17 is a block diagram illustrating an example of a region splitting and still image detection block included in a display device according to some example embodiments.

[0046] Fig.18 is a diagram for describing an example of operations of a region splitting and still image detection block included in a display device according to some example embodiments.

[0047] Fig.19 is a block diagram illustrating an example of a zone splitting and panel zone frequency decision block included in a display device according to some example embodiments.

[0048] Fig. 20is a diagram for describing an example of an operation of a zone splitting and panel zone frequency decision block included in a display device according to some example embodiments.

[0049] Fig.21 is a diagram for describing an example of an operation of a display device according to some example embodiments.

[0050] Fig. 22 is a block diagram illustrating a display device according to some example embodiments.

[0051] Fig.23 is a diagram for describing an example of an operation of a display device according to some example embodiments.

[0052] Fig.24 An electronic device including the display device according to some example embodiments. DETAILED DESCRIPTION

[0053] Hereinafter, aspects of some example embodiments of the inventive concept will be explained in more detail with reference to the accompanying drawings.

[0054] Figure 1 is a block diagram illustrating a display device according to some example embodiments, Figure 2 is a circuit diagram illustrating an example of a pixel included in a display device according to some example embodiments, Figure 3A It shows that Figure 1 The display device is an example of an inward-folding display device. Figure 3B It shows that Figure 1 The display device is an example of an outward folding display device. Figure 4 is a block diagram illustrating an example of a frequency decision block for each panel area included in a display device according to some example embodiments, Figure 5 It is shown Figure 4 An example of a flicker lookup table (LUT) is shown in FIG. Figure 6 is a block diagram illustrating an example of a scan driver control block included in a display device according to some example embodiments, Figure 7 is a block diagram illustrating an example of a scan driver included in a display device according to some example embodiments, Figure 8 is a diagram for describing an example of a first driving frequency and a second driving frequency determined for a first partial panel area and a second partial panel area of ​​a display panel, and Fig. 9 is a timing diagram for describing an example of an operation of a display device according to some example embodiments.

[0055] Reference Figure 1According to some example embodiments, the display device 100 may include: a display panel 110 including a plurality of pixels PX; a data driver 120 providing a data signal DS to the plurality of pixels PX; a scan driver 130 providing a scan signal SS to the plurality of pixels PX based on a scan driver input signal SDIS; and a controller 140 controlling the data driver 120 and the scan driver 130.

[0056] The display panel 110 may include a plurality of data lines, a plurality of scan lines, and a plurality of pixels PX connected to the plurality of data lines and the plurality of scan lines. In some example embodiments, each pixel PX may include at least one capacitor, at least two transistors, and an organic light emitting diode (OLED), and the display panel 110 may be an OLED display panel. In addition, in some example embodiments, each pixel PX may be a mixed oxide polycrystalline (HOP) pixel suitable for low-frequency driving capable of reducing power consumption. In the HOP pixel, at least one first transistor may be implemented by a low temperature polycrystalline silicon (LTPS) PMOS transistor, and at least one second transistor may be implemented by an oxide NMOS transistor.

[0057] For example, Figure 2 As shown in FIG. 1 , each pixel PX may include: a driving transistor T1 that generates a driving current; a switching transistor T2 that transmits a data signal DS from the data driver 120 to the source of the driving transistor T1 in response to a first scanning signal SSP from the scanning driver 130; a compensation transistor T3 that is diode-connected to the driving transistor T1 in response to a second scanning signal SSN from the scanning driver 130; a storage capacitor CST that stores the data signal DS transmitted through the switching transistor T2 and the diode-connected driving transistor T1; and a first initialization transistor T4 that provides an initialization signal to the storage capacitor CST and the gate of the driving transistor T1 in response to a first initialization signal SI from the scanning driver 130. voltage VINIT; a first emission control transistor T5, connecting the line of the high power supply voltage ELVDD to the source of the driving transistor T1 in response to the emission control signal SEM from the emission driver; a second emission control transistor T6, connecting the drain of the driving transistor T1 to the organic light emitting diode EL in response to the emission control signal SEM from the emission driver; a second initialization transistor (or bypass transistor) T7, providing the initialization voltage VINIT to the organic light emitting diode EL in response to a second initialization signal (or bypass signal) SB from the scan driver 130; and the organic light emitting diode EL, emitting light based on a driving current from the line of the high power supply voltage ELVDD to the line of the low power supply voltage ELVSS.

[0058] At least the first one of the driving transistor T1, the switching transistor T2, the compensating transistor T3, the first initialization transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second initialization transistor T7 may be implemented by a PMOS transistor, and at least the second one of the driving transistor T1, the switching transistor T2, the compensating transistor T3, the first initialization transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second initialization transistor T7 may be implemented by an NMOS transistor. For example, Figure 2 As shown in , the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 can be implemented by NMOS transistors, and the other transistors T1, T2, T5, and T6 can be implemented by PMOS transistors. In this case, the second scan signal SSN applied to the compensation transistor T3, the first initialization signal SI applied to the first initialization transistor T4, and the second initialization signal SB applied to the second initialization transistor T7 can be active high signals suitable for NMOS transistors. In this case, because the transistors T3 and T4 directly connected to the storage capacitor CST and the second initialization transistor T7 directly connected to the organic light emitting diode EL are implemented by NMOS transistors, the leakage current from the parasitic capacitor of the storage capacitor CST and / or the organic light emitting diode EL can be reduced, and thus the pixel PX can be suitable for low-frequency driving. Although Figure 2 An example is shown in which the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 are implemented by NMOS transistors, but the configuration of each pixel PX according to some example embodiments is not limited to Figure 2 In other example embodiments, the display panel 110 may be a liquid crystal display (LCD) panel or the like.

[0059] The data driver 120 may generate a data signal DS based on the output image data ODAT and the data control signal DCTRL received from the controller 140, and may provide the data signal DS to a plurality of pixels PX through a plurality of data lines. In some example embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In some example embodiments, the data driver 120 and the controller 140 may be implemented by a single integrated circuit, and the integrated circuit may be referred to as a timing controller embedded data driver (TED). In other example embodiments, the data driver 120 and the controller 140 may be implemented by separate integrated circuits.

[0060] The scan driver 130 may provide a scan signal SS to a plurality of pixels PX through a plurality of scan lines based on a scan driver input signal SDIS received from the controller 140. In some example embodiments, the scan driver 130 may sequentially provide the scan signal SS to the plurality of pixels PX on a row-by-row basis. Furthermore, in some example embodiments, the scan driver input signal SDIS may include, but is not limited to, a scan start signal FLM and a scan clock signal SCLK. In some example embodiments, the scan driver 130 may further receive a scan output mask signal SOMS from the controller 140. In some example embodiments, the scan driver 130 may be integrated or formed in a peripheral portion of the display panel 110. In other example embodiments, the scan driver 130 may be implemented by one or more integrated circuits.

[0061] The controller (e.g., timing controller (TCON)) 140 may receive input image data IDAT and a control signal CTRL from an external host (e.g., a graphics processing unit (GPU) or a graphics card). In some example embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 140 may generate output image data ODAT, a data control signal DCTRL, and a scan driver input signal SDIS based on the input image data IDAT and the control signal CTRL. The controller 140 may control the operation of the data driver 120 by providing the output image data ODAT and the data control signal DCTRL to the data driver 120, and may control the operation of the scan driver 130 by providing the scan driver input signal SDIS to the scan driver 130.

[0062] The display device 100 according to some example embodiments may perform a multi-frequency driving (MFD) that drives a plurality of partial panel zones (or regions) PPZ1 and PPZ2 of the display panel 110 at a plurality of different driving frequencies DF1 and DF2. In order to reduce power consumption, the display device 100 according to some example embodiments may set a non-driving frame period based on the maximum driving frequency among the plurality of driving frequencies DF1 and DF2, and may not provide the scan driver input signal SDIS to the scan driver 130 during the non-driving frame period. Here, not providing the scan driver input signal SDIS to the scan driver 130 may mean not outputting the scan driver input signal SDIS to the scan driver 130, or outputting the scan driver input signal SDIS having a cut-off level (e.g., a ground voltage level or a voltage level close to the ground voltage level) to the scan driver 130. To perform these operations, in some example embodiments, the controller 140 may include a zone splitting block (ZSB) 150, a first panel zone frequency decision block (PZFDB1) 162 and a second panel zone frequency decision block (PZFDB2) 164, a non-driving period setting block (NDPSB) 170, a scan driver control block (SDCB) 180, and a power supply block 190.

[0063] The region splitting block 150 may divide or split the input image data IDAT into first partial image data PDAT1 and second partial image data PDAT2 respectively corresponding to the first partial panel zone PPZ1 and the second partial panel zone PPZ2 of the display panel 110. For example, the region splitting block 150 may divide the input image data IDAT into first partial image data PDAT1 and second partial image data PDAT2, so that each of the first partial panel zone PPZ1 and the second partial panel zone PPZ2 corresponding to the first partial image data PDAT1 and the second partial image data PDAT2 may include one or more scan lines, or one or more pixel rows connected to one or more scan lines, or so that the display panel 110 may be divided (or split) along the data line direction.

[0064] In some example embodiments, the display device 100 may be a foldable display device, and the region splitting block 150 may divide the input image data IDAT into first partial image data PDAT1 and second partial image data PDAT2, so that a boundary between a first partial panel zone PPZ1 and a second partial panel zone PPZ2 corresponding to the first partial image data PDAT1 and the second partial image data PDAT2 may correspond to a folding line, which is a portion in which the foldable display device is folded. In an example, as Figure 3AAs shown in , the display device 100 may be an inward-folding display device 100a including an inward-folding display panel 110a, the inward-folding display panel 110a is folded so that the first partial panel area PPZ1a and the second partial panel area PPZ2a face each other, the first partial panel area PPZ1a may be located in a first direction from the folding line FL of the inward-folding display device 100a, and the second partial panel area PPZ2a may be located in a second direction opposite to the first direction from the folding line FL of the inward-folding display device 100a. In another example, as Figure 3B As shown in , the display device 100 may be an outward-folding display device 100b including an outward-folding display panel 110b, the outward-folding display panel 110b is folded so that one of the first partial panel area PPZ1b and the second partial panel area PPZ2b is located on the front side, and the other of the first partial panel area PPZ1b and the second partial panel area PPZ2b is located on the rear side, the first partial panel area PPZ1b may be located in a first direction from a folding line FL of the outward-folding display device 100b, and the second partial panel area PPZ2b may be located in a second direction opposite to the first direction from the folding line FL of the outward-folding display device 100b. Although Figure 3A and Figure 3B An example is shown in which the display device 100 may be a foldable display device 100a and 100b, but in some example embodiments, the display device 100 may be any flexible display device such as a curved display device, a bent display device, a rollable display device, and a stretchable display device. In other example embodiments, the display device 100 may be a flat (e.g., rigid) display device. The first partial panel area PPZ1a and the first partial panel area PPZ1b may correspond to Figure 1 The first partial panel area PPZ1 in the embodiment, and the second partial panel area PPZ2a and the second partial panel area PPZ2b may correspond to Figure 1 The second part of the panel area PPZ2.

[0065] The zone splitting block 150 may provide the first partial image data PDAT1 for the first partial panel zone PPZ1 to the first panel zone frequency decision block 162 , and may provide the second partial image data PDAT2 for the second partial panel zone PPZ2 to the second panel zone frequency decision block 164 .

[0066] The first panel zone frequency decision block 162 may determine the first driving frequency DF1 for the first partial panel zone PPZ1 by analyzing the first partial image data PDAT1, and the second panel zone frequency decision block 164 may determine the second driving frequency DF2 for the second partial panel zone PPZ2 by analyzing the second partial image data PDAT2. In order to perform these operations, as shown in FIG. Figure 4As shown in , each of the first panel area frequency decision block 162 and the second panel area frequency decision block 164 may include a still image detection unit 210 and a driving frequency decision unit 230. In some example embodiments, each of the first panel area frequency decision block 162 and the second panel area frequency decision block 164 may also include a representative value memory 220, a flicker lookup table (LUT) 240, and a driving frequency mixing unit 260. The first panel area frequency decision block 162 and the second panel area frequency decision block 164 may have substantially the same configuration and operation, and therefore the configuration and operation of the first panel area frequency decision block 162 will be described below.

[0067] The still image detection unit 210 can detect the image at an input frame rate IFF (see Figure 1 ) receives the first partial image data PDAT1 and can determine whether the first partial image data PDAT1 represents a still image.

[0068] In some example embodiments, the still image detection unit 210 may determine whether the first partial image data PDAT1 represents a still image by comparing the first partial image data PDAT1 in the previous frame period with the first partial image data PDAT1 in the current frame period using the representative value memory 220. For example, the representative value memory 220 may store a representative value (e.g., an average value or a checksum) of the first partial image data PDAT1 in the previous frame period. The still image detection unit 210 may calculate a representative value of the first partial image data PDAT1 in the current frame period, and may determine whether the first partial image data PDAT1 represents a still image by comparing the calculated representative value of the first partial image data PDAT1 with the representative value of the first partial image data PDAT1 stored in the representative value memory 220. The still image detection unit 210 may store the calculated representative value of the first partial image data PDAT1 in the current frame period in the representative value memory 220 to be used in the next frame period. In some example embodiments, a single representative value memory 220 may be shared by the first panel area frequency decision block 162 and the second panel area frequency decision block 164 , but the number of representative value memories 220 may not be limited to one.

[0069] The still image detection unit 210 may output the first partial image data PDAT1 to the driving frequency decision unit 230 , and may further output a still image flag signal SIFS representing whether the first partial image data PDAT1 represents a still image.

[0070] The driving frequency determination unit 230 may determine the first driving frequency DF1 for the corresponding first partial panel zone (or area) PPZ1 according to whether the first partial image data PDAT1 represents a still image. In some example embodiments, when the first partial image data PDAT1 does not represent a still image (or represents a moving image), the driving frequency determination unit 230 may determine the first driving frequency DF1 for the first partial panel zone PPZ1 to be the input frame rate IFF, and when the first partial image data PDAT1 represents a still image, the driving frequency determination unit 230 may determine the first driving frequency DF1 for the first partial panel zone PPZ1 to be a frequency lower than the input frame rate IFF.

[0071] In some example embodiments, when the first partial image data PDAT1 represents a still image, the driving frequency decision unit 230 may determine a flicker value according to the grayscale (or brightness) of the first partial image data PDAT1 by using a flicker lookup table (LUT) 240, and may determine the first driving frequency DF1 for the first partial panel zone PPZ1 according to the flicker value. Figure 5 As shown in , the flicker LUT 240 may store flicker values ​​corresponding to respective image data gray levels (e.g., 256 gray levels from 0 gray level to 255 gray level). Here, the flicker value may represent the level of flicker perceived by the user. In the example, Figure 5 As shown in FIG. 1 , the flicker LUT 240 may store one flicker value for every four gray levels, but the number of flicker values ​​stored in the flicker LUT 240 may not be limited to Figure 5For example, in a case where the first partial image data PDAT1 represents gray levels 0 to 7, the driving frequency decision unit 230 may determine that the flicker value of the first partial image data PDAT1 is 0 by using the flicker LUT 240, and may determine that the first driving frequency DF1 for the first partial panel zone PPZ1 is approximately 1 Hz based on the flicker value 0. In another example, in a case where the first partial image data PDAT1 represents gray levels 20 to 23, the driving frequency decision unit 230 may determine that the flicker value of the first partial image data PDAT1 is 160 by using the flicker LUT 240, and may determine that the first driving frequency DF1 for the first partial panel zone PPZ1 is approximately 30 Hz based on the flicker value 160. According to some example embodiments, determining the flicker value and the driving frequency may be performed on a pixel-by-pixel basis, a segment-by-segment basis, or a partial panel zone basis. For example, the first partial image data PDAT1 may be divided into a plurality of segment data for a plurality of segments, a flicker value for each segment may be determined, a driving frequency for each segment may be determined, and a first driving frequency DF1 for the first partial panel zone PPZ1 may be determined to be a maximum one of the determined driving frequencies for each segment. In some example embodiments, the flicker LUT 240 may be shared by the first panel zone frequency decision block 162 and the second panel zone frequency decision block 164, but the number of flicker LUTs 240 may not be limited to one.

[0072] The driving frequency decision unit 230 may output the first partial image data PDAT1 , and may further output a driving frequency signal DFS representing a first driving frequency DF1 for the first partial panel zone PPZ1 .

[0073] When the first driving frequency DF1 determined by the driving frequency decision unit 230 is changed from the previous first driving frequency DF1, the driving frequency mixing unit 250 may gradually change the first driving frequency DF1 from the previous first driving frequency DF1 to the newly determined first driving frequency DF1. For example, in a case where the previous first driving frequency DF1 for the first partial panel zone PPZ1 is about 120 Hz and the newly determined first driving frequency DF1 for the first partial panel zone PPZ1 is about 15 Hz, the driving frequency mixing unit 250 may gradually change the first driving frequency DF1 for the first partial panel zone PPZ1 from about 120 Hz to about 60 Hz, about 30 Hz, and about 30 Hz over a period of time (e.g., a set or predetermined period of time).

[0074] Refer again Figure 1, the non-driving period setting block 170 may determine the maximum driving frequency among the first driving frequency DF1 and the second driving frequency DF2 for the first partial panel zone PPZ1 and the second partial panel zone PPZ2 determined by the first panel zone frequency decision block 162 and the second panel zone frequency decision block 164, and may set the non-driving frame period based on the maximum driving frequency. In some example embodiments, the non-driving period setting block 170 may classify a plurality of frame periods into driving frame periods and non-driving frame periods based on the maximum driving frequency of the first driving frequency DF1 and the second driving frequency DF2. For example, in a case where the input frame rate IFF is approximately 120 Hz and the maximum driving frequency of the first driving frequency DF1 and the second driving frequency DF2 is approximately 30 Hz, based on the maximum driving frequency of approximately 30 Hz, the non-driving period setting block 170 may classify one of the four frame periods as a driving frame period, and may classify three of the four frame periods as non-driving frame periods.

[0075] The scan driver control block 180 may provide the scan driver input signal SDIS to the scan driver 130 in the driving frame period, and may not provide the scan driver input signal SDIS to the scan driver 130 in the non-driving frame period. In some example embodiments, the scan driver input signal SDIS provided from the scan driver control block 180 to the scan driver 130 may include a scan start signal FLM and a scan clock signal SCLK. Therefore, the scan driver control block 180 may not provide the scan start signal FLM and the scan clock signal SCLK as the scan driver input signal SDIS to the scan driver 130 in the non-driving frame period. In some example embodiments, the scan clock signal SCLK provided from the scan driver control block 180 to the scan driver 130 may include, but is not limited to, a plurality of clock signals having different phases.

[0076] In some example embodiments, in order to enable the scan driver control block 180 to not provide the scan start signal FLM and the scan clock signal SCLK to the scan driver 130 in a non-driving frame period, the controller 140 may control the power supply block 190 so that at least one of the high gate voltage VGH or the low gate voltage VGL is not output in the non-driving frame period, or has a cutoff level (for example, a ground voltage level or a voltage level close to the ground voltage level) in the non-driving frame period.

[0077] For example, Figure 6As shown in , the scan driver control block 180 may include a scan driver input signal generating unit 182 and a level shifting unit 184. The scan driver input signal generating unit 182 may generate an initial scan start signal IFLM and an initial scan clock signal ISCLK. The power supply block 190 may provide the level shifting unit 184 with a high gate voltage VGH and / or a low gate voltage VGL. In some example embodiments, the power supply block 190 may further provide the scan driver 130 with a high gate voltage VGH and / or a low gate voltage VGL. The level shifting unit 184 may generate a scan start signal FLM and a scan clock signal SCLK as the scan driver input signal SDIS by changing the voltage levels of the initial scan start signal IFLM and the initial scan clock signal ISCLK based on at least one of the high gate voltage VGH or the low gate voltage VGL generated by the power supply block 190. In a non-driving frame period, the power supply block 190 may change the at least one of the high gate voltage VGH or the low gate voltage VGL to a cut-off level. When receiving the high gate voltage VGH and / or the low gate voltage VGL having a cut-off level, the level shift unit 184 may generate a scan start signal FLM and a scan clock signal SCLK having a low level, and the scan driver control block 180 may output the scan start signal FLM and the scan clock signal SCLK having a low level to the scan driver 130. Therefore, in the non-driving frame period, because the high gate voltage VGH and / or the low gate voltage VGL have a cut-off level, and the scan start signal FLM and the scan clock signal SCLK provided to the scan driver 130 also have a cut-off level, the power consumption of the display device 100 may be further reduced in the non-driving frame period.

[0078] In some example embodiments, the scan driver control block 180 may provide the scan driver 130 with a scan output masking signal SOMS in a partial period of a driving frame period allocated to a portion of the plurality of partial panel areas PPZ1 and PPZ2, so that the plurality of partial panel areas PPZ1 and PPZ2 may be driven at a plurality of different driving frequencies DF1 and DF2, or so that the scan signal SS is not provided to a portion of the plurality of partial panel areas PPZ1 and PPZ2 (e.g., a partial panel area driven at a frequency lower than a maximum driving frequency among the plurality of driving frequencies DF1 and DF2) in at least one driving frame period. In some example embodiments, the operation of selectively providing the scan signal SS may be referred to as a masking operation. For example, Figure 6As shown in , the scan driver input signal generation unit 182 can further generate an initial scan output mask signal ISOMS, the level shift unit 184 can further generate a scan output mask signal SOMS through the voltage level of the initial scan output mask signal ISOMS based on the high gate voltage VGH and / or the low gate voltage VGL, and the scan driver control block 180 can output the scan output mask signal SOMS to the scan driver 130.

[0079] In order to perform a masking operation in response to the scan output masking signal SOMS, as shown in FIG. Figure 7 As shown in , the scan driver 130 may include a plurality of stages 131, 132, 133, 134, ... and a plurality of logic gates 136, 137, 138, 139, ... respectively connected to the plurality of stages 131, 132, 133, 134, .... Figure 7 , stages 131 , 132 , 133 , and 134 are shown as stage 1 , stage 2 , stage 3 , and stage 4 .

[0080] The plurality of stages 131, 132, 133, 134, ... may generate a plurality of intermediate scanning signals ISS1, ISS2, ISS3, ISS4, ... respectively for a plurality of scanning lines included in the display panel 110 based on the scanning start signal FLM and the scanning clock signal SCLK. In some example embodiments, the scanning clock signal SCLK may include, but is not limited to, a plurality of clock signals having different phases.

[0081] The plurality of logic gates 136, 137, 138, 139, ... may selectively output the plurality of scan signals SS1, SS2, SS3, SS4, ... and the plurality of intermediate scan signals ISS1, ISS2, ISS3, ISS4, ... generated by the plurality of stages 131, 132, 133, 134, ... in response to the scan output mask signal SOMS, respectively. In some example embodiments, as Figure 7 As shown in , the plurality of logic gates 136, 137, 138, 139, ... may be, but are not limited to, OR gates that perform an OR operation on the plurality of intermediate scanning signals ISS1, ISS2, ISS3, ISS4, ... and the scan output mask signal SOMS. For example, when the corresponding intermediate scanning signal ISS1 and the scan output mask signal SOMS both have a low level, each logic gate (e.g., 136) may output a corresponding scan signal (e.g., SS1) having a low level.

[0082] For example, Figure 8 and Fig. 9As shown in FIG. 1 , the zone splitting block 150 may receive frame data FDACT as input image data IDAT at an input frame frequency IFF of about 120 Hz from an external host, and may divide the frame data FDACT into first partial image data PDAT1 for a first partial panel zone PPZ1 including the 1st to 1000th scan lines SL1 to SL1000 (or 1000 pixel rows connected to the 1st to 1000th scan lines SL1 to SL1000) and second partial image data PDAT2 for a second partial panel zone PPZ2 including the 1001st to 2000th scan lines SL1001 to SL2000 (or 1000 pixel rows connected to the 1001st to 2000th scan lines SL1001 to SL2000). The first panel zone frequency decision block 162 may determine whether the first partial image data PDAT1 represents a still image, and the second panel zone frequency decision block 164 may determine whether the second partial image data PDAT2 represents a still image. When the first partial image data PDAT1 represents a still image, the first panel zone frequency decision block 162 may determine the first driving frequency DF1 for the first partial panel zone PPZ1 to be approximately 60 Hz based on the flicker value of the first partial image data PDAT1. When the second partial image data PDAT2 represents a still image, the second panel zone frequency decision block 164 may determine the second driving frequency DF2 for the second partial panel zone PPZ2 to be approximately 30 Hz based on the flicker value of the second partial image data PDAT2.

[0083] The non-driving period setting block 170 may set one of the two frame periods (e.g., FP1 and FP2) as a non-driving frame period NDFP based on the first driving frequency DF1 of about 60 Hz, which is the maximum driving frequency of the first driving frequency DF1 and the second driving frequency DF2. In other words, the non-driving period setting block 170 may classify the plurality of frame periods FP1 to FP8 into driving frame periods and non-driving frame periods NDFP based on the maximum driving frequency or the first driving frequency DF1 of about 60 Hz. Here, the driving frame period may be a frame period in which at least one of the plurality of partial panel zones PPZ1 and PPZ2 is driven, and the non-driving frame period NDFP may be a frame period in which all of the plurality of partial panel zones PPZ1 and PPZ2 are not driven. For example, among the first frame period FP1 to the eighth frame period FP8, the non-driving period setting block 170 can classify the first frame period FP1, the third frame period FP3, the fifth frame period FP5 and the seventh frame period FP7 as driving frame periods, and can classify the second frame period FP2, the fourth frame period FP4, the sixth frame period FP6 and the eighth frame period FP8 as non-driving frame periods NDFP.

[0084] In a driving frame period in which all of the first partial panel area PPZ1 and the second partial panel area PPZ2 are driven, for example, in the first frame period FP1 or the fifth frame period FP5, the controller 140 may provide the frame data FDAT including the first partial image data PDAT1 and the second partial image data PDAT2 to the data driver 120. In addition, the scan driver control block 180 can provide a scan start signal FLM and a scan clock signal SCLK to the scan driver 130, and the multiple stages 131, 132, 133, 134, ... of the scan driver 130 can sequentially generate the 1st intermediate scan signal ISS1 to the 2000th intermediate scan signal ISS2000 based on the scan start signal FLM and the scan clock signal SCLK, and the multiple logic gates 136, 137, 138, 139, ... of the scan driver 130 can sequentially output the 1st intermediate scan signal ISS1 to the 2000th intermediate scan signal ISS2000 as the 1st scan signal SS1 to the 2000th scan signal SS2000. Therefore, the scan driver 130 may sequentially provide 1st to 1000th scan signals SS1 to SS1000 to the first partial panel zone PPZ1 , and may sequentially provide 1001st to 2000th scan signals SS1001 to SS2000 to the second partial panel zone PPZ2 .

[0085] In the non-driving frame period NDFP in which all the first partial panel areas PPZ1 and the second partial panel areas PPZ2 are not driven, for example, in the second frame period FP2, the fourth frame period FP4, the sixth frame period FP6, or the eighth frame period FP8, the controller 140 may not provide the output image data ODAT to the data driver 120. In addition, in the non-driving frame period NDFP, the power block 190 may change at least one of the high gate voltage VGH or the low gate voltage VGL to a cut-off level. For example, in the non-driving frame period NDFP, the power block 190 may change the high gate voltage VGH of about 7V to a cut-off level of about 0V, and may change the low gate voltage VGL of about -8V to a cut-off level of about 0V. Therefore, in the non-driving frame period NDFP, the scan start signal FLM and the scan clock signal SCLK having a turn-on level (e.g., about -8V) may be changed to a cut-off level of about 0V based on the low gate voltage VGL having a cut-off level of about 0V. Therefore, the plurality of stages 131 , 132 , 133 , 134 , . . . of the scan driver 130 may not generate the 1st to 2000th intermediate scan signals ISS1 to ISS2000 , and thus the scan driver 130 may not generate the 1st to 2000th scan signals SS1 to SS2000 .

[0086] Even if the conventional display device drives the first partial panel area PPZ1 and the second partial panel area PPZ2 at different first driving frequencies DF1 and second driving frequencies DF2 in the non-driving frame period NDFP in which all the first partial panel area PPZ1 and the second partial panel area PPZ2 are not driven, the scan driver of the conventional display device may generate the scan signal SS, but may not output the scan signal SS by performing a masking operation. Therefore, in the conventional display device, the scan driver input signal SDIS may be provided to the scan driver even in the non-driving frame period NDFP, and the scan driver may generate the scan signal SS. However, in the display device 100 according to some example embodiments, in the non-driving frame period NDFP, the scan driver input signal SDIS may not be provided to the scan driver 130, or the scan driver input signal SDIS having a cut-off level may be provided to the scan driver 130. Therefore, in the non-driving frame period NDFP, the scan driver 130 may not generate the scan signal SS (or the 1st intermediate scan signal ISS1 to the 2000th intermediate scan signal ISS2000). Therefore, the power consumption of the scan driver 130 or the power consumption of the display device 100 can be further reduced.

[0087] In a driving frame period in which the first partial panel area PPZ1 and a part of the second partial panel area PPZ2 or the first partial panel area PPZ1 is driven, for example, in the third frame period FP3 or the seventh frame period FP7, the controller 140 may provide only the first partial image data PDAT1 to the data driver 120. In addition, the scan driver control block 180 may provide the scan driver 130 with a scan start signal FLM and a scan clock signal SCLK, and may further provide a scan output mask signal SOMS in a partial period of the driving frame period allocated to the non-driven second partial panel area PPZ2. The plurality of stages 131, 132, 133, 134, ... of the scan driver 130 may sequentially generate the 1st intermediate scan signal ISS1 to the 2000th intermediate scan signal ISS2000 based on the scan start signal FLM and the scan clock signal SCLK. The plurality of logic gates 136, 137, 138, 139, ... of the scan driver 130 may sequentially output the 1st intermediate scanning signal ISS1 to the 1000th intermediate scanning signal ISS1000 as the 1st scanning signal SS1 to the 1000th scanning signal SS1000, and may not output the 1001st intermediate scanning signal ISS1001 to the 2000th intermediate scanning signal ISS2000 or the 1001st scanning signal SS1001 to the 2000th scanning signal SS2000 in response to the scan output mask signal SOMS. Therefore, in the third frame period FP3 or the seventh frame period FP7, the scan driver 130 may sequentially provide the 1st scanning signal SS1 to the 1000th scanning signal SS1000 to the first partial panel zone PPZ1, and may not provide the 1001st scanning signal SS1001 to the 2000th scanning signal SS2000 to the second partial panel zone PPZ2.

[0088] Therefore, among the first frame period FP1 to the eighth frame period FP8, the first partial panel area PPZ1 may be driven in the first frame period FP1, the third frame period FP3, the fifth frame period FP5, and the seventh frame period FP7, and the second partial panel area PPZ2 may be driven in the first frame period FP1 and the fifth frame period FP5. Therefore, the first partial panel area PPZ1 may be driven at a first driving frequency DF1 of about 60 Hz, and the second partial panel area PPZ2 may be driven at a second driving frequency DF2 of about 30 Hz.

[0089] As described above, the display device 100 according to some example embodiments may perform multi-frequency driving (MFD) that drives the first partial panel zone PPZ1 and the second partial panel zone PPZ2 of the display panel 110 with different first driving frequencies DF1 and second driving frequencies DF2. Therefore, the power consumption of the display device 100 may be reduced. In addition, the display device 100 according to some example embodiments may set the non-driving frame period NDFP based on the maximum driving frequency of the first driving frequencies DF1 and the second driving frequencies DF2 for the first partial panel zone PPZ1 and the second partial panel zone PPZ2, and may not provide the scan driver input signal SDIS to the scan driver 130 in the non-driving frame period NDFP. Therefore, the power consumption of the scan driver 130 may be reduced, and the power consumption of the display device 100 may be further reduced.

[0090] Fig.10 is a block diagram illustrating a display device according to some example embodiments, Fig.11 It is shown that the Fig.10 A block diagram of an example of a scan driver in a display device of Fig.12 is a timing diagram for describing an example of an operation of a display device according to some example embodiments.

[0091] Reference Fig.10 , the display device 300 according to some example embodiments may include a display panel 310, a data driver 320, a scan driver 330, and a controller 340. In some example embodiments, the controller 340 may include a region splitting block 350, a first panel region frequency determination block 362, and a second panel region frequency determination block 364, a non-driving period setting block 370, a scan driver control block 380, and a power supply block 390. In addition to not using the scan output masking signal SOMS, and not providing the scan driver input signal SDIS to the scan driver 330 not only in the non-driving frame period but also in a partial period of at least one driving frame period (which may be referred to as a non-driving partial frame period), Fig.10 The display device 300 may have Figure 1 The display device 100 has a similar configuration and a similar operation.

[0092] In some example embodiments, Figure 1 The scan driver 130 is different. Fig.10 The scan driver 330 included in the display device 300 may not receive the scan output mask signal SOMS and may not include the plurality of logic gates 136, 137, 138, 139, ... For example, Fig.11As shown in , the scan driver 330 may include a plurality of stages 331, 332, 333, 334, ..., which generate a plurality of scan signals SS1, SS2, SS3, SS4, ... respectively for a plurality of scan lines included in the display panel 310 based on the scan start signal FLM and the scan clock signal SCLK. Fig.11 , stages 331 , 332 , 333 , and 334 are shown as stage 1 , stage 2 , stage 3 , and stage 4 .

[0093] For example, Figure 8 and Fig.12 As shown in , in a case where input image data IDAT is received at an input frame rate IFF of approximately 120 Hz, the first driving frequency DF1 for the first partial panel area PPZ1 is determined to be approximately 60 Hz, and the second driving frequency DF2 for the second partial panel area PPZ2 is determined to be approximately 30 Hz, the non-driving period setting block 370 can set the second frame period FP2, the fourth frame period FP4, the sixth frame period FP6, and the eighth frame period FP8 as the non-driving frame period NDFP based on the maximum driving frequency or the first driving frequency DF1 of approximately 60 Hz. In addition, the non-driving period setting block 370 can set a partial period of the driving frame period in which a portion of the first partial panel area PPZ1 and the second partial panel area PPZ2 is driven as the non-driving partial frame period NDPFP based on the driving frequency lower than the maximum driving frequency or the second driving frequency DF2 among the first driving frequency DF1 and the second driving frequency DF2. For example, the first partial panel zone PPZ1 is driven only in the third frame period FP3 and the seventh frame period FP7, and the non-driving period setting block 370 may set partial periods of the third frame period FP3 and the seventh frame period FP7 as the non-driving partial frame period NDPFP.

[0094] The scan driver control block 380 may not provide the scan driver input signal SDIS to the scan driver 330 in the non-driving frame period NDFP and the non-driving partial frame period NDPFP. The power supply block 390 may change at least one of the high gate voltage VGH or the low gate voltage VGL to a cut-off level not only in the non-driving frame period NDFP but also in the non-driving partial frame period NDPFP. Therefore, in the non-driving frame period NDFP and the non-driving partial frame period NDPFP, the scan start signal FLM and the scan clock signal SCLK may also have a cut-off level of about 0V. Therefore, the scan driver 330 may not generate the 1st scan signal SS1 to the 2000th scan signal SS2000 in the non-driving frame period NDFP, may generate the 1st scan signal SS1 to the 1000th scan signal SS1000 in a partial period of the third frame period FP3 or the seventh frame period FP7, and may not generate the 1001st scan signal SS1001 to the 2000th scan signal SS2000 in the remaining period of the third frame period FP3 or the seventh frame period FP7, or in the non-driving partial frame period NDPFP.

[0095] As described above, the display device 300 according to some example embodiments may not provide the scan driver input signal SDIS to the scan driver 330 in not only the non-driving frame period NDFP but also the non-driving partial frame period NDPFP by changing the high gate voltage VGH and / or the low gate voltage VGL to a cut-off level. Therefore, the power consumption of the scan driver 330 may be further reduced, and the power consumption of the display device 300 may be further reduced.

[0096] Fig.13 is a block diagram illustrating a display device according to some example embodiments, Fig.14 is a diagram for describing an example of first to fourth driving frequencies determined for first to fourth partial panel areas of a display panel, and Fig.15 is a timing diagram for describing an example of an operation of a display device according to some example embodiments.

[0097] Reference Fig.13, a display device 400 according to some example embodiments may include a display panel 410, a data driver 420, a scan driver 430, and a controller 440. In some example embodiments, the controller 440 may include a region splitting block 450, a first panel region frequency decision block 462, a second panel region frequency decision block 464, a third panel region frequency decision block 466, and a fourth panel region frequency decision block 468, a non-driving period setting block 470, a scan driver control block 480, and a power supply block 490. In addition to the fact that the input image data IDAT can be divided into first partial image data PDAT1, second partial image data PDAT2, third partial image data PDAT3 and fourth partial image data PDAT4 for the first partial panel area PPZ1, the second partial panel area PPZ2, the third partial panel area PPZ3 and the fourth partial panel area PPZ4, and the first partial panel area PPZ1, the second partial panel area PPZ2, the third partial panel area PPZ3 and the fourth partial panel area PPZ4 can be driven at the first driving frequency DF1, the second driving frequency DF2, the third driving frequency DF3 and the fourth driving frequency DF4, Fig.13 The display device 400 may have Figure 1 The display device 100 has a similar configuration and a similar operation.

[0098] For example, Fig.14 and Fig.15As shown in, the zone splitting block 450 can receive frame data FDACT as input image data IDAT at an input frame rate IFF of approximately 120 Hz, and can divide the frame data FDACT into a first partial image data PDAT1 for a first partial panel zone PPZ1 including the 1st scan line SL1 to the 500th scan line SL500, a second partial image data PDAT2 for a second partial panel zone PPZ2 including the 501st scan line SL501 to the 1000th scan line SL1000, a third partial image data PDAT3 for a third partial panel zone PPZ3 including the 1001st scan line SL1001 to the 1500th scan line SL1500, and a fourth partial image data PDAT4 for a fourth partial panel zone PPZ4 including the 1501st scan line SL1501 to the 2000th scan line SL2000. The first panel area frequency decision block 462, the second panel area frequency decision block 464, the third panel area frequency decision block 466 and the fourth panel area frequency decision block 468 can determine the first driving frequency DF1, the second driving frequency DF2, the third driving frequency DF3 and the fourth driving frequency DF4 for the first partial panel area PPZ1, the second partial panel area PPZ2, the third partial panel area PPZ3 and the fourth partial panel area PPZ4 to be approximately 60 Hz, approximately 15 Hz, approximately 30 Hz and approximately 15 Hz by respectively analyzing the first partial image data PDAT1, the second partial image data PDAT2, the third partial image data PDAT3 and the fourth partial image data PDAT4.

[0099] The non-driving period setting block 470 may set one frame period (e.g., FP2) among two frame periods (e.g., FP1 and FP2) as the non-driving frame period NDFP based on the first driving frequency DF1 of about 60 Hz, which is the maximum driving frequency among the first driving frequency DF1, the second driving frequency DF2, the third driving frequency DF3, and the fourth driving frequency DF4. For example, the non-driving period setting block 470 may classify the second frame period FP2, the fourth frame period FP4, the sixth frame period FP6, and the eighth frame period FP8 as the non-driving frame period NDFP.

[0100] In a driving frame period in which all of the first partial panel area PPZ1, the second partial panel area PPZ2, the third partial panel area PPZ3 and the fourth partial panel area PPZ4 are driven, for example, in the first frame period FP1, the scan driver control block 480 can provide a scan start signal FLM and a scan clock signal SCLK to the scan driver 430, and the scan driver 430 can sequentially provide the 1st scan signal SS1 to the 2000th scan signal SS2000 to the first partial panel area PPZ1, the second partial panel area PPZ2, the third partial panel area PPZ3 and the fourth partial panel area PPZ4.

[0101] In the non-driving frame period NDFP in which all of the first partial panel area PPZ1, the second partial panel area PPZ2, the third partial panel area PPZ3, and the fourth partial panel area PPZ4 are not driven, for example, in the second frame period FP2, the fourth frame period FP4, the sixth frame period FP6, or the eighth frame period FP8, the power supply block 490 may change at least one of the high gate voltage VGH or the low gate voltage VGL to a cut-off level, and the scan driver control block 480 may not provide the scan start signal FLM and the scan clock signal SCLK to the scan driver 430. Therefore, the scan driver 430 may not generate the 1st to 2000th scan signals SS1 to SS2000.

[0102] In a driving frame period in which a portion of the first partial panel area PPZ1, the second partial panel area PPZ2, the third partial panel area PPZ3, and the fourth partial panel area PPZ4 are driven, the scan driver control block 480 may provide a scan start signal FLM, a scan clock signal SCLK, and a scan output mask signal SOMS to the scan driver 430. For example, in the third frame period FP3 or the seventh frame period FP7 in which only the first partial panel area PPZ1 is driven, the scan driver 430 may sequentially provide the first scan signal SS1 to the 500th scan signal SS500 to the first partial panel area PPZ1. In addition, in the fifth frame period FP5 in which only the first partial panel area PPZ1 and the third partial panel area PPZ3 are driven, the scan driver 430 can sequentially provide the 1st scan signal SS1 to the 500th scan signal SS500 to the first partial panel area PPZ1, and can sequentially provide the 1001st scan signal SS1001 to the 1500th scan signal SS1500 to the third partial panel area PPZ3.

[0103] Therefore, among the first frame period FP1 to the eighth frame period FP8, the first partial panel area PPZ1 may be driven in the first frame period FP1, the third frame period FP3, the fifth frame period FP5 and the seventh frame period FP7, the second partial panel area PPZ2 may be driven in the first frame period FP1, the third partial panel area PPZ3 may be driven in the first frame period FP1 and the fifth frame period FP5, and the fourth partial panel area PPZ4 may be driven in the first frame period FP1. Therefore, the first partial panel area PPZ1 may be driven at a first driving frequency DF1 of about 60 Hz, the second partial panel area PPZ2 may be driven at a second driving frequency DF2 of about 15 Hz, the third partial panel area PPZ3 may be driven at a third driving frequency DF3 of about 30 Hz, and the fourth partial panel area PPZ4 may be driven at a fourth driving frequency DF4 of about 15 Hz.

[0104] As described above, the display device 400 according to some example embodiments may perform a multi-frequency driving (MFD) that drives the first partial panel zone PPZ1, the second partial panel zone PPZ2, the third partial panel zone PPZ3, and the fourth partial panel zone PPZ4 of the display panel 410 at different first driving frequencies DF1, second driving frequencies DF2, third driving frequencies DF3, and fourth driving frequencies DF4. Therefore, the power consumption of the display device 400 may be reduced. In addition, the display device 400 according to some example embodiments may set the non-driving frame period NDFP based on the maximum driving frequency among the different first driving frequencies DF1, second driving frequencies DF2, third driving frequencies DF3, and fourth driving frequencies DF4 for the first partial panel zone PPZ1, the second partial panel zone PPZ2, the third partial panel zone PPZ3, and the fourth partial panel zone PPZ4, and may not provide the scan driver input signal SDIS to the scan driver 430 in the non-driving frame period NDFP. Therefore, the power consumption of the scan driver 430 may be reduced in the non-driving frame period NDFP, and the power consumption of the display device 400 may be further reduced.

[0105] although Figure 1 An example is shown in which the display panel 110 is divided into two partial panel zones PPZ1 and PPZ2, and Fig.13 An example is shown in which the display panel 410 is divided into four partial panel zones PPZ1 , PPZ2 , PPZ3 , and PPZ4 , but the display panel according to some example embodiments may be divided into any number of partial panel zones.

[0106] Fig.16 is a block diagram illustrating a display device according to some example embodiments, Fig.17is a block diagram illustrating an example of a region splitting and still image detection block included in a display device according to some example embodiments, Fig.18 is a diagram for describing an example of an operation of a region splitting and still image detection block included in a display device according to some example embodiments, Fig.19 is a block diagram illustrating an example of a region splitting and panel region frequency decision block included in a display device according to some example embodiments, Fig. 20 is a diagram for describing an example of an operation of a region splitting and panel region frequency decision block included in a display device according to some example embodiments, and Fig.21 is a diagram for describing an example of an operation of a display device according to some example embodiments.

[0107] Reference Fig.16 , a display device 500 according to some example embodiments may include a display panel 510, a data driver 520, a scan driver 530, and a controller 540. In some example embodiments, the controller 540 may include a region splitting and still image detection block 550, a region splitting and panel region frequency decision block 560, a non-driving period setting block 570, a scan driver control block 580, and a power supply block 590.

[0108] The region splitting and still image detection block 550 may receive input image data IDAT at an input frame rate IFF, and may divide the input image data IDAT into moving image portion data representing a moving image and still image portion data representing a still image. That is, the region splitting and still image detection block 550 may divide the input image data IDAT into moving image portion data for a region (or area) of the display panel 510 where a moving image is to be displayed and still image portion data for a region (or area) of the display panel 510 where a still image is to be displayed.

[0109] In some example embodiments, Fig.17 As shown in FIG. 5 , the region splitting and still image detection block 550 may include a plurality of representative value memories RVM1, RVM2, . . . , RVMN and a regional still image detection unit 555. For example, referring to Fig.17 and Fig.18, a plurality of representative value memories RVM1, RVM2, ..., RVMN may store a plurality of representative values ​​of a plurality of input partial image data IPIDAT1 to IPIDAT12 in a previous frame period. The regional still image detection unit 555 may receive the input image data IDAT in the current frame period, and may divide the input image data IDAT in the current frame period into a plurality of input partial image data IPIDAT1 to IPIDAT12. According to some example embodiments, the size of each input partial image data (e.g., IPIDAT1) may be changed. The regional still image detection unit 555 may calculate a plurality of representative values ​​of a plurality of input partial image data IPIDAT1 to IPIDAT12 in the current frame period, and may determine whether each of the plurality of input partial image data IPIDAT1 to IPIDAT12 represents a moving image or a still image by comparing the plurality of calculated representative values ​​with the plurality of representative values ​​stored in the plurality of representative value memories RVM1, RVM2, ..., RVMN. The regional still image detection unit 555 can output input partial image data IPIDAT1, IPIDAT2, IPIDAT3, IPIDAT8 and IPIDAT9 representing motion images among multiple input partial image data IPIDAT1 to IPIDAT12 as motion image partial data MIPDAT, and can output input partial image data IPIDAT4, IPIDAT5, IPIDAT6, IPIDAT7, IPIDAT10, IPIDAT11 and IPIDAT12 representing still images among multiple input partial image data IPIDAT1 to IPIDAT12 as still image partial data SIPDAT.

[0110] The region splitting and panel region frequency decision block 560 may determine the first driving frequency for the first partial panel region of the display panel 510 corresponding to the moving image portion data MIPDAT as the input frame rate IFF, and may determine a plurality of second driving frequencies for a plurality of second partial panel regions of the display panel 510 by analyzing the still image portion data SIPDAT. Therefore, the region splitting and panel region frequency decision block 560 may divide the region of the display panel 510 where the still image is to be displayed into a plurality of second partial panel regions, and may determine a plurality of different second driving frequencies for the plurality of second partial panel regions.

[0111] In some example embodiments, Fig.19 As shown in FIG. 5 , the region splitting and panel region frequency decision block 560 may include a flicker lookup table (LUT) 562 and a region drive frequency decision unit 564. The flicker LUT 562 may store flicker values ​​corresponding to respective image data gray levels (e.g., Figure 5256 gray levels from gray level 0 to gray level 255 as shown in FIG. Fig.19 and Fig. 20 , the zone driving frequency determination unit 564 may determine the first driving frequency of the first partial panel zone PPZ1 of the display panel 510a corresponding to the motion image portion data MIPDAT to be the input frame rate IFF, for example, approximately 120 Hz. In addition, the zone driving frequency determination unit 564 may divide the still image portion data SIPDAT into a plurality of segmented data for a plurality of segments SEG11 to SEG54. According to some example embodiments, the size of each segment (e.g., SEG11) may be changed. The zone driving frequency determination unit 564 may determine a plurality of segmented flicker values ​​corresponding to the grayscale levels of the plurality of segmented data by using the flicker LUT 562, and may determine a plurality of segmented driving frequencies corresponding to the plurality of segmented flicker values. Fig. 20An example is shown in which, with respect to the first segment SEG11 to the second segment SEG54, a plurality of segment driving frequencies are determined to be about 30 Hz, about 30 Hz, about 30 Hz, about 30 Hz, about 30 Hz, about 30 Hz, about 30 Hz, about 30 Hz, about 15 Hz, about 6 Hz, about 15 Hz, about 15 Hz, about 30 Hz, about 15 Hz, about 15 Hz, about 30 Hz, about 15 Hz, about 15 Hz, about 30 Hz, about 15 Hz, about 30 Hz, about 15 Hz, about 30 Hz, about 15 Hz, about 30 Hz, about 15 Hz, about 30 Hz, about 15 Hz, and about 30 Hz. The zone driving frequency decision unit 564 may determine a plurality of second partial panel zones PPZ2-1, PPZ2-2, and PPZ2-3 by grouping the plurality of segments SEG11 to SEG54 based on the plurality of segment driving frequencies, and may determine a plurality of second driving frequencies for the plurality of second partial panel zones PPZ2-1, PPZ2-2, and PPZ2-3, respectively, based on the plurality of segment driving frequencies of the plurality of second partial panel zones PPZ2-1, PPZ2-2, and PPZ2-3. The zone driving frequency determination unit 564 may divide the still image portion data SIPDAT into a plurality of still image portion data SIPDAT1 to SIPDATN for a plurality of second partial panel zones PPZ2-1, PPZ2-2, and PPZ2-3, and may output a plurality of still image portion data SIPDAT1 to SIPDATN. For example, the zone driving frequency determination unit 564 may group the first segment SEG11 to the eighth segment SEG24 into one second partial panel zone PPZ2-1, and may determine that the second driving frequency for one second partial panel zone PPZ2-1 is about 30 Hz. In addition, the zone driving frequency determination unit 564 may group the ninth segment SEG31 to the twelfth segment SEG34 into another second partial panel zone PPZ2-2, and may determine that the second driving frequency for another second partial panel zone PPZ2-2 is about 15 Hz. Furthermore, the zone driving frequency decision unit 564 may group the thirteen segments SEG41 to the twenty segments SEG54 into yet another second partial panel zone PPZ2 - 3 , and may determine the second driving frequency for the yet another second partial panel zone PPZ2 - 3 to be about 30 Hz.

[0112] The non-driving period setting block 570 may classify a plurality of frame periods into driving frame periods and non-driving frame periods based on the first driving frequency and the maximum driving frequency among the plurality of second driving frequencies. Fig.21As shown in, in the case where the display panel 510b is divided into two second partial panel areas PPZ2-1 and PPZ2-2, and the second driving frequencies for the two second partial panel areas PPZ2-1 and PPZ2-2 are approximately 60 Hz and approximately 30 Hz, the non-driving period setting block 570 can set the first frame period FP1 and the third frame period FP3 as driving frame periods, and can set the second frame period FP2 and the fourth frame period FP4 as non-driving frame periods NDFP.

[0113] The scan driver control block 580 may provide the scan driver input signal SDIS to the scan driver 530 in the driving frame period, or in the first frame period FP1 and the third frame period FP3, and may not provide the scan driver input signal SDIS to the scan driver 530 in the non-driving frame period NDFP, or in the second frame period FP2 and the fourth frame period FP4. In some example embodiments, the scan driver control block 580 may not provide the scan start signal FLM and the scan clock signal SCLK as the scan driver input signal SDIS to the scan driver 530 in the non-driving frame period NDFP. For example, the power supply block 590 may change at least one of the high gate voltage VGH or the low gate voltage VGL to a cut-off level in the non-driving frame period NDFP, and based on the high gate voltage VGH and / or the low gate voltage VGL having the cut-off level, the scan driver control block 580 may not provide the scan start signal FLM and the scan clock signal SCLK to the scan driver 530, or may provide the scan start signal FLM and the scan clock signal SCLK having the cut-off level to the scan driver 530. Therefore, in the non-driving frame period NDFP, the power consumption of the scan driver 530 may be reduced, and the power consumption of the display device 500 may be further reduced.

[0114] The scan driver control block 580 may provide the scan output mask signal SOMS to the scan driver 530 in the third frame period FP3 in which only one second partial panel zone PPZ2-1 is driven. In response to the scan output mask signal SOMS, the scan driver 530 may sequentially provide the 1st to 1000th scan signals SS1 to SS1000 to one second partial panel zone PPZ2-1, and may not provide the 1001st to 2000th scan signals SS1001 to SS2000 to another second partial panel zone PPZ2-2.

[0115] Fig. 22 is a block diagram illustrating a display device according to some example embodiments, and Fig.23 is a diagram for describing an example of an operation of a display device according to some example embodiments.

[0116] Reference Fig. 22 , the display device 600 according to some example embodiments may include a display panel 610, a data driver 620, a scan driver 630, and a controller 640. In some example embodiments, the controller 640 may include a region splitting and still image detection block 650, a region splitting and panel region frequency determination block 660, a non-driving period setting block 670, a scan driver control block 680, and a power supply block 690. In addition to not using the scan output masking signal SOMS, and not providing the scan driver input signal SDIS to the scan driver 630 not only in the non-driving frame period but also in the non-driving partial frame period, Fig. 22 The display device 600 may have Fig.16 The display device 500 has a similar configuration and a similar operation.

[0117] For example, Fig.23 As shown in, in a case where the display panel 610 is divided into two second partial panel areas PPZ2-1 and PPZ2-2, and the second driving frequencies for the two second partial panel areas PPZ2-1 and PPZ2-2 are approximately 60 Hz and approximately 30 Hz, the non-driving period setting block 670 can set the second frame period FP2 and the fourth frame period FP4 in which both of the two second partial panel areas PPZ2-1 and PPZ2-2 are not driven as the non-driving frame period NDFP, and can set a part of the third frame period FP3 in which only one of the two second partial panel areas PPZ2-1 and PPZ2-2 is driven as the non-driving partial frame period NDPFP.

[0118] The scan driver control block 680 may not provide the scan driver input signal SDIS to the scan driver 630 in the non-driving frame period NDFP and the non-driving partial frame period NDPFP. For example, the power supply block 690 may change at least one of the high gate voltage VGH or the low gate voltage VGL to a cut-off level not only in the non-driving frame period NDFP but also in the non-driving partial frame period NDPFP. Therefore, in the non-driving frame period NDFP and the non-driving partial frame period NDPFP, the scan start signal FLM and the scan clock signal SCLK may also have a cut-off level of about 0V. Therefore, the scan driver 630 may not generate the 1st to 2000th scan signals SS1 to SS2000 in the non-driving frame period NDFP, may generate the 1st to 1000th scan signals SS1 to SS1000 in a partial period of the third frame period FP3, and may not generate the 1001st to 2000th scan signals SS1001 to SS2000 in the remaining period of the third frame period FP3 or in the non-driving partial frame period NDPFP. Therefore, the power consumption of the scan driver 630 can be further reduced, and the power consumption of the display device 600 can be further reduced.

[0119] Fig.24 An electronic device including a display device according to some example embodiments.

[0120] Reference Fig.24 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0121] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, in some example embodiments, the processor 1110 may be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0122] The memory device 1120 may store data used for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0123] The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc. and an output device such as a printer, a speaker, etc. The power supply 1150 may provide power for the operation of the electronic device 1100. The display device 1160 may be coupled to other components via a bus or other communication links.

[0124] The display device 1160 may perform a multi-frequency drive (MFD) that drives a plurality of partial panel areas at a plurality of different drive frequencies. Therefore, the power consumption of the display device 1160 may be reduced. In addition, the display device 1160 may set a non-driving frame period based on the maximum drive frequency among a plurality of drive frequencies for a plurality of partial panel areas, and may not provide a scan driver input signal to the scan driver during the non-driving frame period. Therefore, the power consumption of the scan driver may be reduced during the non-driving frame period, and the power consumption of the display device 1160 may be further reduced.

[0125] The inventive concept may be applied to any display device 1160 and any electronic device 1100 including the display device 1160. For example, the inventive concept may be applied to mobile phones, smart phones, wearable electronic devices, tablet computers, televisions (TVs), digital TVs, 3DTVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, and the like.

[0126] The electronic or electrical devices and / or any other related devices or components according to the exemplary embodiments of the present invention described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, which execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device such as a random access memory (RAM), for example. The computer program instructions can also be stored in other non-temporary computer-readable media such as a CD-ROM or a flash drive, etc. Moreover, it should be appreciated by those skilled in the art that the functions of various computing devices can be combined or integrated into a single computing device without departing from the spirit and scope of the exemplary embodiments of the present invention, or the functions of a specific computing device can be distributed in one or more other computing devices.

[0127] The foregoing is an illustration of the example embodiments and is not to be construed as limiting thereof. Although several example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible in the example embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the present disclosure. Therefore, it should be understood that the foregoing is an illustration of the various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the present disclosure and its equivalents.

Claims

1. A display device, wherein: The display device comprises: A display panel including a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a scan driver configured to provide a scan signal to the plurality of pixels based on a scan driver input signal including a scan start signal and a scan clock signal; and A controller configured to control the data driver and the scan driver, the controller comprising: a region splitting block configured to divide the input image data into a plurality of partial image data respectively corresponding to a plurality of partial panel regions of the display panel; a plurality of panel area frequency determination blocks configured to determine a plurality of driving frequencies for the plurality of partial panel areas by respectively analyzing the plurality of partial image data; A non-driving period setting block configured to classify a plurality of frame periods into a driving frame period and a non-driving frame period based on a maximum driving frequency among the plurality of driving frequencies; and a scan driver control block configured to provide the scan driver input signal to the scan driver in the driving frame period, and not provide the scan start signal and the scan clock signal to the scan driver in the non-driving frame period, The driving frame period is a frame period during which at least one of the plurality of partial panel areas is driven, and the non-driving frame period is a frame period during which all of the plurality of partial panel areas are not driven.

2. The display device according to claim 1, wherein: The controller further includes: a power supply block configured to generate a high gate voltage and a low gate voltage, Wherein, the scan driver control block includes: a scan driver input signal generating unit configured to generate an initial scan start signal and an initial scan clock signal; and a level shift unit configured to generate the scan start signal and the scan clock signal as the scan driver input signal by changing the voltage levels of the initial scan start signal and the initial scan clock signal based on at least one of the high gate voltage and the low gate voltage, and Wherein, in the non-driving frame period, the power supply block is configured to change the at least one of the high gate voltage and the low gate voltage to a cut-off level.

3. The display device according to claim 1, wherein: The scan driver control block is configured to provide a scan output mask signal to the scan driver in a partial period of the drive frame period allocated to a portion of the multiple partial panel areas, so that the scan signal is not provided to the portion of the multiple partial panel areas within the drive frame period.

4. The display device according to claim 3, wherein: The scanning driver comprises: a plurality of stages configured to generate the scan signals for a plurality of scan lines included in the display panel; and A plurality of logic gates are respectively connected to the plurality of stages and are configured to selectively output the scan signals generated by the plurality of stages in response to the scan output mask signals, respectively.

5. The display device according to claim 1, wherein: The display device is a foldable display device, wherein the plurality of partial panel areas include a first partial panel area located in a first direction from a folding line of the foldable display device and a second partial panel area located in a second direction opposite to the first direction from the folding line, and The region splitting block is configured to divide the input image data into first partial image data for the first partial panel region and second partial image data for the second partial panel region as the plurality of partial image data.

6. The display device according to claim 1, wherein: Each of the plurality of panel area frequency decision blocks comprises: a still image detection unit configured to receive corresponding partial image data of the plurality of partial image data at an input frame rate and determine whether the corresponding partial image data represents a still image; and The driving frequency determination unit is configured to determine the corresponding driving frequency among the multiple driving frequencies as the input frame frequency when the corresponding partial image data does not represent the still image, and to determine the corresponding driving frequency as a frequency lower than the input frame frequency when the corresponding partial image data represents the still image.

7. The display device according to claim 6, wherein: Each of the plurality of panel region frequency decision blocks further comprises: a representative value memory configured to store a representative value of the corresponding portion of image data in a previous frame period, and Wherein, the still image detection unit is configured to calculate a representative value of the corresponding partial image data in a current frame period, and determine whether the corresponding partial image data represents the still image by comparing the calculated representative value of the corresponding partial image data with the representative value of the corresponding partial image data stored in the representative value memory.

8. The display device according to claim 6, wherein: Each of the plurality of panel region frequency decision blocks further comprises: a flicker lookup table configured to store flicker values ​​corresponding to respective image data gray levels, and Wherein, the driving frequency determination unit is configured to determine a flicker value corresponding to the grayscale level of the corresponding partial image data based on the corresponding partial image data representing the still image by using the flicker lookup table, and determine the corresponding driving frequency according to the determined flicker value.

9. The display device according to claim 6, wherein: Each of the plurality of panel region frequency decision blocks further comprises: A driving frequency mixing unit is configured to gradually change a corresponding one of the multiple driving frequencies used for a corresponding partial panel area among the multiple partial panel areas from the previous driving frequency used for the partial panel area to the corresponding driving frequency determined by the driving frequency determination unit when the corresponding driving frequency determined by the driving frequency determination unit changes from the previous driving frequency.

10. The display device according to claim 1, wherein: Each of the plurality of pixels comprises: a drive transistor configured to generate a drive current; a switch transistor configured to transmit a corresponding one of the data signals to a source of the drive transistor; a compensation transistor configured to be diode-connected to the driving transistor; a storage capacitor configured to store the corresponding one of the data signals transmitted through the switch transistor and the diode-connected drive transistor; a first initialization transistor configured to provide an initialization voltage to the storage capacitor and a gate of the drive transistor; a first emission control transistor configured to connect a line of a power supply voltage to the source of the drive transistor; a second emission control transistor configured to connect a drain of the drive transistor to an organic light emitting diode; A second initialization transistor configured to provide the initialization voltage to the organic light emitting diode; and The organic light emitting diode is configured to emit light based on the driving current, wherein at least the first one of the driving transistor, the switching transistor, the compensation transistor, the first initialization transistor, the first emission control transistor, the second emission control transistor and the second initialization transistor is implemented by a PMOS transistor, and at least the second one of the driving transistor, the switching transistor, the compensation transistor, the first initialization transistor, the first emission control transistor, the second emission control transistor and the second initialization transistor is implemented by an NMOS transistor.

11. The display device according to claim 1, wherein: The non-driving period setting block is configured to set a partial period of the driving frame period as a non-driving partial frame period based on a driving frequency lower than the maximum driving frequency among the plurality of driving frequencies, and The scan driver control block is configured not to provide the scan driver input signal to the scan driver during the non-driving frame period and the non-driving partial frame period.

12. The display device according to claim 11, wherein: The controller further includes: a power supply block configured to generate a high gate voltage and a low gate voltage, Wherein, the scan driver control block includes: a scan driver input signal generating unit configured to generate an initial scan start signal and an initial scan clock signal; and a level shift unit configured to generate the scan start signal and the scan clock signal as the scan driver input signal by changing the voltage levels of the initial scan start signal and the initial scan clock signal based on at least one of the high gate voltage and the low gate voltage, and The power supply block is configured to change at least one of the high gate voltage and the low gate voltage to a cut-off level during the non-driving frame period and the non-driving partial frame period.

13. A display device, wherein: The display device comprises: A display panel including a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a scan driver configured to provide a scan signal to the plurality of pixels based on a scan driver input signal including a scan start signal and a scan clock signal; and A controller configured to control the data driver and the scan driver, the controller comprising: a region splitting and still image detection block configured to receive input image data at an input frame rate and configured to split the input image data into moving image portion data representing a moving image and still image portion data representing a still image; an area splitting and panel area frequency determination block configured to determine a first driving frequency for a first partial panel area of ​​the display panel corresponding to the moving image portion data as the input frame rate, and determine a plurality of second driving frequencies for a plurality of second partial panel areas of the display panel by analyzing the still image portion data; a non-driving period setting block configured to classify a plurality of frame periods into driving frame periods and non-driving frame periods based on the first driving frequency and a maximum driving frequency among the plurality of second driving frequencies; and a scan driver control block configured to provide the scan driver input signal to the scan driver in the driving frame period, and not provide the scan start signal and the scan clock signal to the scan driver in the non-driving frame period, The driving frame period is a frame period in which at least one of the first partial panel area and the multiple second partial panel areas is driven, and the non-driving frame period is a frame period in which all of the first partial panel areas and the multiple second partial panel areas are not driven.

14. The display device according to claim 13, wherein: The controller further includes: a power supply block configured to generate a high gate voltage and a low gate voltage, Wherein, the scan driver control block includes: a scan driver input signal generating unit configured to generate an initial scan start signal and an initial scan clock signal; and a level shift unit configured to generate the scan start signal and the scan clock signal as the scan driver input signal by changing the voltage levels of the initial scan start signal and the initial scan clock signal based on at least one of the high gate voltage and the low gate voltage, and The power supply block is configured to change at least one of the high gate voltage and the low gate voltage to a cut-off level during the non-driving frame period.

15. The display device according to claim 13, wherein: The region splitting and still image detection block includes: a plurality of representative value memories configured to store a plurality of representative values ​​of a plurality of input partial image data in a previous frame period; and The regional still image detection unit is configured as follows: Receiving the input image data in the current frame period; Dividing the input image data in the current frame period into the plurality of input partial image data; Calculating a plurality of representative values ​​of the plurality of input partial image data in the current frame period; determining whether each of the plurality of input partial image data represents the moving image or the still image by comparing the calculated plurality of representative values ​​with the plurality of representative values ​​stored in the plurality of representative value memory; outputting input partial image data representing the moving image among the plurality of input partial image data as the moving image partial data; and Input partial image data representing the still image among the plurality of input partial image data are output as the still image partial data.

16. The display device according to claim 13, wherein: The zone splitting and panel zone frequency determination block includes: a flicker lookup table configured to store flicker values ​​corresponding to respective image data gray levels; and The zone driving frequency determination unit is configured as follows: determining the first driving frequency for the first portion of the panel area corresponding to the motion image portion data as the input frame rate; dividing the still image portion data into a plurality of segment data for a plurality of segments; determining a plurality of segmented flicker values ​​corresponding to the gray levels of the plurality of segmented data by using the flicker lookup table; determining the plurality of second partial panel areas by grouping the plurality of segments based on a plurality of segment driving frequencies corresponding to the plurality of segment flicker values; and The plurality of second driving frequencies for the plurality of second partial panel areas are respectively determined based on the plurality of segmented driving frequencies of the plurality of second partial panel areas.

17. The display device according to claim 13, wherein: The non-driving period setting block sets a partial period of the driving frame period as a non-driving partial frame period based on the first driving frequency and a driving frequency lower than the maximum driving frequency among the plurality of second driving frequencies, and The scan driver control block does not provide the scan driver input signal to the scan driver in the non-driving frame period and the non-driving partial frame period.

18. The display device according to claim 17, wherein: The controller further includes: a power supply block configured to generate a high gate voltage and a low gate voltage, Wherein, the scan driver control block includes: a scan driver input signal generating unit configured to generate an initial scan start signal and an initial scan clock signal; and a level shift unit configured to generate the scan start signal and the scan clock signal as the scan driver input signal by changing the voltage levels of the initial scan start signal and the initial scan clock signal based on at least one of the high gate voltage and the low gate voltage, and The power supply block is configured to change at least one of the high gate voltage and the low gate voltage to a cut-off level during the non-driving frame period and the non-driving partial frame period.

Images