Electronic devices and methods for forming the same

Abstract

The present disclosure relates to electronic devices and methods of forming the same. A method and electronic device are disclosed. The method can be used to allow processing of a thin layer of a workpiece including a die. The workpiece can include a base substrate and a plurality of layers overlying the base substrate. The method can include forming a polymer support layer over the plurality of layers, thinning or removing the base substrate within a component region of the workpiece, where the component region includes an electronic device, and dicing the workpiece into a plurality of dies after thinning or removing the base substrate. In another aspect, the electronic device can be formed using such a method. In one embodiment, the workpiece can have a size corresponding to a semiconductor wafer to allow wafer-level processing rather than die-level processing.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to methods and electronic devices, and in particular, to methods for removing at least a portion of a base substrate from a workpiece and electronic devices formed by the methods. BACKGROUND

[0002] A die including an electronic device can have all or nearly all of a semiconductor wafer removed from beneath a device layer within a component area of the die. The cumulative thickness of the device layer can be in the range of 2 microns to 7 microns thick. When the area of the electronic device is small, such as for diced dies, the relatively thin cumulative thickness of the device layer can be sufficient mechanical support by itself. However, as the size of the substrate associated with the electronic device increases, for example, when the substrate has a diameter of 100 mm or greater, this relatively thin cumulative thickness of the device layer can not provide sufficient mechanical support by itself.

[0003] Complex processing sequences can be used to attach and remove the substrate, as described in Chung, J.W. et al., "GaN-on-Si Technology, a New Approach for Advanced Devices in Energy and Communications," Proceedings of the European Solid-State Device Research Conference 2010, IEEE, pp. 52-56 (2010). Such complex processing can not be necessary in view of the process flow, and can result in lower yields. Improvements in workpiece processing aspects including relatively thin electronic devices are needed. SUMMARY

[0004] The problem to be solved by the present invention is to allow for removal of a base substrate or to make the thickness of the base substrate substantially thinner than conventionally back-lapped base substrates, and still allow for processing operations to be performed without damaging the device layer.

[0005] In one aspect, a method is provided. The method can include providing a workpiece having a first major surface and a second major surface opposite the first major surface. The workpiece can include a base substrate and a plurality of layers overlying the base substrate. The plurality of layers are closer to the first major surface than the second major surface. The method can also include forming a polymer support layer along the first major surface of the workpiece; and removing at least 50% of a thickness of the base substrate within a component region of the workpiece, wherein the component region includes an electronic device, and a combined thickness of the workpiece and polymer support layer within the component region is at least 30 microns after the at least 50% of the thickness of the base substrate is removed. The method can also include dicing the workpiece into a plurality of dies after the at least 50% of the thickness of the base substrate is removed.

[0006] In one embodiment, the polymer support layer is permanently attached to the first major surface.

[0007] In another embodiment, the method can also include forming a spacer structure along the first major surface of the workpiece prior to forming the polymer support layer.

[0008] In a particular embodiment, the method can also include removing a portion of the polymer support layer to expose the spacer structure. Providing the workpiece can include providing the workpiece, wherein the base substrate is a wafer and has a diameter of at least 200 mm, and forming the spacer structure can include forming a conductive member electrically connected to a terminal of the electronic device, wherein the conductive member has a height of at least 30 microns. Forming the polymer support layer can include forming a molding compound along the first major surface of the workpiece; and curing the molding compound to form the polymer support layer. Removing the portion of the polymer support layer can include grinding away the molding compound to expose the conductive member, and removing at least 50% of a thickness of the base substrate can include removing at least 80% of the thickness of the base substrate within the component region of the workpiece, wherein a combined thickness of the workpiece and polymer support layer within the component region has a thickness in a range of 75 microns to 300 microns after the at least 80% of the thickness of the base substrate is removed.

[0009] In another embodiment, the base substrate is a single-crystalline group 14 element wafer, and a high electron mobility transistor includes at least two layers of the plurality of layers.

[0010] In another aspect, a method is provided. The method can include providing a workpiece having a first major surface and a second major surface opposite the first major surface, wherein the workpiece includes a base substrate and a plurality of layers overlying the base substrate, wherein the plurality of layers are closer to the first major surface than the second major surface. The method can also include forming a trench along the first major surface of the workpiece and extending at least to the base substrate; and forming a polymer support layer extending into the trench and contacting the base substrate. The method can also include removing at least a portion of a thickness of the base substrate within a component region to expose the polymer support layer within the trench, wherein the polymer support layer has a height of at least 30 microns measured within the trench and after the removal of at least the portion of the base substrate, and the component region includes an electronic device; and dicing the workpiece into a plurality of dies after the removal of at least the portion of the thickness of the base substrate.

[0011] In one embodiment, the plurality of layers can include a sacrificial layer, and removing at least a portion of a thickness of the base substrate to expose the sacrificial layer can be performed.

[0012] In another aspect, an electronic device is provided. The electronic device can include a plurality of layers having a first major surface and a second major surface opposite the first major surface; a polymer support layer along the first major surface of the workpiece, wherein a combined thickness of the polymer support layer and the plurality of layers is at least 30 microns within a component region; and a backside member along the second major surface. At least one peripheral side of the polymer support layer and at least one peripheral side of the backside member can be substantially coextensive.

[0013] In one embodiment, a particular layer within the plurality of layers is a semiconductor layer, and the plurality of layers has a cumulative thickness of at most 9 microns.

[0014] In another embodiment, the device can include a high electron mobility transistor, and at least two layers of the plurality of layers can include III-V semiconductor material.

[0015] Technical effects realized by the present disclosure can include forming a polymer support layer along a side of a workpiece opposite a base substrate prior to thinning or removing the base substrate. The polymer support layer allows for the thickness of the device layers and the remaining portion of the base substrate, if present, to be used, whereas without the polymer support layer, the workpiece can have insufficient mechanical support to withstand subsequent processing operations. BRIEF DESCRIPTION OF DRAWINGS

[0016] Embodiments are illustrated by way of example in the accompanying drawings, in which embodiments are not limited.

[0017] Figure 1 Illustration of a top view of a workpiece including a component region and a scribe lane.

[0018] Figure 2 Illustration of a cross-sectional view of a portion of a workpiece including an exemplary device structure within a component region. Figure 1

[0019] Figure 3 Illustration of a cross-sectional view of a portion of a workpiece including another exemplary device structure within a component region. Figure 1

[0020] Figure 4 Illustration of a cross-sectional view of a portion of a workpiece including a base substrate, a plurality of layers, and a spacer structure. Figure 1

[0021] Illustration of a cross-sectional view of a workpiece including a front side polymer support layer after being formed. Figure 5 Figure 4 Illustration of a cross-sectional view of a workpiece including a base substrate after a portion of the base substrate is removed.

[0022] Figure 6 Figure 5 Illustration of a cross-sectional view of a workpiece including a remaining portion of a base substrate after the remaining portion of the base substrate is removed.

[0023] Figure 7 Illustration of a cross-sectional view of a workpiece including a back side polymer support layer after being formed. Figure 6

[0024] Illustration of a cross-sectional view of a workpiece including a front side polymer support layer after a portion of the front side polymer support layer is removed to expose a spacer structure. Figure 8 Figure 7 Illustration of a cross-sectional view of a workpiece including a die after the workpiece is singulated.

[0025] Figure 9 Figure 8 Illustration of a top view of a die after the workpiece is singulated.

[0026] Figure 10 Illustration of a top view of a die after the workpiece is singulated. Figure 9

[0027] Figure 11 Illustration of a top view of a die after the workpiece is singulated.

[0028] Figure 12 ​​​​​​​a cross-sectional view of the workpiece including after forming the electrically insulating thermally conductive layer and attaching the heat sink structure along the back major surface of the workpiece according to another embodiment Figure 7 a graphical illustration of a cross-sectional view of the workpiece including after removing a portion of the front side polymer support layer to expose the spacer structure and removing a portion of the base substrate along the back major surface of the workpiece

[0029] Figure 13 a cross-sectional view of the workpiece including after removing a portion of the front side polymer support layer to expose the spacer structure and removing a portion of the base substrate along the back major surface of the workpiece Figure 5 a graphical illustration of a cross-sectional view of the workpiece including after removing a portion of the base substrate within the scribe lane

[0030] Figure 14 a graphical illustration of a cross-sectional view of the workpiece including after removing a portion of the base substrate within the scribe lane Figure 13 a graphical illustration of a cross-sectional view of the workpiece including after removing a portion of the base substrate within the scribe lane

[0031] Figure 15 a graphical illustration of a cross-sectional view of the workpiece including after forming the back side polymer support layer Figure 14 a graphical illustration of a cross-sectional view of the workpiece including after forming the back side polymer support layer

[0032] Figure 16 a graphical illustration of a cross-sectional view of the workpiece including after removing a portion of the base substrate within the scribe lane Figure 4 a graphical illustration of a cross-sectional view of the workpiece including after removing a portion of the base substrate within the scribe lane

[0033] Figure 17 a graphical illustration of a cross-sectional view of the workpiece including after forming the front side polymer support layer Figure 16 a graphical illustration of a cross-sectional view of the workpiece including after forming the front side polymer support layer

[0034] Figure 18 a graphical illustration of a cross-sectional view of the workpiece including after removing the base substrate Figure 17 a graphical illustration of a cross-sectional view of the workpiece including after removing the base substrate

[0035] Figure 19 a graphical illustration of a cross-sectional view of the workpiece including after forming the back side polymer support layer Figure 18 a graphical illustration of a cross-sectional view of the workpiece including after forming the back side polymer support layer

[0036] Figure 20 a graphical illustration of a cross-sectional view of the workpiece including after removing a portion of the front side polymer support layer to expose the bond pad Figure 19 a graphical illustration of a cross-sectional view of the workpiece including after removing a portion of the front side polymer support layer to expose the bond pad

[0037] Figure 21 a graphical illustration of a cross-sectional view of the workpiece including after removing a portion of the base substrate within the scribe lane Figure 4 a graphical illustration of a cross-sectional view of the workpiece including after removing a portion of the base substrate within the scribe lane

[0038] Figure 22 a graphical illustration of a cross-sectional view of the workpiece including after forming the front side polymer support layer Figure 21 a graphical illustration of a cross-sectional view of the workpiece including after forming the front side polymer support layer

[0039] Figure 23 a graphical illustration of a cross-sectional view of the workpiece including after removing the base substrate Figure 22illustration of a cross-sectional view of a workpiece.

[0040] Figure 24 including after removing portions of the conductive layer within the scribe lanes Figure 23 illustration of a cross-sectional view of a workpiece.

[0041] Figure 25 including after removing portions of the plurality of layers within the scribe lanes Figure 24 illustration of a cross-sectional view of a workpiece.

[0042] Figure 26 including after cutting the workpiece into dies Figure 25 illustration of a cross-sectional view of a workpiece.

[0043] Figure 27 including after removing portions of the plurality of layers within the scribe lanes Figure 4 illustration of a cross-sectional view of a workpiece, wherein the plurality of layers includes a sacrificial layer, a device segment, and an interconnect segment.

[0044] Figure 28 including after forming a frontside polymer support layer Figure 27 illustration of a cross-sectional view of a workpiece.

[0045] Figure 29 including after removing the base base Figure 28 illustration of a cross-sectional view of a workpiece.

[0046] Figure 30 including after removing the sacrificial layer and forming a conductive layer along a back major surface of the workpiece Figure 29 illustration of a cross-sectional view of a workpiece.

[0047] Figure 31 including after removing portions of the base base along a backside of the workpiece other than all of the base base Figure 22 illustration of a cross-sectional view of a workpiece.

[0048] Figure 32 including after removing portions of the base base to define a trench Figure 31 illustration of a cross-sectional view of a workpiece.

[0049] Figure 33 including after forming a conductive layer to fill the trench Figure 32 illustration of a cross-sectional view of a workpiece.

[0050] Figure 34 including after removing portions of the frontside polymer support layer to expose the spacer structure and cutting the workpiece into dies Figure 33 illustration of a cross-sectional view of a workpiece.

[0051] Those skilled in the art recognize that the elements in the figures are shown for the purpose of simplification and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures can be exaggerated relative to other elements to help improve understanding of the embodiments of the application. DETAILED DESCRIPTION

[0052] The following description in combination with the drawings serves to explain the disclosed teachings. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is in no way intended to, and is not to be interpreted as, a limitation of the scope of the teachings. Other embodiments based on the teachings outlined herein are possible.

[0053] The term "width" is intended to mean a dimension measured across a major surface of a substrate. When a substrate has different dimensions along a major surface, the larger dimension is the length, and the smaller dimension is the width. When the dimensions along a major surface are the same (e.g., a square) or uniform (e.g., the diameter of a circle), the dimensions are referred to herein as the width. For a non-equilateral rectangular substrate (a non-square substrate), the width of such a substrate along a major surface is less than the length of the substrate along that major surface. For a major surface of a substrate having dimensions that can be characterized by a minor axis and a major axis (e.g., an elliptical or oval substrate), the minor axis corresponds to the width, and the major axis corresponds to the length. The height and thickness of a layer, structure, or other feature associated with a substrate are measured in a direction perpendicular to the major surface.

[0054] The terms "comprising," "including," "carrying," "having," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited only to those features but can include other features not expressly listed or inherent to such method, article, or apparatus. Further, unless expressly specified, "or" means an inclusive-or, and not an exclusive- or. For example, a condition is satisfied by any one of A or B by: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).

[0055] In addition, use of "a" or "an" is employed to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the application. This description should be read to include one, at least one, or the singular as also including the plural, or vice versa, unless it is clear from the context that it is meant otherwise. For example, when a single item is described herein, more than one item can be used in place of a single item. Similarly, where more than one item is described herein, a single item can be substituted in place of the more than one item.

[0056] The use of the words "about," "approximately," or "substantially" is intended to mean close to as defined in the context in which it is used. However, slight variations can be acceptable depending on the desired practical results.

[0057] Group numbers correspond to columns in the periodic table based on the November 28, 2016 version of the IUPAC Periodic Table of the Elements.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. Many details are set forth in order to provide a thorough understanding of the application. However, well-known details are not described herein in order to avoid obscuring the application.

[0059] Embodiments described herein allow for processing workpieces having at least portions of relatively thin layers that can be exposed during processing. In one embodiment, the workpieces can have permanently attached polymer support layers that help provide adequate mechanical support during subsequent processing operations. Where permanent polymer support layers are used, there is no need to retain a relatively thick base substrate by dicing and die packaging. Thus, workpieces that are substantially larger than a die can be processed so that a processing sequence can only need to be performed once for many dies, as opposed to performing a processing sequence for each die, which can be performed more than 100 times for each semiconductor wafer. This approach is well suited for electronic devices where a thick base substrate can not provide the best electrical characteristics (e.g., a thick Si substrate on a III-V semiconductor device can be undesirable, as the electrical resistance associated with a drain or collector can be higher as the semiconductor substrate is thicker, etc.). Many embodiments can use one or more polymer support layers to ensure that the workpiece has adequate thickness to allow processing to be performed at the wafer level without a significant risk of the relatively thin device layers being damaged during processing. Spacer structures can be used to assist in ensuring adequate thickness of the polymer support layer, as needed or desired.

[0060] In one aspect, a method can include: providing a workpiece having a first major surface and a second major surface opposite the first major surface, wherein the workpiece includes a base substrate and a plurality of layers overlying the base substrate, wherein the plurality of layers are closer to the first major surface than the second major surface; forming a polymer support layer along the first major surface of the workpiece; removing at least 50% of a thickness of the base substrate within a component region of the workpiece, wherein the component region includes an electronic device, and after removing at least 50% of the thickness of the base substrate, a combined thickness of the workpiece and polymer support layer within the component region is at least 30 microns, and after removing at least 50% of the thickness of the base substrate, singulating the workpiece into a plurality of dies.

[0061] In another aspect, a method can include: providing a workpiece having a first major surface and a second major surface opposite the first major surface, wherein the workpiece includes a base substrate and a plurality of layers overlying the base substrate, wherein the plurality of layers are closer to the first major surface than the second major surface; forming a trench along the first major surface of the workpiece, and the trench extends at least to the base substrate; forming a polymer support layer extending into the trench and contacting the base substrate; removing at least a portion of a thickness of the base substrate within a component region to expose the polymer support layer within the trench, wherein within the trench and after removing at least the portion of the base substrate, the polymer support layer has a height measured within the trench of at least 30 microns, and the component region includes an electronic device; and after removing at least the portion of the thickness of the base substrate, singulating the workpiece into a plurality of dies.

[0062] In another aspect, an electronic device can include a plurality of layers having a first major surface and a second major surface opposite the first major surface; a polymer support layer along the first major surface of the workpiece, wherein within a component region, a combined thickness of the polymer support layer and the plurality of layers is at least 30 microns; and a backside member along the second major surface, wherein at least one peripheral side of the polymer support layer and at least one peripheral side of the backside member are substantially co-terminus.

[0063] Figure 1 A diagram including a top view of a front side (device side) major surface of a workpiece 100. A backside major surface is opposite the front side major surface and is not visible in Figure 1 The workpiece 100 includes a base substrate 102, a component region 106, and scribe lanes 108 between the component regions 106. In Figure 1 Device layers are not shown in Figure 2 andFigure 3 The device layer is described in more detail. In one embodiment, the semiconductor material of the base substrate 102 can include a single-crystalline Group 14 element (e.g., silicon or germanium), a III-V semiconductor material, or a II-VI semiconductor material. In particular embodiments, the base substrate 102 can be a semiconductor wafer. The base substrate 102 has two major surfaces along opposite sides of the base substrate 102. The major surface closer to the front side major surface of the base substrate 102 forms the component region 106.

[0064] In the illustrated embodiment, the base substrate 102 is circular and has a diameter along the major surface that is one type of width. The base substrate 102 can have another shape, such as square, rectangular, oval, etc. The base substrate 102 can have a width (diameter in the illustrated embodiment) of at least 100 mm. As the width increases, more mechanical support can be needed or required. Thus, a base substrate 102 having a width of at least 150 mm can be thicker than a width of 100 mm, a base substrate 102 having a width of at least 200 mm can be thicker than a width of 150 mm, a base substrate 102 having a width of at least 300 mm can be thicker than a width of 200 mm, etc. While there can not be a theoretical limit to the width, the base substrate 102 can have a width of at most 400 mm.

[0065] Many different types of electronic components can be located within the component region. Figure 2 and Figure 3 A cross-sectional view including exemplary components is shown to illustrate several different types of electronic components that can be located within the component region. In Figure 2 and Figure 3 The electronic devices shown and described in and are not intended to limit the scope of the present application, which is defined in the appended claims.

[0066] Figure 2A cross-sectional view of a high electron mobility transistor (HEMT) within a component region 106 that includes electronics. A nucleation layer 122, a buffer layer 124, a channel layer 126, and a barrier layer 128 are overlaid on a base substrate 102. Any one or more of the layers 122, 124, 126, and 128 can be a semiconductor layer that includes a semiconductor material having a band gap energy that is greater than a band gap energy of the semiconductor material of the base substrate 102. The semiconductor material of any one or more of the layers 122, 124, 126, and 128 can include a compound semiconductor material. The compound semiconductor material can include a III-V compound or a II-V compound. The III-V compound can include III-N, III-P, III-As, and the III element can be Al, Ga, In, or any combination thereof. The II-VI compound can include II-O, II-S, II-Se, or II-Te, and the II element can include Zn, Cd, Hg, Pb, etc.

[0067] In another implementation, any one or more of the layers 122, 124, 126, and 128 can include Al x Ga (1-x) N, where 0 < x < 1. In a more particular implementation, the nucleation layer 122 includes AlN, the buffer layer 124 includes Al y Ga( 1-y )N, where 0 < y < 1, where y decreases as distance from the nucleation layer 122 increases, the channel layer 126 includes GaN, and the barrier layer 128 includes Al z Ga (1-z) N, where 0 < z < 0.5. A heterojunction can exist at an interface between any one or more pairs of the layers 122, 124, 126, and 128. A two-dimensional charge carrier can be associated with the heterojunction. For example, a two-dimensional electron gas (2DEG) can exist along at least a portion of the heterojunction between the channel layer 126 and the barrier layer 128. A two-dimensional hole gas can or can not exist within the HEMT. An isolation region 130 helps to isolate the transistor structure from other transistor structures (not shown) that can exist within the component region. The isolation region 130 can be formed by implanting nitrogen ions.

[0068] The dielectric layer 140 can include one or more dielectric films. The dielectric layer 140 is etched to define openings, and source and drain electrodes 152 and 154 are formed. The openings for the source and drain electrodes 152 and 154 can extend to an upper surface of the barrier layer 128, partially through the barrier layer 128, or completely through the barrier layer 128, as shown in FIG. 1C. The source and drain electrodes 152 and 154 can be formed by depositing a conductive material, such as titanium, titanium nitride, platinum, gold, silver, aluminum, or any combination thereof, into the openings. Figure 2An opening is formed partially or completely through the dielectric layer 140, and a gate electrode 156 is formed within the opening. The HEMT can be a depletion mode HEMT or an enhancement mode HEMT. Upon reading this specification, a skilled artisan will be capable of determining the relationship between the gate electrode 156 and the opening through at least part of the dielectric layer 140 for implementing a depletion mode HEMT or an enhancement mode HEMT. The portions of the electrodes 152, 154, and 156 that extend beyond the opening of the dielectric layer 140 can be field plates that help affect gate-drain capacitance and gate-source capacitance.

[0069] An interlayer dielectric (ILD) layer 160 is formed on the dielectric layer 140 and the electrodes 152, 154, and 156. The ILD layer 160 can include one or more insulating films. The ILD layer 160 is etched to define openings, and interconnects 162 and 164 are formed. Similar to the electrodes 152, 154, and 156, the portions of the interconnects 162 and 164 that extend in the lateral direction beyond the openings can be field plates that help affect capacitive coupling within the HEMT. In Figure 2 The two portions of the interconnect 162 shown in FIG. 2 are connected to each other at a location not shown, and define an opening on the gate electrode 156. The opening within the interconnect 162 helps reduce gate-source capacitance. Another ILD layer 170 is formed on the ILD layer 160 and the interconnects 162 and 164. The ILD layer 170 can include one or more insulating films, and can have the same composition or a different composition compared to the ILD layer 160. The ILD layer 170 is etched to define openings, and interconnects 172 and 174 are formed. Similar to the interconnects 162 and 164, the portions of the interconnects 172 and 174 that extend in the lateral direction beyond the openings can be field plates that help affect capacitive coupling within the HEMT.

[0070] A passivation layer 180 is formed on the ILD layer 170 and the interconnects 172 and 174. The passivation layer 180 can include nitride or oxynitride and is a moisture barrier for the electronic device. An insulating layer 190 is formed on the passivation layer 180, and the layers 180 and 190 are etched to define an opening, and a source bond pad 192 is formed within the opening and extends over a portion of the HEMT. Other interconnects and bond pads are formed, and are electrically connected to the drain electrode 154 and the gate electrode 156, but are not shown in FIG. 2. In addition, a metal edge ring seal (not shown) can also be used, and is adjacent to the scribe lanes 108. Figure 2

[0071] Figure 3 ​The diagram includes a cross-sectional view of a portion of a workpiece comprising a vertical insulated-gate field-effect transistor (IGFET). In the illustrated embodiment, the base substrate 102 may comprise a Group 14 element (i.e., carbon, silicon, germanium, or any combination thereof) and may be heavily n-type or p-type doped. For the purposes of this specification, heavily doped is intended to mean at least 1 x 10⁻⁶. 18 Peak dopant concentration per atom per cubic centimeter; light doping is defined as less than 1 x 103 atoms per cubic centimeter. 18 A peak dopant concentration of atoms per cubic centimeter. A lightly doped semiconductor layer 103 covers the base substrate 102. In one embodiment, the lightly doped semiconductor layer 103 may be epitaxially grown from the base substrate 102. In a particular embodiment, the lightly doped semiconductor layer 103 may have the same semiconductor material and conductivity type as the base substrate 102. The lightly doped semiconductor layer may be the drift region of an IGFET.

[0072] A well region 104 is formed within the semiconductor layer 103 and has a conductivity type opposite to that of the base substrate 102. The well region 104 is lightly doped and has a higher peak dopant concentration than the lightly doped semiconductor layer 103. A pad layer 107 covers the well region 104 and may include oxides, nitrides, or oxynitrides. A field isolation region 120 is formed adjacent to the pad layer 107. A doped isolation region 123 may be formed, extending through the well region 104 and into the base substrate 102. The doped isolation region 123 may have a conductivity type opposite to that of the base substrate 102.

[0073] A trench is formed, extending through the pad layer 107 and the well region 104 into a lightly doped semiconductor layer 103. A gate dielectric layer 142 and a gate electrode 144 are formed within the trench. A source region 163 may be formed outside and adjacent to the trench. The source region 163 has a conductivity type opposite to that of the well region 104. The source region 163 is heavily doped and, in a certain embodiment, has at least 1x10⁻⁶ Ω·cm². 19 The doping concentration is 1 atom / cubic centimeter. The portion of the well region 104 along the sidewalls of the trench and between the source region 163 and the lightly doped semiconductor layer 103 is the channel region. The gate electrode 144 is slightly recessed along the trench to reduce gate-source capacitive coupling.

[0074] An ILD layer 200 is formed on a workpiece. The ILD layer 200 may comprise a single film or multiple films. The ILD layer 200 may comprise an oxide film, a nitride film, or an oxide nitride film. In a specific embodiment, the ILD layer 200 may comprise a relatively thin etch stop film, a relatively thick oxide film, and a relatively thin anti-reflective film. Many other variations of the ILD layer 200 are possible, and the ILD layer 200 can be customized for a specific application.

[0075] A contact opening is formed in which a contact is formed to the source region 163. A doping step can be performed to form doped well contact regions 304 that allow an ohmic contact to be formed to the well region 104. The source region 163 has an opposite conductivity type compared to the well region 104, and the doped well contact regions 304 have the same conductivity type compared to the well region 104. A contact opening to the gate electrode 144 can be made during the same or a different patterning sequence; however, the gate electrode 144 is not exposed during this doping operation to form the heavily doped well contact regions 304. An interconnect, such as a source interconnect 363, is formed and extends into the contact opening. The source interconnect 363 is electrically connected to the source region 163 and the doped well contact regions 304, and a gate interconnect (not shown) is electrically connected to the gate electrode 144. A backside metal (not shown in Figure 3 ) can be used as a drain contact that is electrically connected to the base substrate 102.

[0076] A passivation layer 380 is deposited over the ILD layer 200 and the source electrode 363. The passivation layer 380 can include nitride or oxynitride and is a moisture barrier for the electronic device. The passivation layer 380 is etched to define an opening, and a source bond pad 393 and a gate bond pad (not shown) are formed within the opening and extend over a portion of the IGFET. The source bond pad 393 contacts the source interconnect 363, and the gate bond pad contacts the gate interconnect. The features shown are located within the component region 106. A scribe lane 108 (not shown in Figure 3 ) can surround the electronic device including the features in Figure 3 . A backside metal (not shown in Figure 3 ) can be used at a drain contact that is electrically connected to the base substrate 102. In the finished device, current can flow from the base substrate 102, through the semiconductor layer 103, the well region 104, the source region 163, and the source interconnect 363, to the source bond pad 393. Thus, each of these features is a current carrying feature within the electronic device.

[0077] Figure 2 and Figure 3Particular embodiments are shown and used to demonstrate that a wide variety of different electronic devices can be used. While not required, electronic devices used in applications involving high voltages (e.g., at least 50 V), high currents (e.g., at least 1 A), or high power (e.g., at least 1 W) can be well suited to the concepts described herein. During subsequent processing as described in more detail below, all or nearly all of the base substrate 102 is subsequently removed from under the plurality of layers overlying the base substrate 102. The thickness of the base substrate 102, if present in the finished device, is substantially thinner than the thickness of the wafer after a conventional backgrinding operation is performed, e.g., in the range of 75 microns to 200 microns, prior to dicing the wafer into dies.

[0078] Methods of forming electronic devices and resulting electronic devices have been developed that can allow for removal of all or nearly all of the thickness of a base substrate from a component region of the electronic device prior to singulating the electronic device into individual dies. The plurality of layers and the remaining portion of the base substrate 102, if present, can be thinner than the substrate after a conventional backgrinding operation, e.g., less than 75 microns. In one embodiment, the thickness of the plurality of layers can be at most 9 microns when using a method as described in more detail below. A skilled artisan can refer to this processing as wafer-level processing, in contrast to die-level processing. Thus, the base substrate 102 can have a dimension of at least 100 mm along a major surface. The dimension can be a width or a length. In one embodiment, the dimension is a width, and the width can comprise a dimension of a square, a smaller of two dimensions of a non-equilateral rectangle, a diameter of a circle, a minor axis of an ellipse, etc. Other sizes of the base substrate 102 are described previously.

[0079] Figure 4 The base substrate 102, the plurality of layers 400 within the component regions 106, the scribe lanes 108, and the spacer structures 403 are included. The plurality of layers 400 correspond to layers formed on the base substrate 102, such as those layers shown in Figure 2 and Figure 3 , including layers used to form features such as electronic devices or components, electrodes, and interconnects. One or more of the plurality of layers 400 can be removed along the scribe lanes 108 shown in Figure 4 , or one or more of the plurality of layers 400 can be continuous between two component regions 106 and extend across the scribe lanes 108.

[0080] The spacer structures 403 can help determine an end point when a subsequently formed polymer support layer is thinned. The spacer structures 403 are not required in all embodiments, and some embodiments can omit the spacer structures 403.

[0081] Before details about the spacer structure 403 are presented, recommended minimum thicknesses of the polymer support layer for different sizes of the base substrate 102 are provided in Table 1. However, depending on the internal stress of the plurality of layers 400 overlying the base substrate 102, a thicker or thinner polymer support layer can be used. In one embodiment, the thickness of the polymer support layer is measured over the plurality of layers 400.

[0082] Table 1 - Base Substrate Width and Polymer Support Layer Thickness

[0083] Base Substrate Width (mm) 100 150 200 300 400 Polymer Support Layer Thickness (microns) 30 40 50 75 100

[0084] The height of the spacer structure 403 can be at least the same as the recommended thickness of the polymer support layer for a particular width of the base substrate 102. In another embodiment, the height of the spacer structure 403 can be at least 1.2 times or at least 1.5 times the recommended minimum thickness for a particular width of the base substrate 102. While the theoretical upper limit of the height of the spacer structure 403 is unknown, method or device complexity can arise when the height of the spacer structure 403 is too large. In another embodiment, the height of the spacer structure 403 can be at most 5 times, at most 4 times, or at most 3 times the recommended minimum thickness for a particular width of the base substrate 102. In another embodiment, a ball drop sphere can be used for the spacer structure 403 and can be 1 mm or 25 times the recommended minimum thickness in size.

[0085] The spacer structure 403 can comprise a material that is different from the polymer support layer that is subsequently formed. The spacer structure 403 can comprise a material that contains a metal; an inorganic oxide, nitride, or oxynitride; a different polymer than the polymer support layer or an additive to assist end point detection (when the spacer structure 403 and the polymer support layer comprise the same base polymer material).

[0086] In one embodiment, the spacer structures 403 can be electrically conductive members and can be metal or metal alloy. The spacer structures 403 can be plated as electrically conductive bumps that are electrically connected to underlying bond pads, interconnects, etc. within the plurality of layers 400. In another embodiment, electrically conductive solder balls can be placed on the exposed bond pads, interconnects, etc. In another embodiment, the spacer structures 403 can be electrically insulating and located within the scribe lanes 108. In a particular embodiment, an insulating material can be formed within the scribe lanes 108. One or more template masks can be used to form the insulating material within the scribe lanes 108 without significantly affecting the electrical connections to the bond pads, interconnects, etc. that have been formed or will be formed into the component areas 106. In another embodiment, the spacer structures 403 can be in the form of a solid lattice that is positioned such that it is aligned to the scribe lanes 108. A relatively thin adhesive layer can be used to prevent the solid lattice from moving when a polymeric support layer is subsequently formed on the base substrate 102 if needed or desired.

[0087] The amount of area covered by the spacer structures 403 can depend on the location of the spacer structures 403 and the underlying device design. When the spacer structures 403 are formed within the scribe lanes 108 and do not extend or only extend a slight distance into the component areas 106, the spacer structures 403 can cover at most 30% of the area along the front side major surface of the base substrate 102.

[0088] When the spacer structures 403 are electrically conductive, the spacer structures can cover at most 95% of each component area 106. This high level of coverage can occur in power electronic devices that have only a few (e.g., no more than five) electrical connections between the electronic device and external electrical components (e.g., circuit board, lead frame, interposer, etc.). When the electronic device has more external electrical connections, the amount of component area covered by the spacer structures 403 can be lower. A microprocessor, microcontroller, or memory can have substantially more terminals than a power device. Each of the spacer structures 403 can be smaller, and the cumulative area occupied by the spacer structures 403 used for a microprocessor, microcontroller, or memory can be less than 50% of the area of the component area 106. In a particular embodiment, the spacer structures 403 can occupy at least 25% of the area of the component area 106. In another embodiment, different electronic devices can have a number of terminals that is between the number of terminals of a power device and the number of terminals of a microprocessor, microcontroller, or memory. The area occupied by the spacer structures 403 can be at least 5% of the area of the component area 106. In a particular embodiment, the spacer structures 403 can occupy an area in the range of 11% to 30% of the component area 106.

[0089] In Figure 5In particular embodiments, a front polymer support layer 503 can be formed on the base substrate 102, the plurality of layers 400, and the spacer structure 403. The polymer support layer 503, alone or in combination with the spacer structure 403, provides sufficient mechanical support when all or nearly all of the base substrate 102 is subsequently removed. Recommended minimum thicknesses for the polymer support layer 503 for particular sizes of base substrate 102 are provided in Table 1 as previously described. While the upper limit on the thickness of the polymer support layer 503 is unknown in theory, a practical upper limit can be used so that the process is not unnecessarily complicated or so that additional material is not wasted. In one embodiment, the polymer support layer 503 can be at most 500 microns, and in many embodiments, a thickness of at most 300 microns can provide sufficient mechanical support. In other embodiments, the thickness can be at least 50 microns or at least 75 microns.

[0090] The polymer support layer 503 can be formed by compression molding, coating, rolling, or otherwise depositing and curing a polymer precursor to form the polymer support layer 503. The curing can be performed thermally or by other means, such as chemical hardeners or exposure to radiation such as ultraviolet radiation or infrared radiation, and can be performed at atmospheric pressure or higher. In particular embodiments, the polymer precursor can be an overmolding compound used to encapsulate semiconductor devices. The polymer precursor can be an epoxy resin that is cured using heat and pressure higher than atmospheric pressure.

[0091] Depending on the needs or desires of a particular application, different processing flows can be used at this time in the process. In one set of embodiments, the base substrate 102 is removed before the polymer support layer 503 is removed. In another set of embodiments, a portion of the polymer support layer 503 is removed before the base substrate 102 is removed. The following description presents embodiments in which the base substrate 102 is removed relatively early in the processing sequence, followed by embodiments in which the base substrate 102 is removed relatively late in the processing sequence.

[0092] Subsequent processing can or can not involve attaching the workpiece to a temporary support. The temporary support can include a tape substrate and a pressure sensitive adhesive, a glass carrier with an adhesive, an electrostatic chuck, etc. In the case of tape, the materials used for the tape substrate and the pressure sensitive adhesive can depend on the particular application. For example, when the workpiece is attached to a high temperature tape, a grinding operation or a thermal curing operation can be performed. The tape substrate can include polyimide or another material that can withstand temperatures of at least 200 °C, and the pressure sensitive adhesive can include silicone or an acrylic material. If the tape is not exposed to high temperatures, a wider variety of tape substrates and pressure sensitive adhesives can be used. The tape substrate can include polyvinyl chloride, polyethylene terephthalate, polyolefins, and the pressure sensitive adhesive can include polyisobutylene, polyvinyl alcohol, etc. A commercially available dicing tape can be used. KaptonTM Tape includes a variety of tapes for different purposes. After reading this specification, the skilled person will be able to determine whether to use or not use tape or other temporary support, and when used, determine the materials for the tape substrate and pressure sensitive adhesive.

[0093] Referring to Figure 6 , the polymer support layer 503 is attached to the tape 605. The base substrate 102 can have a thickness in the range of 500 microns to 900 microns before any portion of the base substrate 102 is removed along the backside major surface of the workpiece. In one embodiment, the first portion of the removal can be performed using a backside grinding operation. The backside grinding operation can be a standard grind, or in some cases can be a Taiko grind. The first portion of the removal of the base substrate 102 can reduce the thickness of the base substrate 102 such that the thickness is in the range of about 20 microns to 200 microns. The frontside polymer support layer 503 allows for a thinner thickness of the base substrate 102 compared to using a conventional backside grinding operation in the absence of the polymer support layer 503.

[0094] After the backside grinding, the workpiece can be transferred to or mounted onto another tape 705 as needed or desired. In Figure 7 , the remaining portion of the base substrate 102 can be removed using a dry or wet stripping technique that is selective to the layers within the plurality of layers 400. The removal of the remaining portion of the base substrate 102 can be performed using end point detection, timed etch, or a combination of end point detection and timed over-etch.

[0095] After the base substrate 102 is removed, the workpiece can be transferred to another tape 805 as needed or desired, as shown in Figure 8 . A backside polymer support layer 803 is formed along the portion of the workpiece where the base substrate 102 has been removed. The polymer support layer 803 can be formed using any of the materials, thicknesses, and formation techniques as previously described with respect to the frontside polymer support layer 503. The polymer support layer 803 can have the same composition or a different composition compared to the polymer support layer 503. The polymer support layer 803 can have the same thickness or a different thickness compared to the polymer support layer 503. The polymer support layer 803 can be formed using the same formation techniques or different formation techniques compared to the polymer support layer 503.

[0096] Referring to Figure 9 , the workpiece is flipped over and the polymer support layer 803 is attached to the tape 905. A portion of the frontside polymer layer 503 is removed to reduce the thickness of the polymer support layer 503. In one embodiment, grinding is performed to remove the polymer support layer 503 until the spacer structures 403 are exposed. The spacer structures 403, whether within the component region 106 (Figure 9 ) or within the scribe lanes 108, end-of-grinding operation detection can assist. In certain embodiments, commercially available planarizers used in the semiconductor industry can be equipped with diamond drills for grinding operations. Portions of the polymer support layer 503 are removed by other means such as chemical etching, when needed or desired, to allow elevated spacer structures 403. This configuration of the die can be desirable when used in flip-chip packaging.

[0097] When needed or desired, the workpiece can be transferred to another tape 1005, as shown in Figure 10 . The backside polymer support layer 803 is attached to the tape 1005. The workpiece can be cut along the scribe lanes 108 to provide dies each including a component region 106, as shown in Figure 10 .

[0098] Figure 11 A top view of a die 1100 including after cutting. The drain terminal 1101, the source terminal 1103, and the gate terminal 1105 are particular types of spacer structures 403 and are within one of the component regions 106. Other component regions 106 can have the same or different terminals compared to the terminals 1101, 1103, and 1105. The rest of the polymer support layer 503 is positioned along the exposed surface and laterally surrounds the terminals 1101, 1103, and 1105. Each of the dies has a peripheral side 1123. At least one peripheral side of the polymer support layer 503 and at least one peripheral side of the polymer support layer 803 are substantially co-terminus. In Figure 10 and Figure 11 , all peripheral sides of the polymer support layer 503 and all peripheral sides of the polymer support layer 803 are substantially co-terminus. The rest of the polymer support layers 503 and 803 are examples of frontside and backside members, respectively. The die 1100 corresponding to one of the component regions 106 can be attached to a package substrate, an interposer, or a leadframe and further processed.

[0099] In another embodiment shown in Figure 12 , a heat sink module 1301 can be used along the backside major surface of the workpiece. The method for the heat sink module 1301 can start after the base substrate 102 is removed, as shown in Figure 7 . In Figure 12In particular embodiments, the fin module 1301 can include a fin layer 1303 and a fin structure 1305, both of which are thermally conductive. In one embodiment, the fin structure 1305 can be electrically conductive and the fin layer 1303 is electrically insulating. The fin layer 1303 can include AIN and be formed by physical vapor deposition, aerosol deposition, or the like. The fin layer 1303 can have a thickness sufficient to electrically insulate the fin structure 1305 from the plurality of layers. In particular embodiments, the fin structure 1305 can be attached to the fin layer 1303 by a thermally conductive epoxy (not shown).

[0100] In another set of embodiments, the front-side polymer support layer 503 can be thinned prior to thinning the base substrate 102. As previously described and illustrated with respect to Figure 4 and Figure 5 The spacer structure 403 and the polymer support layer 503 can be formed along the front-side major surface of the workpiece. The base substrate 102 can be attached to a tape or other temporary support structure. As previously described and illustrated with respect to Figure 9 The polymer support layer 503 can be removed until the spacer structure 403 is exposed.

[0101] As illustrated in Figure 13 the workpiece is flipped over and the spacer structure 403 and the polymer support layer 503 are attached to a tape or other temporary support structure 1405. Prior to thinning, the base substrate 102 can have a thickness in a range from 500 microns to 900 microns. A removal process is performed to remove a majority of the base substrate 102. The removal process can be any of the removal processes previously described and illustrated with respect to Figure 6 After the removal process, the thickness of the base substrate 102 is in a range from 50 microns to 200 microns.

[0102] After thinning, as illustrated in Figure 14 the workpiece and the tape or other temporary support structure 1405 are optionally attached to a tape 1505. The additional tape 1505 can provide additional mechanical support. As previously described and illustrated with respect to Figure 7 the remaining portion of the base substrate 102 can be removed.

[0103] As illustrated in Figure 15 a back-side polymer support layer 803 can be formed along the portion of the workpiece where the base substrate 102 has been removed. The workpiece can be flipped over and the polymer support layer 803 can be attached to a tape 1605. As previously described and illustrated with respect to Figure 10 the workpiece can be diced to provide dies. At least one of the dies can be substantially the same as the dies illustrated in Figure 11

[0104] ​In another set of embodiments, structural support can be provided within the scribe lanes 108 as well as outside the device region 106. The workpiece can be processed as previously described with respect to Figure 4 Referring to Figure 16 , etching, sawing, laser ablation, etc. can remove portions of the base substrate 102 to define trenches 1703 within the scribe lanes 108. The depth of the trenches 1703 can correspond to the thickness of a subsequently formed polymer support layer along the front side major surface of the workpiece. In one embodiment, the depth of the trenches 1703 can have a depth corresponding to the aforementioned thickness of the polymer support layer 503. In one embodiment, the trenches 1703 can have a depth in the range of 50 microns to 200 microns.

[0105] Referring to Figure 17 and Figure 18 , a front side polymer support layer 1803 is formed on the plurality of layers 400, the spacer structures 403, and within the trenches 1703. The polymer support layer 1803 can include any of the materials described with respect to the polymer support layer 503 and is formed using the described processing techniques. The polymer support layer 1803 can be relatively thinner compared to the polymer support layer 503, measured on the plurality of layers 400, as the portions 1903 of the polymer support layer 1803 within the trenches 1703 provide sufficient mechanical support.

[0106] The workpiece can be flipped over and the polymer support layer 1803 can be attached to a tape or other temporary support (not shown). Portions of the base substrate 102 can be removed to create the workpiece shown in Figure 18 in a similar manner to the methods described and shown previously with respect to Figure 6 and Figure 7 . The plurality of layers 400 are exposed within the device region 106. In one embodiment, the backside grinding operation can use the portions 1903 of the polymer support layer 1803 for end point detection, or to control the depth and across wafer uniformity of the grinding by acting as a grinding stop layer. After grinding, the base substrate 102 between the portions 1903 of the polymer support layer 1803 is selectively removed by using an etching process. The portions 1903 of the polymer support layer 1803 that were previously within the trenches 1703 are now exposed. The portions 1903 can be in the form of a grid along the scribe lanes 108 and between the device regions 106.

[0107] As Figure 19As shown in FIG. 20, a backside polymer support layer 2003 is formed on the plurality of layers 400 and the portion 1903. The polymer support layer 2003 can include any of the materials and thicknesses (measured on the plurality of layers 400) and is formed using the processing techniques described with respect to the polymer support layer 1803. In one embodiment, the polymer support layer 2003 can include the same material or a different material as compared to the polymer support layer 1803, the polymer support layer 2003 can have the same thickness or a different thickness as compared to the polymer support layer 1803, and the polymer support layer 2003 can be formed using the same processing techniques or different processing techniques as compared to the polymer support layer 1803.

[0108] The workpiece can be flipped over and the polymer support layer 2003 can be attached to the tape. The polymer support layer 2003 can be removed using the same processing techniques described and shown with respect to the polymer support layer 1803. Figure 9 The method described and shown thins the polymer support layer 1803 to expose the spacer structure 403. The processing can be as described and shown with respect to the method described and shown in FIG. 19. Figure 10 Continues as shown and described in FIG. 21 to provide a diced die.

[0109] In another embodiment, the spacer structure can not be used. The bond pad can be part of the plurality of layers 400, but the bond pad can be shown separately from the plurality of layers to better illustrate the method. Thus, as shown in FIG. 22, the plurality of layers 400 can be a combination of the bond pad 2103 and the rest of the layers 2101. The bond pad 2103 is substantially thinner than the spacer structure 403. Figure 20 In one embodiment, the bond pad 2103 has a thickness of at least 0.2 microns, and in another embodiment, the bond pad 2103 has a thickness of at most 5 microns. The formation of the polymer support layer 503 and 803 and the removal of the base substrate 102 can be performed as previously described and shown with respect to the method described and shown in FIG. 19. Figures 5 to 8 The removal of the polymer support layer 503 can be performed without using endpoint detection, unlike the method described and shown with respect to the method described and shown in FIG. 19. The removal can be timed or monitored using the capacitance between the bond pad 2103 and the measurement probe or monitoring another electronic parameter. The removal can be performed using forward grinding. After the desired thickness of the polymer support layer 503 is removed, the remaining polymer support layer 503 can have the same or a thinner thickness (measured on the plurality of layers 400) as compared to the thickness described with respect to the method described and shown in FIG. 19. Figure 9 In the embodiment shown in FIG. 20, the remaining portion of the polymer support layer 503 can have a thickness of at least 1 micron or at least 10 microns. Figure 9 Figure 20

[0110] ​​Portions of the remaining polymer support layer 503 overlying the bond pad 2103 can be selectively removed to define an opening 2113 and expose the bond pad 2103. In one embodiment, a excimer laser can be used to ablate the polymer support layer 503 overlying the bond pad 2103. In a particular embodiment, a large area ablation can be achieved using a stencil mask between the energy source and the workpiece. Cutting and subsequent processing of the workpiece can be performed as previously described.

[0111] Modifications can be made to the methods so that they are well suited for applications having backside major surface contact with the remainder of the plurality of layers or base substrate. In the embodiments described below, more details will be seen regarding the plurality of layers.

[0112] In one set of embodiments, some of the base substrate 102 can be retained in the finished device. The plurality of layers 400 includes a device section and an interconnect section. In a particular embodiment, the device section can include a Si-doped layer, an epitaxial layer, a well region, and electronic components within the epitaxial layer or well region. The interconnect section can include one or more interlayer levels, which can each include an interlayer dielectric layer and a conductive layer.

[0113] In a particular set of embodiments, some of the base substrate 102 is retained in the finished electronic device. Figure 21 A cross-sectional view is included after formation of the spacer structure 403. The spacer structure 403 is formed using techniques as previously described with respect to Figure 4 The plurality of layers 400 includes a device section 2205 and an interconnect section 2207. In a particular embodiment, the device section 2205 can include an epitaxial layer, a well region, and electronic components within the epitaxial layer or well region. The interconnect section 2207 can include one or more interlayer levels, which can each include an interlayer dielectric layer and a conductive layer. Portions of the plurality of layers 400 can be removed to define a trench 2209 within the scribe lane 108, thereby exposing portions of the base substrate 102 within the scribe lane 108. The trench 2209 can be formed using any of the techniques as previously described with respect to the trench 1703, as described and shown with respect to Figure 16 .

[0114] As shown in Figure 22 , a frontside polymer support layer 2303 is formed over the spacer structure 403, the plurality of layers 400, and within the trench 2209. The polymer support layer 2303 includes a portion 2309 within the scribe lane 108. The polymer support layer 2303 can include any of the materials as previously described with respect to the polymer support layer 1803 in Figure 17 , have any of the thicknesses previously described, and are formed using any of the techniques previously described.

[0115] As Figure 23 shown in FIG. 39B, the workpiece is flipped over and a portion of the base base 102 is removed. The removal of the base base 102 can be performed using any of the techniques as previously described with respect to Figure 6 and Figure 7 ; however, not all of the base base 102 is removed. After performing the back grinding (see Figure 6 ), an etch can be performed to remove some but not all of the base base 102. In one embodiment, this etch can be performed using end point detection to signal when portions 2309 of the polymer support layer 2303 are exposed, and a timed over-etch can be performed to recess the base base 102 between the raised portions 2309 of the polymer support layer 2303. The raised portions 2309 of the polymer support layer 2303 can help improve the stability of the workpiece. The recessed portions of the base base 102 within the component region 106 can simplify subsequent processing.

[0116] As Figure 24 shown in FIG. 40, a conductive layer 2503 can be formed on the remaining plurality of layers 400 and portions of the polymer support layer 2303. The conductive layer 2503 can be electrically conductive and include a metal or metal alloy. The conductive layer 2503 can include Ni, Au, Cu, Al, etc., and be plated or deposited by physical vapor deposition.

[0117] Figure 25 A workpiece is shown after removal of portions of the conductive layer 2503 that overlaid the raised portions 2309 of the polymer support layer 2303. Some of the raised portions 2309 of the polymer support layer 2303 can also be removed. This removal can be performed using grinding, planing, or polishing techniques. In the embodiment shown, little to no conductive layer 2503 is removed that is located within the recesses defined by the raised portions 2309 of the polymer support layer 2303.

[0118] The workpiece can be flipped over and attached to a tape 2605 to continue front side processing as shown in Figure 26 . A portion of the polymer support layer 2303 can be removed to expose the spacer structure 403, and the workpiece can be cut along the scribe lanes 108 to form a die including the component region 106. Processing operations as previously described with respect to Figure 10 may be used. In another embodiment, the spacer structure 403 can not be used. Bonding pads 2103 and laser ablation operations such as described with respect to Figure 20 may be used.

[0119] In another set of embodiments, a sacrificial layer can be used to better control the removal of the base base 102 without significantly removing the device segments of the plurality of layers 400. Figure 27A cross-sectional view is included after formation of spacer structure 403. The plurality of layers 400 includes a sacrificial layer 2803, a device section 2805, and an interconnect section 2807. Sacrificial layer 2803 can have a different composition than the base substrate 102 and the layers of device section 2805 that contact sacrificial layer 2803. In one embodiment, sacrificial layer 2803 can be an oxide, base substrate 102 can be a Si wafer, and the layers that contact the other side of sacrificial layer 2803 can be a doped Si layer. In particular embodiments, the device section 2805 can include a doped Si layer, an epitaxial layer, a well region, and an electronic component within the epitaxial layer, the well region, or both. The interconnect section 2807 can include one or more interlayer levels, which can each include an interlayer dielectric layer and a conductive layer. Portions of the plurality of layers 400 can be removed to define a trench 2809 within scribe lanes 108, thereby exposing portions of base substrate 102 within scribe lanes 108. As Figure 28 illustrated in FIG. 28B, a polymer support layer 2303 is formed on spacer structure 403 and within trench 2809.

[0120] As Figure 29 illustrated in FIG. 28C, the workpiece is flipped over, and base substrate 102 is removed to expose sacrificial layer 2803. Removal of base substrate 102 can be performed using any of the techniques as previously described with respect to Figure 6 and Figure 7 Removal of base substrate 102 can be performed using any of the techniques as previously described with respect to

[0121] In Figure 30 FIG. 28D, a conductive layer 2503 can be formed on portions of the remaining plurality of layers 400 and polymer support layer 2303. Subsequent processing can be performed to remove portions of conductive layer 2503 between component regions, and the workpiece is diced to form dies. Such processing operations are described and illustrated previously with respect to Figure 25 .

[0122] In another set of embodiments, a through-substrate via can provide contact to the backside of base substrate 102, the plurality of layers 400, or both base substrate 102 and the plurality of layers 400. The starting point can be a workpiece as described and illustrated in Figure 22 FIG. 27A. In Figure 31In this case, a portion of the base substrate 102 can be removed to expose the polymer support layer 2303. Unlike... Figure 23 In the implementation scheme, the base 102 does not need to be recessed, or if it is recessed, it does not need to be recessed. Figure 23 It's so concave.

[0123] exist Figure 32 In this process, a patterned mask layer 3301 can be formed having openings in which a base substrate 102 can be etched to define a trench 3303 extending through a portion of the thickness of the base substrate 102. In another embodiment, the trench 3303 may extend through the entire base substrate 102. Figure 33 In the middle, conductive layer 3403 can be used to fill trench 3303 ( Figure 32 The conductive layer 3403 may comprise any of the materials described previously with respect to conductive layer 2503, and is formed using any of the previously described forming techniques. Details regarding the formation of trench 3303 and the filling of trench 3303 with conductive layer 3403 can be found in U.S. Patent No. 8,981,533, which is incorporated herein by reference in its entirety. For this particular embodiment, no insulating layer is formed to line the trench, such that conductive layer 2503 can form ohmic contact with the portion of base substrate 102 between trenches 3303. The rear main surface of the workpiece can be planarized. Figure 33 As shown, the planarization operation may leave a portion of the conductive layer 3403 on a portion 2309 of the polymer support layer 2303, or may remove the conductive layer 2305 from a portion 2309 of the polymer support layer 2303 to expose a portion 2309 (not shown).

[0124] The workpiece can be flipped and attached to tape 3405 to continue as follows Figure 34 The front-side processing is shown in the diagram. A portion of the polymer support layer 2303 can be removed, and the workpiece can be cut along the scribing groove 108 to form a die including the component region 106. As previously described... Figure 10 The described processing operation. In another embodiment, the spacer structure 403 may not be used. Other methods, such as those related to... Figure 20 The described bonding pad 2013 and laser ablation operation.

[0125] In another embodiment, through-substrate vias can be used to form an electrical connection between a component and the rear main surface of the workpiece within a plurality of layers 400. In this embodiment, an insulating layer may line the trench extending from the rear surface to the component before a conductive layer is formed to fill the trench, such that the component is not electrically shorted to the remainder of the base substrate 102 or another feature within the component region 106.

[0126] After reading this specification, a person skilled in the art will appreciate that many other designs and processing sequences can be used to implement the application's requirements or desires. The embodiments described and illustrated herein are intended to be exemplary and not limiting of the application's scope.

[0127] Embodiments as described herein include a workpiece having a plurality of layers that can not provide sufficient mechanical support on their own during processing operations. Thus, there is no need to retain a relatively thick base substrate prior to dicing the workpiece. Thus, a substrate that is substantially larger than a die can be processed so that only one processing sequence need be performed for many dies that can be diced from the substrate, as opposed to performing a processing sequence for each die, which can be performed more than 100 times. This approach is well suited for electronic devices in which a thick base substrate can not provide optimal electrical properties (e.g., a thick Si substrate under a III-V semiconductor device, or the electrical resistance associated with a drain or collector can be higher as the semiconductor substrate is thicker). Many embodiments can use one or more polymer support layers to ensure that the workpiece has sufficient thickness to allow processing to be performed at the wafer level without a significant risk of the relatively thin device layers being damaged during processing. Spacer structures can be used to assist in ensuring that a sufficient thickness of the polymer support layer is retained, if desired or desired.

[0128] Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. After reading this specification, a person skilled in the art will recognize that those aspects and embodiments are merely exemplary and do not limit the application's scope. Embodiments can be implemented according to any or all of the following items.

[0129] Embodiment 1 : A method can include providing a workpiece having a first major surface and a second major surface opposite the first major surface, wherein the workpiece includes a base substrate and a plurality of layers overlying the base substrate, wherein the plurality of layers are closer to the first major surface than the second major surface. The method can also include forming a polymer support layer along the first major surface of the workpiece. The method can also include removing at least 50% of a thickness of the base substrate within a device region of the workpiece, wherein the device region includes an electronic device, and after removing at least 50% of the thickness of the base substrate, a combined thickness of the workpiece and polymer support layer within the device region is at least 30 microns; and dicing the workpiece into a plurality of dies after removing at least 50% of the thickness of the base substrate.

[0130] Embodiment 2: The method of embodiment 1, wherein the base substrate includes a semiconductor wafer.

[0131] Embodiment 3: The method of embodiment 1, wherein the polymer support layer is permanently attached to the first major surface.

[0132] Embodiment 4: The method of embodiment 1, further comprising forming a spacer structure along the first major surface of the workpiece prior to forming the polymer support layer.

[0133] Embodiment 5: The method of embodiment 4, wherein forming a spacer structure comprises forming a conductive member along the first major surface of the workpiece.

[0134] Embodiment 6: The method of embodiment 4, further comprising removing a portion of the polymer support layer to expose the spacer structure.

[0135] Embodiment 7: The method of embodiment 6, wherein:

[0136] providing the workpiece comprises providing the workpiece, wherein the base substrate is a wafer and has a diameter of at least 200 mm,

[0137] forming the spacer structure comprises forming a conductive member electrically connected to a terminal of the electronic device, wherein the conductive member has a height of at least 30 microns,

[0138] forming the polymer support layer comprises:

[0139] forming a molding compound along the first major surface of the workpiece; and

[0140] curing the molding compound to form the polymer support layer,

[0141] removing the portion of the polymer support layer comprises grinding away the molding compound to expose the conductive member,

[0142] removing at least 50% of a thickness of the base substrate comprises removing at least 80% of the thickness of the base substrate within the component region of the workpiece, wherein after removing the at least 80% of the thickness of the base substrate, a combined thickness of the workpiece and polymer support layer within the component region has a thickness in a range of 75 microns to 300 microns.

[0143] Embodiment 8: The method of embodiment 1, wherein the plurality of layers further comprises a bond pad, and the method further comprises selectively removing a portion of the polymer support layer to expose the bond pad.

[0144] Implementation Scheme 9: The method according to Implementation Scheme 1, the method further comprising forming a heat sink along the second main surface of the workpiece after removing at least 50% of the thickness of the base substrate.

[0145] Implementation Scheme 10: According to the method of Implementation Scheme 1, the plurality of layers include semiconductor layers, the semiconductor layers being current-carrying layers or regions of electronic devices within the component region, or heterojunctions between semiconductor layers within the component region, wherein the heterojunctions have corresponding two-dimensional charge carrier gases.

[0146] Implementation Scheme 11: A method may include providing a workpiece having a first main surface and a second main surface opposite to the first main surface, wherein the workpiece includes a base substrate and a plurality of layers covering the base substrate, wherein the plurality of layers are closer to the first main surface than the second main surface. The method may further include forming a trench along the first main surface of the workpiece, and the trench extending at least to the base substrate; forming a polymer support layer extending into the trench and contacting the base substrate; removing at least a portion of the thickness of the base substrate within a component region to expose the polymer support layer within the trench, wherein the polymer support layer has a height of at least 30 micrometers measured within the trench and after removing at least the portion of the base substrate, and the component region includes electronic devices; and after removing at least a portion of the thickness of the base substrate, cutting the workpiece into a plurality of dies.

[0147] Implementation Scheme 12: The method according to Implementation Scheme 11, wherein the base substrate has a dimension along the main surface of the base substrate, wherein the dimension is at least 100 mm.

[0148] Implementation Scheme 13: The method according to Implementation Scheme 11, wherein the plurality of layers includes a sacrificial layer, and at least a portion of the thickness of the base substrate is removed to expose the sacrificial layer.

[0149] Implementation Scheme 14: The method according to Implementation Scheme 11, wherein at least a portion of the thickness of the base substrate is removed, such that at least a portion of the thickness of the base substrate remains within the component region.

[0150] Implementation Scheme 15: The method according to Implementation Scheme 11 further includes forming a conductive layer along the second main surface of the workpiece before cutting the workpiece.

[0151] Implementation Scheme 16: The method according to Implementation Scheme 15 further includes removing a portion of the conductive layer along the scribing path before cutting the workpiece.

[0152] Embodiment 17: An electronic device can comprise: a plurality of layers having a first major surface and a second major surface opposite the first major surface; a polymeric support layer along the first major surface of the workpiece, wherein within a component region, a combined thickness of polymeric support layer and the plurality of layers is at least 30 micrometers; and a backside member along the second major surface, wherein at least one peripheral side of the polymeric support layer and at least one peripheral side of the backside member are substantially coextensive.

[0153] Embodiment 18: The electronic device of embodiment 17, wherein each of the polymeric support layer and the backside member comprises a molded compound.

[0154] Embodiment 19: The electronic device of embodiment 17, wherein:

[0155] a particular layer within the plurality of layers is a semiconductor layer, and

[0156] the plurality of layers has a cumulative thickness of at most 9 micrometers.

[0157] Embodiment 20: The electronic device of embodiment 17, wherein all respective pairs of peripheral sides of the polymeric support layer and the backside member are substantially coextensive.

[0158] It should be noted that not all of the activities described above in the general description or the examples are required, that a portion of a specific activity can not be required, and that one or more further activities can be performed in addition to those described. Still further, the order in which activities are listed are not necessarily the order in which activities are performed.

[0159] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that can cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims.

[0160] The description and drawings of the embodiments described herein are intended to provide a general understanding of the structure of various embodiments. The description and drawings are not intended to serve as an exhaustive and comprehensive description of all the elements and features of apparatuses and systems using the structures or methods described herein. Separate embodiments can also be provided in combination in a single embodiment, and conversely, various features described in the context of a single embodiment can also be provided separately or in any sub-combination. Furthermore, references to values expressed as ranges include all values within that range. Many other embodiments will be readily apparent to those skilled in the art upon reading the description and drawings. Other embodiments can use and derive from the disclosure, such that structural substitutions, logical substitutions, or additional changes can be made without departing from the scope of the disclosure. The disclosure should therefore be considered as exemplary, rather than limiting.

Claims

1. A method of forming an electronic device, the method comprising: providing a workpiece having a first major surface and a second major surface opposite the first major surface, wherein the workpiece includes: a base substrate comprising a Group 14 single crystal wafer; and a plurality of layers overlying the base substrate, wherein the plurality of layers are closer to the first major surface than to the second major surface and the plurality of layers are part of a high electron mobility transistor; forming a first polymeric support layer along the first major surface of the workpiece; removing at least a portion of the base substrate within a component region of the workpiece to expose a layer within the plurality of layers, wherein a combined thickness of the workpiece and the first polymeric support layer within the component region is at least 30 microns after removing at least a portion of the base substrate; and dicing the workpiece into a plurality of dies after removing at least a portion of the base substrate, wherein a portion of the first polymeric support layer remains in a final electronic device.

2. The method of forming an electronic device of claim 1, further comprising forming a second polymeric support layer along the second major surface after removing at least a portion of the base substrate and before dicing the workpiece.

3. The method of forming an electronic device of claim 2, further comprising reducing a thickness of the first polymeric support layer after forming the second polymeric support layer and before dicing the workpiece.

4. The method of forming an electronic device of claim 2, further comprising: forming a spacer structure over the plurality of layers before forming the first polymeric support layer; and removing at least a portion of the first polymeric support layer after forming the second polymeric support layer and before dicing the workpiece.

5. The method of forming an electronic device of any of claims 1-4, wherein: removing the at least a portion of the base substrate includes performing removal of at least 50% of a thickness of the base substrate using a first removal technique and a second removal technique different from the first removal technique, and the first removal technique is terminated prior to exposing the first polymeric support layer.

6. The method of forming an electronic device of claim 5, wherein: the first removal technique includes lapping a portion of the base substrate and the first removal technique is terminated prior to any material other than the base substrate being exposed along the second major surface of the workpiece, and the second removal technique includes etching the base substrate, wherein etching the base substrate is performed after the first removal technique.

7. A method of forming an electronic device, the method comprising: providing a workpiece having a first major surface and a second major surface opposite the first major surface, wherein the workpiece includes a base substrate and a plurality of layers overlying the base substrate and the plurality of layers are closer to the first major surface than to the second major surface; ​ removing a portion of the plurality of layers to define a trench adjacent the first major surface and extending through the plurality of layers and at least to the base substrate; forming a polymer support layer along the first major surface of the workpiece and within the trench; removing a portion of the base substrate along the second major surface of the workpiece, wherein removing the portion of the base substrate exposes a raised portion of the polymer support layer and forms a remaining portion of the base substrate; forming a conductive layer that contacts the remaining portion of the base substrate and the raised portion of the polymer support layer; and removing a portion of the conductive layer and a portion of the raised portion of the polymer support layer, wherein remaining portions of the conductive layer are spaced apart from each other by remaining portions of the raised portion of the polymer support layer, and after removing the portion of the conductive layer, the remaining portions of the conductive layer are in contact with the remaining portions of the raised portion of the polymer support layer.

8. The method of forming an electronic device of claim 7, wherein forming the conductive layer is performed such that the conductive layer is formed over the raised portion of the polymer support layer.

9. The method of forming an electronic device of claim 7, further comprising: forming a spacer structure along the first major surface of the workpiece prior to forming the polymer support layer, wherein the spacer structure comprises a conductive member; and removing a first major surface portion of the polymer support layer along the first major surface to expose the spacer structure.

10. The method of forming an electronic device of any of claims 7 to 9, wherein after removing the portion of the base substrate, an exposed surface of the remaining portion of the base substrate is recessed to a lower height than a distal surface of the raised portion of the polymer support layer.

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