Bidirectional power device and method of manufacturing the same

Abstract

The application discloses a bidirectional power device and a manufacturing method thereof. The bidirectional power device comprises a semiconductor layer, a first doped region in the semiconductor layer, a plurality of trenches in a first trench region in the first doped region, the first doped region being divided into first-type sub-doped regions and second-type sub-doped regions alternately, a gate dielectric layer covering lower sidewalls of the plurality of trenches in the first trench region, a shielding dielectric layer covering upper sidewalls of the plurality of trenches in the first trench region, and a gate conductor in the plurality of trenches in the first trench region and in contact with the gate dielectric layer and the shielding dielectric layer respectively, the gate conductor comprising a control gate and a shielding gate connected to each other, the control gate being in contact with the gate dielectric layer, and the shielding gate being in contact with the shielding dielectric layer, wherein the thickness of the shielding dielectric layer is inconsistent, and the thickness of at least part of the shielding dielectric layer is greater than the thickness of the gate dielectric layer. The device improves the withstand voltage of the device by setting the thickness of at least part of the shielding dielectric layer to be greater than the thickness of the gate dielectric layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and more specifically, to a bidirectional power device and a method for manufacturing the same. Background Technology

[0002] Bidirectional power devices are widely used in charging devices with secondary charging capabilities. Taking a lithium battery charging and discharging device as an example, when the lithium battery charging and discharging device continuously supplies power to the terminal device to a certain level, it is necessary to prevent the lithium battery from over-discharging to avoid the terminal device stopping operation, and it is also necessary to charge the lithium battery in a timely manner. During the charging process, the lithium battery also needs to supply power to the terminal device, while preventing overcharging of the lithium battery. Therefore, in order to manage and control the charging and discharging state of the lithium battery, a charging and discharging protection circuit with bidirectional switching control of current conduction is usually used.

[0003] like Figure 1 As shown, the initial charge / discharge protection circuit uses two single-cell planar gate NMOS transistors M1 and M2 connected to their drains as bidirectional switches. During charging, a high voltage is applied to the gate G1 of M1, turning M1 on, and a low voltage is applied to the gate G2 of M2, turning M2 off. At this time, the current first flows through the parasitic diode D2 of M2 from its source S2 to its drain, and then from the drain of M1 to its source S1. During discharging, a low voltage is applied to the gate G1 of M1, turning M1 off, and a high voltage is applied to the gate G2 of M2, turning M2 on. At this time, the current first flows through the parasitic diode D1 of M1 from its source S1 to its drain, and then from the drain of M2 to its source S2. However, the planar gate NMOS process requires sufficient area to meet higher voltage withstand requirements, and the device has very low conduction efficiency and high power consumption.

[0004] Therefore, it is hoped that the structure of bidirectional power devices can be further optimized to make them smaller in area and higher in performance. Summary of the Invention

[0005] In view of the above problems, the object of the present invention is to provide a bidirectional power device and a method for manufacturing the same, wherein a trench is used to divide a first doped region into alternating first-type sub-doped regions and second-type sub-doped regions to form the source and drain regions of the bidirectional power device, thereby reducing the device area. Furthermore, by setting at least a portion of the thickness of the shielding dielectric layer to be greater than the thickness of the gate dielectric layer, the breakdown voltage of the device is improved.

[0006] According to an aspect of an embodiment of the present application, a bidirectional power device is provided, comprising: a semiconductor layer; a first doped region in the semiconductor layer; a plurality of trenches in a first trench region in the first doped region, separating the first doped region into alternating first-type sub-doped regions and second-type sub-doped regions; a gate dielectric layer covering lower sidewalls of the plurality of trenches in the first trench region; a shielding dielectric layer covering upper sidewalls of the plurality of trenches in the first trench region; and a gate conductor in the plurality of trenches in the first trench region and in contact with the gate dielectric layer and the shielding dielectric layer, respectively, the gate conductor comprising a control gate and a shielding gate connected in series, the control gate in contact with the gate dielectric layer, and the shielding gate in contact with the shielding dielectric layer, wherein the shielding dielectric layer has a non-uniform thickness, and at least part of the shielding dielectric layer has a thickness greater than that of the gate dielectric layer.

[0007] Optionally, when one of the first-type sub-doped regions and the second-type sub-doped regions is a source region and the other is a drain region, the source region and the drain region can be interchangeable.

[0008] Optionally, in the plurality of trenches in the first trench region, the thickness of the shielding dielectric layer gradually increases or gradually decreases along a direction from an opening of the trench to a bottom of the trench.

[0009] Optionally, the shielding dielectric layer comprises a plurality of step portions connected in series, and in the plurality of trenches in the first trench region, the thickness of the shielding dielectric layer changes in a gradient along a direction from an opening of the trench to a bottom of the trench.

[0010] Optionally, the shielding dielectric layer comprises a first step portion, a second step portion, and a third step portion connected in series, and in the plurality of trenches in the first trench region, the third step portion is close to the opening of the trench, and the thicknesses of the first step portion, the second step portion, and the third step portion decrease in turn.

[0011] Optionally, the thickness of the first step portion ranges from 0.1 μm to 50 μm. The thickness of the second step portion ranges from 0 μm to 30 μm. The thickness of the third step portion ranges from 0 μm to 20 μm. wherein the thickness of the gate dielectric layer is less than the thickness of the first step portion.

[0012] Optionally, a distance from a bottom end of the first step portion to the opening of the trench ranges from 0.1 μm to 50 μm, a distance from a bottom end of the second step portion to the opening of the trench ranges from 0 μm to 30 μm, and a distance from a bottom end of the third step portion to the opening of the trench ranges from 0 μm to 20 μm.

[0013] Optionally, a second trench region of trenches is further included in the semiconductor layer and separated from the first doped region, the gate dielectric layer further covers a lower sidewall of the second trench region of trenches, the shielding dielectric layer further covers an upper sidewall of the second trench region of trenches, the gate conductor is further in the second trench region of trenches and in contact with the gate dielectric layer and the shielding dielectric layer respectively, the first trench region of trenches is in communication with the second trench region of trenches, and the gate conductor in the first trench region of trenches is connected with the gate conductor in the second trench region of trenches.

[0014] Optionally, the first trench region of trenches and the second trench region of trenches have the same structure.

[0015] Optionally, the first trench region of trenches includes a first recess in the first doped region and a second recess in the first doped region and part of the semiconductor layer, the second recess is below the first recess and in communication with the first recess.

[0016] Optionally, the depth of the first recess ranges from 0.1 to 50 μm, and the distance from the bottom of the second recess to the bottom of the first recess ranges from 0.1 to 5 μm.

[0017] Optionally, the shielding dielectric layer is on the sidewall of the first recess, and the gate dielectric layer is on the inner surface of the second recess.

[0018] Optionally, a first contact region is in the first type of sub-doped region, a second contact region is in the second type of sub-doped region, and a third contact region is in the semiconductor layer.

[0019] Optionally, a channel region is in the semiconductor layer and adjacent to the control gate.

[0020] Optionally, a covering dielectric layer is on the surface of the semiconductor layer, and a substrate electrode, a first contact electrode, a second contact electrode, and a gate electrode pass through the covering dielectric layer, the substrate electrode is connected with the third contact region, the first contact electrode is connected with the first contact region, the second contact electrode is connected with the second contact region, and the gate electrode is connected with the gate conductor.

[0021] Optionally, in the case of the bidirectional power device being off, the shielding gate depletes the charge of the first type of sub-doped region and the second type of sub-doped region through the shielding dielectric layer to improve the withstand voltage characteristic of the bidirectional power device.

[0022] According to another aspect of the embodiments of the present application, a method for manufacturing a bidirectional power device is provided, including: forming a first doped region in a semiconductor layer; forming a plurality of trenches of a first trench region in the first doped region, the plurality of trenches of the first trench region separating the first doped region into alternating first-type sub-doped regions and second-type sub-doped regions; forming a gate dielectric layer covering lower sidewalls of the plurality of trenches of the first trench region; forming a shielding dielectric layer covering upper sidewalls of the plurality of trenches of the first trench region; and forming a gate conductor in the plurality of trenches of the first trench region, the gate conductor being in contact with the gate dielectric layer and the shielding dielectric layer, the gate conductor including a control gate and a shielding gate connected in series, the control gate being in contact with the gate dielectric layer, and the shielding gate being in contact with the shielding dielectric layer, wherein a thickness of the shielding dielectric layer is not uniform, and at least part of the shielding dielectric layer has a thickness greater than a thickness of the gate dielectric layer.

[0023] Optionally, when one of the first-type sub-doped regions and the second-type sub-doped regions is a source region and the other is a drain region, the source region and the drain region can be interchangeable.

[0024] Optionally, in the plurality of trenches of the first trench region, the thickness of the shielding dielectric layer gradually increases or gradually decreases in a direction from an opening of the trench to a bottom of the trench.

[0025] Optionally, the shielding dielectric layer includes a plurality of stepped portions connected in series, and in the plurality of trenches of the first trench region, the thickness of the shielding dielectric layer changes in a gradient in a direction from an opening of the trench to a bottom of the trench.

[0026] Optionally, the method further includes forming a plurality of trenches of a second trench region in the semiconductor layer, the plurality of trenches of the second trench region being separated from the first doped region, the gate dielectric layer is further formed on lower sidewalls of the plurality of trenches of the second trench region, the shielding dielectric layer is further formed on upper sidewalls of the plurality of trenches of the second trench region, and the gate conductor is further formed in the plurality of trenches of the second trench region and in contact with the gate dielectric layer and the shielding dielectric layer, the plurality of trenches of the first trench region and the plurality of trenches of the second trench region are in communication, and the gate conductor in the plurality of trenches of the first trench region is connected to the gate conductor in the plurality of trenches of the second trench region.

[0027] Optionally, the plurality of trenches of the first trench region and the plurality of trenches of the second trench region have the same structure.

[0028] Optionally, the step of forming the plurality of trenches of the first trench region comprises: forming a plurality of first recesses in the first doped region; filling a dielectric material in the first recesses; and removing part of the dielectric material in each of the first recesses and part of the first doped region and part of the semiconductor layer under the first recesses via the bottom of each of the first recesses to form a second recess, the bottom of the second recess is in the semiconductor layer, the plurality of trenches of the first trench region is formed by the corresponding first recess and the second recess.

[0029] Optionally, the depth of the first recess ranges from 0.1 to 50 μm, and the distance from the bottom of the second recess to the bottom of the first recess ranges from 0.1 to 5 μm.

[0030] Optionally, after forming the second recess, the step of forming a shielding dielectric layer covering the upper sidewall of the plurality of trenches of the first trench region comprises: forming a first sacrificial layer extending from the bottom of the second recess to the surface of the semiconductor layer and covering part of the dielectric material in the first recess; thinning the dielectric material in the first recess which is not covered by the first sacrificial layer, the dielectric material protected by the first sacrificial layer forms a first step; replacing the first sacrificial layer with a second sacrificial layer, the second sacrificial layer extends from the bottom of the second recess to the surface of the semiconductor layer and covers the first step and part of the dielectric material in the first recess; thinning the dielectric material in the first recess which is not covered by the second sacrificial layer to form a third step, the dielectric material protected by the second sacrificial layer except the first step forms a second step.

[0031] Optionally, the thickness of the first step ranges from: the thickness of the second step ranges from: the thickness of the third step ranges from: wherein the thickness of the gate dielectric layer is less than the thickness of the first step.

[0032] Optionally, the distance from the bottom of the first step to the surface of the semiconductor layer ranges from 0.1 to 50 μm, the distance from the bottom of the second step to the surface of the semiconductor layer ranges from 0 to 30 μm, and the distance from the bottom of the third step to the surface of the semiconductor layer ranges from 0 to 20 μm.

[0033] Optionally, further comprising: forming a first contact region in the first type of sub-doped region; forming a second contact region in the second type of sub-doped region; and forming a third contact region in the semiconductor layer.

[0034] Optionally, a channel region adjacent to the control gate is formed in the semiconductor layer.

[0035] Optionally, a covering dielectric layer is formed on the surface of the semiconductor layer, and a substrate electrode, a first contact electrode, a second contact electrode and a gate electrode are formed through the covering dielectric layer, the substrate electrode being connected with the third contact region, the first contact electrode being connected with the first contact region, the second contact electrode being connected with the second contact region, and the gate electrode being connected with the gate conductor.

[0036] Optionally, in the case where the bidirectional power device is off, the shield gate depletes the charges of the first-type sub-doped region and the second-type sub-doped region through the shield dielectric layer, so as to improve the withstand voltage characteristic of the bidirectional power device.

[0037] According to the bidirectional power device and the manufacturing method thereof provided by the embodiments of the present application, the first doped region is formed in the epitaxial layer, and the first doped region is divided into the first-type sub-doped region and the second-type sub-doped region alternately by the trench, and the first contact region and the second contact region are formed in the first-type sub-doped region and the second-type sub-doped region respectively, so as to form two doped regions of the bidirectional power device, and the two doped regions are the source region and the drain region, and the area of the device is reduced.

[0038] More specifically, generally, the depth of the first doped region is deep, and in order to achieve a deeper doped junction depth, a higher diffusion temperature and a longer diffusion time are required. Therefore, according to the product parameter requirement, the first doped region is formed in the first step of the manufacturing method, which is beneficial to select a suitable doping condition to achieve the product structure and parameter requirement. In the case where the junction depth requirement of the first doped region is shallow, the formation of the first doped region can not be placed in the first step of the manufacturing method, and the first doped region can be annealed together with other doped regions in the annealing process of the subsequent manufacturing method, so as to achieve the junction depth and parameter requirement of the device structure.

[0039] Further, by setting the thickness of the shield dielectric layer to gradually increase from the trench opening to the bottom end of the trench, the part of the shield dielectric layer close to the gate dielectric layer (close to the real gate oxide) is thickened, which can further improve the withstand voltage of the lateral electric field.

[0040] Further, the upper part of the groove provides an adhesion surface of the shielding dielectric layer, the lower part of the groove provides an adhesion surface of the gate dielectric layer, and the control gate and the shielding gate are formed in the lower part and the upper part of the groove respectively, the control gate and the shielding gate contact each other, the control gate is separated from the source region, the drain region and the channel by the gate dielectric layer respectively, the shielding gate and the source region and the drain region are separated by the shielding dielectric layer respectively, the shielding gate depletes the charge of the source region and the drain region through the shielding dielectric layer when the bidirectional power device is cut off, and the withstand voltage characteristic of the device is improved; in the case of conduction of the bidirectional power device, the source region and the drain region and the second doped region and the epitaxial layer provide a low-impedance conduction path.

[0041] Further, in the case of conduction of the bidirectional power device, one of the first contact electrode and the second contact electrode is short-circuited with the substrate electrode connected with the substrate, and the bidirectional selection of the current direction is realized. In the case of short-circuiting of the substrate electrode and the first contact electrode, the current flows from the second contact electrode to the first contact electrode through the second sub-doped region, the channel region and the first sub-doped region in sequence; in the case of short-circuiting of the substrate electrode and the second contact electrode, the current flows from the first contact electrode to the second contact electrode through the first sub-doped region, the channel region and the second sub-doped region in sequence.

[0042] Further, the channel length can be reduced by reducing the width of the groove, and the channel resistance is further reduced.

[0043] Further, the device adopts a longitudinal control gate field structure, fully utilizes the charge balance mechanism, and effectively improves the conduction efficiency and reduces the chip size under the condition of meeting the withstand voltage requirement. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, and are not a limitation on the present application.

[0045] Figure 1 A circuit schematic diagram of a bidirectional power device of the prior art is shown.

[0046] Figure 2 A circuit schematic diagram of a bidirectional power device of the embodiment of the present application is shown.

[0047] Figures 3a to 3p A structural diagram of some stages of a method for manufacturing a bidirectional power device of the embodiment of the present application is shown. DETAILED DESCRIPTION

[0048] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0049] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0050] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".

[0051] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0052] This invention can be presented in various forms, some of which will be described below.

[0053] Figure 2 A circuit diagram of a bidirectional power device according to an embodiment of the present invention is shown.

[0054] The bidirectional power device in this embodiment of the invention is formed from a single transistor and has bidirectional conduction functionality. For example... Figure 2 As shown, the bidirectional power device includes: a substrate Sub, two output terminals S1 and S2 located on the substrate Sub, and two parasitic body diodes D1 and D2. When the output terminal S2 and the substrate Sub are short-circuited, a high voltage is applied to the gate G, which is higher than the threshold voltage of the bidirectional power device, and the bidirectional power device is turned on, with current flowing from the output terminal S1 to the output terminal S2; when the output terminal S1 and the substrate Sub are short-circuited, a high voltage is applied to the gate G, which is higher than the threshold voltage of the bidirectional power device, and the bidirectional power device is turned on, with current flowing from the output terminal S2 to the output terminal S1; when the substrate Sub is connected to zero voltage, a low voltage is applied to the gate G, which is lower than the threshold voltage, and the bidirectional power device is turned off. In this embodiment of the invention, the bidirectional power device is a trench-type device, which can be a metal-oxide-semiconductor field-effect transistor (MOSFET), an IGBT device, or a diode. However, the invention is not limited thereto.

[0055] Figures 3a to 3p The structural diagram of the method for manufacturing the bidirectional power device according to the embodiment of the present application is shown in some stages. It should be noted that the structural diagram of each step disclosed in the embodiment does not necessarily represent a cross section, and can be placed in different areas and directions of the product according to the requirements of the product layout, wherein, the structural diagram only contains four trenches, one source region and one drain region, but the number of the trenches, the source region and the drain region in the actual product can be changed, when one of the first type of sub-doped region and the second type of sub-doped region is used as the source region, and the other is used as the drain region, that is, the source region and the drain region of the structure can be interchanged according to different working occasions. In the specific embodiment, in order to facilitate the understanding of the forming process of the device structure in each step, the main structure of the device is shown in a cross section in the embodiment, but it is not used to limit the claims, and any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the embodiment, therefore, the protection scope of the embodiment should be limited by the scope defined in the claims of the present application.

[0056] In the embodiment, the manufacturing process starts from a semiconductor layer with a specific doping type, such as Figure 3a As shown, the semiconductor layer includes a substrate 101 and an epitaxial layer 110 on the substrate 101, wherein the substrate 101 includes a silicon substrate, a germanium-silicon substrate, a group III-V compound substrate or other semiconductor material substrate known to those skilled in the art, and the silicon substrate is used in the embodiment. More specifically, the silicon substrate used in the embodiment can form a MOS field effect transistor, an IGBT insulated gate field effect transistor, a Schottky diode and other semiconductor devices.

[0057] The semiconductor layer with a specific doping type refers to a N-type or P-type substrate 101 doped with a certain amount of impurities and a N-type or P-type epitaxial layer 110 with a certain resistivity and thickness according to the characteristics of the product. For example, in the case of the bidirectional power device being an NMOS tube, the doping type of the substrate 101 and the epitaxial layer 110 is P-type; in the case of the bidirectional power device being a PMOS, the doping type of the substrate 101 and the epitaxial layer 110 is N-type.

[0058] Further, the first doped region 120 is formed in the epitaxial layer 110, as shown in Figure 3a .

[0059] In this step, the first doped region 120 is formed by using one or more of the injection doping, diffusion source doping and coating doping methods, wherein the injection energy is 20-800KeV, the injection dose is 1E11-1E16cm 2 , and the annealing temperature is 600-1200 degrees.

[0060] In this embodiment, the bidirectional power device has a first trench region 103 and a second trench region 104. A first doped region 120 is located in the first trench region 103, and its doping type is opposite to that of the epitaxial layer 110. For example, when the bidirectional power device is a PMOS transistor, the doping type of the first doped region 120 is P-type, and the doping impurity is typically B+; when the bidirectional power device is an NMOS transistor, the doping type of the first doped region 120 is N-type, and the doping impurity is typically As+ or P+. The first trench region 103 and the second trench region 104 are separated, and the second trench region 104 is located in the epitaxial layer 110.

[0061] Furthermore, first recesses 111a1 to 111d1 are formed in the semiconductor layer, such as... Figure 3b As shown.

[0062] In this step, for example, a barrier layer is first formed on the surface of the epitaxial layer 110 by means of thermal oxidation or deposition. The barrier layer is then selectively removed by photolithography and etching processes to expose the area where trenches need to be made, forming an opening to expose part of the first doped region 120 and the epitaxial layer 110. Then, the semiconductor layer is etched through the opening to form the first recesses 111a1 to 111d1.

[0063] Figure 3b As shown in the cross-sectional view, the first recess 111a1 extends from the surface of the first doped region 120 toward the substrate 101, and its bottom is located in the first doped region 120; the first recesses 111b1 and 111c1 are located on both sides of the first doped region and are adjacent to the first doped region 120, and the first recess 111d1 is located in the epitaxial layer 110 and does not contact the first doped region 120.

[0064] In this embodiment, the width of the first recesses 111a1 to 111d1 is determined based on the product structure and manufacturing capabilities, and the depth h1 of the first recesses 111a1 to 111d1 is determined based on parameters such as the product's withstand voltage. Specifically, the width of the first recesses 111a1 to 111d1 ranges from 0.05 to 5 μm, and the depth h1 ranges from 0.1 to 50 μm. However, this embodiment of the invention is not limited to this, and those skilled in the art can match the depth h1 and width of the first recess according to the product's epitaxial growth, withstand voltage, doping, gate oxide thickness, and other conditions as needed.

[0065] Furthermore, a dielectric material is formed on the surface of the epitaxial layer 110 and in the first recesses 111a1 to 111d1, and the dielectric material is made to fill the first recesses 111a1 to 111d1 to form a first dielectric layer 102, such as... Figure 3c As shown.

[0066] In this step, the material of the first dielectric layer 102 can be undoped silicon dioxide, silicon nitride, silicon oxynitride, or one or more combinations of the above materials. The first dielectric layer 102 can be formed by oxidation growth process, chemical vapor deposition process, or one or more combinations of the above processes, such as LPCVD, SACVD, HTO, SRO.

[0067] In this embodiment, the material of the first dielectric layer 102 is silicon dioxide, and the thickness of the first dielectric layer 102 is determined by the process of filling the trench. The thickness of the first dielectric layer 102 is usually greater than half of the width of the first recess. The portion of the first dielectric layer 102 filled in the first recess will be used as the shielding dielectric layer 151 in the subsequent steps.

[0068] Further, the portion of the first dielectric layer 102 is removed to expose the bottom end of the first recess 111a1 to 111d1, as shown in FIG. 1C. Figure 3d

[0069] In this step, the portion of the first dielectric layer 102 filled in the first recess 111a1 to 111d1 is removed by photolithography and etching process to expose the bottom end of the first recess 111a1 to 111d1. The dielectric material remaining on the sidewall of the first recess 111a1 to 111d1 will form the shielding dielectric layer 151 in the subsequent steps, and the thickness of the shielding dielectric layer 151 is T1, wherein the range of T1 includes

[0070] Further, the second recess 111a2 to 111d2 extending from the bottom end of the first recess 111a1 to 111d1 to the substrate 101 is formed, and the bottom end of the second recess 111a2 to 111d2 is located in the epitaxial layer 110, wherein the first recess 111a1 and the second recess 111a2 form the trench 111a, the first recess 111b1 and the second recess 111b2 form the trench 111b, the first recess 111c1 and the second recess 111c2 form the trench 111c, and the first recess 111d1 and the second recess 111d2 form the trench 111d, as shown in FIG. 1D. Figure 3e

[0071] In this step, the portion of the first doped region 120 and the epitaxial layer 110 located at the bottom end of the first recess 111a1 to 111d1 is removed by etching process to form the second recess 111a2 to 111d2, wherein the depth of the bottom end of the second recess from the bottom end of the first recess is h2, and the range of h2 includes 0.1-5 μm.

[0072] Figure 3e ​​As shown in the sectional view, there are four trenches including trench 111a, trench 111b, trench 111c and trench 111d. The trenches 111a, 111b and 111c are located in the first trench area 103, the bottom of the trenches 111a, 111c and 111d is located in the epitaxial layer 110, and the trench 111d is located in the second trench area 104. Specifically, the trench 111a is located in the first doped area 120, the trench 111b and the trench 111c are located at the boundary of the first doped area 120, and the three trenches separate the first doped area 120 into the first sub-doped area 121 and the second sub-doped area 122. The trench 111d is located in the epitaxial layer 110 and separates the first doped area 120. The trench 111b and the trench 111c are located on both sides of the first doped area 120 and contact it, for example, the trench 111c contacts the second sub-doped area 122, and the trench 111b contacts the first sub-doped area 121. The trench 111c is located between the trench 111a and the trench 111d. In the plane perpendicular to the thickness direction of the substrate 101, the trench 111a, the trench 111b, the trench 111c located in the first trench area 103 and the trench 111d located in the second trench area 104 are connected, for example, sequentially in the shape of "S", but the embodiment of the present application is not limited thereto, and those skilled in the art can separate at least two trenches according to the needs.

[0073] In this embodiment, those skilled in the art can make other settings for the number of trenches located in the first trench area 103 according to the needs, so that the plurality of trenches separate the first doped area 120 into the first sub-doped area 121 and the second sub-doped area 122 alternately.

[0074] Further, the channel area 130 is formed in the epitaxial layer 110 through the plurality of trenches 111 at the bottom, as shown. Figure 3f

[0075] In this step, the channel area 130 is formed at the bottom of the trench 111 by using a zero-angle injection process, for example, to adjust the threshold voltage of the device, wherein the injection energy is 20-800KeV, the injection dose is 1E11-1E16cm 2 , and the annealing temperature is 600-1200 degrees.

[0076] In this embodiment, the channel area 130 contacts the first sub-doped area 121 and the second sub-doped area 122 respectively, and the doping type of the channel area 130 is the same as that of the first sub-doped area 121 and the second sub-doped area 122. For example, in the case of PMOS tube as a bidirectional power device, the doping type of the channel area 130 is P type, and the doping impurity is usually B+; in the case of NMOS as a bidirectional power device, the doping type of the channel area 130 is N type, and the doping impurity is usually As+ or P+. ​

[0077] Further, a first sacrificial layer 203 is formed in the trench 111, as shown in Figure 3g .

[0078] In this step, the trench 111 is filled with undoped silicon dioxide, silicon nitride, silicon oxynitride, or one or more combinations of the above materials, or photoresist, which can be positive or negative, in some other embodiments. In the case where the first sacrificial layer 203 is photoresist, the first sacrificial layer 203 is usually extended from the bottom of the second recess of the trench 111 to the surface of the epitaxial layer 110 and covers part of the first dielectric layer 102 in the first recess of the trench 111 by exposure and development. The depth of the surface of the first sacrificial layer 203 from the surface of the epitaxial layer 110 is h3, where h3 ranges from 0 to 30 μm. The depth h3 needs to be matched with the epitaxial layer, voltage resistance, doping, gate oxide thickness, and other product parameters.

[0079] Further, the first dielectric layer 102 that is not covered by the first sacrificial layer 203 is thinned, and the first dielectric layer 102 that is covered and protected by the first sacrificial layer 203 forms a first step portion 151a, as shown in Figure 3h .

[0080] In this step, the thinning is usually performed by a wet etching process. The dielectric material of the first step portion 151a is retained due to the shielding of the first sacrificial layer 203. After the thinning step is completed, the first sacrificial layer 203 is removed by a wet removal process or a dry or wet photoresist removal process.

[0081] In this embodiment, the thickness T1 of the first step portion 151a ranges from: The distance from the bottom of the first step portion 151a to the surface of the epitaxial layer 110 ranges from 0.1 to 50 μm.

[0082] Further, a second sacrificial layer 204 is formed in the trench 111, as shown in Figure 3i .

[0083] In this step, for example, the trench 111 is filled with undoped silicon dioxide, silicon nitride, silicon oxynitride, or other materials, or one or more combinations of the above materials. In some other embodiments, the trench 111 is filled with photoresist, which can be positive photoresist or negative photoresist. In the case where the material of the second sacrificial layer 204 is photoresist, the second sacrificial layer is usually extended from the bottom end of the second recess of the trench 111 to the surface of the epitaxial layer 110 and covers the first step portion 151a and part of the first dielectric layer 102 in the first recess of the trench 111 by exposure and development. The surface of the second sacrificial layer 204 is at a depth h4 from the surface of the epitaxial layer 110, where h4 ranges from 0 to 20 μm. The depth h4 needs to be matched with the epitaxial layer, voltage resistance, doping, gate oxide thickness, and other product parameters.

[0084] Further, the first dielectric layer 102 that is not covered by the second sacrificial layer 204 is thinned to form a third step portion 151c. The dielectric material covered and protected by the second sacrificial layer 204 in addition to the first step portion 151a forms a second step portion 151b, as shown in Figure 3j

[0085] In this step, for example, the wet etching process is used for thinning. The dielectric material of the first step portion 151a and the second step portion 151b is retained due to the shielding of the second sacrificial layer 204. After the thinning step is completed, the second sacrificial layer 204 is removed by wet removal or dry or wet stripping.

[0086] In this embodiment, the first step portion 151a, the second step portion 151b, and the third step portion 151c constitute a shielding dielectric layer 151. The thickness T2 of the second step portion 151b ranges from: The distance from the bottom end of the second step portion 151b to the surface of the epitaxial layer 110 ranges from 0 to 30 μm. The thickness T3 of the third step portion 151c ranges from: The distance from the bottom end of the third step portion 151c to the surface of the epitaxial layer 110 ranges from 0 to 20 μm.

[0087] In this embodiment, the first dielectric layer 102 after two selective thinning processes has a stepped shape on the sidewall of the first recess 111a and a gradient change in thickness from the surface of the epitaxial layer 110 to the substrate 101: T3 < T2 < T1.

[0088] However, the embodiments of the present application are not limited thereto. Those skilled in the art can make other settings for the number of step portions according to needs, for example, N times of filling of the sacrificial layer and thinning of the first dielectric layer can be performed to make the shielding dielectric layer 151 have multiple stepped thickness changes.

[0089] ​Further, a gate dielectric layer 152 is formed on the inner surface of the second recess 111b, as shown in Figure 3k

[0090] In this step, the material of the gate dielectric layer 152 can be undoped silicon dioxide, silicon nitride, silicon oxynitride, or a combination of one or more of the above materials. The gate dielectric layer 152 can be formed by oxidation growth process, chemical vapor deposition process, or a combination of one or more of the following processes: LPCVD, SACVD, HTO, SRO.

[0091] In this embodiment, the gate dielectric layer 152 is formed by oxidation growth process, and the thickness T4 is determined according to the threshold voltage required by the product, the matching of the trench depth, the well doping concentration, and the junction depth in the device structure, and T4 is less than T1. In this embodiment, the range of T4 includes: During the growth of the gate dielectric layer 152, the channel region 130 can be annealed. In this embodiment, the first recess of the trench 111 and the shielding dielectric layer 151 mainly function as voltage division, and the second recess 111b of the trench 111 and the gate dielectric layer 152 mainly function as channel regulation.

[0092] In this embodiment, the thickness of the shielding dielectric layer 151 is processed in a gradient manner, and the shielding dielectric layer 151 at the bottom (close to the first step portion 151a of the gate dielectric layer 152) is thickened, which can further improve the withstand voltage of the lateral electric field. However, this embodiment is not limited thereto, and those skilled in the art can make other settings to the number of steps of the gradient change of the shielding dielectric layer 151 according to the needs, such as increasing or decreasing.

[0093] In some other embodiments, the thickness of the shielding dielectric layer 151 gradually increases or gradually decreases from the surface of the epitaxial layer 110 to the substrate 101. In some other embodiments, the thickness of the shielding dielectric layer 151 is not uniformly consistent, but as long as the thickness of a part of the shielding dielectric layer 151 is greater than that of the gate dielectric layer 152.

[0094] Further, a gate conductor 153 is formed in the trench 111 and on the first dielectric layer 102, as shown in Figure 3l

[0095] In this step, the conductive material 105 is filled in the trench 111 and on the first dielectric layer 102 by, for example, a deposition process. The conductive material 105 includes in-situ doped polysilicon, and in some other embodiments, undoped polysilicon can be deposited first, and then doped impurities are implanted. The conductive material 105 is used to form the gate conductor 153 in the subsequent steps.

[0096] ​​In the embodiment, the doping type of the gate conductor 153 is P type when the bidirectional power device is PMOS, and is N type when the bidirectional power device is NMOS. The gate conductor 153 includes a control gate and a shield gate connected in series, the shield gate is in contact with the shield dielectric layer 151, and the control gate is in contact with the gate dielectric layer 152.

[0097] Further, the conductive material 105 above the first dielectric layer 102 is removed, as shown in Fig. 2c. Figure 3m

[0098] In this step, the conductive material 105 above the epitaxial layer 110 is removed by using one or more of dry etching, wet etching, and CMP process, so that the first dielectric layer 102 on the surface of the epitaxial layer 110 is exposed.

[0099] Further, the first dielectric layer 102 and the conductive material 105 above the epitaxial layer 110 are removed, as shown in Fig. 2d. Figure 3n

[0100] In this step, the first dielectric layer 102 above the epitaxial layer 110 is removed by using one or more of dry etching, wet etching, and CMP process, so that the surface of the epitaxial layer 110 is exposed, the first dielectric layer 102 remaining in the trench 111 serves as the shield dielectric layer 151, and the conductive material 105 in the trench 111 serves as the gate conductor 153, wherein the part of the conductive material 105 in the bottom of the trench 111 in contact with the gate dielectric layer 152 is the control gate conductor, and the part of the conductive material 105 in the upper half of the trench 111 in contact with the shield dielectric layer 151 is the shield gate conductor.

[0101] In some specific embodiments, the removal of the conductive material above the epitaxial layer 110 usually adopts the CMP plus dry etching process, and can also adopt only the dry etching process. The removal of the first dielectric layer 102 above the epitaxial layer 110 usually adopts the CMP plus wet etching process.

[0102] Further, the first contact region 161 is formed in the first type of sub-doped region 121, the second contact region 162 is formed in the second type of sub-doped region 122, and the third contact region 163 is formed in the epitaxial layer 110, as shown in Fig. 2e. Figure 3n

[0103] In this step, the first type of sub-doped region 121, the second type of sub-doped region 122, and the epitaxial layer 110 are doped by using implantation and diffusion through a photolithographic mask. The implantation energy of the doping process is 20-180 Kev, and the implantation dose is 1E11-1E16 cm 2 .

[0104] ​​​In the embodiment, the doping type of the first contact region 161 and the second contact region 162 is the same as the first type sub-doped region 121, and the doping type of the third contact region 163 is the same as the doping type of the epitaxial layer 110. For example, in the case of a PMOS bidirectional power device, the doping type of the first contact region 161 and the second contact region 162 is P type, and the doping type of the third contact region 163 is N type; in the case of an NMOS bidirectional power device, the doping type of the first contact region 161 and the second contact region 162 is N type, and the doping type of the third contact region 163 is P type. The P type contact region doping commonly uses B+ / BF2+, and the N type contact region doping commonly uses As+and P+.

[0105] Further, the cover dielectric layer 106 is formed on the epitaxial layer 110, and a plurality of contact holes 106a are formed through the cover dielectric layer 106, as shown in FIG. 1C. Figure 3o

[0106] In this step, the cover dielectric layer 106 is formed by a chemical vapor deposition process, which includes one or more combinations of LPCVD, SACVD, HTO, SRO. The material of the cover dielectric layer 106 includes one or more combinations of undoped silicon dioxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, boron and phosphorus co-doped silicon dioxide, undoped polysilicon, silicon nitride, and silicon oxynitride. Then, the contact hole 106a is formed by a photolithography and etching process, wherein the contact hole 106a passes through the cover dielectric layer 106, and the depth h5 of the bottom of the contact hole from the surface of the epitaxial layer 110 ranges from 0.1 μm to 1 μm.

[0107] In the embodiment, the positions of the contact holes 106a correspond to the first contact region 161, the second contact region 162, the third contact region 163, and the trench 111d separating the first type sub-doped region 121 and the second type sub-doped region 122, respectively.

[0108] Further, the substrate electrode 173, the first contact electrode 171, the second contact electrode 172, and the gate electrode 174 are formed through the cover dielectric layer 106, as shown in FIG. 1D. Figure 3n

[0109] ​​In this step, for example, a metal conductive layer is first deposited on the covering medium layer 106, and a photoetching and etching process is used to form the substrate electrode 173, the first contact electrode 171, the second contact electrode 172, and the gate electrode 174. The first contact electrode 171 is connected to the first contact region 161, the second contact electrode 172 is connected to the second contact region 162, the substrate electrode 173 is connected to the third contact region 163, and the gate electrode 174 is connected to the gate conductor 153. The first contact electrode 171 and the second contact electrode 172 are source electrodes and drain electrodes, and can be interchanged.

[0110] In this embodiment, the material of the metal conductive layer can be one or a combination of Ti, TiN, TiSi, W, Al, AlSi, AlCu, AlSiCu, Cu, Ni, etc. The metal etching can be one or a combination of wet etching and plasma etching, to form the substrate electrode 173, the first contact electrode 171, the second contact electrode 172, and the gate electrode 174, and to apply voltage or current through the four electrodes to achieve the performance of the device.

[0111] In this embodiment, the position of the gate electrode 174 corresponds to the trench 111d, but the embodiment of the present application is not limited thereto. Since the plurality of trenches 111a to 111d are connected, the gate conductor 153 in the plurality of trenches 111a to 111d is connected to each other, and therefore the position of the gate electrode 174 can also correspond to the trench 111a and / or the trench 111b and / or the trench 111c.

[0112] Further, the first embodiment of the present application discloses a bidirectional power device and a manufacturing method thereof, and the resistance of the device during use can be minimized and signal interference can be reduced to the maximum by increasing the metal layer and optimizing the wiring method.

[0113] Further, the first embodiment of the present application discloses a bidirectional power device and a manufacturing method thereof, which can be combined with the actual use of the product, and a passivation layer, polyimide, etc. structure is added to protect the device and enhance the reliability.

[0114] Further, the first embodiment of the present application discloses a bidirectional power device and a manufacturing method thereof, which can form the required structure of the product through thinning, back evaporation, etc. post-process to achieve the function.

[0115] Further, the bidirectional power device with bidirectional conduction function realized by the first embodiment of the present application can lead out the gate electrode 174, the substrate electrode 173, the first contact electrode 171, and the second contact electrode 172 from the surface of the semiconductor structure to meet the packaging requirements of chip-scale packaging (CSP).

[0116] Further, the first embodiment of the present application discloses a bidirectional power device and a manufacturing method thereof, which can be applied to power MOSFET, CMOS, BCD, high-power transistor, IGBT and Schottky products.

[0117] According to the bidirectional power device and the manufacturing method thereof provided by the embodiment of the present application, the first doped region is formed in the epitaxial layer, and the first doped region is separated into the first type of sub-doped region and the second type of sub-doped region alternately by the groove, and the first contact region and the second contact region are respectively formed in the first type of sub-doped region and the second type of sub-doped region, so as to form two doped regions of the bidirectional power device, and the two doped regions are the source region and the drain region, thereby reducing the area of the device.

[0118] More specifically, generally, the depth of the first doped region is deep, and in order to achieve a deeper doping junction depth, a higher diffusion temperature and a longer diffusion time are required. Therefore, according to the product parameter requirements, the first doped region is formed in the first step of the manufacturing method, which is beneficial to select appropriate doping conditions to achieve the requirements of product structure and parameters. In the case that the junction depth of the first doped region is shallow, the formation of the first doped region can not be placed in the first step of the manufacturing method, and the first doped region can be annealed together with other doped regions in the subsequent annealing process of other doped regions, so as to achieve the requirements of the junction depth and parameters required by the device structure.

[0119] Further, by setting the thickness of the shielding dielectric layer to gradually increase from the groove opening to the bottom end of the groove, the part of the shielding dielectric layer close to the gate dielectric layer (close to the real gate oxide) is thickened, which can further improve the withstand voltage of the lateral electric field.

[0120] Further, the attachment surface of the shielding dielectric layer is provided at the upper part of the groove, the attachment surface of the gate dielectric layer is provided at the lower part of the groove, the control gate and the shielding gate are respectively formed at the lower part and the upper part of the groove, the control gate and the shielding gate contact each other, the control gate is separated from the source region, the drain region and the channel by the gate dielectric layer, the shielding gate is separated from the source region and the drain region by the shielding dielectric layer, the shielding gate depletes the charge of the source region and the drain region through the shielding dielectric layer when the bidirectional power device is off, thereby improving the withstand voltage characteristics of the device; in the case that the bidirectional power device is on, the source region and the drain region provide a low-impedance conduction path with the second doped region and the epitaxial layer.

[0121] Further, when the bidirectional power device is turned on, the substrate electrode connected with the substrate is short-circuited with one of the first contact electrode and the second contact electrode, thereby realizing bidirectional selection of the current direction. In the case of short-circuiting the substrate electrode with the first contact electrode, the current flows from the second contact electrode to the first contact electrode through the second sub-doped region, the channel region and the first sub-doped region in sequence; in the case of short-circuiting the substrate electrode with the second contact electrode, the current flows from the first contact electrode to the second contact electrode through the first sub-doped region, the channel region and the second sub-doped region in sequence.

[0122] Further, the channel length can be reduced by reducing the width of the trench, thereby reducing the channel resistance.

[0123] Further, the device adopts a longitudinal control gate field structure, fully utilizes the charge balance mechanism, and effectively improves the on-state efficiency and reduces the chip size by reducing the drift region resistance while meeting the voltage withstand requirement.

[0124] The above describes the embodiments of the present application. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present application. The scope of the present application is defined by the appended claims and their equivalents. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present application.

Claims

1. A method for manufacturing a bidirectional power device, comprising: forming a first doped region in a semiconductor layer; forming a plurality of trenches of a first trench region in the first doped region, the plurality of trenches of the first trench region separating the first doped region into alternating first-type sub-doped regions and second-type sub-doped regions; forming a gate dielectric layer covering lower sidewalls of the plurality of trenches of the first trench region; forming a shield dielectric layer covering upper sidewalls of the plurality of trenches of the first trench region; and forming gate conductors in the plurality of trenches of the first trench region in contact with the gate dielectric layer and the shield dielectric layer, respectively, the gate conductors comprising a control gate in contact with the gate dielectric layer and a shield gate in contact with the shield dielectric layer, wherein the shield dielectric layer has a thickness that is not uniform, and at least a portion of the shield dielectric layer has a thickness that is greater than a thickness of the gate dielectric layer. one of the first-type sub-doped regions and the second-type sub-doped regions is a source region, and the other of the first-type sub-doped regions and the second-type sub-doped regions is a drain region.

2. The manufacturing method according to claim 1, wherein, in the plurality of trenches of the first trench region, the thickness of the shield dielectric layer gradually increases or gradually decreases in a direction from an opening of the trench to a bottom of the trench.

3. The manufacturing method according to claim 1, wherein, the shield dielectric layer comprises a plurality of steps connected in sequence, and in the plurality of trenches of the first trench region, the thickness of the shield dielectric layer changes in a gradient in a direction from an opening of the trench to a bottom of the trench.

4. The manufacturing method according to claim 1, wherein, the method further comprises forming a plurality of trenches of a second trench region in the semiconductor layer and separated from the first doped region, 5. The manufacturing method according to claim 1, wherein, the gate dielectric layer is further formed on lower sidewalls of the plurality of trenches of the second trench region, the shield dielectric layer is further formed on upper sidewalls of the plurality of trenches of the second trench region, and the gate conductors are further formed in the plurality of trenches of the second trench region in contact with the gate dielectric layer and the shield dielectric layer, respectively, the plurality of trenches of the first trench region and the plurality of trenches of the second trench region are in communication, and the gate conductors in the plurality of trenches of the first trench region are connected to the gate conductors in the plurality of trenches of the second trench region. the plurality of trenches of the first trench region and the plurality of trenches of the second trench region have the same structure.

6. The manufacturing method according to claim 5, wherein the step of forming the plurality of trenches of the first trench region comprises:

7. The production method according to any one of claims 1 to 6, wherein forming a plurality of first recesses in the first doped region; filling a dielectric material in the first recesses; and removing a portion of the dielectric material in each of the first recesses and a portion of the first doped region and a portion of the semiconductor layer below each of the first recesses through a bottom end of each of the first recesses to form a second recess, a bottom end of the second recess being in the semiconductor layer, the plurality of trenches of the first trench region being formed by the corresponding first recesses and the second recesses. a depth of the first recesses ranges from 0.1 μm to 50 μm, and a distance from the bottom end of the second recess to the bottom end of the first recess ranges from 0.1 μm to 5 μm.

8. The manufacturing method according to claim 7, wherein, the step of forming the shield dielectric layer covering the upper sidewalls of the plurality of trenches of the first trench region after forming the second recess comprises:

9. The manufacturing method according to claim 7, wherein, ​ forming a first sacrificial layer extending from a bottom end of the second recess to the surface of the semiconductor layer and covering part of the dielectric material located in the first recess; thinning the dielectric material located in the first recess not covered by the first sacrificial layer, the dielectric material protected by the first sacrificial layer forming a first step; replacing the first sacrificial layer with a second sacrificial layer extending from a bottom end of the second recess to the surface of the semiconductor layer and covering the first step and part of the dielectric material located in the first recess; thinning the dielectric material located in the first recess not covered by the second sacrificial layer forming a third step, the dielectric material protected by the second sacrificial layer except the first step forming a second step.

10. The manufacturing method according to claim 9, wherein, The thickness of the first step ranges from 20 to 10,000 Å, the thickness of the second step ranges from 20 to 9,000 Å, and the thickness of the third step ranges from 20 to 8,000 Å. The thickness of the gate dielectric layer is less than the thickness of the first step.

11. The manufacturing method according to claim 9, wherein, The distance from the bottom end of the first step to the surface of the semiconductor layer ranges from 0.1 to 50 μm, the distance from the bottom end of the second step to the surface of the semiconductor layer ranges from 0 to 30 μm, and the distance from the bottom end of the third step to the surface of the semiconductor layer ranges from 0 to 20 μm.

12. The manufacturing method of any one of claims 1-6, further comprising: forming a first contact region in the first type of sub-doped region; forming a second contact region in the second type of sub-doped region; and forming a third contact region in the semiconductor layer.

13. The manufacturing method of any one of claims 1-6, further comprising forming a channel region in the semiconductor layer adjacent to the control gate.

14. The manufacturing method of claim 12, further comprising: forming a covering dielectric layer on the surface of the semiconductor layer; and forming a substrate electrode, a first contact electrode, a second contact electrode, and a gate electrode through the covering dielectric layer, the substrate electrode connected to the third contact region, the first contact electrode connected to the first contact region, the second contact electrode connected to the second contact region, and the gate electrode connected to the gate conductor. In the case that the bidirectional power device is off, the shield gate depletes the charge of the first type of sub-doped region and the second type of sub-doped region through the shield dielectric layer to improve the withstand voltage characteristic of the bidirectional power device.

16. A bidirectional power device formed by the manufacturing method of any one of claims 1-15, the bidirectional power device comprising:

15. The production method according to any one of claims 1 to 6, wherein a semiconductor layer; a first doped region in the semiconductor layer; a plurality of trenches of a first trench region in the first doped region separating the first doped region into alternating first type of sub-doped region and second type of sub-doped region; a gate dielectric layer covering a lower sidewall of the plurality of trenches of the first trench region; a shield dielectric layer covering an upper sidewall of the plurality of trenches of the first trench region; and a control gate conductor in the first type of sub-doped region and the second type of sub-doped region. ​ ​ a gate conductor located in the trenches of the first trench region and in contact with the gate dielectric layer and the shield dielectric layer respectively, the gate conductor comprises a control gate and a shield gate connected in series, the control gate is in contact with the gate dielectric layer, and the shield gate is in contact with the shield dielectric layer, wherein the thickness of the shield dielectric layer is inconsistent, and the thickness of at least part of the shield dielectric layer is greater than the thickness of the gate dielectric layer.

17. The bidirectional power device of claim 16, wherein, In the case that one of the first type of sub-doped region and the second type of sub-doped region is a source region, the other of the first type of sub-doped region and the second type of sub-doped region is a drain region.

18. The bidirectional power device of claim 16, wherein, In the trenches of the first trench region, the thickness of the shield dielectric layer gradually increases or gradually decreases along the direction from the opening of the trench to the bottom of the trench.

19. The bidirectional power device of claim 16, wherein, The shield dielectric layer comprises a plurality of step portions connected in series, and in the trenches of the first trench region, the thickness of the shield dielectric layer changes in a gradient along the direction from the opening of the trench to the bottom of the trench.

20. The bidirectional power device of claim 16, wherein, The shield dielectric layer comprises a first step portion, a second step portion and a third step portion connected in series, and in the trenches of the first trench region, the third step portion is close to the opening of the trench, The thickness of the first step portion, the second step portion and the third step portion decreases in turn.

21. The bidirectional power device of claim 20, wherein, The thickness of the first step portion ranges from 20 to 10,000 angstroms, the thickness of the second step portion ranges from 20 to 9,000 angstroms, and the thickness of the third step portion ranges from 20 to 8,000 angstroms. The thickness of the gate dielectric layer is less than the thickness of the first step portion.

22. The bidirectional power device of claim 20, wherein, The distance from the bottom end of the first step portion to the opening of the trench ranges from 0.1 to 50 microns, the distance from the bottom end of the second step portion to the opening of the trench ranges from 0 to 30 microns, and the distance from the bottom end of the third step portion to the opening of the trench ranges from 0 to 20 microns.

23. The bidirectional power device of claim 16, wherein, Further comprising a trench of a second trench region located in the semiconductor layer and separated from the first doped region, The gate dielectric layer also covers the lower sidewall of the trench of the second trench region, the shield dielectric layer also covers the upper sidewall of the trench of the second trench region, and the gate conductor is also located in the trench of the second trench region and in contact with the gate dielectric layer and the shield dielectric layer respectively, The trench of the first trench region and the trench of the second trench region are in communication, and the gate conductor located in the trench of the first trench region is connected with the gate conductor located in the trench of the second trench region.

24. The bidirectional power device of claim 23, wherein, The trench of the first trench region and the trench of the second trench region have the same structure.

25. The bidirectional power device according to any of claims 16-24, wherein, The plurality of trenches of the first trench region comprises: a first recess located in the first doped region; and a second recess located in the first doped region and part of the semiconductor layer, the second recess is located below the first recess and in communication with the first recess.

26. The bidirectional power device of claim 25, wherein, The depth of the first recess ranges from 0.1 to 50 microns, and the distance from the bottom end of the second recess to the bottom end of the first recess ranges from 0.1 to 5 microns.

27. The bidirectional power device of claim 25, wherein, The shield dielectric layer is located on the sidewall of the first recess, and the gate dielectric layer is located on the inner surface of the second recess.

28. The bidirectional power device of any of claims 16-24, wherein, Further comprising: a first contact region in the first type of sub-doped region; a second contact region in the second type of sub-doped region; and a third contact region in the semiconductor layer.

29. The bidirectional power device of any of claims 16-24, wherein, a channel region in the semiconductor layer and adjacent to the control gate.

30. The bidirectional power device of claim 28, wherein, further comprising: a covering dielectric layer on the surface of the semiconductor layer; and a substrate electrode, a first contact electrode, a second contact electrode and a gate electrode through the covering dielectric layer, the substrate electrode connected to the third contact region, the first contact electrode connected to the first contact region, the second contact electrode connected to the second contact region, and the gate electrode connected to the gate conductor. In the case of the bidirectional power device being off, the shield gate depletes the charge of the first type of sub-doped region and the second type of sub-doped region through the shield dielectric layer to improve the withstand voltage characteristic of the bidirectional power device.

31. The bidirectional power device of any of claims 16-24, wherein, ​

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