Semiconductor device and method for forming the same

Abstract

A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) located in the substrate, and an interconnection structure located above the DTC and the substrate. The interconnection structure includes a sealing ring structure electrically contacting the substrate, a first conductive via electrically contacting the DTC, and a first wire electrically coupling the sealing ring structure to the first conductive via.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography and etching processes to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise in each process used and these additional problems should be solved. Summary of the invention

[0004] Some embodiments of the present invention provide a semiconductor device, comprising: a substrate; a deep trench capacitor (DTC) located within the substrate; and an interconnect structure located above the deep trench capacitor and the substrate, the interconnect structure comprising: a sealing ring structure electrically contacting the substrate; a first conductive via electrically contacting the deep trench capacitor; and a first wire electrically coupling the sealing ring structure to the first conductive via.

[0005] Some other embodiments of the present invention provide a semiconductor device, comprising: a substrate; a deep trench capacitor (DTC) located in the substrate; and an interconnect structure located above the deep trench capacitor and the substrate, the interconnect structure comprising: a sealing ring structure electrically contacting the substrate; a first wire electrically contacting the deep trench capacitor; and a second wire electrically coupling the sealing ring structure to the first wire.

[0006] Still other embodiments of the present invention provide a method for forming a semiconductor device, comprising: forming a groove in a substrate; forming a doped region adjacent to the groove in the substrate; forming a deep trench capacitor (DTC) in the groove; and forming an interconnect structure above the deep trench capacitor and the substrate, wherein forming the interconnect structure comprises: forming a sealing ring structure electrically contacting the doped region; forming a first conductive via electrically contacting the deep trench capacitor; and forming a first conductive wire above the first conductive via, the first conductive wire electrically coupling the sealing ring structure to the first conductive via. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figures 1 to 7 Cross-sectional views of various intermediate stages in the fabrication of a semiconductor device wafer are shown in accordance with some embodiments.

[0009] Figure 8 A cross-sectional view of a deposition apparatus according to some embodiments is shown.

[0010] Fig. 9 A cross-sectional view of a semiconductor device wafer is shown in accordance with some embodiments.

[0011] Fig.10 A cross-sectional view of a semiconductor device wafer is shown in accordance with some embodiments.

[0012] Fig.11 is a flow chart illustrating a method of forming a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] Embodiments will be described with reference to a specific context, i.e., the interconnect structure layout of a semiconductor device. The semiconductor device may be composed of an integrated passive device (IPD) including a deep trench capacitor (DTC). However, the embodiments discussed herein may also be applied to other semiconductor devices, such as planar CMOS devices, FinFET devices, etc. The various embodiments discussed herein allow for avoiding burnout and circuit short circuits of various components (such as, for example, DTC) of the semiconductor device caused by a plasma arc during a deposition step for forming an under-bump metal (UBM). In addition, the various embodiments discussed herein allow for increasing capacitor density and improving semiconductor device yield.

[0016] Figures 1 to 7 Cross-sectional views of various intermediate stages of fabrication of a semiconductor device wafer 100 are shown in accordance with some embodiments. Figure 1 A cross-sectional view of an edge portion of a semiconductor device wafer 100 is shown, wherein the sidewall 101 is the edge of the semiconductor device wafer 100. In some embodiments, the semiconductor device wafer 100 includes a substrate 103. The substrate 103 may include, for example, bulk silicon that is doped or undoped, or an active layer of a semiconductor on insulator (SOI) substrate. Typically, an SOI substrate includes a semiconductor material layer such as silicon formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on a substrate such as a silicon or glass substrate. Optionally, the substrate 103 may include: another element semiconductor such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. Other substrates such as multilayer or gradient substrates may also be used.

[0017] In some embodiments, one or more recesses 105 are formed in the substrate 103 (in Figure 1 105). In some embodiments, the substrate 103 may be patterned using suitable photolithography and etching methods to form the groove 105. For example, a photoresist (not shown) may be formed and patterned over the substrate 103, and one or more etching processes (e.g., a dry etching process) may be utilized to remove those portions of the substrate 103 that are desired to be the groove 105. In some embodiments, the groove 105 may have a width W1 between about 100 nm and about 1000 nm. In some embodiments, the groove 105 may have a depth D1 between about 1000 nm and about 5000 nm. In some embodiments, the ratio W1 / D1 is between about 0.02 and about 1. As described in more detail below, a deep trench capacitor (DTC) is formed in the groove 105.

[0018] In some embodiments, one or more doped regions 107 are formed in the substrate 103 ( Figure 1 The doped region 107 may be formed using implantation, thermal diffusion, a combination thereof, or the like. In some embodiments, the doped region 107 is formed by implanting arsenic (As) or phosphorus (P) into the substrate 103. In some embodiments, the implanted dose is about 1E13 ions / cm 2 and about 1E15 ions / cm 2 In some embodiments, the implantation energy is between about 1 KeV and about 10 KeV. In some embodiments, the width W2 of the doped region 107 is between about 50 nm and about 500 nm. In some embodiments, the depth D2 of the doped region 107 is between about 10 nm and about 100 nm. In some embodiments, the ratio W2 / D2 is between about 0.5 and about 50. In some embodiments, the one or more doped regions 107 are formed after forming one or more grooves 105. In other embodiments, the one or more doped regions 107 are formed before forming one or more grooves 105. As described in more detail below, the doped region 107 is formed at the interface between the substrate 103 and a subsequently formed seal ring (SR) structure. The doped region 107 reduces the resistivity of the substrate 103 and reduces or eliminates charge accumulation at the interface between the substrate 103 and the seal ring (SR) structure.

[0019] refer to Figure 2 , in groove 105 (see Figure 1 ) to form a DTC 213 in the substrate 103. In some embodiments, a liner layer 201 is formed over the substrate 103 and along the sidewalls and bottom of the recess 105. In some embodiments, the liner layer 201 may include a dielectric material such as silicon oxide, SiON, SiCON, combinations thereof, and the like, and may be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), combinations thereof, and the like. In some embodiments, the liner layer 201 has a thickness between about 5 nm and about 100 nm. In some embodiments, the liner layer 201 is patterned to expose the top surface of the substrate 103. In some embodiments, the patterning process may include suitable photolithography and etching methods. Figure 2 In the illustrated embodiment, after the patterning process is completed, the liner layer 201 completely covers the doped region 107. In other embodiments, the liner layer 201 may partially cover the doped region 107.

[0020] In some embodiments, after forming the liner layer 201, the grooves 105 (see Figure 1) are formed in the conductive layer 203A-203D and the dielectric layer 205A-205D. The conductive layer 203A-203D may also be referred to as a capacitor electrode 203A-203D. In some embodiments, each conductive layer 203A-203D may include a conductive material such as doped silicon, polysilicon, copper, tungsten, aluminum or copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, etc., and may be formed using plating, physical vapor deposition (PVD), ALD, CVD, combinations thereof, etc. In some embodiments, each conductive layer 203A-203D has a thickness between about 10 nm and about 100 nm. In some embodiments, each dielectric layer 205A-205D may include a high-K dielectric material such as aluminum oxide, zirconium oxide, combinations thereof, multilayers thereof, etc. In an embodiment, each dielectric layer 205A-205D includes a multilayer including two zirconium oxide layers and an aluminum oxide layer between the zirconium oxide layers. In some embodiments, each dielectric layer 205A- 205D has a thickness between about 0.3 nm and about 10 nm.

[0021] In some embodiments, after forming the conductive layer 203A over the liner layer 201, the conductive layer 203A is patterned to expose a portion of the top surface of the liner layer 201. In some embodiments, the patterning process may include suitable photolithography and etching methods. Subsequently, spacers 207A are formed along the opposite sidewalls of the conductive layer 203A. Each spacer 207A may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, a multilayer thereof, and the like. In some embodiments, the spacer 207A is formed by blanket depositing the dielectric material using ALD, CVD, a combination thereof, and anisotropically etching the dielectric material to remove a horizontal portion of the dielectric material. The remaining vertical portion of the dielectric material forms the spacer 207A. In some embodiments, each spacer 207A has a width between about 5nm and about 50nm. Subsequently, a dielectric layer 205A is formed over the conductive layer 203A and the spacer 207A. In some embodiments, the dielectric layer 205A is patterned to remove a portion of the dielectric layer 205 extending beyond the spacer 207A. In some embodiments, the patterning process may include suitable photolithography and etching methods.

[0022] Next, a conductive layer 203B is blanket-formed over the dielectric layer 205A and the substrate 103. The conductive layer 203B is then patterned to expose a portion of the top surface of the dielectric layer 205A. In some embodiments, the patterning process may include suitable photolithography and etching methods. Subsequently, spacers 207B are formed along the opposite sidewalls of the conductive layer 203B. In some embodiments, the spacers 207B may be formed using materials and methods similar to those of the spacers 207A, and are not described again herein. In some embodiments, each spacer 207B has a width between about 5 nm and about 50 nm. Subsequently, a dielectric layer 205B is formed over the conductive layer 203B and the spacers 207B. In some embodiments, the dielectric layer 205B is patterned to remove portions of the dielectric layer 205B that extend beyond the spacers 207B. In some embodiments, the patterning process may include suitable photolithography and etching methods.

[0023] Next, the process steps described above with reference to forming conductive layer 203B, spacer 207B, and dielectric layer 205B are repeated to form conductive layer 203C, spacer 207C, and dielectric layer 205C over dielectric layer 205B and to form conductive layer 203D, spacer 207D, and dielectric layer 205D. In some embodiments, spacers 207C and 207D may be formed using materials and methods similar to those of spacer 207A, and are not described again herein. In some embodiments, each spacer 207C has a width between about 5 nm and about 50 nm. In some embodiments, each spacer 207D has a width between about 5 nm and about 50 nm. Figure 2 In the illustrated embodiment, the DTC 213 includes four capacitor electrodes. In other embodiments, the DTC 213 may include more or less than four capacitor electrodes based on the design requirements of the DTC 213. One of ordinary skill in the art will recognize that the above-described process for forming a DTC is only one method of forming a DTC, and other methods are fully intended to be included within the scope of the embodiments.

[0024] Further references Figure 2 After forming the DTC 213 in the substrate 103, the recess 105 is filled with a dielectric material 209 (see Figure 1 ). In some embodiments, dielectric material 209 may include an oxide such as silicon oxide, a nitride such as silicon nitride, a combination thereof, multiple layers thereof, etc. In some embodiments, dielectric material 209 is patterned to remove portions of dielectric material 209 extending beyond spacer 207D. In some embodiments, the patterning process may include suitable photolithography and etching methods.

[0025] In some embodiments, after the dielectric material 209 is formed and patterned, an etch stop layer (ESL) 211 is formed over the DTC 213. In some embodiments, the ESL 211 may include one or more dielectric material layers. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), oxycarbides (such as SiOC, etc.), carbonitrides (such as SiCN, etc.), carbides (such as SiC, etc.), combinations thereof, etc., and may be formed using spin coating, CVD, plasma enhanced CVD (PECVD), ALD, combinations thereof, etc. In some embodiments, the ESL 211 has a thickness between about 3 nm and about 30 nm. In some embodiments, the ESL 211 is used to help form conductive vias to provide electrical connections to the conductive layers 203A-203D of the DTC 213. The ESL 211 may also be referred to as a contact etch stop layer (CESL).

[0026] refer to Figure 3 After forming the DTC 213, an interconnect structure 301 is formed over the substrate 103 and the DTC 213. In some embodiments, the interconnect structure 301 includes a plurality of dielectric layers and conductive components embedded in the plurality of dielectric layers. Figure 3 In the illustrated embodiment, interconnect structure 301 includes dielectric layer 303A and conductive vias 307A-307E embedded in dielectric layer 303A, dielectric layer 303B and conductive lines 309A-309C embedded in dielectric layer 303B, dielectric layer 303C and conductive vias 311A-311E embedded in dielectric layer 303C, and dielectric layer 303D and conductive lines 313A-313C embedded in dielectric layer 303D. Figure 3 In the illustrated embodiment, the interconnect structure 301 includes four dielectric layers with embedded conductive features. In other embodiments, the interconnect structure 301 may include more or less than four dielectric layers with embedded conductive features based on the design requirements of the interconnect structure 301.

[0027] In some embodiments, dielectric layers 303A-303D may include low-k dielectric materials such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO x C y, spin-on glass, spin-on polymer, silicon carbon material, compounds thereof, composites thereof, combinations thereof, etc., and can be formed by any suitable method, such as spin coating, CVD, PECVD, ALD, combinations thereof, etc. Conductive components (such as conductive vias 307A-307E and 311A-311E and conductive lines 309A-309C and 313A-313C) can be formed using any suitable method, such as a damascene method, etc. In some embodiments, the steps for forming the conductive components include forming openings in the corresponding dielectric layers, depositing one or more barrier / adhesion layers (not shown) in the openings, depositing a seed layer (not shown) over the one or more barrier / adhesion layers, and filling the openings with a conductive material. Chemical mechanical polishing (CMP) is then performed to remove excess material of the one or more barrier / adhesion layers, the seed layer, and the conductive material that fills the openings.

[0028] In some embodiments, one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, etc., and may be formed using PVD, CVD, ALD, combinations thereof, etc. The seed layer may include copper, titanium, nickel, gold, manganese, combinations thereof, etc., and may be formed by plating, ALD, CVD, PVD, sputtering, combinations thereof, etc. The conductive material may include copper, aluminum, tungsten, combinations thereof, alloys thereof, etc., and may be formed using, for example, plating or other suitable methods.

[0029] In some embodiments, the interconnect structure 301 further includes an etch stop layer (ESL) 305A-305C formed between adjacent dielectric layers 303A-303D. The material for the ESL 305A-305C is selected so that the etching rate of the ESL 305A-305C is less than the etching rate of the corresponding dielectric layer 303A-303D. In some embodiments, the etching rate of the ESL 305A is less than the etching rate of the dielectric layer 303B. In some embodiments, the etching rate of the ESL 305B is less than the etching rate of the dielectric layer 303C. In some embodiments, the etching rate of the ESL 305C is less than the etching rate of the dielectric layer 303D. In some embodiments, each ESL 305A-305C may include the same as described above. Figure 2 The materials described are similar to those of ESL 211 and will not be described again here.

[0030] In some embodiments, conductive via 307A extends through dielectric layer 303A, ESL 211, and liner layer 201, and physically contacts doped region 107. Conductive via 307A electrically couples doped region 107 to conductive line 309A. Conductive via 307B extends through dielectric layer 303A, ESL 211, and dielectric layer 205A, and physically contacts conductive layer 203A. Conductive via 307B electrically couples conductive layer 203A to conductive line 309A. Conductive via 307C extends through dielectric layer 303A, ESL 211, and dielectric layer 205C, and physically contacts conductive layer 203C. Conductive via 307C electrically couples conductive layer 203C to conductive line 309A. Conductive via 307D extends through dielectric layer 303A, ESL 211, dielectric material 209, and dielectric layer 205D, and physically contacts conductive layer 203D. Conductive via 307D electrically couples conductive layer 203D to conductive line 309B. Conductive via 307E extends through dielectric layer 303A, ESL 211, dielectric material 209, dielectric layers 205B-205D, conductive layers 203C and 203D, and physically contacts conductive layer 203B. Conductive via 307E electrically couples conductive layer 203B to conductive line 309C. Figure 3 In the illustrated embodiment, the conductive vias 307A-307E extend partially into the respective conductive layers 203A-203D. In other embodiments, one or more conductive vias 307A-307E may extend completely through the respective conductive layers 203A-203D.

[0031] In some embodiments, conductive via 311A ​​extends through dielectric layer 303C and ESL 305B and electrically couples wire 313A to wire 309A. Conductive vias 311B and 311C extend through dielectric layer 303C and ESL 305B and electrically couple wire 313B to wire 309A. Conductive via 311D extends through dielectric layer 303C and ESL 305B and electrically couples wire 313C to wire 309B. Conductive via 311E extends through dielectric layer 303C and ESL 305B and electrically couples wire 313C to wire 309C.

[0032] Further references Figure 3 In some embodiments, some conductive features of the interconnect structure 301 near the edge 101 of the semiconductor device wafer 100 form a seal ring structure 315. Figure 3In the illustrated embodiment, the seal ring structure 315 includes conductive vias 307A and 311A, a conductive line 313A, and a portion of a conductive line 309A. In such an embodiment, the conductive line 309A electrically couples the seal ring structure 315 to the rest of the interconnect structure 301. In some embodiments, by forming the conductive line 309A as a single continuous structure shared between the seal ring structure 315 and the rest of the interconnect structure 301, the number of masks and the number of mask processes used to form the conductive line are reduced. In some embodiments, the seal ring structure 315 extends along the edge 101 of the semiconductor device wafer 100 and surrounds the interior of the semiconductor device wafer 100 in a plan view.

[0033] refer to Figure 4 , contact pads 401A and 401B are formed over interconnect structure 301. Contact pad 401A is in electrical contact with wire 313B. Contact pad 401B is in electrical contact with wire 313C. In some embodiments, contact pads 401A and 401B may include a conductive material such as aluminum, copper, tungsten, silver, gold, combinations thereof, etc. In some embodiments, a conductive material may be formed over interconnect structure 301 using, for example, PVD, ALD, electrochemical plating, chemical plating, combinations thereof, etc. Subsequently, the conductive material is patterned to form contact pads 401A and 401B. In some embodiments, a suitable photolithography and etching method may be used to pattern the conductive material.

[0034] In some embodiments, a passivation layer 403 is formed over the interconnect structure 301 and the contact pads 401A and 401B. In some embodiments, the passivation layer 403 may include one or more non-photo-patternable insulating material layers, one or more photo-patternable insulating material layers, combinations thereof, and the like. The non-photo-patternable insulating material may include silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, and the like, and may be formed using CVD, PVD, ALD, a spin coating process, combinations thereof, and the like. The photo-patternable insulating material may include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), combinations thereof, and the like, and may be formed using a spin coating process, and the like. In some embodiments, the passivation layer 403 has a thickness between about 5 nm and about 50 nm.

[0035] In some embodiments, openings 405A and 405B are formed in passivation layer 403 to expose portions of contact pads 401A and 401B, respectively. In some embodiments, suitable photolithography and etching methods may be used to pattern passivation layer 403. In some embodiments, openings 405A and 405B have a width between about 500 nm and about 5000 nm.

[0036] Figure 5 and Figure 6 The formation of under-bump metal (UBM) 601A and 601B above contact pads 401A and 401B, respectively, is shown. In some embodiments, each UBM 601A and 601B may include multiple conductive material layers, such as titanium layers, copper layers, and nickel layers. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers suitable for forming UBMs 601A and 601B, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold. Any suitable material or material layer that may be used for UBMs 601A and 601B is fully intended to be included within the scope of the present application.

[0037] refer to Figure 5 , a mask layer 501 is formed over the passivation layer 403. In some embodiments, the mask layer 501 includes a photoresist or the like. In some embodiments, the mask layer 501 is patterned to form openings 503A and 503B in the mask layer 501. In some embodiments where the mask layer 501 includes a photoresist, the patterning process may include a suitable photolithography method. The opening 503A exposes the opening 405A in the passivation layer 403. The opening 503B exposes the opening 405B in the passivation layer 403. In some embodiments, the openings 503A and 503B have a width between about 1000 nm and about 5000 nm.

[0038] In some embodiments, after openings 503A and 503B are formed in mask layer 501, conductive layer 505 is formed over the sidewalls and bottom of mask layer 501 and the combined openings including openings 503A and 503B and openings 405A and 405B. In some embodiments, conductive layer 505 includes titanium, copper, nickel, chromium, gold, tungsten, alloys thereof, multilayers thereof, etc., and may be formed using PVD, ALD, CVD, electrochemical plating, chemical plating, combinations thereof, etc. In some embodiments, conductive layer 505 has a thickness between about 5 nm and about 100 nm.

[0039] refer to Figure 6 After forming the conductive layer 505, the mask layer 501 and the portion of the conductive layer 505 formed thereon are removed. The remaining portion of the conductive layer 505 forms UBMs 601A and 601B over the contact pads 401A and 401B, respectively. In some embodiments where the mask layer 501 includes a photoresist, the removal process may include an ashing process followed by a wet cleaning process.

[0040] refer to Figure 7, connectors 701A and 701B are formed above UBMs 601A and 601B, respectively, and are electrically coupled to UBMs 601A and 601B. In some embodiments, each connector 701A and 701B may be a solder ball, a controlled collapse chip connection (C4) bump, a ball grid array (BGA) ball, a microbump, a bump formed by electroless nickel plating-electroless palladium immersion gold technology (ENEPIG), a copper pillar, a combination thereof, or the like. In some embodiments in which connectors 701A and 701B are formed by solder material, a reflow process may be implemented to shape the solder material into a desired bump shape. In some embodiments, after forming connectors 701A and 701B, semiconductor device wafer 100 is cut to form individual semiconductor devices. The cutting process may include sawing, a laser ablation method, an etching process, a combination thereof, or the like. Subsequently, each individual semiconductor device may be tested to identify a known qualified die (KGD) for further processing.

[0041] Figure 8 A cross-sectional view of a deposition apparatus 800 according to some embodiments is shown. In some embodiments, the deposition apparatus 800 is used as described above with reference to Figure 5 The conductive layer 505 is deposited over the semiconductor device wafer 100. In some embodiments, the deposition apparatus 800 is a PVD apparatus that implements a direct current (DC) magnetron sputtering process. In some embodiments, the deposition apparatus 800 includes a chamber 801, which is a vacuum chamber. In some embodiments, a pump 803 is coupled to the chamber 801 to adjust the pressure within the chamber 801. In some embodiments, during the deposition process, the process pressure may be between about 1 mTorr and about 100 mTorr. A chuck 805 is disposed in the chamber 801. The chuck 805 is configured to hold the semiconductor device wafer 100 while depositing the conductive layer 505 over the semiconductor device wafer 100. In some embodiments, the chuck 805 may be an electrostatic chuck, a vacuum chuck, etc. In some embodiments, the chuck 805 may be configured as an anode, and may also be referred to as an anode 805. A shadow edge ring 807 is disposed over the chuck 805 in the chamber 801 and around the semiconductor device wafer 100. In some embodiments, the shadow edge ring 807 protects the chuck 805 during the deposition process.

[0042] In some embodiments, cathode 809 is disposed on chuck 805 so that semiconductor device wafer 100 is between cathode 809 and chuck 805. In some embodiments, cathode 809 includes magnetic array 811. In some embodiments, magnetic array 811 includes one or more magnets. Magnetic array 811 generates a magnetic field in chamber 801. Figure 8The magnetic field is represented by the magnetic field lines 813 in FIG. The target material layer 815 is disposed on the cathode 809 such that the target material layer 815 is between the cathode 809 and the semiconductor device wafer 100. The target material layer 815 includes a material that forms the conductive layer 505 during the deposition process.

[0043] In some embodiments, the voltage source 817 is coupled to the cathode 809 and generates a desired voltage between the cathode 809 and the anode 805. In some embodiments, the voltage source 817 is a DC voltage source. In some embodiments, the voltage source 817 generates a negative voltage between the cathode 809 and the anode 805, such that the negative voltage is between about 50 V and about 350 V, such as about 300 V. In some embodiments, the voltage source 817 has a power between about 0.5 kW and about 50 kW, such as about 1 kW.

[0044] In some embodiments, the gas inlet 819 provides a suitable process gas to the chamber 801. In some embodiments, the suitable process gas includes an inert gas such as He, Ne, Ar, Kr, Xe, Ra, combinations thereof, and the like. In some embodiments, electrons (not shown) accelerated by the voltage generated by the voltage source 817 collide with atoms of the process gas to ionize the atoms and generate a plasma 821 within the chamber 801. The plasma 821 includes ions 823 of the process gas. In some embodiments, the magnetic array 811 captures the plasma 821 near the lower surface of the cathode 809 to form a high-density plasma region 825. The high-density plasma region 825 improves the sputtering efficiency of the ions 823. During the deposition process, the positively charged ions 823 are accelerated toward the target material layer 815 and collide with the target material layer 815. The collision expels atoms 827 of the target material, which are then deposited on the semiconductor device wafer 100 to form the conductive layer 505.

[0045] Further references Figure 5 and Figure 8 During the deposition of the conductive layer 505, charge may accumulate on the shadow edge ring 807, and a potential difference may be generated between the shadow edge ring 807 and the semiconductor device wafer 100. In some embodiments, due to improper spacing between the edge 101 of the semiconductor device wafer 100 and the shadow edge ring 807, an arc 829 is formed between the edge 101 of the semiconductor device wafer 100 and the shadow edge ring 807, and a large current pulse flows through the semiconductor device wafer 100.

[0046] Further references Figure 5 During the arc discharge, the current pulse has a path 507 through the interconnect structure 301 of the semiconductor device wafer 100. Figure 5In the illustrated embodiment, path 507 extends through conductive layer 505, contact pad 401A, conductive line 313B, conductive vias 311B and 311C, conductive line 309A, and conductive via 307A. Along path 507, the current pulse flows to doped region 107, and then flows to substrate 103. By forming doped region 107, the resistivity of substrate 103 is reduced at the interface between conductive via 307A and substrate 103, and no significant charge is accumulated at the interface between conductive via 307A and substrate 103. Therefore, by forming doped region 107, a low resistivity path is formed to allow the current pulse to flow into substrate 103.

[0047] By electrically coupling the seal ring structure 315 to the rest of the interconnect structure 301 using the wire 309A, no significant current flows to the DTC 213 through the conductive vias 307B and 307C. Therefore, no significant charge is accumulated at the interface between the conductive layer 203A of the DTC 213 and the conductive via 307B, and no significant voltage drop is generated across the conductive layer 203A and the pad layer 201. Therefore, the burning of the conductive layer 203A and the pad layer 201 due to a large voltage drop and a short circuit of the DTC 213 is avoided. In addition, no significant charge is accumulated at the interface between the conductive layer 203C of the DTC 213 and the conductive via 307C, and no significant voltage drop is generated across the conductive layer 203C and the dielectric layer 205B. Therefore, the burning of the conductive layer 203C and the dielectric layer 205B due to a large voltage drop and a short circuit of the DTC 213 is avoided.

[0048] Fig. 9 FIG. 9 is a cross-sectional view of a semiconductor device wafer 900 according to some embodiments. Figure 7 The semiconductor device wafer 100 shown in FIG. 1 is similar to the semiconductor device wafer 100 shown in FIG. 1 , and the same components are represented by the same reference numerals, and the description of the same components is not repeated here. In some embodiments, the same components as those in the above reference numerals may be used. Figures 1 to 7The semiconductor device wafer 900 is formed by similar process steps as described above, and the description is not repeated here. Compared with the interconnect structure 301 of the semiconductor device wafer 100, the interconnect structure 901 of the semiconductor device wafer 900 has a different layout. Instead of inserting a single continuous wire 309A between the conductive vias 307A-307C and the conductive vias 311A-311C in the interconnect structure 301, the interconnect structure 901 includes three disconnected wires 903A-903C respectively between the conductive vias 307A-307C and the conductive vias 311A-311C. In addition, instead of the two disconnected wires 313A and 313B in the interconnect structure 301, the interconnect structure 901 includes a single continuous wire 905A. Therefore, the wire 905A electrically couples the sealing ring structure 907 to the rest of the interconnect structure 901.

[0049] In some embodiments, as described above with reference to Figure 5 , Figure 6 and Figure 8 During the formation of the UBMs 601A and 601B, a current pulse flows through the semiconductor device wafer 900 along a path 909 due to arc discharge during the deposition of the conductive layer 505. Fig. 9 In the illustrated embodiment, path 909 extends through conductive layer 505, contact pad 401A, conductive line 905A, conductive via 311A, conductive line 903A, and conductive via 307A. Along path 909, the current pulse flows to doped region 107, and then flows to substrate 103. By forming doped region 107, the resistivity of substrate 103 is reduced at the interface between conductive via 307A, and no significant charge is accumulated at the interface between conductive via 307A and substrate 103. Therefore, by forming doped region 107, a low resistivity path is formed to allow the current pulse to flow into substrate 103.

[0050] By electrically coupling the seal ring structure 907 to the rest of the interconnect structure 901 using the wire 905A, no significant current flows to the DTC 213 through the conductive vias 307B and 307C. Therefore, no significant charge is accumulated at the interface between the conductive layer 203A of the DTC 213 and the conductive via 307B, and no significant voltage drop is generated across the conductive layer 203A and the pad layer 201. Therefore, the burning of the conductive layer 203A and the pad layer 201 due to a large voltage drop and a short circuit of the DTC 213 is avoided. In addition, no significant charge is accumulated at the interface between the conductive layer 203C of the DTC 213 and the conductive via 307C, and no significant voltage drop is generated across the conductive layer 203C and the dielectric layer 205B. Therefore, the burning of the conductive layer 203C and the dielectric layer 205B due to a large voltage drop and a short circuit of the DTC 213 is avoided.

[0051] Fig.10 FIG. 1 shows a cross-sectional view of a semiconductor device wafer 1000 according to some embodiments. In some embodiments, the semiconductor device wafer 1000 and Figure 7 The semiconductor device wafer 100 shown in FIG. 1 is similar to the semiconductor device wafer 100 shown in FIG. 1 , and the same components are represented by the same reference numerals, and the description of the same components is not repeated here. In some embodiments, the same components as those in the above reference numerals may be used. Figures 1 to 7 The semiconductor device wafer 1000 is formed by similar process steps as described above, and will not be described again herein. The interconnect structure 1001 of the semiconductor device 1000 has a different layout compared to the interconnect structure 301 of the semiconductor device wafer 100. Instead of two disconnected wires 313A and 313B in the interconnect structure 301, the interconnect structure 1001 includes a single continuous wire 1003A. Therefore, the wires 1003A and 309A electrically couple the seal ring structure 1005 to the rest of the interconnect structure 1001.

[0052] In some embodiments, as described above with reference to Figure 5 , Figure 6 and Figure 8 During the formation of the depicted UBMs 601A and 601B, current pulses flow through the semiconductor device wafer 1000 along path 1007 due to arcing during deposition of the conductive layer 505. Fig.10 In the illustrated embodiment, path 1007 extends through conductive layer 505, contact pad 401A, conductive line 1003A, conductive vias 311A-311C, conductive line 309A, and conductive via 307A. Along path 1007, the current pulse flows to doped region 107, and then flows to substrate 103. By forming doped region 107, the resistivity of substrate 103 is reduced at the interface between conductive via 307A and substrate 103, and no significant charge is accumulated at the interface between conductive via 307A and substrate 103. Therefore, by forming doped region 107, a low resistivity path is formed to allow the current pulse to flow into substrate 103.

[0053] By electrically coupling the seal ring structure 1005 to the rest of the interconnect structure 1001 using the wires 1003A and 309A, no significant current flows through the conductive vias 307B and 307C to the DTC 213. Therefore, no significant charge is accumulated at the interface between the conductive layer 203A of the DTC 213 and the conductive via 307B, and no significant voltage drop is generated across the conductive layer 203A and the pad layer 201. Therefore, burning of the conductive layer 203A and the pad layer 201 due to a large voltage drop and a short circuit of the DTC 213 is avoided. In addition, no significant charge is accumulated at the interface between the conductive layer 203C of the DTC 213 and the conductive via 307C, and no significant voltage drop is generated across the conductive layer 203C and the dielectric layer 205B. Therefore, burning of the conductive layer 203C and the dielectric layer 205B due to a large voltage drop and a short circuit of the DTC 213 is avoided.

[0054] Further references Figure 7 , Fig. 9 and Fig.10 , the illustrated embodiments have been described in the context of a layout of an interconnect structure for protecting a DTC from arcing during the formation of a UBM. One of ordinary skill in the art will appreciate that the above-described layout of interconnect structures 301, 901, and 1001 may be used to protect other types of devices from arcing during the formation of a UBM. In some embodiments, instead of a DTC, a device such as a planar CMOS device, a FinFET device, or the like may be formed within or on a substrate. In such embodiments, the layout of interconnect structures 301, 901, and 1001 may protect source / drain regions and / or gate stacks of transistor devices (such as FinFET devices or planar transistor devices) from arcing.

[0055] Fig.11 1 is a flow chart showing a method 1100 of forming a semiconductor device according to some embodiments. The method 1100 begins at step 1101, wherein as described above with reference to Figure 1 and Figure 2 As described above, on a substrate (such as Figure 2 Devices (such as Figure 2 In step 1103, as described above with reference to DTC 213. Figure 3 As described above, interconnect structures (such as Figure 3 In step 1105, as shown in the above reference Figure 4 As described above, a contact pad (such as Figure 4 In step 1107, as described above with reference to the contact pads 401A and 401B. Figure 5 and Figure 6 As described above, an under bump metallization (such as Figure 6 In step 1109, as described above with reference to UBM 601A and 601B. Figure 7 As described above, a connector (such as Figure 7 Connectors 701A and 701B shown).

[0056] In an embodiment, a semiconductor device includes: a substrate; a deep trench capacitor (DTC) located in the substrate; an interconnect structure located above the DTC and the substrate, the interconnect structure including: a seal ring structure electrically in contact with the substrate; a first conductive via electrically in contact with the DTC; and a first wire electrically coupling the seal ring structure to the first conductive via. In an embodiment, the semiconductor device also includes a doped region located in the substrate, the doped region electrically in contact with the seal ring structure. In an embodiment, the seal ring structure includes: a second conductive via physically in contact with the doped region and the first wire; and a second wire located above the second conductive via, the second wire being located above the first wire. In an embodiment, the seal ring structure includes: a second conductive via physically in contact with the doped region; and a second wire located above the second conductive via, the second wire being located below the first wire. In an embodiment, the interconnect structure also includes a second wire located above the first wire, the second wire electrically coupling the seal ring structure to the first conductive via. In an embodiment, the interconnect structure also includes a second conductive via electrically in contact with the DTC. In an embodiment, the first wire electrically couples the seal ring structure to the second conductive via.

[0057] In another embodiment, a semiconductor device includes: a substrate; a deep trench capacitor (DTC) located in the substrate; and an interconnect structure located above the DTC and the substrate, the interconnect structure including: a seal ring structure electrically in contact with the substrate; a first wire electrically in contact with the DTC; and a second wire electrically coupling the seal ring structure to the first wire. In an embodiment, the second wire is between the first wire and the DTC. In an embodiment, the first wire is between the second wire and the DTC. In an embodiment, the interconnect structure also includes a first conductive via electrically coupling the first wire to the second wire. In an embodiment, the semiconductor device also includes a doped region located in the substrate, the doped region being in physical contact with the seal ring structure. In an embodiment, the seal ring structure includes: a first conductive via, the first conductive via being in physical contact with the doped region; and a second conductive via located above the first conductive via, the second conductive via being in physical contact with the first wire. In an embodiment, the seal ring structure includes: a first conductive via, the first conductive via being in physical contact with the doped region; and a second conductive via located above the first conductive via, the second conductive via being in physical contact with the second wire.

[0058] In yet another embodiment, a method includes: forming a groove in a substrate; forming a doped region adjacent to the groove in the substrate; forming a deep trench capacitor (DTC) in the groove; and forming an interconnect structure above the DTC and the substrate, wherein forming the interconnect structure includes: forming a seal ring structure electrically in contact with the doped region; forming a first conductive via electrically in contact with the DTC; and forming a first conductive wire above the first conductive via, the first conductive wire electrically coupling the seal ring structure to the first conductive via. In an embodiment, forming the interconnect structure also includes forming a second conductive wire above the first conductive wire. In an embodiment, forming the interconnect structure also includes forming a second conductive wire between the first conductive via and the first conductive wire. In an embodiment, forming the interconnect structure also includes forming a second conductive via electrically in contact with the DTC. In an embodiment, forming the DTC in the groove includes forming a plurality of conductive layers and a plurality of dielectric layers in the groove in an alternating manner. In an embodiment, forming the doped region in the substrate includes performing an implantation process on the substrate.

[0059] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: substrate; a deep trench capacitor (DTC) disposed within the substrate; as well as An interconnect structure, located above the deep trench capacitor and the substrate, the interconnect structure comprising: a sealing ring structure in electrical contact with the substrate; a first conductive via in electrical contact with the deep trench capacitor; and A first conductive line electrically couples the sealing ring structure to the first conductive via, wherein a portion of the first conductive line is a portion of the sealing ring. 2 . The semiconductor device according to claim 1 , further comprising a doped region in the substrate, the doped region being in electrical contact with the seal ring structure.

3. The semiconductor device according to claim 2, wherein: The sealing ring structure comprises: a second conductive via, the second conductive via being in physical contact with the doped region and the first conductive line; and The second conductive wire is located above the second conductive through hole, and the second conductive wire is located above the first conductive wire.

4. The semiconductor device according to claim 2, wherein: The sealing ring structure comprises: a second conductive via in physical contact with the doped region; and The second conductive line is located above the second conductive through hole, and the second conductive line is located below the first conductive line.

5. The semiconductor device according to claim 2, wherein: The interconnect structure also includes a second conductive line located above the first conductive line, the second conductive line electrically coupling the seal ring structure to the first conductive via.

6. The semiconductor device according to claim 1, wherein The interconnect structure also includes a second conductive via in electrical contact with the deep trench capacitor.

7. The semiconductor device according to claim 6, wherein: The first conductive line electrically couples the seal ring structure to the second conductive via.

8. A semiconductor device comprising: substrate; a deep trench capacitor (DTC) disposed within the substrate; as well as An interconnect structure, located above the deep trench capacitor and the substrate, the interconnect structure comprising: a sealing ring structure in electrical contact with the substrate; a first conductive line in electrical contact with the deep trench capacitor; a second wire electrically coupling the sealing ring structure to the first wire; and A contact pad is located above the interconnect structure, the contact pad is electrically coupled to the substrate through the sealing ring structure, and the contact pad is in physical contact with the first conductive line or the second conductive line.

9. The semiconductor device according to claim 8, wherein: The second conductive line is between the first conductive line and the deep trench capacitor.

10. The semiconductor device according to claim 8, wherein The first conductive line is interposed between the second conductive line and the deep trench capacitor.

11. The semiconductor device according to claim 8, wherein The interconnect structure also includes a first conductive via that electrically couples the first conductive line to the second conductive line. 12 . The semiconductor device of claim 8 , further comprising a doped region in the substrate, the doped region being in physical contact with the seal ring structure.

13. The semiconductor device according to claim 12, wherein: The sealing ring structure comprises: a first conductive via, the first conductive via being in physical contact with the doped region; and The second conductive via is located above the first conductive via, and the second conductive via is in physical contact with the first conductive line.

14. The semiconductor device according to claim 12, wherein: The sealing ring structure comprises: a first conductive via, the first conductive via being in physical contact with the doped region; and The second conductive via is located above the first conductive via, and the second conductive via is in physical contact with the second conductive wire.

15. A method of forming a semiconductor device, comprising: forming a groove in a substrate; forming a doped region in the substrate adjacent to the recess; forming a deep trench capacitor (DTC) in the groove; as well as An interconnect structure is formed over the deep trench capacitor and the substrate, wherein forming the interconnect structure comprises: forming a sealing ring structure in electrical contact with the doped region; forming a first conductive via in electrical contact with the deep trench capacitor; and A first conductive line is formed over the first conductive via, the first conductive line electrically coupling the seal ring structure to the first conductive via, wherein a portion of the first conductive line is a portion of the seal ring.

16. The method according to claim 15, wherein: Forming the interconnect structure also includes forming a second conductive line over the first conductive line.

17. The method according to claim 15, wherein: Forming the interconnect structure also includes forming a second conductive line between the first conductive via and the first conductive line.

18. The method according to claim 15, wherein: Forming the interconnect structure also includes forming a second conductive via in electrical contact with the deep trench capacitor.

19. The method according to claim 15, wherein: Forming the deep trench capacitor in the recess includes forming a plurality of conductive layers and a plurality of dielectric layers in the recess in an alternating manner.

20. The method according to claim 15, wherein: Forming the doped region in the substrate includes performing an implantation process on the substrate.

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