Semiconductor package structure

Abstract

The present invention discloses a semiconductor packaging structure, comprising: an antenna device, including: a conductive pattern layer, including a first antenna element, formed in an insulating substrate and adjacent to a first surface of the insulating substrate; a second antenna element, formed on a second surface of the insulating substrate opposite to the first surface; and a semiconductor package, including: a redistribution layer structure, bonded and electrically connected to the conductive pattern layer; a first semiconductor die, electrically connected to the redistribution layer structure; and a sealing layer, formed on the redistribution layer structure and surrounding the first semiconductor die. In this way, the semiconductor package is disposed outside the insulating substrate, so that the thickness of the insulating substrate with an antenna can be reduced, and the size of the semiconductor packaging structure and the loss from the die to the antenna can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor package structure. Background Art

[0002] To ensure the continuous miniaturization and multifunctionality of electronic products and communication devices, semiconductor packages must be small in size, support multi-pin connections, operate at high speeds, and have high functionality. In addition, in high-frequency applications such as radio frequency (RF) system-in-package (SiP) components, antennas are typically used to enable wireless communication.

[0003] When constructing a wireless communication package with an antenna, the package design needs to provide good antenna characteristics (such as high efficiency, wide bandwidth, etc.), while providing a reliable and low-cost package solution. In a conventional semiconductor package structure, a substrate-based antenna is bonded to a chip. Since the substrate-based antenna is relatively thick, it is difficult to reduce the package size, and there is a high antenna loss between chips due to the long trace length. Moreover, the substrate-based antenna provides poor thermal performance due to the long heat dissipation path of the chip bonded thereto. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor package structure to solve the above problems.

[0005] According to a first aspect of the present invention, a semiconductor package structure is disclosed, including:

[0006] An antenna device, including: a conductive pattern layer including a first antenna element formed in an insulating substrate and adjacent to a first surface of the insulating substrate; a second antenna element formed on a second surface of the insulating substrate opposite to the first surface; and

[0007] A semiconductor package, including: a redistribution layer structure bonded and electrically connected to the conductive pattern layer; a first semiconductor die electrically connected to the redistribution layer structure; and a sealing layer formed on the redistribution layer structure and surrounding the first semiconductor die.

[0008] According to a second aspect of the present invention, a semiconductor package structure is disclosed, including:

[0009] A redistribution layer structure having a first surface and a second surface opposite to the first surface;

[0010] A first semiconductor die having an active surface formed on the first surface of the redistribution layer structure;

[0011] A first electrical connector is formed on the second surface of the redistribution layer structure;

[0012] An insulating substrate having a first surface is stacked on the second surface of the redistribution layer structure;

[0013] A conductive pattern layer including a first antenna element is formed in the insulating substrate and adjacent to the first surface of the insulating substrate;

[0014] A second antenna element is formed on the second surface of the insulating substrate opposite to the first surface of the insulating substrate; and

[0015] A second electrical connector is formed on the first surface of the insulating substrate and electrically connected to the first antenna element, wherein the size of the second electrical connector is larger than the size of the first electrical connector.

[0016] The semiconductor package structure of the present invention includes an antenna device, comprising: a conductive pattern layer including a first antenna element formed in an insulating substrate and adjacent to the first surface of the insulating substrate; a second antenna element formed on the second surface of the insulating substrate opposite to the first surface; and a semiconductor package including: a redistribution layer structure bonded and electrically connected to the conductive pattern layer; a first semiconductor die electrically connected to the redistribution layer structure; and a sealing layer formed on the redistribution layer structure and surrounding the first semiconductor die. In this way, the semiconductor package is disposed outside the insulating substrate, thereby reducing the thickness of the insulating substrate with an antenna, and reducing the size of the semiconductor package structure and the loss from the die to the antenna. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments.

[0018] Figure 2 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments.

[0019] Figure 3 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments.

[0020] Figure 4 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments. DETAILED DESCRIPTION

[0021] The following description is the best contemplated mode for carrying out the invention. This description is for the purpose of illustrating the general principles of the invention and should not be taken as restrictive. The scope of the invention is defined by the appended claims.

[0022] The present invention will be described with respect to specific embodiments and with reference to certain drawings, but the present invention is not limited thereto and is only limited by the claims. The described drawings are merely illustrative and not restrictive. In the drawings, for purposes of illustration, the sizes of some elements may be enlarged and not drawn to scale. In the practice of the present invention, the sizes and relative sizes do not correspond to actual sizes.

[0023] Figure 1 is a cross-sectional view of an exemplary semiconductor package structure 10 according to some embodiments. In some embodiments, the semiconductor package structure 10 is a wafer-level semiconductor package structure and is a flip-chip semiconductor package structure. The semiconductor package structure 10 may be mounted on a base (not shown). For example, the semiconductor package structure 10 may be a system-on-chip (SOC) package structure. Moreover, the base may include a printed circuit board (PCB) and may be formed of polypropylene (PP).

[0024] Alternatively, the base is a package substrate. The semiconductor package structure 10 is mounted on the base by a bonding process. For example, the semiconductor package structure 10 includes an electrical connector 150 that is mounted on the base by a bonding process and is electrically coupled to the base. As Figure 1 shown, in some embodiments, each electrical connector 150 includes a conductive bump structure, such as a copper bump or a solder ball. Alternatively, each electrical connector 150 includes a conductive pillar structure, a wire structure, or a conductive paste structure.

[0025] In some embodiments, as Figure 1 shown, the semiconductor package structure 10 further includes a semiconductor package 110a, an electrical connector 140, and an antenna device 130 stacked and mounted on the semiconductor package 110a below via the electrical connector 140. In some embodiments, each electrical connector 140 includes a conductive bump structure, such as a copper bump or a solder ball. Optionally, each electrical connector 140 includes a conductive pillar structure, a wire structure, or a conductive paste structure. In some embodiments, the electrical connector 140 and the electrical connector 150 are solder balls, and the size (such as height or volume, etc.) of the electrical connector 140 is different from (e.g., smaller than) the size of the electrical connector 150. For example, the height H1 of the electrical connector 140 is lower than the height H2 of the electrical connector 150, as Figure 1 shown.

[0026] In some embodiments, the semiconductor package 110a includes a semiconductor die 100. For example, the semiconductor die 100 is a system-on-chip (SOC) die, which may include a microcontroller (MCU), a microprocessor (MPU), a power management integrated circuit (PMIC), a global positioning system (GPS) device, or a radio frequency (RF) device, or any combination thereof.

[0027] The semiconductor die 100 has two opposite sides. More specifically, the semiconductor die 100 has an active surface 100a and a non-active surface 100b opposite to the active surface 100a. The non-active surface 100b may also be referred to as the rear surface, and the active surface 100a may also be referred to as the front surface opposite to the rear surface. In some embodiments, the semiconductor die 100 includes pads 101, which are disposed on the active surface 100a and electrically connected to one or more functional circuits (not shown) of the semiconductor die 100. In some embodiments, the pads 101 of the semiconductor die 100 belong to the top metal layer of the interconnect structure (not shown) of the semiconductor die 100.

[0028] In some embodiments, the semiconductor package 110a of the semiconductor package structure 10 includes a redistribution layer (RDL) structure 102 having a first surface 102a and a second surface 102b opposite to the first surface 102a. The RDL structure 102 is also referred to as a fan-out RDL structure. In some embodiments, the RDL structure 102 is disposed on the active surface 100a of the semiconductor die 100 and is electrically connected to the semiconductor die 100 through the pads 101 of the semiconductor die 100.

[0029] In some embodiments, the RDL structure 102 includes one or more conductive traces disposed in an inter-metal dielectric (IMD) layer. For example, a first conductive trace is disposed in a first tier of the IMD layer adjacent to the first surface 102a of the RDL structure 102. At least one of the first conductive traces is electrically coupled to the semiconductor die 100. A conductive trace is disposed at a second tier above the first tier of the IMD layer and adjacent to the second surface 102b of the RDL structure 102. Additionally, at least one of the second conductive traces is bonded and electrically coupled to one or more electrical connectors 140 such that the electrical connectors 140 are electrically coupled to the semiconductor die 100 through the RDL structure 102.

[0030] The IMD layer may include a first sub-dielectric layer and a second sub-dielectric layer stacked continuously from the active surface 100a of the semiconductor die 100, thereby forming the first conductive trace in the first sub-dielectric layer and the second conductive trace in the second sub-dielectric layer. In some embodiments, the IMD layer is formed of an organic material (which includes a polymer base material), a non-organic material (which includes silicon nitride (SiNX), silicon oxide (SiOX), graphene, etc.). For example, the first sub-dielectric layer and the second sub-dielectric layer may be made of a polymer base material. In some other embodiments, the IMD layer is made of a high-k (k is the dielectric constant of the dielectric layer) dielectric layer.

[0031] It should be noted that Figure 1 the number of conductive traces of the illustrated RDL structure 102 and the number of sub-dielectric layers are merely examples and are not limited to what is disclosed in the embodiments.

[0032] In some embodiments, the semiconductor package 110a of the semiconductor package structure 10 further includes a package layer 104 formed on the first surface 102a of the RDL structure 102. The package layer 104 surrounds the semiconductor die 100 and covers the non-active surface. The package layer 104 has sidewalls (or edges) that are substantially aligned (or in alignment) with the sidewalls (or edges) of the RDL structure 102.

[0033] Additionally, the package layer 104 and the semiconductor die 100 are separated from the electrical connectors 140 by the RDL structure 102. In other words, the electrical connectors 140 do not contact the package layer 104 and the semiconductor die 100.

[0034] The encapsulation layer 104 can be made of a molding compound material, such as epoxy resin, resin, moldable polymer, etc. The molding compound material can be applied while being substantially liquid, and then can be cured through a chemical reaction, such as curing it in epoxy resin or resin. For example, the molding compound material can be an ultraviolet (UV) or heat-cured polymer, which is applied as a gel or malleable solid capable of being disposed around the semiconductor die 100, and then cured through a UV or heat-curing process. The molding compound can be cured using a mold (not shown).

[0035] In some embodiments, the antenna device 130 includes an insulating substrate 120. The insulating substrate 120 has a first surface 120a and a second surface 120b opposite to the first surface 120a. In some embodiments, the first surface 120a of the insulating substrate 120 is adhered to the second surface RDL structure 102 via an electrical connector 140.

[0036] The insulating substrate 120 can be a single-layer or multi-layer structure, and includes any one of core insulating materials, such as glass epoxy resin, bismaleimide-triazine (BT), or ABF (Ajinomoto Build up Film). In some embodiments, the insulating substrate 120 includes a first sub-dielectric layer 115a, a second sub-dielectric layer 115b, and a third sub-dielectric layer 115c that are continuously stacked from the first surface 120a of the insulating substrate 120.

[0037] In some embodiments, the antenna device 130 includes a conductive pattern layer 116, which includes a first antenna element 116a and one or more conductive traces 116b. The conductive pattern layer 116 is formed in the first sub-dielectric layer 115a of the insulating substrate 120. The first antenna element 116a is joined and electrically connected to one or more electrical connectors 150, and the conductive traces 116b are joined and electrically connected to the electrical connectors 140 and 150.

[0038] In those cases, the electrical connector 140 is joined between the RDL structure 102 and the conductive pattern layer 116, such that the conductive pattern layer 116 is separated from the RDL structure 102 by a gap 141. In addition, the electrical connector 150 is electrically connected to the first antenna element 116a of the conductive pattern layer 116 and surrounds the semiconductor package 110a.

[0039] In some embodiments, the antenna device 130 further includes a second antenna element 118 formed on the second surface 120b of the insulating substrate 120 (i.e., the upper surface of the third sub-dielectric layer 115c) and one or more through-via structures 119 (or via structures 119) formed in the first sub-dielectric layer 115a, the second sub-dielectric layer 115b, and the third sub-dielectric layer 115c. The through-via structure 119 may be referred to as a through insulator via (TIV) and is electrically connected between the first antenna element 116a and the second antenna element 118 to form an antenna in the antenna device 130. The conductive pattern layer 116, the second antenna element 118, and the via structure 119 are made of a metal material such as copper or other suitable antenna materials.

[0040] It should be noted that Figure 1 the number of conductive pattern layers and the number of sub-dielectric layers of the illustrated insulating substrate are merely examples and are not limited to what is disclosed in the embodiments.

[0041] Figure 2 is a cross-sectional view of an exemplary semiconductor package structure 20 according to some embodiments of the present invention. For the sake of brevity, descriptions of elements that are the same or similar to those described in the previous references Figure 1 in the following embodiments may be omitted. In this embodiment, the semiconductor package structure 20 is similar to Figure 1 the semiconductor package structure 10 shown. As Figure 2 shown, different from the semiconductor package 110a of the semiconductor package structure 10, the semiconductor package 110b of the semiconductor package structure 20 includes a plurality of semiconductor dies. In some embodiments, the semiconductor package 110b includes semiconductor dies 200 and 300 that are electrically connected to the RDL structure 102 and surrounded by a package layer 104. More specifically, similar to Figure 1 the semiconductor die 100 shown, the semiconductor die 200 has an active surface 200a and a non-active surface 200b opposite to the active surface 200a. The semiconductor die 300 has an active surface 300a and a non-active surface 300b opposite to the active surface 300a. In addition, the RDL structure 102 is disposed and bonded to the active surface 200a of the semiconductor die 200 and the active surface 300a of the semiconductor die 300, so that the semiconductor die 200 and the semiconductor die 300 are electrically connected to each other through the pads 101 and the RDL structure 102.

[0042] In some embodiments, the size of the semiconductor die 200 is different from the size of the semiconductor die 300. For example, the size (such as height or volume, etc.) of the semiconductor die 200 is smaller than the size of the semiconductor die 300.

[0043] It should be noted thatFigure 2 The number of semiconductor dies shown is merely an example and is not limited to the number disclosed in the embodiments.

[0044] In some other embodiments, the functional circuits of semiconductor die 200 are different from those of semiconductor die 300. For example, semiconductor die 200 and / or semiconductor die 300 include a central processing unit (CPU), a graphics processing unit (GPU), a dynamic random access memory (DRAM) controller, or any combination thereof. Alternatively, semiconductor die 200 and / or semiconductor die 300 are system-on-a-chip (SOC) dies. In those cases, semiconductor dies 200 and 300 may be formed by different technology nodes (such as 10 nm and 14 nm, etc.). The size and functional circuits of semiconductor die 200 may be different from both the size and functional circuits of semiconductor die 300, or at least either one of them is different.

[0045] Figure 3 is a cross-sectional view of an exemplary semiconductor package structure 30 according to some embodiments of the present invention. For simplicity, descriptions of elements that are the same or similar to those described in the previous references Figure 2 in the following embodiments may be omitted. In this embodiment, semiconductor package structure 30 is similar to Figure 2 the semiconductor package structure 20 shown, except that semiconductor package structure 30 further includes a passive device 170 formed in a gap 141 between the conductive pattern layer 116 and the RDL structure 102, and the passive device 170 is electrically connected to the RDL structure 102. The passive device 170 may be disposed between at least two electrical connectors 140, as Figure 3 shown. In some embodiments, the passive device 170 includes a capacitor, an inductor, a resistor, or a combination thereof. In some embodiments, the passive device 170 is an integrated passive device (IPD). In some embodiments, the passive device 170 may contact the second surface 120b of the insulating substrate 120.

[0046] Figure 4 is a cross-sectional view of an exemplary semiconductor package structure 40 according to some embodiments of the present invention. For simplicity, descriptions of elements that are the same or similar to those described in the previous references Figure 3 in the following embodiments may be omitted. In this embodiment, semiconductor package structure 40 is similar to Figure 3The semiconductor package structure 30 shown in [description], in addition to the semiconductor package structure 40, further includes a passive device 172 having dimensions (such as height or volume, etc.) different from those of the passive device 170. In some embodiments, the passive device 172 is electrically connected to the conductive pattern layer 116 and is between at least one of the semiconductor package 110b and the electrical connector 150. In some embodiments, the passive device 172 has a larger size than the passive device 170. Additionally, the passive device 172 has a larger size (e.g., height H3) than the electrical connector 140 and the passive device 170. As an example, the passive device 172 has a height H3 of not less than 100 um, and the height of the passive device 170 is not greater than 100 um. Moreover, the height H3 of the passive device 172 is greater than the height of the passive device 170. In this embodiment, either the passive device 170 or the passive device 172 can be selected and disposed in the semiconductor package structure according to requirements, or both can be disposed in the semiconductor package structure.

[0047] In the prior art, usually a single semiconductor die or chip is mounted on a substrate and connected to the RDL structure of the substrate through solder balls or electrical connectors, etc. This method requires the formation of an RDL structure and an antenna structure in the substrate. However, the manufacturing processes required for the RDL structure and the antenna structure are different, and their respective requirements are also different (for example, the RDL structure requires a smaller pitch to achieve more dense wiring; while the layout of the antenna structure takes more into account reducing the interference received). Therefore, if the RDL structure and the antenna structure are formed on the same substrate, it will make the manufacturing process of the substrate more complex, the cost higher, and the yield difficult to guarantee. In the embodiment of the present invention, the RDL structure is disposed in the package structure where the die is located, and the RDL structure (for electrically connecting the die to other structures) is disposed in the package structure where the die is located. In this way, the two wirings with different requirements (the RDL structure and the antenna structure) can be formed separately in two packages; in this way, the RDL structure that requires a more precise manufacturing process is manufactured and formed with the die in one package, and the antenna structure that does not require such a precise manufacturing process is formed together in the manufacturing process of the substrate; to achieve higher manufacturing efficiency, simplify the manufacturing steps, reduce the cost, and at the same time, separate manufacturing can not only improve the yield during manufacturing, but also use known good packages for assembly when assembling the two packages, thereby further improving the yield. In addition, in this embodiment, a larger electrical connector 150 is disposed on the substrate (insulating substrate 120) where the antenna structure is located to adapt to the manufacturing process of the antenna structure (the wiring pitch of the antenna structure is wider, so it is easier to dispose a larger solder ball or electrical connector), which is convenient for manufacturing. There is only a smaller electrical connector 140 on the semiconductor package (semiconductor package 110a or 110b), and it is located between the antenna substrate (insulating substrate 120) and the semiconductor package (semiconductor package 110a or 110b) to electrically connect the two. Therefore, the size (such as height or thickness) of the entire semiconductor package structure (semiconductor package structure 10-40, or called antenna package structure) is smaller, the applicable range is wider, and the usage scenario is more flexible. In this embodiment, the semiconductor die 30 or 40 can be connected to the outside only through the electrical connector 140. Therefore, the wiring of the RDL structure and the like is more consistent, which is convenient for wiring and manufacturing. In this embodiment, the die can be connected to the electrical connector 150 through the conductive trace 116b, and the antenna element (such as the second antenna element 118) can also be connected to the electrical connector 150. In this way, not only can they be connected to the outside of the package structure (or antenna package) through the electrical connector 150, but also the antenna element can be electrically connected to the semiconductor die. Therefore, this connection method uses a more simple and short path for electrical connection, simplifies the wiring and improves the transmission efficiency, and reduces the transmission loss. According to the foregoing embodiment, the semiconductor package structure is designed to integrate antenna manufacturing into the semiconductor package structure.In a semiconductor package structure, an antenna is allowed to be formed in an insulating substrate, which is bonded to the RDL structure of the semiconductor package by using a bump structure (e.g., solder ball). Compared with a substrate-based antenna bonded with a semiconductor die / chip, due to the fine pitch RDL structure of the underlying semiconductor package, the thickness of the insulating substrate with the antenna can be reduced. Therefore, the size of the semiconductor package structure and the loss from the die to the antenna can be reduced. Since the antenna is fabricated by mature substrate technology, a compact and fan-out package integrated with the antenna can reduce the manufacturing cost of the semiconductor package structure and simplify the manufacturing process of the semiconductor package structure.

[0048] According to the foregoing embodiments, since the thickness of the insulating substrate having the antenna therein is reduced to provide a short heat dissipation path for the semiconductor die in the semiconductor package, the thermal performance can be improved.

[0049] According to the foregoing embodiments, since the antenna is formed in an insulating substrate separated from the semiconductor package having the semiconductor die therein, known good die packaging and known good antennas can be used during the manufacture of the semiconductor package structure, thereby preventing yield loss and further reducing the manufacturing cost of the semiconductor package structure.

[0050] According to the foregoing embodiments, since the semiconductor die can be formed by different technology nodes before being placed in the semiconductor package, die partitioning can be enabled and the manufacturing process of the semiconductor package can be simplified, thereby reducing the manufacturing cost of the semiconductor package.

[0051] According to the foregoing embodiments, since passive devices are integrated in the semiconductor package structure, the electrical performance can be improved.

[0052] According to the foregoing embodiments, since passive devices with different sizes can be integrated in the semiconductor package structure, the electrical performance can be further improved. In addition, the flexibility of integrating large passive devices into the semiconductor package structure can be increased.

[0053] Those skilled in the art will readily observe that many modifications and changes can be made to the apparatus and methods while maintaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the bounds and scope of the appended claims.

Claims

1. A semiconductor package structure, characterized in that, Comprising: An antenna device, comprising: a conductive pattern layer including a first antenna element formed in an insulating substrate and adjacent to a first surface of the insulating substrate; a second antenna element formed on a second surface of the insulating substrate opposite to the first surface; and A semiconductor package, comprising: a redistribution layer structure bonded and electrically connected to the conductive pattern layer; a first semiconductor die electrically connected to the redistribution layer structure; a sealing layer formed on the redistribution layer structure and surrounding the first semiconductor die; The semiconductor package structure further comprises: A first solder ball bonding the redistribution layer structure to the conductive pattern layer such that the conductive pattern layer and the redistribution layer structure are separated by a gap; and A second solder ball electrically connected to the conductive pattern layer and surrounding the semiconductor package having the redistribution layer structure, the first semiconductor die, and the sealing layer, the second solder ball being disposed on the insulating substrate and electrically connected to the first antenna element, the size of the first solder ball being smaller than the size of the second solder ball; A first capacitor formed in the gap between the conductive pattern layer of the antenna device and the redistribution layer structure of the semiconductor package and electrically connected to the redistribution layer structure of the semiconductor package, the first capacitor being disposed between at least two first solder balls; A second passive device electrically connected to the conductive pattern layer of the antenna device and between the semiconductor package and the second solder ball.

2. The semiconductor package structure according to claim 1, wherein, The height of the second passive device is greater than the height of the first capacitor.

3. The semiconductor package structure according to claim 1, wherein, The height of the first solder ball is lower than the height of the second passive device.

4. The semiconductor package structure according to claim 1, wherein The semiconductor package further comprises: A second semiconductor die electrically connected to the redistribution layer structure and surrounded by a package layer, wherein the size of the second semiconductor die is different from the size of the first semiconductor die, and / or the functional circuit of the second semiconductor die is different from the functional circuit of the first semiconductor die.

5. The semiconductor package structure as described in claim 1, wherein, The antenna device further comprises: At least one via structure formed in the insulating substrate and electrically connecting between the first antenna element and the second antenna element.

6. The semiconductor package structure according to claim 1, wherein The redistribution layer structure has a first surface and a second surface opposite to the first surface; The first semiconductor die has an active surface formed on the first surface of the redistribution layer structure; The first solder ball is formed on the second surface of the redistribution layer structure; The insulating substrate has a first surface and the insulating substrate is stacked on the second surface of the redistribution layer structure; The second solder ball is formed on the first surface of the insulating substrate.

7. The semiconductor package structure according to claim 6, wherein Further comprising: A second semiconductor die having the active surface formed on the first surface of the redistribution layer structure; Wherein the sealing layer is further between the first semiconductor die and the second semiconductor die and surrounds the first semiconductor die and the second semiconductor die.

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