Method of forming a semiconductor device

Abstract

A method includes forming an image sensor in a semiconductor substrate. A first alignment mark is formed proximate to a front side of the semiconductor substrate. The method also includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the back side of the semiconductor substrate, and forming a component on the back side of the semiconductor substrate. The component is formed using the second alignment mark for alignment. Embodiments of the present invention relate to methods of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention are directed to methods of forming semiconductor devices. Background Art

[0002] Semiconductor image sensors operate to sense light. Typically, semiconductor image sensors include complementary metal oxide semiconductor (CMOS) image sensors (CIS) and charge coupled device (CCD) sensors, which are widely used in various applications, such as digital still cameras (DSC), mobile phone cameras, digital video (DV), and digital video recorder (DVR) applications. These semiconductor image sensors utilize an array of image sensor elements, each of which includes a photodiode and other elements to absorb light and convert the sensed light into digital data or electrical signals.

[0003] Front side illumination (FSI) CMOS image sensors and back side illumination (BSI) CMOS image sensors are two types of CMOS image sensors. FSI CMOS image sensors are operable to detect light projected from their front sides, while BSI CMOS image sensors are operable to detect light projected from their back sides. When light is projected into an FSI CMOS image sensor or a BSI CMOS image sensor, photoelectrons are generated, and then the photoelectrons are sensed by photosensitive devices in the pixels of the image sensor. The more photoelectrons are generated, the better the quantum efficiency (QE) of the image sensor, thus improving the image quality of the CMOS image sensor. Summary of the invention

[0004] An embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming an image sensor in a semiconductor substrate, wherein a first alignment mark is formed near the front side of the semiconductor substrate; performing a backside polishing process to thin the semiconductor substrate; forming a second alignment mark on the back side of the semiconductor substrate; and forming a component on the back side of the semiconductor substrate, wherein the component is formed using the second alignment mark for alignment.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a shallow trench isolation (STI) region in a semiconductor substrate, wherein the shallow trench isolation region includes a first alignment mark; forming an image sensor in the semiconductor substrate; performing a backside polishing process from the back side of the semiconductor substrate; forming a second alignment mark in the semiconductor substrate, wherein the second alignment mark is formed by using the first alignment mark for alignment; and forming a color filter on the back side of the semiconductor substrate.

[0006] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate, wherein the shallow trench isolation regions include: a shallow trench isolation grid; a shallow trench isolation pad; and a first alignment mark; forming an image sensor in the shallow trench isolation grid; and forming a second alignment mark from the back side of the semiconductor substrate, wherein the second alignment mark is formed by aligning with the first alignment mark. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 16 A cross-sectional view illustrates an intermediate stage in the formation of an image sensor chip in accordance with some embodiments.

[0009] Fig.17 A circuit diagram of a pixel of an image sensor according to some embodiments is shown.

[0010] Fig.18 A plan view illustrating partitions of an image sensor chip according to some embodiments.

[0011] Fig.19 Example alignment marks are shown in accordance with some embodiments.

[0012] Fig. 20 Alignment marks and processes in which the alignment marks may be used are shown in accordance with some embodiments.

[0013] Fig.21 A process flow for forming an image sensor chip according to some embodiments is shown. DETAILED DESCRIPTION

[0014] The present invention provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] In addition, for ease of description, spacing relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relationship terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relationship descriptors used herein should be interpreted accordingly.

[0016] According to some embodiments of the present invention, a backside illumination (BSI) image sensor chip and a method for forming the same are provided. According to some embodiments of the present invention, an intermediate stage in the formation of a BSI image sensor chip is shown. Some variations of some embodiments are discussed. The embodiments discussed herein will provide examples to enable the subject matter of the present invention to be performed or used, and those skilled in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. Throughout the various views and exemplary embodiments, the same reference numerals are used to indicate the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order. According to some embodiments of the present invention, a backside alignment mark is formed on the back side of a BSI image sensor chip, and the backside alignment mark is formed by aligning with the front side alignment mark. The backside alignment mark is formed once, while the front side alignment mark can still be observed from the back side. In the backside process for forming a BSI image sensor chip, the backside alignment mark may be used for alignment.

[0017] Figures 1 to 16 1 shows a cross-sectional view of an intermediate stage in the formation of a backside alignment mark according to some embodiments of the present invention. The corresponding process is also schematically shown in Fig.21 In the process flow 200 shown.

[0018] Figure 1The formation of an initial structure of an image sensor chip 22 is shown, which initial structure may be part of a wafer 20 in which a plurality of image sensor chips 22 are included. The image sensor chip 22 includes a semiconductor substrate 24. According to some embodiments of the present invention, the semiconductor substrate 24 is a crystalline silicon substrate. According to other embodiments of the present invention, the semiconductor substrate 24 includes an elemental semiconductor such as germanium; a compound semiconductor including carbon silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Throughout the specification, the main surface 24A of the substrate 24 is referred to as the front surface of the semiconductor substrate 24, and the main surface 24B is referred to as the back surface of the semiconductor substrate 24. The surfaces 24A and 24B may be in the (100) or (001) plane.

[0019] Isolation region 32 is formed to extend into semiconductor substrate 24 to define an area (such as an active area), and isolation region 32 is optionally referred to as shallow trench isolation (STI) region 32. According to some embodiments of the present invention, STI region 32 includes multiple parts with different functions. For example, STI region 32 includes STI grid 32A, landing pad 32B for forming metal pads, and front side alignment mark 32C. STI grid 32A is a grid for forming an image sensor array therein. Landing pad 32B can be a pad large enough to accommodate a metal pad, as will be discussed in subsequent paragraphs. Front side alignment mark 32C may include a patterned STI region having a unique pattern, and thus serves as an alignment mark. Alignment mark 32C can be used for alignment purposes in the formation of a front side structure. According to some embodiments of the present invention, the height H1 of alignment mark 32C can be in the range of about 1000 angstroms to about 2000 angstroms. According to some embodiments of the present invention, alignment mark 32C is formed in metal pad region 112 ( Fig.18 According to other embodiments, the alignment mark 32C is formed in any other region, including the scribe line region 114, the pixel region 110 where the image sensor is located (when space is available), etc. Fig.19 An example plan view of an alignment mark according to some embodiments of the present invention is shown, which has a pattern that can be adopted by the alignment mark 32C. For example, the bars and crosses can be STI regions or spaces between STI regions. The alignment mark 32C can also adopt any other available pattern.

[0020] Reference again Figure 1, image sensor 26 is formed to extend from front surface 24A into semiconductor substrate 24. The formation of image sensor 26 may include an implantation process. Image sensor 26 is configured to convert light signals (photons) into electrical signals. Image sensor 26 may be a photosensitive metal oxide semiconductor (MOS) transistor, a photosensitive diode, etc. Throughout the specification, image sensor 26 is optionally referred to as photodiode 26, although they may be other types of image sensors. According to some embodiments of the present invention, photodiode 26 forms an image sensor array. Each photodiode 26 may be located in a grid cell of a grid formed by STI region 32A.

[0021] Figure 1 Also shown is pixel cell 30 having at least some portion within the active area defined by STI grid 32A. Fig.17 A circuit diagram of an example of a pixel cell 30 is shown. According to some embodiments of the present invention, the pixel cell 30 includes a photodiode 26 having an anode coupled to an electrical ground GND and a cathode coupled to a source of a transfer gate transistor 34. The drain of the transfer gate transistor 34 can be coupled to the drain of a reset transistor 38 and the gate of a source follower 42. The gate of the reset transistor 38 is coupled to a reset line RST. The source of the reset transistor 38 can be coupled to a pixel power supply voltage VDD. A floating diffusion capacitor 40 can be coupled between the source / drain of the transfer gate transistor 34 and the gate of the source follower 42. The reset transistor 38 is used to preset the voltage at the floating diffusion capacitor 40 to VDD. The drain of the source follower 42 is coupled to the power supply voltage VDD. The source of the source follower 42 is coupled to a row selector 43. The source follower 42 provides a high impedance output for the pixel cell 30. The row selector 43 functions as a selection transistor of the corresponding pixel unit 30 , and a gate of the row selector 43 is coupled to a selection line SEL.

[0022] Reference again Figure 1 , showing an example of a transistor as a device in the pixel unit 30 (eg, Fig.17 34, 38, 42 and 44 in FIG. 3 ). For example, in Figure 1A transfer gate transistor 34 is shown as an example. According to some embodiments of the present invention, each photodiode 26 is electrically coupled to a first source / drain region of a transfer gate transistor 34, and the transfer gate transistor 34 includes a gate 28 and a gate dielectric 31. The gate dielectric 31 is in contact with the front surface 24A of the substrate 24. The first source / drain region of the transfer gate transistor 34 can be shared by the corresponding connected photodiode 26. For example, by implanting p-type impurities and n-type impurities into the substrate 24 to different depths to form a pn junction, a floating diffusion capacitor 40 is formed in the substrate 24, and the pn junction serves as the floating diffusion capacitor 40. The floating diffusion capacitor 40 can be formed in the second source / drain region of the transfer gate transistor 34, and thus one of the capacitor plates of the floating diffusion capacitor 40 is electrically coupled to the second source / drain region of the transfer gate transistor 34. The photodiode 26, the corresponding transfer gate transistor 34 and the floating diffusion capacitor 40 in the same active area form a pixel unit 30, also as shown Figure 1 Marked.

[0023] Fig.18 shows a schematic partitioning scheme of the BSI chip 22 according to some embodiments of the present invention, and Figure 1 Shows that from Fig.18 The BSI chip 22 may include a pixel region 110 in which a pixel unit 30 ( Figure 1 ), the pixel unit is also formed into an array. The scribe line region 114 is formed as a grid on the entire corresponding wafer to separate the BSI image sensor chips 22 from each other. A metal pad region 112 (also a peripheral region) is formed between the scribe line region 114 and the pixel region 110. According to some embodiments of the present invention, the peripheral region 112 can be formed as a ring surrounding the pixel region 110, such as Fig.18 According to an alternative embodiment, instead of forming a ring, the peripheral region 112 extends to one, two or three sides of the pixel region 110 but not to the remaining sides.

[0024] Back again Figure 1, a contact etch stop layer 29 is formed on the substrate 24 and the transistors such as the transfer gate transistor 34. The CESL 29 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc. or a multilayer thereof. For example, a conformal deposition method such as atomic layer deposition (ALD) or chemical vapor deposition (CVD) may be used to form the CESL 29. An interlayer dielectric (ILD) 33 is formed over the CESL 29. The ILD 33 may include a dielectric material formed using, for example, flowable chemical vapor deposition (FCVD), spin coating, CVD, or other deposition methods. The ILD 33 may also be formed of an oxygen-containing dielectric material, which may be an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.

[0025] The front-side interconnect structure 44 is formed above the semiconductor substrate 24. The front-side interconnect structure 44 is used to electrically interconnect the devices in the image sensor chip 22 and to connect to other package components. The front-side interconnect structure 44 includes a dielectric layer 46 and metal lines 48 and vias 50 located in the dielectric layer 46. Throughout the specification, the metal lines 48 in the same dielectric layer 46 are collectively referred to as metal layers. The front-side interconnect structure 44 may include multiple metal layers. According to some embodiments of the present invention, the dielectric layer 46 includes a low-k dielectric layer. The low-k dielectric layer has a low k value, for example, less than 3.8, and may be less than about 3.0.

[0026] Surface dielectric layer 52 is formed as a top dielectric layer of wafer 20. Surface dielectric layer 52 may be formed of a non-low-k dielectric material having a k value equal to or greater than about 3.8. According to some embodiments of the present invention, surface dielectric layer 52 is formed of or includes silicon oxide.

[0027] Bond pad 54 is also formed at the top of wafer 20. Bond pad 54 may be formed of or include copper. Bond pad 54 may also include a barrier layer surrounding the copper. The top surface of bond pad 54 may be coplanar with the top surface of surface dielectric layer 52.

[0028] Next, refer to Figure 2 , bonding wafer 20 to wafer 120. The corresponding process is shown as Fig.21 Process 202 in the process flow shown. According to some embodiments of the present invention, bonding is performed by hybrid bonding. Thus, surface dielectric layer 52 in wafer 20 is bonded to surface dielectric layer 252 in wafer 120 by, for example, fusion bonding with SO-Si bonds formed. Bond pads 54 of wafer 20 are also bonded to metal pads 254 in wafer 120 by metal-to-metal direct bonding.

[0029] According to some embodiments of the present invention, wafer 120 includes chip 222, which further includes logic circuit 226. Logic circuit 226 may include application circuits for processing and using electrical signals obtained from BSI chip 22. For example, logic circuit 226 may include one or more image signal processing (ISP) circuits for processing image-related signals obtained from image sensor chip 22. Image signal processing (ISP) circuits may include analog-to-digital converters (ADCs), correlated double sampling (CDS) circuits, row decoders, etc. Circuits in wafer 120 are electrically and signally connected to image sensor circuits in wafer 20 through bonding pads 54 and 254.

[0030] Further references Figure 2 , a backside grinding process is performed to grind the back surface 24B into a thin semiconductor substrate 24. The corresponding process is shown as Fig.21 The process flow shown is process 204. The resulting back surface is called Figure 2 The thickness of substrate 24 may be reduced to less than about 20 μm or less than about 15 μm so that light can penetrate from back surface 24B′ into semiconductor substrate 24 and reach photodiode 26. To improve light receiving efficiency, thickness T1 of substrate 24 is maintained to have a larger value, for example, greater than about 6 μm.

[0031] Figure 3 The formation of alignment mark 56 is shown, and alignment mark 56 includes one or more trenches extending from back surface 24B' into semiconductor substrate 24. The corresponding process is shown as Fig.21 The process 206 in the process flow shown. The trenches may be formed by a dry etching process, which may be performed using a process gas such as C2F6; CF4; SO2; a mixture of HBr, Cl2, and O2; a mixture of HBr, Cl2, and O2; or a mixture of HBr, Cl2, O2, and CF2. The pattern of the alignment mark 56 may be any distinguishable pattern, which may include Fig.19 The depth D1 of alignment mark 56 may be in the range between about 1800 angstroms and about 2000 angstroms. The position of alignment mark 56 is determined using alignment mark 32C as an alignment mark. In other words, alignment mark 56 is formed using alignment mark 32C for alignment.

[0032] According to some embodiments of the present invention, in the metal pad region 112 ( Fig.18 ) is formed in alignment mark 56. According to other embodiments, alignment mark 56 is formed in any other region, including scribe line region 114, pixel region 110 (when space is available), etc. Alignment mark 56 may be vertically aligned with alignment mark 32C, or may be laterally offset from alignment mark 32C.

[0033] Figure 4 The formation of a backside high absorption (BSHA) region 58 is shown. The BSHA region 58 has the function of focusing light to improve light absorption. The corresponding process is shown as Fig.21 Process 208 in the process flow shown. According to some embodiments of the present invention, there are single or multiple (such as two, three, four or more) BSHA regions 58 overlapping the same pixel unit 30. According to some embodiments of the present invention, the formation of the BSHA region 58 includes forming an etching mask over the semiconductor substrate 24. The etching mask has openings aligned with the pixel units, each opening corresponding to a BSHA region 58 to be formed. The formation of the etching mask can be performed using one of the alignment marks 32C or the alignment marks 56 for alignment. Then, the semiconductor substrate 24 is etched through the openings to form a plurality of pyramid-shaped openings, which can be achieved by a wet etching process so that etching along the lattice direction will produce a pyramid-shaped opening. Next, a transparent material is deposited, which can be a transparent material such as silicon oxide, and the transparent material is filled into the opening. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical polishing process is then performed to produce the BSHA region 58.

[0034] According to some embodiments of the present invention, while filling opening 56, alignment mark 56 is also filled with the same material to form alignment mark 60. According to alternative embodiments, instead of filling opening 56 while forming BSHA region 58, opening 56 may be masked during the filling process and filled with other materials in a subsequent process. For example, in Figure 6 and / or Figure 8 The process shown fills the opening 56 and the resulting alignment mark 60 will be formed by the dielectric layer 64 ( Figure 6 ) and / or 68( Figure 8 ) are formed of the same material.

[0035] refer to Figure 5 , forming a deep trench isolation (DTI) region 62. The corresponding process is shown as Fig.21 Process 210 in the process flow shown. According to some embodiments of the present invention, the formation of the DTI region 62 includes etching the semiconductor substrate 24 and filling the resulting trench with a high-k dielectric material such as Ta2O5, an opaque material such as a metal (e.g., tungsten), or a combination thereof. The DTI region 62 has the function of preventing light from penetrating, and has the function of preventing crosstalk of optical signals. According to some embodiments of the present invention, the DTI region 62 forms a grid, wherein the grid lines of the DTI region 62 are vertically aligned with the grid lines of the STI grid 32A.

[0036] Figure 6The formation of dielectric layer 64 is shown. The corresponding process is shown as Fig.21 Process 212 in the process flow shown. According to some embodiments of the present invention, dielectric layer 64 is a high-k dielectric layer and can be made of or include aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), etc. The thickness of dielectric layer 64 can be in the range between about 30 angstroms and about 80 angstroms. The deposition process can include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0037] Next, if Figure 7 As shown, a trench 66 is formed. The corresponding process is shown as Fig.21 The process 214 in the process flow shown. The formation of the trench 66 can be performed using a dry etching process. The trench 66 can have any distinguishable pattern, and the distinguishable pattern can include as an example Fig.19 . The depth D2 of trench 66 may be in the range between about 1800 angstroms and about 2000 angstroms. Alignment mark 32C or alignment mark 60 is used as an alignment mark to determine the position of trench 66. Trench 66 may be vertically aligned with alignment mark 32C, or may be laterally offset from alignment mark 32C.

[0038] Figure 8 The formation of dielectric layer 68 and the filling of trench 66 to form alignment mark 70 are shown. The corresponding process is shown as Fig.21 Process 216 in the process flow shown. According to some embodiments of the present invention, dielectric layer 68 is a single layer or a composite layer including multiple layers. For example, dielectric layer 68 can be or include a hafnium oxide layer, and may or may not include a tantalum oxide (Ta2O5) layer above the hafnium oxide layer. The thickness of the hafnium oxide layer can be in a range between about 30 angstroms to about 80 angstroms. The thickness of the tantalum oxide layer can be in a range between about 300 angstroms and about 800 angstroms. The deposition process can include CVD, PECVD, ALD, etc. Depending on the width of the trench, trench 66 can be completely filled at this time, or trench 66 can be partially filled and will be replaced by subsequently deposited layers (such as Fig. 9 The dielectric layer 72 in further fills the trench 66.

[0039] Fig. 9 The formation of dielectric layer 72 is shown. The corresponding process is shown as Fig.21 Process 218 in the process flow shown. According to some embodiments of the present invention, the dielectric layer 72 is formed of a transparent material such as silicon oxide. The thickness of the dielectric layer 72 can be in the range between about 1000 angstroms and about 2000 angstroms. The deposition process can include CVD, PECVD, ALD, etc.

[0040] Fig.10 The formation of a metal grid 76, a metal ground structure 78, a dielectric layer 74, and a trench 80 according to some embodiments of the present invention is shown. The formation process may include etching the dielectric layers 72, 68, and 64 to form one or more openings so that the semiconductor substrate 24 is exposed. The opening may also extend into the semiconductor substrate 24. Next, a metal material is deposited. According to some embodiments of the present invention, the metal material includes an adhesion layer 73 and a metal material 75 located on the adhesion layer 73. The adhesion layer 73 may include a titanium layer, a titanium nitride layer, or a composite layer including a titanium layer and a titanium nitride layer located above the titanium layer. The thickness of the adhesion layer 73 may be in the range of about 400 angstroms to about 600 angstroms. The metal material 75 may include tungsten, chromium, etc., and may have a thickness in the range of about 1.5 kiloangstroms and about 2.5 kiloangstroms.

[0041] After deposition, a patterning process is performed by etching, and the metal material 75 and the adhesive layer 73 are patterned into a metal grid 76 and a grounding structure 78. The corresponding process is shown as Fig.21 221 in the process flow shown in . When viewed from the top of the metal grid 76, the metal grid 76 includes a plurality of first strips extending in a first direction, and a plurality of second strips extending in a second direction perpendicular to the first direction, wherein the plurality of second strips are connected to the plurality of first strips. The grid openings in the metal grid 76 also overlap with the grid openings of the DTI region 62 and the STI grid 32A, so that light can pass through and be confined in the openings to reach the photodiode 26 below. The ground structure 78 extends into the openings in the dielectric layers 72, 68, and 64 to make physical and electrical contact with the semiconductor layer 24.

[0042] After forming the metal grid 76 and the ground structure 78, the dielectric layer 74 is deposited. The corresponding process is shown as Fig.21 223 in the process flow shown in FIG. According to some embodiments of the present invention, dielectric layer 74 is formed of a transparent material such as silicon oxide. The thickness of dielectric layer 74 may be in a range between about 4000 angstroms and about 6000 angstroms. Dielectric layer 74 may be planarized in a CMP process or a mechanical polishing process so that its top surface is flat.

[0043] Next, as Fig.10 As shown, a groove 80 is formed. The corresponding process is shown as Fig.21 The process 224 in the process flow shown. The formation can be performed using a dry etching process. The groove 80 can adopt any distinguishable pattern, and the distinguishable pattern can include as an example Fig.19. The depth D3 of the groove 80 can be in the range between about 2000 angstroms and about 3000 angstroms. The depth D3 of the groove 80 is controlled so that the groove 80 does not undesirably reach the high-k dielectric layer by etching through the dielectric layer 74, because this may cause the high-k dielectric layer to be exposed and degraded. The position of the groove 66 is determined using the alignment mark 60 or the alignment mark 70 as an alignment mark. Since the semiconductor substrate 24 is very thick, it may be difficult to align the groove 80 using the alignment mark 32C. The groove 80 can be vertically aligned with the alignment mark 32C, or it can be laterally offset from the alignment mark 32C. The groove 80 can be partially or completely filled in a subsequent process, and the corresponding filling is also referred to as the alignment mark 80.

[0044] Fig.11 2 shows the formation of an opening 82, which is formed by etching a dielectric layer formed on the back side of the semiconductor substrate 24 and then etching through the semiconductor substrate 24. The corresponding process is shown as Fig.21 227 in the process flow shown in FIG. The etching is stopped on STI pad 32B, while some over-etching may occur so that opening 82 extends partially into STI pad 32B. The etching is controlled so that it does not etch through STI pad 32B. The formation of opening 82 may be performed using alignment mark 80, alignment mark 70, or alignment mark 60 to determine the location of opening 82.

[0045] Next, if Fig.12 As shown, dielectric layer 84 is formed as a blanket layer including some portions extending into opening 82 and other portions overlapping dielectric layer 74. The corresponding process is shown as Fig.21 Process 228 in the process flow shown. According to some embodiments of the present invention, dielectric layer 84 is formed of silicon oxide, which can be formed by PECVD or other suitable methods. The thickness of dielectric layer 84 can range between about 1500 angstroms and about 2500 angstroms. Dielectric layer 84 is sometimes referred to as a passivation layer.

[0046] Fig.13 The formation of an opening 86 at the bottom of the opening 82 by etching the ILD 33 and the CESL 29 and possible dielectric layer 46 in the interconnect structure 44 is shown. The corresponding process is shown as Fig.21 Process 230 in the process flow is shown. As a result, metal pad 48A in interconnect structure 44 is exposed. The formation of opening 86 may be performed using alignment mark 80, alignment mark 70, or alignment mark 60 to determine the location of opening 86.

[0047] Fig.14 The deposition of metal layer 88 is shown. The corresponding process is shown as Fig.21Process 232 in the process flow shown. According to some embodiments of the present invention, metal layer 88 is formed of or includes copper, AlCu, etc. The thickness of metal layer 88 may be in the range between about 1 μm and about 1.5 μm. The formation method may include, for example, PVD, CVD, etc.

[0048] Next, if Fig.15 As shown, metal layer 88 is patterned to form metal pad 90, which includes at least a portion of opening 82. The corresponding process is shown as Fig.21 Process 234 in the process flow is shown. Patterning of metal layer 88 may be performed using alignment mark 80, alignment mark 70, or alignment mark 60 to determine the location of metal layer 88.

[0049] In subsequent processes, such as Fig.16 As shown, additional components such as color filters 94 are formed. Microlenses 96 are then formed. Each image sensor 26 is aligned with one of the color filters 94 and one of the microlenses 96. The formation of the color filters 94 and the microlenses 96 may be aligned with the alignment marks 60, 70, or 80. Thus, the image sensor chip 22 (and the corresponding wafer 20) is formed. For example, a protective layer (not shown) may be formed on the microlenses 96 by depositing a conformal silicon oxide layer. In a subsequent process, the image sensor wafer 20 and the wafer 120 are sawn into the image sensor chip 22 and the device chip 222. The image sensor chip 22 and its bonded device chip 222 are collectively referred to as a package 300. Depending on the position where the alignment marks 60, 70, and / or 80 are formed, the alignment marks 60, 70, and / or 80 may remain in the image sensor chip 22, or they may be removed (for example, if the alignment marks are formed in the scribe area 114 ( Fig.18 When the package 300 is packaged, a wire bonding process may be performed to form a bonding ball 92 on the metal pad 90 , wherein a bonding wire 93 is attached to the bonding ball 92 .

[0050] As some examples, the foregoing processes illustrate the formation of backside alignment marks 60, 70, and 80, which are formed at different stages of forming the backside structure. According to other embodiments, the backside alignment marks may be formed at any other stage, such as after forming dielectric layers 68 and / or 72. According to some embodiments of the present invention, any one, two, or all three alignment marks 60, 70, and 80 are formed in any combination, as long as the frontside alignment mark 32C can still be clearly seen from the backside of the image sensor chip 22 when the first of the backside alignment marks 60, 70, and 80 is formed. The alignment marks 60, 70, and 80 formed later may or may not be formed using the previously formed alignment marks 60, 70, and 80 as alignment marks.

[0051] In the foregoing examples, the alignment marks are shown as being filled with a single material of the layer immediately above. It should be understood that, depending on the depth and width of the trenches used to form the alignment marks, the trenches may or may not be completely filled by a subsequently deposited layer. When they are not completely filled, they will be filled with subsequently deposited materials.

[0052] Fig. 20 Example embodiments of points in time at which alignment marks are formed, and example processes for forming components that can be aligned using previously formed alignment marks are shown. Horizontal straight lines represent processes and components, and the processes and components at lower locations are performed / formed earlier than the processes and components shown at upper locations. The cross marked with the letter "A" indicates that at the stage of forming opening 86, the total thickness of the combination of the underlying dielectric layer and semiconductor substrate 24 may be too great to align with alignment mark 32C. The cross marked with the letter "B" indicates that at the stage of forming opening 86, the total thickness of the combination of the underlying dielectric layer and semiconductor substrate may be too great to align with alignment marks 60 and 70. Therefore, alignment marks 60, 70 and / or 80 are formed to provide additional alignment so that the backside component can be aligned with the previously formed backside alignment mark, which is further aligned with the frontside alignment mark. Arrows without crosses represent possible alignment actions, where the starting point of the arrow represents the action taken or component formed, and the end point represents the alignment mark used. As shown in FIG. Fig. 20 As shown, due to the increased thickness and the formation of more backside components, it may be necessary to use the backside alignment marks formed later rather than the backside alignment marks formed earlier for alignment. For example, it may be necessary to use alignment mark 80 to perform the formation of metal pad 90, while alignment marks 60 and / or 70 may or may not be available.

[0053] In the illustrated discussed embodiment, the backside alignment mark is formed by aligning with the frontside alignment mark. According to other embodiments, the backside component may be formed first, then the frontside component may be formed, and the frontside alignment mark may be formed by aligning with the backside alignment mark.

[0054] According to some embodiments of the present invention, Fig. 20 As shown, alignment mark 80 may be formed by aligning with alignment mark 70 or 60. Metal grid 76 may be formed by aligning with alignment mark 70 or 60, and DTI region 62 may be formed by aligning with alignment mark 60 or alignment mark 32C. BSHA region 58 may be formed by aligning with alignment mark 32C.

[0055] Embodiments of the present invention have some advantageous features. In order to improve the efficiency of collecting light by the image sensor, the semiconductor substrate of the image sensor can be left thicker (e.g., thicker than about 6 μm) after the backside grinding process. This causes an alignment problem for aligning the backside components with the frontside alignment marks. According to some embodiments of the present invention, better alignment can be achieved by forming alignment marks on the backside of the BSI image sensor chip. Moreover, more alignment marks can be formed on the backside of the BSI image sensor chip, so that alignment can be well performed as the formation of the backside structure of the BSI image sensor chip proceeds.

[0056] According to some embodiments of the present invention, a method includes forming an image sensor in a semiconductor substrate, wherein a first alignment mark is formed proximate to a front side of the semiconductor substrate; performing a backside polishing process to thin the semiconductor substrate; forming a second alignment mark on the back side of the semiconductor substrate; and forming a component on the back side of the semiconductor substrate, wherein the component is formed using the second alignment mark for alignment. In an embodiment, forming the second alignment mark includes etching the semiconductor substrate to form a trench extending from the back side of the semiconductor substrate into the semiconductor substrate. In an embodiment, forming the second alignment mark includes depositing a dielectric layer to fill the trench. In an embodiment, the method further includes depositing an additional dielectric layer in contact with the back surface of the semiconductor substrate before etching the semiconductor substrate, wherein the trench penetrates the additional dielectric layer. In an embodiment, the method further includes forming a deep trench isolation region extending from the back surface of the semiconductor substrate into the semiconductor substrate, wherein the second alignment mark is formed before forming the deep trench isolation region. In an embodiment, the method further includes forming a metal grid on the back side of the semiconductor substrate; and depositing a dielectric layer on the metal grid, wherein forming the second alignment mark includes etching the dielectric layer to form a trench. In an embodiment, the depth of the trench is less than the thickness of the dielectric layer. In an embodiment, forming the feature includes etching the semiconductor substrate to form a through opening penetrating the semiconductor substrate; and forming a bonding pad extending into the through opening, wherein the bonding pad is electrically connected to the metal feature on the front side of the semiconductor substrate.

[0057] According to some embodiments of the present invention, a structure includes a BSI image sensor chip, which includes a semiconductor substrate; an image sensor located in the semiconductor substrate; a first alignment mark extending from the front side of the semiconductor substrate into the semiconductor substrate; and a second alignment mark located on the back side of the semiconductor substrate. In an embodiment, the first alignment mark is formed by a shallow trench isolation region. In an embodiment, the second alignment mark is formed by a dielectric region, and the dielectric region extends from the back surface of the semiconductor substrate into the semiconductor substrate. In an embodiment, the entire second alignment mark is located in the semiconductor substrate. In an embodiment, a dielectric layer contacts the back surface of the semiconductor substrate, wherein the second alignment mark penetrates the dielectric layer. In an embodiment, the structure also includes a metal grid located on the back side of the semiconductor substrate; and a dielectric layer located on the metal grid and filling the space in the metal grid; and a third alignment mark extending into the dielectric layer. In an embodiment, the structure also includes a device die bonded to the front side of the BSI image sensor chip.

[0058] According to some embodiments of the present invention, a structure includes a BSI image sensor chip, which includes a semiconductor substrate; an image sensor located in the semiconductor substrate; a first alignment mark extending from the front surface of the semiconductor substrate into the semiconductor substrate, wherein the first alignment mark includes a pattern of a shallow trench isolation region; and a second alignment mark extending from the back surface of the semiconductor substrate into the semiconductor substrate, wherein at least a portion of the second alignment mark is located in the semiconductor substrate. In an embodiment, the entire second alignment mark is located in the semiconductor substrate. In an embodiment, the second alignment mark includes a first portion located in the semiconductor substrate; a second portion located outside the semiconductor substrate. In an embodiment, the second alignment mark is formed of a dielectric material. In an embodiment, the structure also includes a metal grid located on the back side of the semiconductor substrate; a dielectric layer located above the metal grid and filling the space in the metal grid; and a third alignment mark extending into the dielectric layer.

[0059] An embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a shallow trench isolation (STI) region in a semiconductor substrate, wherein the shallow trench isolation region includes a first alignment mark; forming an image sensor in the semiconductor substrate; performing a backside polishing process from the back side of the semiconductor substrate; forming a second alignment mark in the semiconductor substrate, wherein the second alignment mark is formed by using the first alignment mark for alignment; and forming a color filter on the back side of the semiconductor substrate.

[0060] In the above method, wherein the color filter is formed by using the second alignment mark for alignment.

[0061] In the above method, it also includes: forming a dielectric layer on the back surface of the semiconductor substrate; and forming a third alignment mark extending into the dielectric layer and the semiconductor substrate, wherein forming the color filter is performed by using the third alignment mark for alignment.

[0062] In the above method, the method further includes: forming a plurality of transparent layers on the back side of the semiconductor substrate, wherein the color filter is formed above the plurality of transparent layers.

[0063] In the above method, the method further includes: forming a microlens on the color filter, wherein the microlens is formed by using the second alignment mark for alignment.

[0064] In the above method, the method further includes: etching the semiconductor substrate from a back side of the semiconductor substrate by using the second alignment mark for alignment, wherein after etching the semiconductor substrate, a shallow trench isolation pad in the shallow trench isolation region is exposed.

[0065] In the above method, it also includes: etching the semiconductor substrate from the back side of the semiconductor substrate by using the second alignment mark for alignment, wherein after etching the semiconductor substrate, the shallow trench isolation pad in the shallow trench isolation area is exposed, and further includes: etching the shallow trench isolation pad to form an opening extending through the shallow trench isolation pad, wherein the opening is formed by using the second alignment mark for alignment.

[0066] An embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate, wherein the shallow trench isolation regions include: a shallow trench isolation grid; a shallow trench isolation pad; and a first alignment mark; forming an image sensor in the shallow trench isolation grid; and forming a second alignment mark from the back side of the semiconductor substrate, wherein the second alignment mark is formed by aligning with the first alignment mark.

[0067] In the above method, it also includes: forming a deep trench isolation grid in the semiconductor substrate, wherein the deep trench isolation grid is vertically aligned with the shallow trench isolation grid, and the deep trench isolation grid is formed using the first alignment mark for alignment.

[0068] In the above method, it also includes: forming a deep trench isolation grid in the semiconductor substrate, wherein the deep trench isolation grid is vertically aligned with the shallow trench isolation grid, and the deep trench isolation grid is formed using the second alignment mark for alignment.

[0069] In the above method, the method further includes: forming a color filter on the back side of the semiconductor substrate, wherein the color filter is formed by using the second alignment mark for alignment.

[0070] In the above method, wherein the second alignment mark is formed to extend into the semiconductor substrate.

[0071] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent configuration does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without deviating from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: forming an image sensor in a semiconductor substrate, wherein a first alignment mark is formed proximate a front side of the semiconductor substrate; performing a backside polishing process to thin the semiconductor substrate; forming a second alignment mark on the back side of the semiconductor substrate; After forming the second alignment mark, forming a deep trench isolation region extending from the back surface of the semiconductor substrate into the semiconductor substrate; forming a component on the back side of the semiconductor substrate, wherein the component is formed using the second alignment mark for alignment; forming a dielectric layer on the deep trench isolation region and the back side of the semiconductor substrate; and A third alignment mark extending into the dielectric layer is formed, wherein the third alignment mark is located at a level above the deep trench isolation region and does not overlap with the deep trench isolation region in a direction perpendicular to a direction in which the deep trench isolation region extends.

2. The method according to claim 1, wherein: Forming the second alignment mark includes: The semiconductor substrate is etched to form a trench extending from a back side of the semiconductor substrate into the semiconductor substrate.

3. The method according to claim 2, wherein: Forming the second alignment mark includes depositing a dielectric layer to fill the trench.

4. The method according to claim 2, further comprising: Before etching the semiconductor substrate, an additional dielectric layer is deposited in contact with a back surface of the semiconductor substrate, wherein the trench penetrates the additional dielectric layer.

5. The method according to claim 1, further comprising: The third alignment mark is aligned with the first alignment mark.

6. The method according to claim 1, further comprising: forming a metal grid on the back side of the semiconductor substrate; as well as depositing the dielectric layer on the metal grid; Wherein, forming the third alignment mark includes etching the dielectric layer to form a trench.

7. The method according to claim 6, wherein: The depth of the trench is less than the thickness of the dielectric layer.

8. The method according to claim 1, wherein: Forming the component comprises: etching the semiconductor substrate to form a through opening penetrating the semiconductor substrate; and A bonding pad is formed extending into the through opening, wherein the bonding pad is electrically connected to a metal feature on a front side of the semiconductor substrate.

9. A method of forming a semiconductor device, comprising: forming a shallow trench isolation (STI) region in a semiconductor substrate, wherein the shallow trench isolation region includes a first alignment mark; forming an image sensor in the semiconductor substrate; performing a backside polishing process from a backside of the semiconductor substrate; forming a second alignment mark in the semiconductor substrate, wherein the second alignment mark is formed by using the first alignment mark for alignment; etching the semiconductor substrate from a back side of the semiconductor substrate by using the second alignment mark for alignment to form a deep trench isolation region extending from a back surface of the semiconductor substrate into the semiconductor substrate; forming a color filter on a back side of the semiconductor substrate; forming a dielectric layer on the deep trench isolation region and the back side of the semiconductor substrate; and A third alignment mark extending into the dielectric layer is formed, wherein the third alignment mark is located at a level above the deep trench isolation region and does not overlap with the deep trench isolation region in a direction perpendicular to a direction in which the deep trench isolation region extends.

10. The method according to claim 9, wherein: The color filter is formed by using the second alignment mark for alignment.

11. The method according to claim 9, wherein: Forming the color filter is performed by using the third alignment mark for alignment.

12. The method according to claim 9, further comprising: A plurality of transparent layers are formed on a back side of the semiconductor substrate, wherein the color filter is formed over the plurality of transparent layers.

13. The method according to claim 9, further comprising: A microlens is formed on the color filter, wherein the microlens is formed by using the second alignment mark for alignment.

14. The method according to claim 9, wherein: After etching the semiconductor substrate, shallow trench isolation pads in the shallow trench isolation region are exposed.

15. The method according to claim 14, further comprising: The shallow trench isolation pad is etched to form an opening extending through the shallow trench isolation pad, wherein the opening is formed by using the second alignment mark for alignment.

16. A method of forming a semiconductor device, comprising: A plurality of shallow trench isolation (STI) regions are formed in a semiconductor substrate, wherein the shallow trench isolation regions include: Shallow Trench Isolation Grid; Shallow trench isolation pads; and a first alignment mark; forming an image sensor in the shallow trench isolation grid; and forming a second alignment mark from a back side of the semiconductor substrate, wherein the second alignment mark is formed by aligning with the first alignment mark; and forming a deep trench isolation grid in the semiconductor substrate using the second alignment mark for alignment; forming a dielectric layer over the deep trench isolation grid; and A third alignment mark extending into the dielectric layer is formed, wherein the third alignment mark is located at a level above the deep trench isolation grid and does not overlap with the deep trench isolation grid in a direction perpendicular to a direction in which the deep trench isolation grid extends.

17. The method according to claim 16, wherein: The deep trench isolation grid is vertically aligned with the shallow trench isolation grid.

18. The method according to claim 16, further comprising: The third alignment mark is aligned with the first alignment mark.

19. The method according to claim 16, further comprising: A color filter is formed on a back side of the semiconductor substrate, wherein the color filter is formed by using the third alignment mark for alignment.

20. The method according to claim 16, wherein: The second alignment mark is formed to extend into the semiconductor substrate.

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