Display device

Abstract

The present disclosure relates to a display device, the display device comprising: a display panel; and a first substrate connected to the display panel, wherein the first substrate comprises: a first base substrate; a first wiring layer having a plurality of first signal wirings located on the first base substrate; and a first ground wiring layer located on the first wiring layer, wherein the first ground wiring layer comprises a grid pattern region and a non-grid pattern region, wherein the grid pattern region comprises a plurality of first grid patterns and a plurality of openings surrounded by adjacent first grid patterns, and the non-grid pattern region comprises a plurality of second grid patterns and a plurality of non-grid patterns surrounded by adjacent second grid patterns, wherein the plurality of non-grid patterns are physically connected to the adjacent second grid patterns.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0092403, filed on Jul. 30, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of some example embodiments of the present disclosure relate to a display device. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being utilized through various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart televisions. Such display devices may include flat panel display devices such as liquid crystal display devices, field emission display devices, and organic light emitting display devices. Among these flat panel display devices, since each pixel of the display panel includes a light emitting element capable of emitting light by itself, the organic light emitting display device can display an image without a backlight unit for providing light to the display panel.

[0005] Each pixel of the organic light emitting display device may include a light emitting element, a driving transistor, and an emission control transistor, where the driving transistor controls the amount of driving current supplied from a power line to the light emitting element according to the voltage of a gate electrode, and the emission control transistor controls the connection between the driving transistor and the light emitting element.

[0006] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0007] Aspects of some example embodiments of the present disclosure include a display device in which a change in impedance of a transmission signal wiring of a driver circuit board for driving a display panel due to adjacent wirings can be prevented or reduced.

[0008] However, aspects of the example embodiments of the present disclosure are not limited to the example embodiments specifically described herein. Through reference to the detailed description of the present disclosure given below, the above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0009] According to some example embodiments of the present disclosure, a display device includes: a display panel; and a first substrate connected to the display panel, wherein the first substrate includes: a first base substrate; a first wiring layer having a plurality of first signal wirings located on the first base substrate; and a first ground wiring layer located on the first wiring layer, wherein the first ground wiring layer includes a grid pattern region and a non-grid pattern region, wherein the grid pattern region includes a plurality of first grid patterns and a plurality of openings surrounded by adjacent first grid patterns, and the non-grid pattern region includes a plurality of second grid patterns and a plurality of non-grid patterns surrounded by adjacent second grid patterns, wherein the plurality of non-grid patterns are physically connected to the adjacent second grid patterns.

[0010] According to some example embodiments, the display device may further include a second wiring layer having a plurality of second signal wirings located on the first ground wiring layer, wherein the first signal wirings may extend along a first direction, and the second signal wirings may extend along a second direction intersecting the first direction.

[0011] According to some example embodiments, the grid pattern region is located in a region where the first signal wirings and the second signal wirings do not overlap, and the non-grid pattern region is located in a region where the first signal wirings and the second signal wirings overlap.

[0012] According to some example embodiments, the first substrate may further include a second ground wiring layer and a second base substrate, the second ground wiring layer is spaced apart from the first wiring layer, the first base substrate is interposed between the second ground wiring layer and the first wiring layer, the second base substrate is spaced apart from the first base substrate, the first wiring layer is interposed between the second base substrate and the first base substrate, wherein the first ground wiring layer may be spaced apart from the first wiring layer, and the second base substrate is interposed between the first ground wiring layer and the first wiring layer.

[0013] According to some example embodiments, the display device may further include a second substrate connected to the display panel and the first substrate, wherein the second substrate includes a driver chip.

[0014] According to some example embodiments, the first substrate may include a circuit board, and the second substrate may include a flexible circuit film.

[0015] According to some example embodiments, the display device may further include a main circuit board electrically connected to the first substrate, wherein the first signal wirings may be configured to receive transmission signals from the main circuit board.

[0016] According to some example embodiments, the transmission signal may include an image signal or a timing control signal, and the first signal wiring may be electrically connected to the driver chip.

[0017] According to some example embodiments, the second signal wiring may include power signal wiring.

[0018] According to some example embodiments, the first substrate may further include a power supply unit, and the second signal wiring may pass through the second substrate and may be electrically connected to the power wiring of the display panel.

[0019] According to some example embodiments, the first signal wiring may include a positive signal wiring and a negative signal wiring, wherein the absolute values of the signal intensities of the positive signal wiring and the negative signal wiring may be the same.

[0020] According to some example embodiments, the first ground wiring layer may include a shielding metal.

[0021] According to some example embodiments of the present disclosure, a display device includes: a display panel; and a first substrate connected to the display panel, wherein the first substrate includes: a first base substrate; a first wiring layer having a plurality of first signal wirings located on the first base substrate; a first ground wiring layer located on the first wiring layer; and a second wiring layer located on the first ground wiring layer and having a plurality of second signal wirings, wherein the first ground wiring layer includes a plurality of grid patterns and a plurality of openings surrounded by adjacent grid patterns, and the second signal wiring overlaps with the grid patterns in the thickness direction.

[0022] According to some example embodiments, the second signal wiring may not overlap with the plurality of openings in the thickness direction.

[0023] According to some example embodiments, the width of each of the second signal wirings may be less than the width of each of the grid patterns.

[0024] According to some example embodiments, the first signal wiring may extend along a first direction, and the grid pattern may include a first extension portion and a second extension portion that extend along the first direction and are spaced apart from each other in a second direction intersecting the first direction, and a connection portion physically connecting the first extension portion and the second extension portion, wherein the second signal wiring may extend along the direction in which the connection portion extends.

[0025] According to some example embodiments, the first substrate may further include a second ground wiring layer and a second base substrate. The second ground wiring layer is spaced apart from the first wiring layer. The first base substrate is interposed between the second ground wiring layer and the first wiring layer. The second base substrate is spaced apart from the first base substrate. The first wiring layer is interposed between the second base substrate and the first base substrate. Herein, the first ground wiring layer may be spaced apart from the first wiring layer, and the second base substrate is interposed between the first ground wiring layer and the first wiring layer.

[0026] According to some example embodiments, the display device may further include a second substrate connected to the display panel and the first substrate. Herein, the second substrate may include a driver chip.

[0027] According to some example embodiments, the display device may further include a main circuit board electrically connected to the first substrate. Herein, the first signal wiring may be configured to receive a transmission signal from the main circuit board.

[0028] According to some example embodiments, the transmission signal may include an image signal or a timing control signal, and the first signal wiring may be electrically connected to the driver chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other aspects will become more apparent and easier to understand by the following description of embodiments in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a perspective view of a display device according to some example embodiments;

[0031] Figure 2 is an exploded perspective view of a display device according to some example embodiments;

[0032] Figure 3 is a plan view of a display device according to some example embodiments;

[0033] Figure 4 is a block diagram of a display device according to some example embodiments;

[0034] Figure 5 is a plan layout view of a display panel, a flexible circuit film, and a driver circuit board according to some example embodiments;

[0035] Figure 6 is along Figure 5 a cross-sectional view taken along line VI-VI';

[0036] Figure 7 is Figure 5 an enlarged plan view of region A of

[0037] Figure 8 is a sectional view taken along the line VIII-VIII' of Figure 7 ;

[0038] Figure 9 is a sectional view taken along the line IX-IX' of Figure 7 ;

[0039] Figure 10 is a plan layout view of a display panel, a flexible circuit film, and a driver circuit board according to some example embodiments;

[0040] Figure 11 is Figure 10 a partially enlarged view of

[0041] Figure 12 is Figure 11 an enlarged plan view of region B of

[0042] Figure 13 is an exploded perspective view of a display device according to some example embodiments; and

[0043] Figure 14 is a plan layout view of a display panel, a flexible circuit film, and a driver circuit board according to some example embodiments. DETAILED DESCRIPTION

[0044] Certain features and characteristics of some example embodiments of the present disclosure and methods of implementing the same can be more readily understood by reference to the following detailed description of some example embodiments and the accompanying drawings. However, the embodiments according to the present disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art.

[0045] It will be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer can be directly on the other element or layer or there can be intervening elements or layers. The same reference numerals always refer to the same elements. The shapes, sizes, ratios, angles, and quantities, etc. shown in the drawings for describing the embodiments are only examples, and the present disclosure is not limited thereto.

[0046] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0047] The various features of some example embodiments of the present disclosure may be partially or fully combined or combined with each other, and various linkages and drives may be possible technically. The embodiments may be implemented independently or in association with each other.

[0048] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0049] Figure 1 is a perspective view of a display device 10 according to some example embodiments. Figure 2 is an exploded perspective view of a display device 10 according to some example embodiments. Figure 3 is a plan view of a display device 10 according to some example embodiments. Figure 4 is a block diagram of a display device 10 according to some example embodiments.

[0050] In this specification, the terms "above", "top", and "upper surface" indicate an upward direction from the display panel 300, that is, the Z-axis direction, and the terms "below", "bottom", and "lower surface" indicate a downward direction from the display panel 300, that is, the direction opposite to the Z-axis direction. Additionally, "left", "right", "up", and "down" indicate directions when observing the display panel 300 in a plan view (e.g., from a direction orthogonal to the main plane or flat surface of the display panel 300). For example, "left" indicates the direction opposite to the X-axis direction, "right" indicates the X-axis direction, "up" indicates the Y-axis direction, and "down" indicates the direction opposite to the Y-axis direction.

[0051] Referring to Figures 1 to 4 , the display device 10 is a device for displaying moving images or still images. The display device 10 may be used as a display screen in portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), and as a display screen in various products such as televisions, notebook computers, monitors, billboards, and any suitable electronic devices operating as part of the Internet of Things (IoT) (e.g., smart electronic devices, smart household appliances, proximity sensing devices, etc.).

[0052] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a micro light-emitting diode display device using micro light-emitting diodes. Hereinafter, the case where the display device 10 is an organic light-emitting display device will be mainly described, but the embodiments are not limited thereto. The display surface MA of the display device 10 may include a display area DA for displaying an image and a non-display area NDA positioned around the display area DA.

[0053] The display device 10 may include a cover window 100, a display panel 300, a flexible circuit film 400 or a second substrate, a circuit board 500 or a first substrate, a bracket 600, a main circuit board 700, and a bottom cover 900.

[0054] The cover window 100 may be positioned on the display panel 300 to cover the upper surface of the display panel 300. Accordingly, the cover window 100 may be used to protect the upper surface of the display panel 300 from, for example, external contaminants or damage caused by a force from an external object.

[0055] The cover window 100 may include a light-transmitting portion DA100 corresponding to the display panel 300 and a light-shielding portion NDA100 corresponding to regions other than the display panel 300. The cover window 100 may be positioned in a first region DR1 and a second region DR2. The light-transmitting portion DA100 may be positioned in a part of the first region DR1 and a part of each second region DR2. The light-shielding portion NDA100 may be formed to be opaque. Alternatively, the light-shielding portion NDA100 may be formed as a decorative layer having a pattern shown to a user when no image is being displayed. That is, according to some example embodiments, the light-shielding portion NDA100 may include decorative engraving or elements.

[0056] The display panel 300 may be positioned below the cover window 100. The display panel 300 may overlap with the light-transmitting portion DA100 of the cover window 100. The display panel 300 may be positioned in the first region DR1 and the second region DR2. Accordingly, an image of the display panel 300 may be seen not only in the first region DR1 but also in the second region DR2.

[0057] The display panel 300 may be a light-emitting display panel including a plurality of light-emitting elements. For example, the display panel 300 may be an organic light-emitting display panel using organic light-emitting diodes including an organic light-emitting layer, a micro light-emitting diode display panel using micro light-emitting diodes, a quantum dot light-emitting display panel including quantum dot light-emitting diodes including a quantum dot light-emitting layer, or an inorganic light-emitting display panel using inorganic light-emitting elements including an inorganic semiconductor. Embodiments in which the display panel 300 is an organic light-emitting display panel will be mainly described below, but the embodiments are not limited thereto.

[0058] The flexible circuit film 400 and the circuit board 500 may be attached to one side of the display panel 300. The flexible circuit film 400 may include a base film 410 and a driver circuit 450 positioned on the base film 410.

[0059] The end of the flexible circuit film 400 can be attached to the pad DP provided on one side of the display panel 300 by using an anisotropic conductive film. The flexible circuit film 400 can be a flexible printed circuit board capable of being bent, a rigid printed circuit board that is rigid and not easily bent, or a composite printed circuit board including both a rigid printed circuit board and a flexible printed circuit board.

[0060] The driver circuit 450 and the power supply unit 580 (as shown in Figure 5 the figure) for supplying a driving voltage to drive the display panel 300 can be positioned on the circuit board 500.

[0061] The bracket 600 can be positioned below the display panel 300. The bracket 600 can include plastic, metal, or both plastic and metal. The bracket 600 can include a first camera hole CMH1 into which the camera device 720 is inserted, a battery hole BH in which the battery BT is positioned, and a cable hole CAH through which the cable 590 connected to the circuit board 500 passes.

[0062] The main circuit board 700 and the battery BT can be positioned below the bracket 600. The main circuit board 700 can be a printed circuit board or a flexible printed circuit board.

[0063] The main circuit board 700 can include a main processor 710, a camera device 720, and a main connector 730. The main processor 710 can be formed as an integrated circuit.

[0064] The camera device 720 can be positioned on both the upper surface and the lower surface of the main circuit board 700, the main processor 710 can be positioned on the upper surface of the main circuit board 700, and the main connector 730 can be positioned on the lower surface of the main circuit board 700.

[0065] The main processor 710 can control all functions of the display device 10. For example, the main processor 710 can output digital video data to the flexible circuit film 400 through the circuit board 500 so that the display panel 300 can display an image.

[0066] The main processor 710 can be an application processor, a central processing unit, or a system-on-chip formed as an integrated circuit.

[0067] The camera device 720 processes image frames such as still images or moving images obtained by the image sensor in the camera mode and outputs the processed image frames to the main processor 710.

[0068] The cable 590 passing through the cable hole CAH of the bracket 600 can be connected to the main connector 730. Thus, the main circuit board 700 can be electrically connected to the circuit board 500.

[0069] The battery BT can be arranged such that it does not overlap with the main circuit board 700 in the third direction (Z-axis direction). The battery BT can overlap with the battery hole BH of the bracket 600.

[0070] The bottom cover 900 can be positioned below the main circuit board 700 and the battery BT. The bottom cover 900 can be fastened and fixed to the bracket 600. The bottom cover 900 can form the bottom outside the display device 10. The bottom cover 900 can include plastic, metal, or both plastic and metal.

[0071] A second camera hole CMH2 exposing the lower surface of the camera device 720 can be formed in the bottom cover 900. The position of the camera device 720 and the positions of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the camera device 720 are not limited to Figure 2 the embodiments shown.

[0072] The display panel 300 can be formed as a rectangular plane having a short side in the first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). Each corner where the short side extending in the first direction (X-axis direction) intersects the long side extending in the second direction (Y-axis direction) can be rounded with a curvature (e.g., a set or predetermined curvature), or can be a right angle. The planar shape of the display panel 300 is not limited to a quadrilateral shape, but can also be another polygon shape, a circular shape, or an oval shape. The display panel 300 can be formed flat. However, the embodiments are not limited thereto, and the display panel 300 can also include curved portions formed at its left and right ends and having a constant curvature or a varying curvature. Additionally, the display panel 300 can be formed to be flexible such that it can be bent, curved, folded, or curled.

[0073] The display panel 300 can include a display area DA in which pixels SP are formed to display an image and a non-display area NDA positioned around the display area DA (e.g., outside the occupancy area of the display area DA). The sub-pixels SP and the scan lines SL, emission lines EL, data lines DL, and first driving voltage lines VDDL connected to the sub-pixels SP can be positioned in the display area DA. The scan lines SL and the emission lines EL can extend parallel to each other in the first direction (X-axis direction), and the data lines DL can extend parallel to each other in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The first driving voltage lines VDDL can extend parallel to each other in the display area DA along the second direction (Y-axis direction). The first driving voltage lines VDDL extending parallel to each other in the display area DA along the second direction (Y-axis direction) can be connected to each other in the non-display area NDA.

[0074] Each sub-pixel SP may be connected to at least any one scanning line SL, any one data line DL, at least one emission line EL, and any one first driving voltage line VDDL. In Figure 3 as an example, a case is shown in which each sub-pixel SP is connected to two scanning lines SL, one data line DL, one emission line EL, and one first driving voltage line VDDL. However, the embodiments are not limited thereto. For example, each sub-pixel SP may also be connected to three scanning lines SL instead of two scanning lines SL.

[0075] Each sub-pixel SP may include a driving transistor, one or more switching transistors, a light-emitting element, and a capacitor. The switching transistor is turned on in response to a scanning signal received from the scanning line SL. Therefore, the data voltage of the data line DL can be applied to the gate electrode of the driving transistor. The driving transistor may supply a driving current to the light-emitting element according to the data voltage applied to the gate electrode, so that the light-emitting element emits light. The driving transistor and the switching transistor may be thin-film transistors. The light-emitting element may emit light according to the driving current of the driving transistor. The light-emitting element may be an organic light-emitting diode including a first electrode, an organic light-emitting layer, and a second electrode. The capacitor may keep the data voltage applied to the gate electrode of the driving transistor constant.

[0076] The non-display area NDA may be defined as an area extending from the outside of the display area DA to the edge of the display panel 300. In the non-display area NDA, a scan driver SCP for transmitting a scan signal to the scan line SL, a fan-out line FL located between the data line DL and the flexible circuit film 400, and a pad DP connected to the flexible circuit film 400 may be located. The flexible circuit film 400 and the pad DP may be located at the edge of the display panel 300. The pad DP may be located closer to the edge of the display panel 300 than the flexible circuit film 400.

[0077] The scan driver SCP may be connected to the flexible circuit film 400 through a plurality of scan control lines SCL. The scan driver SCP may receive a scan control signal SCS and an emission control signal ECS from the flexible circuit film 400 through the scan control line SCL.

[0078] The scan driver SCP may include a scan signal driver SDP and an emission signal driver EDP as shown in Figure 4 .

[0079] The scan signal driver SDP may generate a scan signal according to the scan control signal SCS and sequentially output the scan signal to the scan line SL. The emission signal driver EDP may generate an emission control signal according to the emission control signal ECS and sequentially output the emission control signal to the emission line EL.

[0080] The scan driver SCP may include a plurality of thin film transistors. The plurality of thin film transistors of the scan driver SCP may be formed on the same layer as the thin film transistors of the sub-pixels SP. Although the scan driver SCP is formed in the non-display area NDA located on one side of the display area DA (e.g., on the left side of the display area DA in Figure 3 ), the embodiments are not limited thereto. For example, according to some example embodiments, the scan driver SCP may be formed in the non-display areas NDA located on both sides of the display area DA (e.g., on the left and right sides of the display area DA).

[0081] The flexible circuit film 400 may include a timing controller TCP, a data driver DDP, and a power supply circuit PSP as shown in Figure 4 .

[0082] The timing controller TCP receives digital video data DATA and timing signals from the circuit board 500. According to the timing signals, the timing controller TCP may generate a scan control signal SCS for controlling the operation timing of the scan signal driver SDP, generate a transmission control signal ECS for controlling the operation timing of the emission signal driver EDP, and generate a data control signal DCS for controlling the operation timing of the data driver DDP. The timing controller TCP may output the scan control signal SCS to the scan signal driver SDP and output the transmission control signal ECS to the emission signal driver EDP through the scan control line SCL. The timing controller TCP may output the digital video data DATA and the data control signal DCS to the data driver DDP.

[0083] The data driver DDP converts the digital video data DATA into an analog positive / negative data voltage and outputs the analog positive / negative data voltage to the data lines DL through the fan-out lines FL. The sub-pixels SP are selected by the scan signal of the scan driver SCP, and the data voltage is supplied to the selected sub-pixels SP.

[0084] The power supply circuit PSP may generate a first driving voltage and supply the first driving voltage to the first driving voltage line VDDL. In addition, the power supply circuit PSP may generate a second driving voltage and supply the second driving voltage to the cathodes of the organic light emitting diodes of each sub-pixel SP. The first driving voltage may be a high potential voltage for driving the organic light emitting diodes, and the second driving voltage may be a low potential voltage for driving the organic light emitting diodes. That is, the first driving voltage may have a higher potential than the second driving voltage.

[0085] The flexible circuit film 400 may include a substrate film 410 and a driver circuit 450 positioned on the substrate film 410. That is, the driver circuit 450 may be formed as an integrated circuit and mounted on the substrate film 410 of the flexible circuit film 400 using a chip-on-flex (COF) method. However, the embodiments are not limited thereto, and the driver circuit 450 may also be positioned on the display panel 300 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic welding method.

[0086] The flexible circuit film 400 may be attached to the pad DP using an anisotropic conductive film. Accordingly, the lead lines ( Figure 5 the signal wirings TSL1 and TSL2 of Figure 5 and the signal wirings PL1 and PL2 of

[0087] Figure 5 is a plan layout view of the display panel 300, the flexible circuit film 400, and the driver circuit board 500 according to some example embodiments. Figure 6 is a cross-sectional view taken along the line Figure 5 VI-VI' of

[0088] Referring to Figure 5 and Figure 6 , the circuit board 500 includes a plurality of stacked components. The circuit board 500 may include a first substrate base SUB1, a first wiring layer 530 positioned on the first substrate base SUB1 and including a plurality of signal wirings TSL1 and TSL2, a second substrate base SUB2 positioned on the first wiring layer 530, a first ground wiring layer 550 positioned on the second substrate base SUB2, a third substrate base SUB3 positioned on the first ground wiring layer 550, and a second wiring layer 540 positioned on the third substrate base SUB3 and including a plurality of signal wirings PL1 and PL2.

[0089] Each of the substrate bases SUB1 to SUB3 may support the first wiring layer 530, the first ground wiring layer 550, and the second wiring layer 540. The substrate bases SUB1 to SUB3 may include a flexible material.

[0090] The circuit board 500 may further include a second ground wiring layer 510 spaced apart from the first wiring layer 530, with the first substrate base SUB1 interposed between the first wiring layer 530 and the second ground wiring layer 510.

[0091] The first signal wiring TSL1 and the second signal wiring TSL2 can electrically connect the main processor 710 of the main circuit board 700 to the driver circuit 450. The first signal wiring TSL1 and the second signal wiring TSL2 can receive an image data signal or a timing control signal generated by the main processor 710. The first signal wiring TSL1 and the second signal wiring TSL2 adjacent to each other can have signals of the same magnitude but opposite signs. For example, the first signal wiring TSL1 can have a positive value, and the second signal wiring TSL2 can have a negative value, but their signal magnitudes can be the same (having the same absolute value). Since the adjacent first signal wiring TSL1 and second signal wiring TSL2 have signals of the same magnitude and opposite signs, even if noise appears, the adjacent first signal wiring TSL1 and second signal wiring TSL2 can cancel out the noise.

[0092] The signal wirings TSL1 and TSL2 can extend upward to the region where the cable 590 (see Figure 2 ) is located.

[0093] Referring to Figure 5 , the first ground wiring layer 550 can be positioned in the central portion of the circuit board 500. In the region overlapping with the first ground wiring layer 550, the first signal wiring TSL1 and the second signal wiring TSL2 can extend along the second direction (Y-axis direction).

[0094] The first ground wiring layer 550 can prevent or reduce the electrical / magnetic effects or interactions between the first wiring layer 530 and the second wiring layer 540. The first ground wiring layer 550 can include a shielding metal. The shielding metal can be copper (Cu), but is not limited to copper (Cu).

[0095] In a plan view, the first ground wiring layer 550 can include a grid pattern region and a non-grid pattern region. Since the first ground wiring layer 550 has a grid pattern region, it can reduce the impedance of the signal wirings TSL1 and TSL2 of the first wiring layer 530.

[0096] The mesh pattern region of the first ground wiring layer 550 may include a plurality of mesh patterns and a plurality of openings surrounded by the plurality of mesh patterns. Among the plurality of openings, the signal wirings TSL1 and TSL2 of the first wiring layer 530 and the signal wirings PL1 and PL2 of the second wiring layer 540 may electrically affect each other, thereby degrading the signal quality. However, in the display device 10 according to some example embodiments, the first ground wiring layer 550 further includes a non-mesh pattern region in a region where the signal wiring of the first wiring layer 530 and the signal wiring of the second wiring layer 540 overlap each other in the thickness direction. Accordingly, the electrical effects between the signal wirings TSL1 and TSL2 of the first wiring layer 530 and the signal wirings PL1 and PL2 of the second wiring layer 540, which may otherwise cause signal quality degradation, can be prevented or reduced.

[0097] The signal wirings PL1 and PL2 of the second wiring layer 540 may extend from the power supply unit 580 and may be connected to the flexible circuit film 400. The signal wirings PL1 and PL2 may pass through the flexible circuit film 400 and may then be electrically connected to the first driving voltage line VDDL of the display panel 300 or the cathodes of each organic light emitting diode.

[0098] As Figure 5 shown, the third signal wiring PL1 extending from the power supply unit 580 may extend along the second direction (Y-axis direction) and may be connected to one side of the flexible circuit film 400 in the first direction (X-axis direction). On the other hand, as Figure 5 shown, the fourth signal wiring PL2 may extend along the first direction (X-axis direction) and may then be connected to the other side of the flexible circuit film 400 in the first direction (X-axis direction). The fourth signal wiring PL2 may overlap the first ground wiring layer 550 and the signal wirings TSL1 and TSL2 in the thickness direction. The fourth signal wiring PL2 and the signal wirings TSL1 and TSL2 that overlap each other may electrically affect each other. However, as described above, the first ground wiring layer 550 according to the embodiment further includes a non-mesh pattern region in a region where the signal wiring of the first wiring layer 530 and the signal wiring of the second wiring layer 540 overlap each other in the thickness direction. Accordingly, the electrical effects between the signal wirings TSL1 and TSL2 of the first wiring layer 530 and the signal wirings PL1 and PL2 of the second wiring layer 540, which may otherwise degrade the signal quality, can be prevented or reduced.

[0099] Similar to the first ground wiring layer 550, the second ground wiring layer 510 can prevent or reduce the degradation of the signal quality of the signal wirings TSL1 and TSL2 of the first wiring layer 530 due to other conductive elements located below the first substrate base SUB1. Different from the first ground wiring layer 550, the second ground wiring layer 510 may not include a grid pattern area and may include only a non-grid pattern area. However, embodiments are not limited thereto.

[0100] Figure 7 is Figure 5 an enlarged plan view of region A of. Figure 8 is a cross-sectional view taken along Figure 7 line VIII-VIII' of. Figure 9 is a cross-sectional view taken along Figure 7 line IX-IX' of.

[0101] Referring to Figures 7 to 9 , the first ground wiring layer 550 may include a grid pattern area and a non-grid pattern area. The grid pattern area may include a plurality of grid patterns and a plurality of openings surrounded by adjacent grid patterns. The non-grid pattern area may include a plurality of grid patterns and a plurality of non-grid patterns surrounded by adjacent grid patterns.

[0102] The grid patterns of the grid pattern area and the grid patterns of the non-grid pattern area may include extension portions 551 and 552 extending in a first direction (X-axis direction). The first extension portion 551 may be spaced apart from the second extension portion 552 in a second direction (Y-axis direction). The extension portions 551 and 552 may overlap the signal wirings PL1 and PL2 of the second wiring layer 540.

[0103] The grid patterns of the grid pattern area and the grid patterns of the non-grid pattern area may include a plurality of connection portions 553 to 562 physically connecting the first extension portion 551 and the second extension portion 552.

[0104] The second direction (Y-axis direction) may include a first side direction as the downward direction in Figure 7 and a second side direction as the upward direction in Figure 7 .

[0105] The connecting portions 553 to 557 may extend in a direction between the first direction (X-axis direction) and the first side direction of the second direction (Y-axis direction), and the connecting portions 558 to 562 may extend in a direction between the first direction (X-axis direction) and the second side direction of the second direction (Y-axis direction). That is, the extending directions of the connecting portions 553 to 557 and the extending directions of the connecting portions 558 to 562 may cross each other at the intersection point CSP. The connecting portions 553 to 557 may extend in a lower right direction from the first extending portion 551 and may be connected to the second extending portion 552, and the connecting portions 558 to 562 may extend in a lower left direction from the first extending portion 552 and may be connected to the second extending portion 552.

[0106] The first opening OP1 may be positioned in the space surrounded by the first extending portion 551, the first connecting portion 553, and the sixth connecting portion 558. The second opening OP2 may be positioned in the space surrounded by the first extending portion 551, the second connecting portion 554, and the seventh connecting portion 559. The third opening OP3 may be positioned in the space surrounded by the second extending portion 552, the first connecting portion 553, and the sixth connecting portion 558. The fourth opening OP4 may be positioned in the space surrounded by the second extending portion 552, the second connecting portion 554, and the seventh connecting portion 559. The fifth opening OP5 may be positioned in the space surrounded by the first extending portion 551, the second extending portion 552, the sixth connecting portion 558, the second connecting portion 554, the first connecting portion 553, and the seventh connecting portion 559. The sixth opening OP6 may be positioned in the space surrounded by the first extending portion 551, the third connecting portion 555, and the eighth connecting portion 560. The seventh opening OP7 may be positioned in the space surrounded by the second extending portion 552, the third connecting portion 555, and the eighth connecting portion 560. The first non-grid pattern 563 may be positioned in the space surrounded by the first extending portion 551, the second extending portion 552, the seventh connecting portion 559, the second connecting portion 554, the third connecting portion 555, and the eighth connecting portion 560. The fourth non-grid pattern 566 may be positioned in the space surrounded by the first extending portion 551, the fourth connecting portion 556, and the ninth connecting portion 561. The third non-grid pattern 565 may be positioned in the space surrounded by the second extending portion 552, the fourth connecting portion 556, and the ninth connecting portion 561. The second non-grid pattern 564 may be positioned in the space surrounded by the first extending portion 551, the second extending portion 552, the ninth connecting portion 561, the fourth connecting portion 556, the fifth connecting portion 557, and the tenth connecting portion 562.

[0107] The non-grid patterns 563 to 566 may be physically connected to adjacent connecting portions.

[0108] The openings OP1 to OP7 can completely penetrate the first ground wiring layer 550 in the thickness direction from the surface of the first ground wiring layer 550.

[0109] Referring Figure 7 and Figure 8 , the signal wirings TSL1 and TSL2 can overlap, in the thickness direction, with the connection portions 553 to 557 extending in a direction between the first side direction of the first direction (X-axis direction) and the second direction (Y-axis direction), the connection portions 558 to 562 extending in a direction between the second side direction of the first direction (X-axis direction) and the second direction (Y-axis direction), the openings OP1 to OP7, and the non-mesh patterns 563 to 566.

[0110] The signal wirings PL1 and PL2 can overlap, in the thickness direction, with the signal wirings TSL1 and TSL2.

[0111] As Figure 7 and Figure 9 shown, the signal wirings PL1 and PL2 located on the right side can overlap, in the thickness direction, with the third connection portion 555, the first non-mesh pattern 563, and the eighth connection portion 560. The signal wirings PL1 and PL2 located on the left side can overlap, in the thickness direction, with the fourth non-mesh pattern 566, the fourth connection portion 556, the ninth connection portion 561, the third non-mesh pattern 565, and the second non-mesh pattern 564.

[0112] The signal wirings PL1 and PL2 located on the right side can overlap, in the thickness direction, with the extension portions 551 and 552, the seventh connection portion 559, the third connection portion 555, the first non-mesh pattern 563, the second connection portion 554, and the eighth connection portion 560 in the region where they overlap with the signal wirings TSL1 and TSL2 in the thickness direction. The signal wirings PL1 and PL2 located on the left side can overlap, in the thickness direction, with the extension portions 551 and 552, the fourth connection portion 556, the ninth connection portion 561, the fifth connection portion 557, and the non-mesh patterns 564 to 566 in the region where they overlap with the signal wirings TSL1 and TSL2 in the thickness direction.

[0113] As described above, the fourth signal wiring PL2 can overlap with the first ground wiring layer 550 and the signal wirings TSL1 and TSL2 in the thickness direction. The fourth signal wiring PL2 and the signal wirings TSL1 and TSL2 that overlap with each other may electrically affect each other. However, as described above, the first ground wiring layer 550 according to the embodiment further includes a non-grid pattern region in a region where the signal wiring of the first wiring layer 530 and the signal wiring of the second wiring layer 540 overlap with each other in the thickness direction. Therefore, the electrical influence or interaction between the signal wirings TSL1 and TSL2 of the first wiring layer 530 and the signal wirings PL1 and PL2 of the second wiring layer 540 that may otherwise deteriorate the signal quality can be prevented or reduced.

[0114] Now, further details according to some example embodiments will be described in more detail below. In the following embodiments, the description of elements that are the same as those in the above embodiments may be omitted or briefly described, and the differences will be mainly described.

[0115] Figure 10 is a plan layout diagram of a display panel 300, a flexible circuit film 400, and a driver circuit board 500 according to some example embodiments. Figure 11 is Figure 10 a partial enlarged view of Figure 12 is Figure 11 an enlarged plan view of region B of

[0116] Referring to Figures 10 to 12 , the display device according to some example embodiments is different from the display device 10 shown in Figure 5 in that the fourth signal wiring PL2_1 extends between the first side direction of the first direction (X-axis direction) and the second direction (Y-axis direction) in a region where they overlap with the signal wirings TSL1 and TSL2.

[0117] Each fourth signal wiring PL2_1 may include a first sub-wiring portion PL21 extending in the first direction (X-axis direction), a second sub-wiring portion PL22, and a third sub-wiring portion PL23 physically connecting the first sub-wiring portion PL21 and the second sub-wiring portion PL22. The third sub-wiring portion PL23 may overlap with the signal wirings TSL1 and TSL2 in the thickness direction.

[0118] The first ground wiring layer 550_1 may include a grid pattern region. Different from the first ground wiring layer 550 of Figure 7 , the first ground wiring layer 550_1 may not include a non-grid pattern region. The grid pattern region may include a plurality of grid patterns and a plurality of openings surrounded by adjacent grid patterns.

[0119] The grid pattern in the grid pattern region may include extension portions 551 and 552 extending in a first direction (X-axis direction). The first extension portion 551 may be spaced apart from the second extension portion 552 in a second direction (Y-axis direction). The extension portions 551 and 552 may overlap with the signal wirings PL1 and PL2_1 of the second wiring layer 540.

[0120] The grid pattern in the grid pattern region and the grid pattern in the non-grid pattern region may include a plurality of connection portions 553 to 556 physically connecting the first extension portion 551 and the second extension portion 552.

[0121] The connection portions 553 and 554 may extend in a direction between the first direction (X-axis direction) and a first side direction of the second direction (Y-axis direction), and the connection portions 555 and 556 may extend in a direction between the first direction (X-axis direction) and a second side direction of the second direction (Y-axis direction).

[0122] That is, the extending directions of the connection portions 553 and 554 and the extending directions of the connection portions 555 and 556 may cross each other at the intersection point CSP. The connection portions 553 and 554 may extend from the first extension portion 551 in the lower right direction and may be connected to the second extension portion 552, and the connection portions 555 and 556 may extend from the first extension portion 551 in the lower left direction and may be connected to the second extension portion 552.

[0123] The first opening OP1 may be positioned in the space surrounded by the first extension portion 551, the first connection portion 553, and the third connection portion 555. The second opening OP2 may be positioned in the space surrounded by the first extension portion 551, the second connection portion 554, and the fourth connection portion 556. The third opening OP3 may be positioned in the space surrounded by the second extension portion 552, the first connection portion 553, and the third connection portion 555. The fourth opening OP4 may be positioned in the space surrounded by the second extension portion 552, the second connection portion 554, and the fourth connection portion 556. The fifth opening OP5 may be positioned in the space surrounded by the first extension portion 551, the second extension portion 552, the first connection portion 553, the second connection portion 554, the third connection portion 555, and the fourth connection portion 556.

[0124] The openings OP1 to OP4 may completely penetrate the first ground wiring layer 550_1 in the thickness direction from the surface of the first ground wiring layer 550_1.

[0125] Refer to Figure 11, the signal wirings TSL1 and TSL2 can overlap in the thickness direction with the connection portions 553 and 554 extending in a direction between the first side direction of the first direction (X-axis direction) and the second direction (Y-axis direction), the connection portions 555 and 556 extending in a direction between the second side direction of the first direction (X-axis direction) and the second direction (Y-axis direction), and the openings OP1 to OP5.

[0126] The signal wirings PL1 and PL2_1 can overlap with the signal wirings TSL1 and TSL2 in the thickness direction.

[0127] The signal wirings PL1 and PL2_1 can overlap with the first connection portion 553 or the second connection portion 554 in the thickness direction. According to some example embodiments, the signal wirings PL1 and PL2_1 can extend in the same direction as the connection portions 553 and 554.

[0128] In some embodiments, when the signal wirings PL1 and PL2_1 extend in the same direction as the connection portions 555 and 556, the signal wirings PL1 and PL2_1 can overlap with the third connection portion 555 or the fourth connection portion 556 in the thickness direction.

[0129] Referring to Figure 12 , the width W1 of each of the signal wirings PL1 and PL2_1 in the first direction (X-axis direction) can be smaller than the width W2 of each of the connection portions 553 and 554 in the first direction (X-axis direction).

[0130] The fourth signal wiring PL2_1 can overlap with the first ground wiring layer 550_1 and the signal wirings TSL1 and TSL2 in the thickness direction. The fourth signal wiring PL2_1 overlapping with the signal wirings TSL1 and TSL2 may electrically affect each other. However, only the connection portions of the first ground wiring layer 550_1 including the grid pattern regions cover the fourth signal wiring PL2_1 in a region in a plan view where the signal wirings of the first wiring layer 530 and the signal wirings of the second wiring layer 540 overlap with each other in the thickness direction. Therefore, the electrical influence or interaction between the signal wirings TSL1 and TSL2 of the first wiring layer 530 and the signal wirings PL1 and PL2_1 of the second wiring layer 540 that may otherwise deteriorate the signal quality can be prevented or reduced.

[0131] Figure 13 is an exploded perspective view of the display device 11 according to some example embodiments. Figure 14 is a planar layout diagram of the display panel 300, the flexible circuit film 400, and the driver circuit board 500 according to some example embodiments.

[0132] Referring to Figure 13 andFigure 14 , the display device 11 according to some example embodiments differs from the display device 10 shown in Figure 2 in that the power driver is omitted from the circuit board 500, and the main circuit board 700 further includes a power driver 740.

[0133] For example, in the display device 11 according to some example embodiments, the power driver may be omitted from the circuit board 500, and the main circuit board 700 may further include a power driver 740.

[0134] Referring to Figure 14 , the signal wirings TSL1 and TSL2 and the signal wirings PL1_1 and PL2_2 may extend upward to the region where the cable 590 is located (see Figure 2 ).

[0135] Although the present disclosure has been specifically shown and described with reference to example embodiments of the present disclosure, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the present disclosure. The example embodiments should be considered only in a descriptive sense and not for purposes of limitation.

Claims

1. A display device, wherein, The display device includes: A display panel; and A first substrate connected to the display panel, wherein the first substrate includes: A first base substrate; A first wiring layer having a plurality of first signal wirings located on the first base substrate; A first ground wiring layer located on the first wiring layer; and A second wiring layer located on the first ground wiring layer, the second wiring layer having a plurality of second signal wirings, wherein the first ground wiring layer includes a grid pattern region and a non-grid pattern region, wherein the grid pattern region includes a plurality of first grid patterns and a plurality of openings surrounded by adjacent first grid patterns, and the non-grid pattern region includes a plurality of second grid patterns and a plurality of non-grid patterns surrounded by adjacent second grid patterns, wherein the plurality of non-grid patterns are physically connected to the adjacent second grid patterns, wherein the first signal wirings extend in a first direction, and the second signal wirings extend in a second direction intersecting the first direction, the grid pattern region is located in a region where the first signal wirings and the second signal wirings do not overlap, and the non-grid pattern region is located in a region where the first signal wirings and the second signal wirings overlap.

2. The display device according to claim 1, wherein, The first substrate further includes a second ground wiring layer and a second base substrate, the second ground wiring layer is spaced apart from the first wiring layer, the first base substrate is interposed between the second ground wiring layer and the first wiring layer, the second base substrate is spaced apart from the first base substrate, the first wiring layer is interposed between the second base substrate and the first base substrate, wherein the first ground wiring layer is spaced apart from the first wiring layer, and the second base substrate is interposed between the first ground wiring layer and the first wiring layer.

3. The display device according to claim 1, wherein, The display device further includes a second substrate connected to the display panel and the first substrate, wherein the second substrate includes a driver chip.

4. The display device according to claim 3, wherein, The first substrate includes a circuit board, and the second substrate includes a flexible circuit film.

5. The display device according to claim 3, wherein, The display device further includes a main circuit board electrically connected to the first substrate, wherein the first signal wirings are configured to receive transmission signals from the main circuit board.

6. The display device according to claim 5, wherein, The transmission signals include image signals or timing control signals, and the first signal wirings are electrically connected to the driver chip.

7. The display device according to claim 6, wherein, The second signal wirings include power signal wirings.

8. The display device according to claim 7, wherein, The first substrate further includes a power supply unit, and the second signal wirings pass through the second substrate and are electrically connected to the power wirings of the display panel.

9. The display device according to claim 1, wherein, The first signal wirings include positive signal wirings and negative signal wirings, wherein the absolute values of the signal strengths of the positive signal wirings and the negative signal wirings are the same.

10. The display device according to claim 1, wherein, The first ground wiring layer includes a shielding metal.

11. A display device, wherein, The display device includes: A display panel; and A first substrate connected to the display panel, wherein the first substrate includes: A first base substrate; A first wiring layer having a plurality of first signal wirings located on the first base substrate; A first ground wiring layer located on the first wiring layer; and A second wiring layer is located on the first ground wiring layer and has a plurality of second signal wirings. Among them, the first ground wiring layer includes a plurality of grid patterns and a plurality of openings surrounded by adjacent grid patterns, and the second signal wirings overlap with the grid patterns in the thickness direction. Among them, the first signal wiring extends along a first direction, and the grid pattern includes a first extension portion and a second extension portion that extend along the first direction and are spaced apart from each other in a second direction intersecting the first direction, and a connection portion that physically connects the first extension portion and the second extension portion. Among them, the second signal wiring extends along the direction in which the connection portion extends, and Among them, in the thickness direction, the connection portion overlaps with the second signal wiring in a region where the first signal wiring and the second signal wiring overlap each other.

12. The display device according to claim 11, wherein, The second signal wirings do not overlap with the plurality of openings in the thickness direction.

13. The display device according to claim 11, wherein, The width of each second signal wiring is smaller than the width of each grid pattern.

14. The display device according to claim 11, wherein, The first substrate further includes a second ground wiring layer and a second base substrate. The second ground wiring layer is spaced apart from the first wiring layer. The first base substrate is interposed between the second ground wiring layer and the first wiring layer. The second base substrate is spaced apart from the first base substrate. The first wiring layer is interposed between the second base substrate and the first base substrate. Among them, the first ground wiring layer is spaced apart from the first wiring layer. The second base substrate is interposed between the first ground wiring layer and the first wiring layer.

15. The display device according to claim 11, wherein, The display device further includes a second substrate connected to the display panel and the first substrate. Among them, the second substrate includes a driver chip.

16. The display device according to claim 15, wherein, The display device further includes a main circuit board electrically connected to the first substrate. Among them, the first signal wiring is configured to receive a transmission signal from the main circuit board.

17. The display device according to claim 16, wherein, The transmission signal includes an image signal or a timing control signal, and the first signal wiring is electrically connected to the driver chip.

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