semiconductor devices

Abstract

A semiconductor device is provided, the semiconductor device comprising: a substrate having a first region and a second region; a first nanowire and a second nanowire sequentially disposed on the substrate in the first region and extending in a first direction; a third nanowire and a fourth nanowire sequentially disposed on the substrate in the second region and extending in a first direction; a first inner spacer located between the first nanowire and the second nanowire and comprising hydrogen with a first hydrogen molar fraction; and a second inner spacer located between the third nanowire and the fourth nanowire and comprising hydrogen with a second hydrogen molar fraction greater than the first hydrogen molar fraction.

Description

[0001] Korean Patent Application No. 10-2019-0091531, entitled "Semiconductor Device," filed on July 29, 2019, in the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments relate to a semiconductor device. BACKGROUND

[0003] A multi-gate transistor has been proposed as one of scaling techniques for increasing the density of a semiconductor device, in which a fin-shaped silicon body or a nanowire-shaped silicon body is formed on a substrate, and then a gate is formed on a surface of the silicon body.

[0004] Such a multi-gate transistor allows easy scaling since it uses a three-dimensional channel. Furthermore, current control capability can be enhanced without increasing the gate length of the multi-gate transistor. Not only that, but it is also possible to effectively suppress a short channel effect (SCE) in which the potential of a channel region is affected by a drain voltage. SUMMARY

[0005] Embodiments relate to a semiconductor device including a substrate having a first region and a second region; first and second nanowires disposed sequentially on the substrate in the first region and each extending in a first direction; third and fourth nanowires disposed sequentially on the substrate in the second region and each extending in the first direction; a first inner spacer between the first and second nanowires and including hydrogen at a first hydrogen mole fraction; and a second inner spacer between the third and fourth nanowires and including hydrogen at a second hydrogen mole fraction greater than the first hydrogen mole fraction.

[0006] Embodiments also relate to a semiconductor device including a substrate having a first region and a second region; first and second nanowires disposed sequentially on the substrate in the first region and each extending in a first direction; third and fourth nanowires disposed sequentially on the substrate in the second region and each extending in the first direction; a first gate electrode surrounding the first and second nanowires and extending in a second direction different from the first direction; a second gate electrode surrounding the third and fourth nanowires and extending in the second direction; a first inner spacer on at least one side of the first gate electrode between the first and second nanowires and including oxygen at a first oxygen mole fraction; and a second inner spacer on at least one side of the second gate electrode between the third and fourth nanowires and including oxygen at a second oxygen mole fraction greater than the first oxygen mole fraction.

[0007] Embodiments also relate to a semiconductor device including a substrate having a first region and a second region; a first nanowire, a second nanowire, and a third nanowire disposed sequentially on the substrate in the first region and each extending in a first direction; a fourth nanowire, a fifth nanowire, and a sixth nanowire disposed sequentially on the substrate in the second region and each extending in the first direction; a first gate electrode surrounding the first nanowire, the second nanowire, and the third nanowire and extending in a second direction different from the first direction; a second gate electrode surrounding the fourth nanowire, the fifth nanowire, and the sixth nanowire and extending in the second direction; a first source / drain region on at least one side of the first nanowire, the second nanowire, and the third nanowire; a second source / drain region on at least one side of the fourth nanowire, the fifth nanowire, and the sixth nanowire; a first inner spacer on at least one side of the first gate electrode between the first nanowire and the second nanowire and including oxygen at a first oxygen mole fraction and hydrogen at a first hydrogen mole fraction; a second inner spacer on at least one side of the second gate electrode between the fourth nanowire and the fifth nanowire and including oxygen at a second oxygen mole fraction greater than the first oxygen mole fraction and hydrogen at a second hydrogen mole fraction greater than the first hydrogen mole fraction; a first source contact / drain contact connected to the first source / drain region; and a second source contact / drain contact connected to the second source / drain region. BRIEF DESCRIPTION OF DRAWINGS

[0008] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example embodiments in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A schematic top view of a semiconductor device according to an example embodiment is shown;

[0010] Figure 2 A cross-sectional view taken along line A-A' of Figure 1 is shown;

[0011] Figure 3 A cross-sectional view taken along line B-B' of Figure 1 is shown;

[0012] Figure 4 An enlarged view of regions R1 and R2 of Figure 2 is shown;

[0013] Figure 5 An enlarged view of regions R1 and R2 of Figure 2 according to another example embodiment is shown;

[0014] Figure 6 An enlarged view of regions R1 and R2 of Figure 2 according to another example embodiment is shown;

[0015] Figure 7 An example embodiment is shown. Figure 2 Enlarged views of regions R1 and R2;

[0016] Figure 8 An example embodiment is shown. Figure 2 Enlarged views of regions R1 and R2;

[0017] Figure 9 An example embodiment is shown. Figure 2 Enlarged views of regions R1 and R2;

[0018] Figure 10 An example embodiment is shown. Figure 2 Enlarged views of regions R1 and R2;

[0019] Figure 11 A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0020] Figure 12 A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0021] Figure 13 A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0022] Figure 14 A cross-sectional view of a semiconductor device according to another example embodiment is shown; and

[0023] Figure 15 A cross-sectional view of a semiconductor device according to another example embodiment is shown. Detailed Implementation

[0024] In the following text, reference will be made to Figures 1 to 4 A semiconductor device according to an example embodiment is described. Figure 1 It is a schematic top view. Figure 2 It is along Figure 1 A sectional view taken by line A-A'. Figure 3 It is along Figure 1 The sectional view taken by line B-B'. Figure 4 yes Figure 2 Enlarged views of regions R1 and R2.

[0025] Reference Figures 1 to 4According to an example embodiment, a semiconductor device includes a substrate 100, a device isolation film 105, a first lower pattern 101, a second lower pattern 102, a first nanowire 111, a second nanowire 112, a third nanowire 113, a fourth nanowire 114, a fifth nanowire 115, and a sixth nanowire 116, a first gate structure 120, a second gate structure 130, a first pinched gate structure 120_1, a second pinched gate structure 120_2, a third pinched gate structure 130_1, and a fourth pinched gate structure 130_2, a first source / drain region 151, a second source / drain region 152, a first interlayer insulating film 162, a second interlayer insulating film 170, a first source / drain contact 181, a second source / drain contact 182, a first silicide film 191, and a second silicide film 192. (For ease of explanation, Figure 1 The first interlayer insulating film 162, the second interlayer insulating film 170, the first source / drain contact 181, and the second source / drain contact 182 are not shown.

[0026] The substrate 100 can be, for example, bulk silicon or silicon-on-insulator (SOI). In an embodiment, the substrate 100 can be a silicon substrate, or can include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, etc.

[0027] On the substrate 100, a first region I and a second region II can be defined. The first region I can include the first lower pattern 101, and the second region II can include the second lower pattern 102. The first region I can be, for example, an NMOS region, and the second region II can be, for example, a PMOS region.

[0028] Threshold voltages in the first region I and the second region II can be different from each other. For example, the threshold voltage of the first region I can be greater than the threshold voltage of the second region II.

[0029] The first lower pattern 101 and the second lower pattern 102 can respectively protrude from the substrate 100. The first lower pattern 101 and the second lower pattern 102 can respectively extend longitudinally in a first direction X. The first lower pattern 101 and the second lower pattern 102 can be aligned in the first direction X as a length direction. The first lower pattern 101 and the second lower pattern 102 can be spaced apart from each other in the first direction X.

[0030] The first lower pattern 101 and the second lower pattern 102 can be respectively formed by etching a portion of the substrate 100, and can include an epitaxial layer grown from the substrate 100.

[0031] The first lower pattern 101 and the second lower pattern 102 can have, for example, a needle-type pattern shape. The first lower pattern 101 and the second lower pattern 102 can be isolated by the device isolation film 105.

[0032] The device isolation film 105 can be provided on the substrate 100. The device isolation film 105 can be provided on the sidewalls of the first lower pattern 101 and the second lower pattern 102. The device isolation film 105 can include, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0033] Figure 2 An example in which three nanowires 111, 112, 113 are sequentially stacked on the substrate 100 in the first region I and other three nanowires 114, 115, 116 are sequentially stacked on the substrate 100 in the second region II is shown. According to another example embodiment, the number of nanowires provided on the substrate 100 in the first region I can be different from the above, and the number of nanowires provided on the substrate 100 in the second region II can also be different from the above.

[0034] The first nanowire 111, the second nanowire 112, and the third nanowire 113 can be sequentially spaced apart from each other in the first region I on the substrate 100 in a third direction Z, in which Z is a thickness direction of the substrate 100. For example, the first nanowire 111 can be provided on the substrate 100 in the first region I to be spaced apart therefrom in the third direction Z. The second nanowire 112 can be provided on the first nanowire 111 to be spaced apart therefrom in the third direction Z. The third nanowire 113 can be provided on the second nanowire 112 to be spaced apart therefrom in the third direction Z.

[0035] Each of the first nanowire 111, the second nanowire 112, and the third nanowire 113 can extend in the first direction X. Each of the first nanowire 111, the second nanowire 112, and the third nanowire 113 can serve as a channel region of an NMOS transistor. Each of the first nanowire 111, the second nanowire 112, and the third nanowire 113 can include, for example, a material having a high mobility with respect to electrons.

[0036] The fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116 can be provided on the substrate 100 in the second region II to be sequentially spaced apart from each other in the third direction Z. For example, the fourth nanowire 114 can be provided on the substrate 100 in the second region II to be spaced apart therefrom in the third direction Z. The fifth nanowire 115 can be provided on the fourth nanowire 114 to be spaced apart therefrom in the third direction Z. The sixth nanowire 116 can be provided on the fifth nanowire 115 to be spaced apart therefrom in the third direction Z.

[0037] The fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116 can each extend in the first direction X. Each of the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116 can function as a channel region of a PMOS transistor. Each of the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116 can include a material having a high mobility with respect to holes, for example.

[0038] The first nanowire 111 can be disposed at the same level as the fourth nanowire 114. The second nanowire 112 can be disposed at the same level as the fifth nanowire 115. The third nanowire 113 can be disposed at the same level as the sixth nanowire 116.

[0039] The first gate structure 120 can be disposed on the substrate 100 in the first region I. The first gate structure 120 can extend in the second direction Y and cross the first lower pattern 101.

[0040] The first pinched gate structure 120_1 can be spaced apart from the first gate structure 120 on the substrate 100 in the first region I in the first direction X. The first pinched gate structure 120_1 can extend in the second direction Y and cross the first lower pattern 101.

[0041] In the first region I, the second pinched gate structure 120_2 can be spaced apart from the first gate structure 120 on the substrate 100 in the first direction X. The second pinched gate structure 120_2 can extend in the second direction Y and cross the first lower pattern 101. The first gate structure 120 can be disposed between the first pinched gate structure 120_1 and the second pinched gate structure 120_2.

[0042] The first gate structure 120 can be completely overlapped with the first lower pattern 101. Each of the first pinched gate structure 120_1 and the second pinched gate structure 120_2 can be overlapped with a portion of the first lower pattern 101. For example, a width in which the first gate structure 120 in the first direction X crosses the first lower pattern 101 can be the same as a width of the first gate structure 120 in the first direction X. A width in which the first pinched gate structure 120_1 in the first direction X crosses the first lower pattern 101 can be smaller than a width of the first pinched gate structure 120_1 in the first direction X. A width in which the second pinched gate structure 120_2 in the first direction X crosses the first lower pattern 101 can be smaller than a width of the second pinched gate structure 120_2 in the first direction X.

[0043] The first gate structure 120 can surround the first nanowire 111, the second nanowire 112, and the third nanowire 113. The first trenched gate structure 120_1 can surround (e.g., completely surround) an end portion of each of the first nanowire 111, the second nanowire 112, and the third nanowire 113. The second trenched gate structure 120_2 can completely surround another end portion of each of the first nanowire 111, the second nanowire 112, and the third nanowire 113, the other end portion being opposite to the end portion of each of the first nanowire 111, the second nanowire 112, and the third nanowire 113 surrounded by the first trenched gate structure 120_1.

[0044] The first source / drain region 151 can be disposed between the first nanowire 111, the second nanowire 112, and the third nanowire 113 surrounded by the first gate structure 120 and the first nanowire 111, the second nanowire 112, and the third nanowire 113 surrounded by the first trenched gate structure 120_1. Also, the first source / drain region 151 can be disposed between the first nanowire 111, the second nanowire 112, and the third nanowire 113 surrounded by the first gate structure 120 and the first nanowire 111, the second nanowire 112, and the third nanowire 113 surrounded by the second trenched gate structure 120_2.

[0045] The second gate structure 130 can be disposed on the substrate 100 in the second region II. The second gate structure 130 can extend in the second direction Y and cross the second lower pattern 102.

[0046] The third trenched gate structure 130_1 can be spaced apart from the second gate structure 130 on the substrate 100 in the second region II in the first direction X. The third trenched gate structure 130_1 can extend in the second direction Y and cross the second lower pattern 102.

[0047] The fourth trenched gate structure 130_2 can be spaced apart from the second gate structure 130 on the substrate 100 in the second region II in the first direction X. The fourth trenched gate structure 130_2 can extend in the second direction Y and cross the second lower pattern 102. The second gate structure 130 can be disposed between the third trenched gate structure 130_1 and the fourth trenched gate structure 130_2.

[0048] The second gate structure 130 can be completely stacked with the second lower pattern 102. Each of the third pin-cut gate structure 130_1 and the fourth pin-cut gate structure 130_2 can be stacked with a portion of the second lower pattern 102. For example, the width at which the second gate structure 130 intersects with the second lower pattern 102 in the first direction X can be the same as the width of the second gate structure 130 in the first direction X. The width at which the third pin-cut gate structure 130_1 intersects with the second lower pattern 102 in the first direction X can be less than the width of the third pin-cut gate structure 130_1 in the first direction X. The width at which the fourth pin-cut gate structure 130_2 intersects with the second lower pattern 102 in the first direction X can be less than the width of the fourth pin-cut gate structure 130_2 in the first direction X.

[0049] The second gate structure 130 may surround the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116. The third pin-cut gate structure 130_1 may surround (e.g., completely surround) one end of each of the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116. The fourth pin-cut gate structure 130_2 may surround (e.g., completely surround) the other end of each of the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116, said other end being opposite the end of each of the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116 surrounded by the third pin-cut gate structure 130_1.

[0050] The second source / drain region 152 can be disposed between the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116 surrounded by the second gate structure 130 and the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116 surrounded by the third pin-cut gate structure 130_1. Furthermore, the second source / drain region 152 can be disposed between the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116 surrounded by the second gate structure 130 and the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116 surrounded by the fourth pin-cut gate structure 130_2.

[0051] Each of the first gate structure 120, the first pin-cut gate structure 120_1, and the second pin-cut gate structure 120_2 may include a first gate electrode 121, a first gate insulating film 122, a first capping pattern 123, a first outer spacer 124, and a first inner spacer 141.

[0052] Each of the second gate structure 130, the third pin-cut gate structure 130_1, and the fourth pin-cut gate structure 130_2 may include a second gate electrode 131, a second gate insulating film 132, a second capping pattern 133, a second outer spacer 134, and a second inner spacer 142.

[0053] In the following text, the first gate structure 120, the first pin-cut gate structure 120_1, and the second pin-cut gate structure 120_2 will be described. The descriptions related to the second gate structure 130, the third pin-cut gate structure 130_1, and the fourth pin-cut gate structure 130_2 can be readily understood from the descriptions related to the first gate structure 120, the first pin-cut gate structure 120_1, and the second pin-cut gate structure 120_2.

[0054] In the first region I, the first gate electrode 121 may extend on the substrate 100 in the second direction Y. The first gate electrode 121 may surround each of the first nanowire 111, the second nanowire 112, and the third nanowire 113.

[0055] The first gate electrode 121 may include at least one of the following materials, such as titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and carbonitride. Tantalum (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. The first gate electrode 121 may comprise conductive metal oxides, conductive metal nitrides, or oxides of the aforementioned materials.

[0056] The first gate insulating film 122 can be disposed along the two sidewalls and the bottom surface of the first gate electrode 121. The first gate insulating film 122 can be disposed between the substrate 100 and the first gate electrode 121, between the device isolation film 105 and the first gate electrode 121, between the first nanowire 111 and the first gate electrode 121, between the second nanowire 112 and the first gate electrode 121, and between the third nanowire 113 and the first gate electrode 121 in the first region I. Furthermore, the first gate insulating film 122 can be disposed between the first inner spacer 141 and the first gate electrode 121, and between the first outer spacer 124 and the first gate electrode 121.

[0057] The first gate insulating film 122 may comprise at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k dielectric material (i.e., a material having a higher dielectric constant than silicon oxide). For example, the high-k dielectric material may comprise one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0058] The first capping pattern 123 may be disposed on the first gate electrode 121. Although the first gate insulating film 122 is shown not disposed between the first outer spacer 124 and the first capping pattern 123, this is provided only for ease of explanation.

[0059] although Figure 2 The illustration shows a first capping pattern 123 formed between the inner sidewalls of the first outer spacer 124. However, according to another example embodiment, the upper surface of the first outer spacer 124 may be recessed below the upper surface of the first interlayer insulating film 162, as is the case with the first gate electrode 121. In this case, the first capping pattern 123 may be disposed on the upper surfaces of both the first outer spacer 124 and the first gate electrode 121.

[0060] The upper surface of the first capping pattern 123 may be formed on the same plane as the upper surface of the first interlayer insulating film 162. The first capping pattern 123 may include, for example, a material that is etch-selective to the first interlayer insulating film 162. For example, the first capping pattern 123 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbide nitride (SiCN), silicon carbonitride oxycarbonide (SiOCN), and combinations thereof.

[0061] The first outer spacer 124 may extend along the sidewall of the first gate electrode 121 on the third nanowire 113 in the second direction Y. The first outer spacer 124 may intersect with the first nanowire 111, the second nanowire 112 and the third nanowire 113.

[0062] The portion of the first outer spacer 124 included in the first pin-cut gate structure 120_1 may extend along the sidewall of the first gate electrode 121 in the second direction Y on the device isolation film 105. Furthermore, the portion of the first outer spacer 124 included in the second pin-cut gate structure 120_2 may extend along the sidewall of the first gate electrode 121 in the second direction Y on the device isolation film 105.

[0063] although Figure 2 The first outer spacer 124 is shown to be formed as a single membrane, but according to another example embodiment, the first outer spacer 124 may be formed as a multilayer membrane.

[0064] The first outer spacer 124 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon oxycarbonitride (SiOC), and combinations thereof.

[0065] The first source / drain region 151 can be disposed between the first gate structure 120 and the first pin-cut gate structure 120_1 and between the first gate structure 120 and the second pin-cut gate structure 120_2, respectively. The first source / drain region 151 can be disposed on the first lower pattern 101. The first source / drain region 151 can be in direct contact with the first nanowire 111, the second nanowire 112 and the third nanowire 113, respectively.

[0066] The upper surface of the first source / drain region 151 can be formed on substantially the same plane as the upper surface of the third nanowire 113, which is the uppermost nanowire located on the first lower pattern 101.

[0067] The second source / drain region 152 can be disposed between the second gate structure 130 and the third pin-cut gate structure 130_1, and between the second gate structure 130 and the fourth pin-cut gate structure 130_2, respectively. The second source / drain region 152 can be disposed on the second lower pattern 102. The second source / drain region 152 can be in direct contact with the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116, respectively.

[0068] The upper surface of the second source / drain region 152 can be formed on substantially the same plane as the upper surface of the sixth nanowire 116, which is the uppermost nanowire located on the second lower pattern 102.

[0069] A first inner spacer 141 may be disposed on at least one side of the first gate electrode 121 between the first lower pattern 101 and the first nanowire 111. A first inner spacer 141 may be disposed on at least one side of the first gate electrode 121 between the first nanowire 111 and the second nanowire 112. A first inner spacer 141 may be disposed on at least one side of the first gate electrode 121 between the second nanowire 112 and the third nanowire 113.

[0070] A first inner spacer 141 may be disposed between the first source / drain region 151 and the first gate electrode 121 included in the first gate structure 120. A first inner spacer 141 may be disposed between the first source / drain region 151 and the first gate electrode 121 included in the first pin-cut gate structure 120_1. A first inner spacer 141 may be disposed between the first source / drain region 151 and the first gate electrode 121 included in the second pin-cut gate structure 120_2.

[0071] The first inner spacer 141 may have two sidewalls formed as curved surfaces in a quadrilateral shape. Therefore, each of the sidewalls of the first inner spacer 141 that contacts the first source / drain region 151 and the sidewalls of the first inner spacer 141 that contacts the first gate insulating film 122 may be formed as curved surfaces.

[0072] The second inner spacer 142 may be disposed on at least one side of the second gate electrode 131 between the second lower pattern 102 and the fourth nanowire 114. The second inner spacer 142 may be disposed on at least one side of the second gate electrode 131 between the fourth nanowire 114 and the fifth nanowire 115. The second inner spacer 142 may be disposed on at least one side of the second gate electrode 131 between the fifth nanowire 115 and the sixth nanowire 116.

[0073] The second inner spacer 142 may be disposed between the second source / drain region 152 and the second gate electrode 131 included in the second gate structure 130. The second inner spacer 142 may be disposed between the second source / drain region 152 and the second gate electrode 131 included in the third pin-cut gate structure 130_1. The second inner spacer 142 may be disposed between the second source / drain region 152 and the second gate electrode 131 included in the fourth pin-cut gate structure 130_2.

[0074] The second inner spacer 142 may have two sidewalls formed as curved surfaces in a quadrilateral shape. Therefore, each of the sidewalls of the second inner spacer 142 that contacts the second source / drain region 152 and the sidewalls of the second inner spacer 142 that contacts the second gate insulating film 132 may be formed as curved surfaces.

[0075] The first inner spacer 141 and the second inner spacer 142 may have different properties from each other. For example, at least one of the hydrogen mole fraction and the oxygen mole fraction may be different in the first inner spacer 141 and the second inner spacer 142. The term "mole fraction" as used herein refers to the molar ratio of one component to all components in a material system comprising two or more components. For example, a 10% content of the first material may indicate that the molar ratio of the first material to all components is 1 / 10.

[0076] According to an example embodiment, the oxygen mole fraction in each of the first inner spacer 141 and the second inner spacer 142 can be the same, while the hydrogen mole fraction in each of the first inner spacer 141 and the second inner spacer 142 can be different. For example, the first inner spacer 141 may include hydrogen with a first hydrogen mole fraction, and the second inner spacer 142 may include hydrogen with a second hydrogen mole fraction greater than the first hydrogen mole fraction. In this case, for example, the first hydrogen mole fraction may be 2% to 5%, and the second hydrogen mole fraction may be 5% to 10%.

[0077] According to another example embodiment, the first oxygen mole fraction included in the first inner spacer 141 and the second oxygen mole fraction included in the second inner spacer 142 may be different from each other.

[0078] According to an example embodiment, the hydrogen mole fraction in each of the first inner spacer 141 and the second inner spacer 142 can be the same, while the oxygen mole fraction in each of the first inner spacer 141 and the second inner spacer 142 can be different. For example, the first inner spacer 141 may include oxygen with a first oxygen mole fraction, and the second inner spacer 142 may include oxygen with a second oxygen mole fraction greater than the first oxygen mole fraction. In this case, for example, the first oxygen mole fraction may be 2% to 5%, and the second oxygen mole fraction may be 5% to 10%.

[0079] According to another example embodiment, the first hydrogen mole fraction included in the first inner spacer 141 and the second hydrogen mole fraction included in the second inner spacer 142 may be different from each other. Therefore, the first inner spacer 141 may include oxygen with a first oxygen mole fraction and hydrogen with a first hydrogen mole fraction, and the second inner spacer 142 may include oxygen with a second oxygen mole fraction greater than the first oxygen mole fraction and hydrogen with a second hydrogen mole fraction greater than the first hydrogen mole fraction.

[0080] The thickness of each of the first inner spacer 141 and the second inner spacer 142 disposed at the same level in the first direction X can be the same as each other. For example, the first thickness t1 of the first inner spacer 141 disposed between the first nanowire 111 and the second nanowire 112 in the first direction X can be the same as the second thickness t2 of the second inner spacer 142 disposed between the fourth nanowire 114 and the fifth nanowire 115 in the first direction X. In an example embodiment, the thickness of the first inner spacer 141 in the first direction X can be 3 nm to 5 nm, and the thickness of the second inner spacer 142 in the first direction X can be 2 nm to 4 nm.

[0081] The first hydrogen molar fraction, the first oxygen molar fraction, and the thickness in the first direction X of the first inner spacer 141 can be adjusted synergistically to adjust the threshold voltage of the NMOS transistor formed in the first region I of the substrate 100. Similarly, the second hydrogen molar fraction, the second oxygen molar fraction, and the thickness in the first direction X of the second inner spacer 142 can be adjusted synergistically to adjust the threshold voltage of the PMOS transistor formed in the second region II of the substrate 100.

[0082] The first inner spacer 141 and the second inner spacer 142 may comprise different materials from each other. For example, the first inner spacer 141 may comprise SiN, and the second inner spacer 142 may comprise SiON. According to another example embodiment, the first inner spacer 141 and the second inner spacer 142 may comprise the same material as each other. For example, each of the first inner spacer 141 and the second inner spacer 142 may comprise SiN. Furthermore, for example, each of the first inner spacer 141 and the second inner spacer 142 may comprise SiON.

[0083] The etch stop film 161 may be disposed along the outer sidewall of the first outer spacer 124, the outer sidewall of the second outer spacer 134, and the upper surface of the device isolation film 105. The etch stop film 161 may include, for example, any of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), and combinations thereof. The etch stop film 161 may include a material that has etch selectivity for the first interlayer insulating film 162, as will be described below.

[0084] The first interlayer insulating film 162 may be disposed on the etch stop film 161. The first interlayer insulating film 162 may surround the sidewalls of the first outer spacer 124 and the second outer spacer 134. The first interlayer insulating film 162 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0085] The second interlayer insulating film 170 may be disposed on the first interlayer insulating film 162. The second interlayer insulating film 170 may cover the first gate structure 120, the first pin-cut gate structure 120_1, the second pin-cut gate structure 120_2, the second gate structure 130, the third pin-cut gate structure 130_1, and the fourth pin-cut gate structure 130_2. The second interlayer insulating film 170 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0086] The first source / drain contact 181 and the second source / drain contact 182 can be disposed within the second interlayer insulating film 170 and the first interlayer insulating film 162.

[0087] The first source / drain contact 181 may extend within the first source / drain region 151 on the first lower pattern 101. The first source / drain contact 181 may extend to, for example, the same level as the second nanowire 112.

[0088] The second source / drain contact 182 may extend within the second source / drain region 152 on the second lower pattern 102. The second source / drain contact 182 may extend to, for example, the same level as the fifth nanowire 115.

[0089] A first silicide film 191 may be disposed between a first source / drain contact 181 and a first source / drain region 151. A second silicide film 192 may be disposed between a second source / drain contact 182 and a second source / drain region 152.

[0090] The semiconductor device according to the example embodiment can enhance the reliability of the semiconductor device by adjusting the properties of the first inner spacer 141 disposed on the NMOS region and the properties of the second inner spacer 142 disposed on the PMOS region and effectively forming a threshold voltage offset between the threshold voltage of the NMOS transistor and the threshold voltage of the PMOS transistor.

[0091] In the following text, reference will be made to Figure 5 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with... Figure 4 The differences in semiconductor devices are shown in the figure. Figure 5 According to another example embodiment Figure 2 Enlarged views of regions R1 and R2.

[0092] Reference Figure 5 In a semiconductor device according to another example embodiment, the first thickness t1 of the first inner spacer 141 disposed on the first lower pattern 101 in the first direction X may be greater than the third thickness t3 of the second inner spacer 242 disposed on the second lower pattern 102 in the first direction X.

[0093] In the following text, reference will be made to Figure 6 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with... Figure 4 The differences in semiconductor devices are shown in the figure. Figure 6 According to another example embodiment Figure 2 Enlarged views of regions R1 and R2.

[0094] Reference Figure 6In a semiconductor device according to another example embodiment, a first inner spacer 341 disposed on a first lower pattern 101 may be formed to protrude toward a first gate electrode 121. Furthermore, a second inner spacer 342 disposed on a second lower pattern 102 may be formed to protrude toward a second gate electrode 131. Here, the protrusion formation indicates that the sidewalls generally have a curved surface shape.

[0095] In the following text, reference will be made to Figure 7 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with... Figure 4 The differences in semiconductor devices are shown in the figure. Figure 7 According to another example embodiment Figure 2 Enlarged views of regions R1 and R2.

[0096] Reference Figure 7 In a semiconductor device according to another example embodiment, each of the inner spacer 441 disposed on the first lower pattern 101 and the inner spacer 442 disposed on the second lower pattern 102 can be formed as a multilayer film.

[0097] For example, the inner spacer 441 may include a first inner spacer 441_1 that contacts the first gate insulating film 122 and a third inner spacer 441_2 disposed between the first inner spacer 441_1 and the first source / drain region 151.

[0098] The upper surface of the first inner spacer 441_1 can contact the second nanowire 112, and the lower surface of the first inner spacer 441_1 can contact the first nanowire 111. The third inner spacer 441_2 can be formed to protrude toward the first inner spacer 441_1.

[0099] For example, the inner spacer 442 may include a second inner spacer 442_1 that contacts the second gate insulating film 132 and a fourth inner spacer 442_2 disposed between the second inner spacer 442_1 and the second source / drain region 152.

[0100] The upper surface of the second inner spacer 442_1 can contact the fifth nanowire 115, and the lower surface of the second inner spacer 442_1 can contact the fourth nanowire 114. The fourth inner spacer 442_2 can be formed to protrude toward the second inner spacer 442_1.

[0101] The first inner spacer 441_1 and the second inner spacer 442_1 may have different properties from each other. The third inner spacer 441_2 and the fourth inner spacer 442_2 may have the same properties.

[0102] The first inner spacer 441_1 and the second inner spacer 442_1 may comprise a material other than the materials of the third inner spacer 441_2 and the fourth inner spacer 442_2. For example, each of the first inner spacer 441_1 and the second inner spacer 442_1 may comprise SiON, and each of the third inner spacer 441_2 and the fourth inner spacer 442_2 may comprise SiN.

[0103] In the following text, reference will be made to Figure 8 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with... Figure 4 The differences in semiconductor devices are shown in the figure. Figure 8 According to another example embodiment Figure 2 Enlarged views of regions R1 and R2.

[0104] Reference Figure 8 In a semiconductor device according to another example embodiment, each of the inner spacer 541 disposed on the first lower pattern 101 and the inner spacer 542 disposed on the second lower pattern 102 can be formed as a multilayer film.

[0105] For example, the inner spacer 541 may include a first inner spacer 541_1 that contacts the first gate insulating film 122 and a third inner spacer 541_2 disposed between the first inner spacer 541_1 and the first source / drain region 151.

[0106] The upper surface of the first inner spacer 541_1 can contact the second nanowire 112, and the lower surface of the first inner spacer 541_1 can contact the first nanowire 111. The upper surface of the third inner spacer 541_2 can contact the second nanowire 112, and the lower surface of the third inner spacer 541_2 can contact the first nanowire 111.

[0107] For example, the inner spacer 542 may include a second inner spacer 542_1 that contacts the second gate insulating film 132 and a fourth inner spacer 542_2 disposed between the second inner spacer 542_1 and the second source / drain region 152.

[0108] The upper surface of the second inner spacer 542_1 can contact the fifth nanowire 115, and the lower surface of the second inner spacer 542_1 can contact the fourth nanowire 114. The upper surface of the fourth inner spacer 542_2 can contact the fifth nanowire 115, and the lower surface of the fourth inner spacer 542_2 can contact the fourth nanowire 114.

[0109] The first inner spacer 541_1 and the second inner spacer 542_1 may have different properties from each other. The third inner spacer 541_2 and the fourth inner spacer 542_2 may have the same properties. For example, the first inner spacer 541_1 and the second inner spacer 542_1 may include materials different from those of the third inner spacer 541_2 and the fourth inner spacer 542_2.

[0110] In the following text, reference will be made to Figure 9 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with... Figure 4 The differences in semiconductor devices are shown in the figure. Figure 9 According to another example embodiment Figure 2 Enlarged views of regions R1 and R2.

[0111] Reference Figure 9 In a semiconductor device according to another example embodiment, each of the inner spacer 641 disposed on the first lower pattern 101 and the inner spacer 642 disposed on the second lower pattern 102 can be formed as a multilayer film.

[0112] For example, the inner spacer 641 may include a first inner spacer 641_1 that contacts the first gate insulating film 122 and a third inner spacer 641_2 disposed between the first inner spacer 641_1 and the first source / drain region 151.

[0113] The first inner spacer 641_1 can be conformally disposed along the upper surface of the first gate insulating film 122, the first nanowire 111, and the lower surface of the second nanowire 112.

[0114] For example, the inner spacer 642 may include a second inner spacer 642_1 that contacts the second gate insulating film 132 and a fourth inner spacer 642_2 disposed between the second inner spacer 642_1 and the second source / drain region 152.

[0115] The second inner spacer 642_1 can be conformally disposed along the upper surface of the second gate insulating film 132, the fourth nanowire 114, and the lower surface of the fifth nanowire 115.

[0116] The first inner spacer 641_1 and the second inner spacer 642_1 may have different properties from each other. The third inner spacer 641_2 and the fourth inner spacer 642_2 may have the same properties. For example, the first inner spacer 641_1 and the second inner spacer 642_1 may be made of a different material than the third inner spacer 641_2 and the fourth inner spacer 642_2.

[0117] In the following text, reference will be made to Figure 10 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with...Figure 4 The differences in semiconductor devices are shown in the figure. Figure 10 According to another example embodiment Figure 2 Enlarged views of regions R1 and R2.

[0118] Reference Figure 10 In a semiconductor device according to another example embodiment, each of the inner spacer 741 disposed on the first lower pattern 101 and the inner spacer 742 disposed on the second lower pattern 102 can be formed as a multilayer film.

[0119] For example, the inner spacer 741 may include a first inner spacer 741_1 that contacts the first gate insulating film 122 and a third inner spacer 741_2 disposed between the first inner spacer 741_1 and the first source / drain region 151. Each of the first inner spacer 741_1 and the third inner spacer 741_2 may be formed to protrude toward the first gate electrode 121.

[0120] For example, the inner spacer 742 may include a second inner spacer 742_1 that contacts the second gate insulating film 132 and a fourth inner spacer 742_2 disposed between the second inner spacer 742_1 and the second source / drain region 152. Each of the second inner spacer 742_1 and the fourth inner spacer 742_2 may be formed to protrude toward the second gate electrode 131.

[0121] The first inner spacer 741_1 and the second inner spacer 742_1 may have different properties from each other. The third inner spacer 741_2 and the fourth inner spacer 742_2 may have the same properties. For example, the first inner spacer 741_1 and the second inner spacer 742_1 may be made of a different material than the third inner spacer 741_2 and the fourth inner spacer 742_2.

[0122] In the following text, reference will be made to Figure 11 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with... Figure 2 The differences in semiconductor devices are shown in the figure. Figure 11 This is a cross-sectional view of a semiconductor device according to another example embodiment.

[0123] Reference Figure 11 In a semiconductor device according to another example embodiment, substrate 800 may be a silicon-on-insulator (SOI) substrate. Therefore, substrate 800 may include a silicon layer 800_1 and an insulating layer 800_2 disposed on the silicon layer 800_1. Each of the first lower pattern 101 and the second lower pattern 102 may be disposed on the insulating layer 800_2. Insulating layer 800_2 may include, for example, silicon oxide (SiO2). Silicon layer 800_1 may be, for example, a silicon substrate.

[0124] In the following text, reference will be made to Figure 12 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with... Figure 2 The differences in semiconductor devices are shown in the figure. Figure 12 This is a cross-sectional view of a semiconductor device according to another example embodiment.

[0125] Reference Figure 12 In a semiconductor device according to another example embodiment, the upper surface of the first source / drain region 951 may be formed higher than the upper surface of the third nanowire 113, which is the uppermost nanowire located on the first lower pattern 101. Furthermore, the upper surface of the second source / drain region 952 may be formed higher than the upper surface of the sixth nanowire 116, which is the uppermost nanowire located on the second lower pattern 102.

[0126] The upper surface of the first silicide film 991 can be formed to be higher than the upper surface of the third nanowire 113. The upper surface of the second silicide film 992 can be formed to be higher than the upper surface of the sixth nanowire 116.

[0127] In the following text, reference will be made to Figure 13 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with... Figure 2 The differences in semiconductor devices are shown in the figure. Figure 13 This is a cross-sectional view of a semiconductor device according to another example embodiment.

[0128] Reference Figure 13 In a semiconductor device according to another example embodiment, the first source / drain contact 1081 may not extend within the first source / drain region 151. Therefore, the first source / drain contact 1081 may be disposed on the upper surface of the first source / drain region 151. Furthermore, the second source / drain contact 1082 may not extend within the second source / drain region 152. Therefore, the second source / drain contact 1082 may be disposed on the upper surface of the second source / drain region 152.

[0129] A first silicide film 1091 may be disposed between a first source / drain contact 1081 and a first source / drain region 151. A second silicide film 1092 may be disposed between a second source / drain contact 1082 and a second source / drain region 152.

[0130] In the following text, reference will be made to Figure 14 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with... Figure 2 The differences in semiconductor devices are shown in the figure. Figure 14 This is a cross-sectional view of a semiconductor device according to another example embodiment.

[0131] Reference Figure 14In a semiconductor device according to another example embodiment, the sidewalls of the first source / drain region 1151 in contact with the first nanowire 111, the second nanowire 112 and the third nanowire 113 may extend in the third direction Z to have a profile with a certain slope.

[0132] The length of each of the first nanowires 111, second nanowire 112, and third nanowire 113 disposed between the first source / drain region 1151 in the first direction X can be the same as that of each other.

[0133] In the following text, reference will be made to Figure 15 A semiconductor device according to another example embodiment is described. Highlights will be used in conjunction with... Figure 2 The differences in semiconductor devices are shown in the figure. Figure 15 This is a cross-sectional view of a semiconductor device according to another example embodiment.

[0134] Reference Figure 15 In a semiconductor device according to another example embodiment, the sidewalls of the first source / drain region 1251, which contacts the first nanowire 111, the second nanowire 112, and the third nanowire 113, may extend in the third direction Z to have a profile with a certain slope. Furthermore, the sidewalls of the second source / drain region 1252, which contacts the fourth nanowire 114, the fifth nanowire 115, and the sixth nanowire 116, may extend in the third direction Z to have a profile with a certain slope.

[0135] The length of each of the first nanowires 111, 112, and 113 disposed between the first source / drain region 1251 in the first direction X can be the same as that of each other. Furthermore, the length of each of the fourth nanowires 114, 115, and 116 disposed between the second source / drain region 1252 in the first direction X can be the same as that of each other.

[0136] As described above, the embodiments involve multi-bridge channel field-effect transistors (MBCFETs). TM Semiconductor devices.

[0137] The embodiments can provide semiconductor devices with enhanced reliability by adjusting the properties of the inner spacers disposed in the NMOS region and the properties of the inner spacers disposed in the PMOS region, and effectively forming a threshold voltage offset between the threshold voltage of the NMOS transistor and the threshold voltage of the PMOS transistor.

[0138] Example embodiments have been disclosed herein, and while specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some cases, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, as of the time of filing of this application, unless otherwise specifically stated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: The substrate has a first region and a second region; The first nanowire and the second nanowire are sequentially disposed on the substrate in the first region and extend in the first direction, respectively. The third and fourth nanowires are sequentially disposed on the substrate in the second region and extend in the first direction, respectively. A first inner spacer is located between the first nanowire and the second nanowire and includes hydrogen with a first hydrogen mole fraction; as well as The second inner spacer is located between the third and fourth nanowires and includes a second hydrogen mole fraction that is larger than the first hydrogen mole fraction. The first inner spacer and the second inner spacer are made of different materials.

2. The semiconductor device according to claim 1, wherein: The first inner spacer includes oxygen with a first oxygen mole fraction, and The second inner spacer includes a second oxygen mole fraction that is greater than the first oxygen mole fraction.

3. The semiconductor device according to claim 1, wherein: The first inner spacer and the second inner spacer are positioned at the same horizontal level, and The first thickness of the first inner spacer in the first direction is greater than the second thickness of the second spacer in the first direction.

4. The semiconductor device according to claim 3, wherein: The first thickness of the first inner spacer is 3nm to 5nm, and The second thickness of the second inner spacer is 2 nm to 4 nm.

5. The semiconductor device according to claim 1, wherein, The first inner spacer comprises SiN and the second inner spacer comprises SiON.

6. The semiconductor device according to claim 1, further comprising: The third inner spacer is located on the first inner spacer between the first nanowire and the second nanowire, and The fourth inner spacer is located on the second inner spacer between the third and fourth nanowires.

7. The semiconductor device according to claim 6, wherein, The first and second inner spacers are made of materials different from those of the third and fourth inner spacers.

8. The semiconductor device according to claim 7, wherein: Each of the third and fourth inner spacers includes SiN.

9. The semiconductor device according to claim 1, further comprising: A first gate electrode, surrounding a first nanowire and a second nanowire and extending in a second direction different from the first direction, and The second gate electrode surrounds the third and fourth nanowires and extends in the second direction.

10. The semiconductor device according to claim 1, wherein, The threshold voltage of the first region is different from the threshold voltage of the second region.

11. A semiconductor device, the semiconductor device comprising: The substrate has a first region and a second region; The first nanowire and the second nanowire are sequentially disposed on the substrate in the first region and extend in the first direction, respectively. The third and fourth nanowires are sequentially disposed on the substrate in the second region and extend in the first direction, respectively. A first gate electrode extends around a first nanowire and a second nanowire in a second direction different from the first direction; The second gate electrode surrounds the third and fourth nanowires and extends in the second direction; The first inner spacer is located on at least one side of the first gate electrode between the first nanowire and the second nanowire, and includes oxygen with a first molar fraction of oxygen. as well as The second inner spacer is located on at least one side of the second gate electrode between the third and fourth nanowires, and includes a second oxygen mole fraction greater than the first oxygen mole fraction. The first inner spacer and the second inner spacer are made of different materials.

12. The semiconductor device according to claim 11, wherein: The first inner spacer comprises hydrogen of a first hydrogen mole fraction, and The second inner spacer includes a second hydrogen mole fraction that is greater than the first hydrogen mole fraction.

13. The semiconductor device according to claim 11, wherein: The first inner spacer and the second inner spacer are positioned at the same horizontal level, and The first thickness of the first inner spacer in the first direction is greater than the second thickness of the second inner spacer in the first direction.

14. The semiconductor device of claim 11, further comprising: The third inner spacer is located on the first inner spacer between the first nanowire and the second nanowire, and The fourth inner spacer is located on the second inner spacer between the third and fourth nanowires.

15. The semiconductor device according to claim 14, wherein, The third and fourth inner spacers are made of the same material.

16. A semiconductor device, the semiconductor device comprising: The substrate has a first region and a second region; A first nanowire, a second nanowire, and a third nanowire are sequentially disposed on a substrate in a first region and each extends in a first direction. The fourth, fifth, and sixth nanowires are sequentially disposed on the substrate in the second region and extend in the first direction, respectively. The first gate electrode extends around the first nanowire, the second nanowire, and the third nanowire and in a second direction different from the first direction; The second gate electrode surrounds the fourth nanowire, the fifth nanowire, and the sixth nanowire and extends in the second direction; The first source / drain region is located on at least one side of the first nanowire, the second nanowire, and the third nanowire; The second source / drain region is located on at least one side of the fourth, fifth, and sixth nanowires; The first inner spacer is located on at least one side of the first gate electrode between the first nanowire and the second nanowire, and includes oxygen in a first molar fraction of oxygen and hydrogen in a first molar fraction of hydrogen. The second inner spacer is located on at least one side of the second gate electrode between the fourth nanowire and the fifth nanowire, and includes oxygen with a second oxygen mole fraction greater than the first oxygen mole fraction and hydrogen with a second hydrogen mole fraction greater than the first hydrogen mole fraction. The first source / drain contact is connected to the first source / drain region; as well as The second source / drain contact is connected to the second source / drain region. The first inner spacer and the second inner spacer are made of different materials.

17. The semiconductor device of claim 16, further comprising: The third inner spacer is located on the first inner spacer between the first nanowire and the second nanowire, and The fourth inner spacer is located on the second inner spacer between the fourth nanowire and the fifth nanowire.

18. The semiconductor device according to claim 16, wherein, The first inner spacer comprises SiN, and the second inner spacer comprises SiON.

19. The semiconductor device according to claim 17, wherein, The first inner spacer comprises SiN and the second inner spacer comprises SiON, and Each of the third and fourth inner spacers includes SiN.

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