Semiconductor device

Abstract

A semiconductor device includes a substrate, a channel on or in the substrate, a source / drain pair on opposite ends of the channel, and a gate structure on the channel between the source / drain pair, wherein the gate structure includes, in order, an interface layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer on the channel.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0092002, filed on July 29, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates to semiconductor devices and methods for manufacturing the same. Specifically, this invention relates to semiconductor devices comprising a ferroelectric layer and methods for manufacturing the same semiconductor device. Background Technology

[0004] Theoretically, the minimum subthreshold swing of a field-effect transistor is considered to be 60 mV / dec. However, to overcome this theoretical limitation, a ferroelectric field-effect transistor (FeFET) has been considered, which includes a ferroelectric layer that provides negative capacitance when used as a gate insulating layer. For a ferroelectric material to exhibit ferroelectric properties, it must possess a phase with a specific crystal structure. Therefore, after forming the ferroelectric layer, an annealing process can be performed to form the desired phase with a specific crystal structure within it. Summary of the Invention

[0005] This invention provides a semiconductor device having a thin interface layer and a method for manufacturing the semiconductor device. This invention also provides a semiconductor device comprising a ferroelectric layer having improved ferroelectric properties and a method for manufacturing the semiconductor device.

[0006] According to one aspect of the present invention, a semiconductor device is provided, comprising: a substrate; a channel located in or on the substrate; and a source / drain pair located at opposite ends of the channel. A gate structure is also disposed on the channel and located between the source / drain pairs. The gate structure includes an interface layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that can be sequentially stacked on the channel.

[0007] According to another embodiment of the inventive concept, a semiconductor device is provided that includes a substrate having a first region and a second region. A first transistor including a first gate structure is disposed on the first region of the substrate, and a second transistor including a second gate structure is disposed on the second region of the substrate. According to some embodiments of the invention, the first gate structure includes a first interface layer, a first ferroelectric layer, a first stabilizing layer, and a first threshold voltage control layer that can be sequentially stacked on the first region of the substrate. Further, the second gate structure can include a second interface layer, a second ferroelectric layer, and a second threshold voltage control layer directly on the second ferroelectric layer, and these layers can be sequentially stacked on the second region of the substrate.

[0008] According to another embodiment of the invention, a semiconductor device is provided that includes a substrate having a first region and a second region therein. A first gate structure is disposed on the first region of the substrate, and a second gate structure is disposed on the second region of the substrate. The first gate structure includes a first interface layer, a first ferroelectric layer, a first stabilizing layer, a first oxygen diffusion barrier layer, and a first threshold voltage control layer that are sequentially stacked on the first region of the substrate. The second gate structure includes a second interface layer, a second ferroelectric layer, a second stabilizing layer, and a second threshold voltage control layer directly on the second stabilizing layer. These layers can be sequentially stacked on the second region of the substrate.

[0009] According to yet another embodiment of the invention, a method of fabricating a semiconductor device includes sequentially forming an interface layer and a ferroelectric layer on a substrate; forming a stabilizing layer on the ferroelectric layer; forming an oxygen diffusion barrier layer on the stabilizing layer; forming a silicon layer on the oxygen diffusion barrier layer; and then annealing the ferroelectric layer.

[0010] According to another embodiment of the invention, a method of fabricating a semiconductor device includes sequentially forming an interface layer, a ferroelectric layer, a stabilizing layer, and a sacrificial layer on each of a first region and a second region of a substrate. A step of annealing the ferroelectric layer is also performed. Additional steps include removing the sacrificial layer; and removing a portion of the stabilizing layer on the second region of the substrate. The following steps are also performed: forming a first threshold voltage control layer on the stabilizing layer (on the first region of the substrate); and forming a second threshold voltage control layer on a portion of the ferroelectric layer (on the second region of the substrate).

[0011] According to another embodiment of the present inventive concept, a method of fabricating a semiconductor device is provided that includes forming a channel in or on a substrate; sequentially forming an interface layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a sacrificial layer on the channel prior to annealing the ferroelectric layer. The sacrificial layer is then removed. A threshold voltage control layer is also formed on the oxygen diffusion barrier layer. BRIEF DESCRIPTION OF DRAWINGS

[0012] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and in which:

[0013] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment;

[0014] Figure 2A is a perspective view of a semiconductor device according to an embodiment;

[0015] Figure 2B and Figure 2C is a cross-sectional view of a semiconductor device according to an embodiment taken along lines BB' and CC'; Figure 2A

[0016] Figure 3 is a cross-sectional view of a semiconductor device according to an embodiment;

[0017] Figures 4A-4E is a cross-sectional view of a semiconductor device according to one or more embodiments;

[0018] Figure 5 is a flowchart illustrating a method of fabricating a semiconductor device according to an embodiment;

[0019] Figures 6A-6E is a diagram illustrating a method of fabricating a semiconductor device according to an embodiment;

[0020] Figures 7A-7H is a diagram illustrating a method of fabricating a semiconductor device according to an embodiment;

[0021] Figure 8A and Figure 8B is a diagram illustrating a method of fabricating a semiconductor device according to an embodiment;

[0022] Figures 9A-9G is a diagram illustrating a method of fabricating a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0023] Figure 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment. Referring to FIG. 1, Figure 1 ​semiconductor material, such as a Group IV semiconductor material, a Group III-V semiconductor material, or a Group II-VI semiconductor material. The Group IV semiconductor material can include, for example, silicon (Si), germanium (Ge), or Si-Ge. The Group III-V semiconductor material can include, for example, gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), or indium gallium arsenide (InGaAs). The Group II-VI semiconductor material can include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS). The substrate 10 can be formed from a bulk wafer material (e.g., a boule) or as an epitaxial layer.

[0024] The transistor TR can include a channel 11, a source / drain pair 12, and a gate structure 20. The channel 11 can be disposed in the substrate 10 or on the substrate 10. In some embodiments, the channel 11 can be formed from the substrate 10, i.e., from a portion of the substrate 10. In another embodiment, the channel 11 can be formed on the substrate 10 and can not be a portion of the substrate 10. The channel 11 can include a semiconductor material that is the same as or different from the material of the substrate 10. When the transistor TR is an n-type transistor, the channel 11 can include a semiconductor material doped with p-type impurities. When the transistor TR is a p-type transistor, the channel 11 can include a semiconductor material doped with n-type impurities.

[0025] The source / drain pair 12 can be located at opposite ends of the channel 11. The source / drain pair 12 can be formed in the substrate 10 or on the substrate 10. In some embodiments, the source / drain pair 12 can be formed from the substrate 10, i.e., from a portion of the substrate 10. In another embodiment, the source / drain pair 12 can be formed on the substrate 10 and can not be a portion of the substrate 10. The source / drain pair 12 can include a semiconductor material that is the same as or different from the material of the substrate 10. When the transistor TR is an n-type transistor, the source / drain pair 12 can include a semiconductor material doped with n-type impurities. When the transistor TR is a p-type transistor, the source / drain pair 12 can include a semiconductor material doped with p-type impurities.

[0026] The gate structure 20 can include an interface layer 21, a ferroelectric layer 22, and a stabilization layer 23 sequentially stacked on the channel 11. In some embodiments, the interface layer 21 can be located directly on the channel 11 without any additional layers. The interface layer 21 can include, for example, silicon oxide, silicon nitride, or a combination thereof (such as silicon oxynitride), but is not limited thereto. The interface layer 21 can have a thickness of about to about When the thickness of the interface layer 21 is greater than When the thickness of the interface layer 21 is greater than or equal to about 1 nm, the equivalent oxide thickness (EOT) increases, thereby degrading the characteristics of the semiconductor device 100. In contrast, when the thickness of the interface layer 21 is less than about 1 nm, the leakage current increases.

[0027] The ferroelectric layer 22 and the interface layer 21 can function as a gate insulating layer of the gate structure 20 in the transistor TR. In some embodiments, the ferroelectric layer 22 can be directly on the interface layer 21 without any intervening layer therebetween. The ferroelectric layer 22 can exhibit ferroelectric properties. The ferroelectric layer 22 includes a ferroelectric material. The ferroelectric material can exhibit ferroelectricity only in a phase having a specific crystal structure, and in this specification, the phase is referred to as a ferroelectric phase. The ferroelectric layer 22 can include Hf02, doped Hf02(such as Si-doped Hf02or Al-doped Hf02), Zr02, doped Zr02(such as Li-doped Zr02or Mg-doped Zr02), Hf x Zr 1-x 02(0 < x < 1), ATi03(A is Ba, Sr, Ca, or Pb), or a combination thereof, but is not limited thereto.

[0028] In some embodiments, the stabilization layer 23 can be directly on the ferroelectric layer 22 without any intervening layer therebetween. The stabilization layer 23 can stabilize the ferroelectric phase in the ferroelectric layer 22. For example, the stabilization layer 23 can help the ferroelectric phase to form in the ferroelectric layer 22 at the same time as annealing the ferroelectric layer 22. Further, for example, the stabilization layer 23 prevents the ferroelectric phase in the ferroelectric layer 22 from disappearing during a post-annealing process (such as a high-temperature process), thereby preventing the ferroelectric layer 22 from losing ferroelectricity. In this specification, preventing a certain effect can include at least partially reducing the certain effect, as well as completely eliminating the effect. In some embodiments, the stabilization layer 23 can stabilize the ferroelectric phase by affecting the internal stress of the ferroelectric layer 22. For example, the stabilization layer 23 can stabilize the ferroelectric phase in the ferroelectric layer 22 by putting the ferroelectric layer 22 under a large tensile stress or a large compressive stress.

[0029] In some embodiments, the stabilization layer 23 can include a material having a relatively large coefficient of thermal expansion. The stabilization layer 23 can include, for example, TiN, MoN, Mo, AI2O3, AlN, W, WN, WCN, La, LaO, LaN, TiAlN, TiON, or a combination thereof, but is not limited thereto. The thickness of the stabilization layer 23 can be about to about For example, about to about However, the application is not limited thereto. When the stabilization layer 23 includes a material having a large work function such as MoN and the transistor TR is a p-type transistor, the threshold voltage of the transistor TR can be easily controlled. In contrast, when the stabilization layer 23 includes a material having a relatively small work function and the transistor TR is an n-type transistor, the threshold voltage of the transistor TR can be easily controlled.

[0030] In some embodiments, the gate structure 20 can further include an oxygen diffusion barrier layer 24. The oxygen diffusion barrier layer 24 can be located on the stabilization layer 23. The oxygen diffusion barrier layer 24 can prevent oxygen from diffusing into the interface layer 21 to prevent an increase in the thickness of the interface layer 21 when annealing the ferroelectric layer 22. The oxygen diffusion barrier layer 24 can include, for example, TiN, AlN, TaN, TiSiN, TiON, TiAlN, WCN, WN, W, or a combination thereof, but is not limited thereto. The thickness of the oxygen diffusion barrier layer 24 can be about 1 A to about 100 A, but is not limited thereto. to about 100 A. For example, about 1 A to about 10 A. to about 100 A. However, the application is not limited thereto.

[0031] In some embodiments, the gate structure 20 can further include a threshold voltage control layer 25. The threshold voltage control layer 25 can be located on the oxygen diffusion barrier layer 24. The threshold voltage control layer 25 can control the threshold voltage of the transistor TR. In some embodiments, the threshold voltage control layer 25 can include a material different from that of the stabilization layer 23. When the transistor TR is a p-type transistor, the threshold voltage control layer 25 can include a material having a relatively large work function. For example, the threshold voltage control layer 25 can include Ti, W, Mo, Al, Si, a compound of at least one of these elements and at least another element, or a combination thereof, but is not limited thereto. When the transistor TR is an n-type transistor, the threshold voltage control layer 25 can include a material having a relatively small work function. For example, the threshold voltage control layer 25 can include Ti, Al, Ta, V, Nb, Si, a compound of these elements, or a combination thereof, but is not limited thereto. In some embodiments, the threshold voltage control layer 25 can include TiN. The threshold voltage control layer 25 can have a thickness of about 1 A to about 100 A, but is not limited thereto. to about 100 A. In some embodiments, the threshold voltage of the transistor TR can be affected by the stabilization layer 23 and the oxygen diffusion barrier layer 24 as well as the threshold voltage control layer 25. In some embodiments, the work function of the material included in the stabilization layer 23 can be greater than the work function of the material included in the threshold voltage control layer 25.

[0032] In some embodiments, the threshold voltage control layer 25 can include a lower threshold voltage control layer 25a located on the oxygen diffusion barrier layer 24 and an upper threshold voltage control layer 25b located on the lower threshold voltage control layer 25a. In some embodiments, a work function of a material included in the lower threshold voltage control layer 25a can be greater than a work function of a material included in the upper threshold voltage control layer 25b. In some embodiments, the lower threshold voltage control layer 25a includes TiN and the upper threshold voltage control layer 25b includes TiAlC, but is not limited thereto. In some embodiments, a work function of a material included in the stabilization layer 23 can be greater than a work function of a material included in the upper threshold voltage control layer 25b. In some embodiments, a work function of a material included in the stabilization layer 23 can be greater than a work function of a material included in the lower threshold voltage control layer 25a.

[0033] In some embodiments, the gate structure 20 can further include an upper barrier layer 26. The upper barrier layer 26 can be located on the threshold voltage control layer 25. The upper barrier layer 26 can include TiN, TaN, or a combination thereof, but is not limited thereto. In some embodiments, the gate structure 20 can further include a gate fill layer 27. The gate fill layer 27 can include, for example, W, but is not limited thereto.

[0034] In some embodiments, the semiconductor device 100 can further include a device isolation layer 13, such as a shallow trench isolation (STI) layer. The device isolation layer 13 can be formed in the substrate 10 or on the substrate 10. The device isolation layer 13 can include, for example, silicon oxide, silicon nitride, or a combination thereof, but is not limited thereto. The device isolation layer 13 can include a single layer or a multi-layer structure.

[0035] In some embodiments, the semiconductor device 100 can further include a gate spacer 30 located on opposite sidewalls of the gate structure 20. The gate spacer 30 can include, for example, silicon oxide, silicon nitride, or a combination thereof, but is not limited thereto.

[0036] In some embodiments, the semiconductor device 100 can further include an interlayer insulating layer 40. The interlayer insulating layer 40 can fill a space from an upper surface of the substrate 10 to a height of an upper end of the gate structure 20. The interlayer insulating layer 40 can cover the source / drain pair 12, the device isolation layer 13, and sidewalls of the gate spacer 30.

[0037] The semiconductor device 100 according to an embodiment may include a ferroelectric layer 22 having improved ferroelectric properties by including a stabilizing layer 23. Therefore, the transistor TR of the semiconductor device 100 according to an embodiment may have a relatively small subthreshold swing. For example, the subthreshold swing of the semiconductor device 100 may be less than 60 mV / dec, which is a theoretical limit. Furthermore, the semiconductor device 100 according to an embodiment may include an oxygen diffusion barrier layer 24 to prevent the thickness of the interface layer 21 from increasing during the annealing of the ferroelectric layer 22. Therefore, according to an embodiment, the thickness of the EOT of the gate structure 20 in the transistor TR of the semiconductor device 100 can be prevented from increasing.

[0038] Figure 2A This is a perspective view of the semiconductor device 100b according to an embodiment. Figure 2B and Figure 2C It is according to the embodiment along Figure 2A The cross-sectional views of semiconductor device 100b taken by lines BB' and CC' are shown below. The following will describe... Figure 1 Semiconductor device 100 and Figures 2A-2C The differences between semiconductor devices 100b. (Refer to...) Figures 2A-2C The transistor TR can be a fin field-effect transistor (FinFET). That is, the channel 11 of the transistor TR can have a fin shape protruding from the upper surface 10U of the substrate 10. Therefore, the gate structure 20 can contact the upper surface and the opposite side surface of the channel 11.

[0039] Figure 3 This is a cross-sectional view of the semiconductor device 100c according to an embodiment. The following will describe... Figure 1 Semiconductor device 100 and Figure 3 The differences between semiconductor devices 100c. (Refer to...) Figure 3 The transistor TR can be a gate-all-around field-effect transistor (GAAFET) or a multi-bridge channel field-effect transistor (MBCFET). The channel 11 can include multiple portions 11a to 11d separated from each other in the vertical direction. The multiple portions 11b to 11d of the channel 11 can each have a nanowire shape or a nanosheet shape. The gate structure 20 can surround the upper surface of the lowermost portion 11a of the channel 11 and the upper surface, lower surface, and opposite side surface (not shown) of each of the other portions 11b to 11d of the channel 11. The interface layer 21, the ferroelectric layer 22, the stabilization layer 23, the oxygen diffusion barrier layer 24, the threshold voltage control layer 25, the upper barrier layer 26, and the gate fill layer 27 can be sequentially stacked on the upper portion 11a of the channel 11, and stacked on the upper surface, lower surface, and opposite side surface (not shown) of each of the other portions 11b to 11d of the channel 11.

[0040] One of the source / drain pair 12 can be in common contact with end portions 11a to 11d of the channel 11. The other of the source / drain pair 12 can be in common contact with opposite end portions of the channel 11.

[0041] The first gate spacer 30a can be located on an opposite upper sidewall of the gate structure 20 higher than the uppermost portion 11d of the channel 11. The second gate spacer 30b can be located on an opposite lower sidewall of the gate structure 20 lower than the uppermost portion 11d of the channel 11. Each of the first gate spacer 30a and the second gate spacer 30b can include, for example, silicon oxide, silicon nitride, or a combination thereof, but is not limited thereto.

[0042] Figures 4A-4E is a cross-sectional view of a semiconductor device 200 and 200b to 200e according to one or more embodiments. Referring to Figure 4A , the semiconductor device 200 can include a substrate 10, a first transistor TR1, and a second transistor TR2. The substrate 10 can include a first region R1 and a second region R2. The first transistor TR1 can be located on the first region R1 of the substrate 10, and the second transistor TR2 can be located on the second region R2 of the substrate 10. Each of the first transistor TR1 and the second transistor TR2 can be one of the transistors TR shown in FIG. 1. In some embodiments, the first transistor TR1 and the second transistor TR2 can be a p-type transistor and an n-type transistor, respectively. Figures 1-3

[0043] The first transistor TR1 can include a first channel 111, a first source / drain pair 112, and a first gate structure 120. The second transistor TR2 can include a second channel 211, a second source / drain pair 212, and a second gate structure 220. The first channel 111 and the second channel 211 can be the same as the channel 11 described above with reference to FIG. 1. The first channel 111 and the second channel 211 can include the same or different semiconductor materials from each other. Figures 1-3 The first source / drain pair 112 and the second source / drain pair 212 can be the same as the source / drain pair 12 described above with reference to FIG. 1. In some embodiments, the first source / drain pair 112 and the second source / drain pair 212 can include different semiconductor materials from each other. For example, the first source / drain pair 112 can include Si-Ge, and the second source / drain pair 212 can include Si. Figures 1-3

[0044] ​​The first gate structure 120 can include a first interface layer 121, a first ferroelectric layer 122, a first stabilization layer 123, a first oxygen diffusion barrier layer 124, a first threshold voltage control layer 125, a first upper barrier layer 126, and a first gate fill layer 127, which are sequentially stacked on the first channel 111. In some embodiments, at least one of the first threshold voltage control layer 125, the first upper barrier layer 126, and the first gate fill layer 127 can be omitted.

[0045] The second gate structure 220 can include a second interface layer 221, a second ferroelectric layer 222, a second stabilization layer 223, a second oxygen diffusion barrier layer 224, a second threshold voltage control layer 225, a second upper barrier layer 226, and a second gate fill layer 227, which are sequentially stacked on the second channel 211. In some embodiments, at least one of the second threshold voltage control layer 225, the second upper barrier layer 226, and the second gate fill layer 227 can be omitted.

[0046] Each of the first interface layer 121 and the second interface layer 221 can be the same as the interface layer 21 described above with reference to Figures 1-3 In some embodiments of the present application, the first interface layer 121 and the second interface layer 221 can include the same material as each other. In some other embodiments, the first interface layer 121 and the second interface layer 221 can have substantially the same thickness as each other. In the present specification, that the first thickness and the second thickness are substantially the same as each other means that the difference between the first thickness and the second thickness is equal to or less than 10% of the first thickness or the second thickness.

[0047] Each of the first ferroelectric layer 122 and the second ferroelectric layer 222 can be the same as the ferroelectric layer 22 described above with reference to Figures 1-3 In some embodiments, the first ferroelectric layer 122 and the second ferroelectric layer 222 can include the same material as each other. In other embodiments, the first ferroelectric layer 122 and the second ferroelectric layer 222 can have substantially the same thickness as each other.

[0048] Each of the first stabilization layer 123 and the second stabilization layer 223 can be the same as the stabilization layer 23 described above with reference to Figures 1-3 In some embodiments, the first stabilization layer 123 and the second stabilization layer 223 can include the same material as each other. The above-described material can be MoN, but is not limited thereto. In some embodiments, the first stabilization layer 123 and the second stabilization layer 223 can have substantially the same thickness as each other.

[0049] Each of the first oxygen diffusion barrier layer 124 and the second oxygen diffusion barrier layer 224 can be the same as the oxygen diffusion barrier layer 24 described above with reference to Figures 1-3The described oxygen diffusion barrier layer 24 is the same. In some embodiments, the first and second oxygen diffusion barrier layers 124 and 224 can include the same material as each other. In some embodiments, the first and second oxygen diffusion barrier layers 124 and 224 can have substantially the same thickness as each other.

[0050] Each of the first and second threshold voltage control layers 125 and 225 can be the same as the described threshold voltage control layer 25 above. Figures 1-3 The described threshold voltage control layer 25 is the same. In some embodiments, the first and second threshold voltage control layers 125 and 225 can include different materials as each other.

[0051] In some further embodiments, the first threshold voltage control layer 125 can include a first lower threshold voltage control layer 125a and a first upper threshold voltage control layer 125b, and the second threshold voltage control layer 225 can include a second lower threshold voltage control layer 225a and a second upper threshold voltage control layer 225b. In some embodiments, the first and second lower threshold voltage control layers 125a and 225a can include the same material as each other, but have different thicknesses as each other. The above-mentioned material can be, for example, TiN, but is not limited thereto. For example, the thickness of the first lower threshold voltage control layer 125a can be greater than the thickness of the second lower threshold voltage control layer 225a. In some other embodiments, the first and second upper threshold voltage control layers 125b and 225b can include the same material as each other. The above-mentioned material can be, for example, TiAlC, but is not limited thereto. The first and second upper threshold voltage control layers 125b and 225b can have the same thickness as each other or different thicknesses as each other.

[0052] Each of the first and second upper barrier layers 126 and 226 can be the same as the described upper barrier layer 26 above. Figures 1-3 The described upper barrier layer 26 is the same. In some embodiments, the first and second upper barrier layers 126 and 226 can include the same material as each other. The above-mentioned material can be, for example, TiN, but is not limited thereto. In some other embodiments, the first and second upper barrier layers 126 and 226 can have equal thicknesses, although unequal thicknesses are also possible.

[0053] Each of the first and second gate fill layers 127 and 227 can be the same as the described gate fill layer 27 above. Figures 1-3 The described gate fill layer 27 is the same. In some embodiments, the first and second gate fill layers 127 and 227 can include the same material. The above-mentioned material can be W, but is not limited thereto. The first and second gate fill layers 127 and 227 can have the same thickness as each other or different thicknesses as each other.

[0054] The semiconductor device 200 can further include a first gate spacer 130 on sidewalls of the first gate structure 120 and a second gate spacer 230 on sidewalls of the second gate structure 220. Each of the first gate spacer 130 and the second gate spacer 230 can be the same as the gate spacer 30 described above with reference to FIG. 1. Figures 1-3 In some embodiments, the first gate spacer 130 and the second gate spacer 230 can have the same material as each other.

[0055] The device isolation layer 13 can electrically isolate the first transistor TR1 and the second transistor TR2 from each other. The interlayer insulating layer 40 can fill a space from an upper surface of the substrate 10 to a height of upper ends of the first gate structure 120 and the second gate structure 220. The interlayer insulating layer 40 can cover the first source / drain pair 112, the second source / drain pair 212, the device isolation layer 13, sidewalls of the first gate spacer 130, and sidewalls of the second gate spacer 230.

[0056] Referring to Figure 4B , the first transistor TR1 includes both the first stabilization layer 123 and the first oxygen diffusion barrier layer 124, whereas the second transistor TR2 can include the second stabilization layer 223 and can not include the second oxygen diffusion barrier layer 224 (see Figure 4A ). That is, the second threshold voltage control layer 225 can be directly on the second stabilization layer 223. The second transistor TR2 can not include the second oxygen diffusion barrier layer 224 (see Figure 4A ) for controlling the threshold voltage of the second transistor TR2. For example, when the first transistor TR1 is a p-type transistor and the second transistor TR2 is an n-type transistor (e.g., CMOS device applications) and the second oxygen diffusion barrier layer 224 (see Figure 4A ) includes a material having a relatively high work function, the second transistor TR2 can not include the second oxygen diffusion barrier layer 224 (see Figure 4A ) for controlling the threshold voltage.

[0057] Referring to Figure 4C , the first transistor TR1 includes both the first stabilization layer 123 and the first oxygen diffusion barrier layer 124, whereas the second transistor TR2 can not include both the second stabilization layer 223 (see Figure 4A ) and the second oxygen diffusion barrier layer 224 (see Figure 4A ). That is, the second threshold voltage control layer 225 can be directly on the second ferroelectric layer 222. The second transistor TR2 can not include the second stabilization layer 223 (see Figure 4A). For example, when the first transistor TR1 is a p-type transistor and the second transistor TR2 is an n-type transistor and the second stabilization layer 223 (see Figure 4A ) includes a material having a relatively high work function, the second transistor TR2 can not include the second stabilization layer 223 (see Figure 4A ) for controlling the threshold voltage.

[0058] Referring to Figure 4D , the first transistor TR1 can not include the first oxygen diffusion barrier layer 124 (see Figure 4A ), and the second transistor TR2 can omit the second oxygen diffusion barrier layer 224 (see Figure 4A ). That is, the first threshold voltage control layer 125 can be directly on the first stabilization layer 123, and the second threshold voltage control layer 225 can be directly on the second stabilization layer 223.

[0059] Referring to Figure 4E , the first transistor TR1 can include the first stabilization layer 123 and can not include the first oxygen diffusion barrier layer 124 (see Figure 4A ), and the second transistor TR2 can not include the second stabilization layer 223 (see Figure 4A ) and the second oxygen diffusion barrier layer 224 (see Figure 4A ). That is, the first threshold voltage control layer 125 can be directly on the first stabilization layer 123, and the second threshold voltage control layer 225 can be directly on the second ferroelectric layer 222. For example, when the first transistor TR1 is a p-type transistor and the second transistor TR2 is an n-type transistor and the second stabilization layer 223 (see Figure 4A ) includes a material having a relatively high work function, the second transistor TR2 can not need the second stabilization layer 223 (see Figure 4A ) to properly control the threshold voltage of the n-type transistor.

[0060] Figure 5 is a flowchart illustrating a method (1000) of manufacturing a semiconductor device according to an embodiment. Figures 6A-6E is a diagram illustrating a method (1000) of manufacturing a semiconductor device according to an embodiment. Referring to Figure 5 and Figure 6A , an interface layer 21 can be formed on the substrate 10. The formed interface layer 21 can have a thickness of about to about . The interface layer 21 can be formed by, for example, natural oxidation, thermal oxidation, or atomic layer deposition (ALD) (S1100). In some embodiments, the interface layer 21 can be formed together with the ferroelectric layer 22 when the ferroelectric layer 22 is formed.

[0061] Referring toFigure 5 and Figure 6B A ferroelectric layer 22 can be formed on the interface layer 21 (S1200). The ferroelectric layer 22 can be formed by, for example, atomic layer deposition (ALD). The ferroelectric layer 22 can not have a ferroelectric phase, or only a small portion of the ferroelectric layer 22 can have a ferroelectric phase. Thus, the ferroelectric layer 22 can not exhibit ferroelectricity, or only exhibit relatively small ferroelectricity. Referring to FIG. 1, the ferroelectric layer 22 can be formed on the interface layer 21. Figure 5 and Figure 6C A stabilization layer 23 can be formed on the ferroelectric layer 22 (S1300). The stabilization layer 23 can be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, or a combination thereof.

[0062] Referring to FIG. 1, the stabilization layer 23 can be formed on the ferroelectric layer 22. Figure 5 and Figure 6D An oxygen diffusion barrier layer 24 can be formed on the stabilization layer 23 (S1400). The oxygen diffusion barrier layer 24 can be formed by, for example, CVD, PVD, ALD, or a combination thereof.

[0063] Referring to FIG. 1, the oxygen diffusion barrier layer 24 can be formed on the stabilization layer 23. Figure 5 and Figure 6E A silicon layer 50 can be formed on the oxygen diffusion barrier layer 24 (S1500). The silicon layer 50 can be formed by, for example, CVD, PVD, ALD, or a combination thereof. Thereafter, the ferroelectric layer 22 can be annealed. For example, the ferroelectric layer 22 can be annealed at a temperature in a range from about 200 °C to about 1000 °C (e.g., from about 200 °C to about 500 °C, and possibly from about 400 °C to about 700 °C or from about 600 °C to about 1000 °C). The ferroelectric layer 22 can be annealed in an atmosphere containing at least one of Ar, N2, O2. During the annealing, a ferroelectric phase can be generated in the ferroelectric layer 22. Thus, the ferroelectric layer 22 can exhibit ferroelectricity after the annealing. Alternatively, the ferroelectric layer 22 can exhibit stronger ferroelectricity compared to before the annealing. The stabilization layer 23 can help form the ferroelectric phase in the ferroelectric layer 22 during the annealing. In addition, the stabilization layer 23 can prevent the ferroelectric phase in the ferroelectric layer 22 from disappearing after the annealing. Thus, according to the manufacturing method (1000) of embodiments, the ferroelectric layer 22 having improved ferroelectric properties can be obtained.

[0064] In addition, the oxygen diffusion barrier layer 24 and the silicon layer 50 can prevent oxygen from moving into the interface layer 21 and prevent the thickness of the interface layer 21 from increasing during the annealing. For example, the increase in the thickness of the interface layer 21 during the annealing can be in a range from about 0.1 nm to about 10 nm (e.g., from about 0.1 nm to about 5 nm, and possibly from about 0.1 nm to about 2 nm or from about 0.1 nm to about 1 nm). Thus, according to the manufacturing method (1000) of embodiments, the thickness of the interface layer 21 can be prevented from increasing during the annealing process. to about Thus, according to the manufacturing method (1000) of embodiments, the thickness of the interface layer 21 can be prevented from increasing during the annealing process.

[0065] In some embodiments, a process of removing the silicon layer 50 can be further provided after the annealing. In this case, the silicon layer 50 can also be referred to as a sacrificial layer. In some embodiments, the sacrificial layer can include a material that can be used as an oxygen diffusion barrier in addition to silicon. The silicon layer 50 can be removed by a wet etching process or a dry etching process. In some embodiments, a process of removing the oxygen diffusion barrier layer 24 can be further performed after the silicon layer 50 is removed. In some embodiments, a process of removing the stabilization layer 23 can be further performed after the oxygen diffusion barrier layer 24 is removed. In some embodiments, the process of forming the oxygen diffusion barrier layer 24 (S1400) can be omitted.

[0066] Figures 7A-7H is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present application. Referring to Figure 7A The trench 11 and the device isolation layer 13 can be formed in or on the substrate 10. In some embodiments, the trench 11 can be formed from the substrate 10, or from an epitaxial layer grown on the substrate 10. Referring to Figure 7B A dummy gate structure 60 can be formed on the trench 11. In some embodiments of the present application, the dummy gate structure 60 can include a dummy gate insulating layer 61, a dummy gate electrode layer 62, and a dummy gate mask 63 stacked on the trench 11. The dummy gate insulating layer 61 can include, for example, silicon oxide, silicon nitride, or a combination thereof, but is not limited thereto. The dummy gate electrode layer 62 can include, for example, silicon, but is not limited thereto. The dummy gate mask 63 can include silicon oxide, silicon nitride, or a combination thereof, but is not limited thereto.

[0067] Referring to Figure 7C A gate spacer 30 can be formed on opposite sidewalls of the dummy gate structure 60. In detail, a gate spacer layer is formed on the dummy gate structure 60, and then the gate spacer layer is anisotropically etched to form the gate spacer 30. Referring to Figure 7D A source / drain pair 12 can be formed on opposite ends of the trench 11. The source / drain pair 12 can be formed from the substrate 10 by implanting impurities into the substrate 10. Alternatively, the source / drain pair 12 can be formed on the trench 11 by an epitaxial process.

[0068] Referring to Figure 7E An interlayer insulating layer 40 can be formed to fill a space having a height from an upper surface of the substrate 10 to an upper end of the dummy gate structure 60. In detail, the interlayer insulating layer 40 is formed on the source / drain pair 12, the device isolation layer 13, and the dummy gate structure 60, and then the interlayer insulating layer 40 can be planarized to expose the dummy gate electrode layer 62 of the dummy gate structure 60. The planarization can be performed by, for example, chemical mechanical polishing (CMP).

[0069] Referring toFigure 7F The dummy gate structure 60 is removed to form a gate trench GT exposing the inner wall of the gate spacer 30 and the channel 11. For example, the dummy gate structure 60 can be removed by a wet etching process, for example. Referring to Figure 7G The processes of the method (1000) of manufacturing a semiconductor device described above with reference to Figure 5 and Figures 6A-6E may be performed. That is, the interface layer 21, the ferroelectric layer 22, the stabilization layer 23, the oxygen diffusion barrier layer 24, and the silicon layer 50 are sequentially formed on the channel 11, and the ferroelectric layer 22 can be annealed. Next, the silicon layer 50 can be removed.

[0070] Referring to Figure 7H , the threshold voltage control layer 25, the upper barrier layer 26, and the gate fill layer 27 can be sequentially formed on the oxygen diffusion barrier layer 24. In some embodiments of the present application, forming the threshold voltage control layer 25 can include a process of forming a lower threshold voltage control layer 25a on the oxygen diffusion barrier layer 24 and a process of forming an upper threshold voltage control layer 25b on the lower threshold voltage control layer 25a. The threshold voltage control layer 25, the upper barrier layer 26, and the gate fill layer 27 can be formed by CVD, PVD, ALD, or a combination thereof, respectively.

[0071] Next, the ferroelectric layer 22, the stabilization layer 23, the oxygen diffusion barrier layer 24, the threshold voltage control layer 25, the upper barrier layer 26, and the gate fill layer 27 can be planarized to expose the interlayer insulating layer 40. In this way, the semiconductor device 100 shown in Figure 1 may be manufactured. In some embodiments, in the processes shown in Figure 7A , the channel 11 can be formed in a fin type. In this case, the semiconductor device 100b shown in Figures 2A-2C may be manufactured.

[0072] Figure 8A and Figure 8B are diagrams showing a method of manufacturing a semiconductor device according to an embodiment of the present application. Referring to Figure 8A , according to the method shown in Figures 7A-7H , a first channel 111, a first source / drain pair 112, a first gate spacer 130, and a first gate trench GT1 are formed on a first region R1 of the substrate 10, and a second channel 211, a first source / drain pair 212, a second gate spacer 230, and a second gate trench GT2 are formed on a second region R2 of the substrate 10. In addition, a device isolation layer 13 and an interlayer insulating layer 40 can be formed on the first region R1 and the second region R2 in the substrate 10.

[0073] Next, a first interface layer 121 can be formed on the first region Rl of the substrate 10, and a second interface layer 221 can be formed on the second region R2 of the substrate 10. Then, the ferroelectric layer 22, the stabilization layer 23, the oxygen diffusion barrier layer 24, and the silicon layer 50 are sequentially formed on the first region Rl and the second region R2 of the substrate 10, and the ferroelectric layer 22 can be annealed. Next, the silicon layer 50 can be removed.

[0074] Referring to Figure 8B A first threshold voltage control layer 125 is formed on the first region Rl of the substrate 10, and a second threshold voltage control layer 225 is formed on the second region R2 of the substrate 10. Next, an upper barrier layer 26 is formed on the first region Rl and the second region R2 of the substrate 10, and a gate fill layer 27 can be formed on the first region Rl and the second region R2 of the substrate 10.

[0075] The ferroelectric layer 22, the stabilization layer 23, the oxygen diffusion barrier layer 24, the first threshold voltage control layer 125, the second threshold voltage control layer 225, the upper barrier layer 26, and the gate fill layer 27 can be planarized to expose the interlayer insulating layer 40. In this way, the semiconductor device 200 shown in FIG. 1 can be manufactured. Figure 4A

[0076] Since the first ferroelectric layer 122 and the second ferroelectric layer 222 can be formed from the ferroelectric layer 22, the first ferroelectric layer 122 and the second ferroelectric layer 222 can include the same material and can have the same thickness as each other. Since the first stabilization layer 123 and the second stabilization layer 223 can be formed from the stabilization layer 23, the first stabilization layer 123 and the second stabilization layer 223 can include the same material and can have substantially the same thickness as each other. Since the first oxygen diffusion barrier layer 124 and the second oxygen diffusion barrier layer 224 can be formed from the oxygen diffusion barrier layer 24, the first oxygen diffusion barrier layer 124 and the second oxygen diffusion barrier layer 224 can include the same material and can have substantially the same thickness as each other. Since the first upper barrier layer 126 and the second upper barrier layer 226 can be formed from the upper barrier layer 26, the first upper barrier layer 126 and the second upper barrier layer 226 can include the same material and can have substantially the same thickness as each other. Since the first gate fill layer 127 and the second gate fill layer 227 can be formed from the gate fill layer 27, the first gate fill layer 127 and the second gate fill layer 227 can include the same material. Figure 4A Figure 4A Figure 4B Figure 4B Figure 4B

[0077] ​​​​​​In some embodiments, the method of manufacturing a semiconductor device can further include a process of removing a portion of the oxygen diffusion barrier layer 24 on the second region R2 of the substrate 10. In this case, a semiconductor device 200b as illustrated can be manufactured. Figure 4B Because the portion of the oxygen diffusion barrier layer 24 on the second region R2 of the substrate 10 is removed while the oxygen diffusion barrier layer 24 on the first region Rl of the substrate 10 is retained, the threshold voltages of the first transistor TRl and the second transistor TR2 can be easily controlled.

[0078] In some embodiments of the present application, the method of manufacturing a semiconductor device can further include removing a portion of the oxygen diffusion barrier layer 24 on the second region R2 of the substrate 10 and removing a portion of the stabilization layer 23 on the second region R2 of the substrate 10. In this case, a semiconductor device 200c as illustrated can be manufactured. Figure 4C Because the portion of the stabilization layer 23 on the second region R2 of the substrate 10 is removed while the portion of the stabilization layer 23 on the first region Rl of the substrate 10 is retained, the threshold voltages of the first transistor TRl and the second transistor TR2 can be easily controlled.

[0079] In some embodiments, the process of forming the oxygen diffusion barrier layer 24 on the first region Rl and the second region R2 of the substrate 10 can be omitted. In this case, a semiconductor device 200d as illustrated can be manufactured. Figure 4D In other embodiments, the process of forming the oxygen diffusion barrier layer 24 on the first region Rl and the second region R2 of the substrate 10 can be omitted and the method of manufacturing a semiconductor device can further include a process of removing a portion of the stabilization layer 23 on the second region R2 of the substrate 10. In this case, a semiconductor device 200e as illustrated can be manufactured. Figure 4E

[0080] Figures 9A-9G is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment. Referring to Figure 9A A plurality of sacrificial layers 70 and a plurality of channel layers 11' can be alternately provided on the substrate 10. In Figure 9A In the embodiment, three sacrificial layers 70 and three channel layers 11' are formed, but the number of the sacrificial layers 70 and the number of the channel layers 11' are not limited to the above-described example. The sacrificial layers 70 and the channel layers 11' can be formed by epitaxial growth. The sacrificial layers 70 can include a material having etching selectivity with respect to the channel layers 11'. For example, when the channel layers 11' include Si, the sacrificial layers 70 can include Si-Ge. When the channel layers 11' include Ge or Si-Ge, the sacrificial layers 70 can include Si.

[0081] Referring to Figure 9B ​A dummy gate structure 60 can be formed on the uppermost channel layer 11'. The dummy gate structure 60 can include a dummy gate insulating layer 61, a dummy gate electrode layer 62, and a dummy gate mask 63, which are sequentially stacked on the channel layer 11'. The dummy gate structure 60 can be formed by etching the dummy gate insulating layer 61 and the dummy gate electrode layer 62 using the dummy gate mask 63 as an etching mask. Thereafter, the first gate spacers 30a can be formed on the sidewalls of the dummy gate structure 60. For example, a first gate spacer layer is formed on the dummy gate structure 60 and the uppermost channel layer 11', and then the first gate spacer layer is anisotropically etched to form the first gate spacers 30a.

[0082] Referring to Figure 9C The plurality of sacrificial layers 70 and the plurality of channel layers 11' can be etched using the dummy gate structure 60 and the first gate spacers 30a as etching masks (see Figure 9B ). In this way, the channel 11 can be obtained. The channel 11 can include a plurality of portions 11b to 11d formed from the plurality of channel layers 11' (see Figure 9B ), respectively. In addition, the channel 11 can include a lowermost portion 11a, which can be formed from the substrate. The plurality of portions 11b to 11d of the channel 11 can be separated from each other due to the sacrificial layers 70 in the vertical direction.

[0083] Referring to Figure 9D , the sidewall portions of the sacrificial layers 70 are removed to form recesses R. For example, a wet etching can be performed to form the recesses R. The recesses R can expose a lower surface of the uppermost portion 11d of the channel 11, upper and lower surfaces of the intermediate portions 11b and 11c of the channel 11, an upper surface of the lowermost portion 11a of the channel 11, and sidewalls of the sacrificial layers 70.

[0084] Next, the second gate spacers 30b filling the recesses R can be formed. For example, a second gate spacer layer is formed on the substrate 10, and then the second gate spacer layer is anisotropically etched to form the second gate spacers 30b.

[0085] Referring to Figure 9E The source / drain pair 12 can be formed on the substrate 10. The source / drain pair 12 can be formed by epitaxial growth. One of the source / drain pair 12 can be formed to contact end portions of the plurality of portions 11a to 11d of the channel 11. The other of the source / drain pair 12 can be formed to contact opposite end portions of the plurality of portions 11a to 11d of the channel 11.

[0086] Referring to Figure 9FAn interlayer insulating layer 40 can be formed on the substrate 10, the source / drain pair 12, and the dummy gate structure 60. Thereafter, the interlayer insulating layer 40 can be planarized to expose the dummy gate electrode layer 62. The dummy gate mask 63 can be removed by the planarization. The planarization can include, for example, a CMP process.

[0087] Referring to Figure 9G The dummy gate electrode layer 62 and the sacrificial layer 70 can be removed (see Figure 9F ). Here, for example, a wet etching process can be performed. In this way, the gate trench GT can be formed, and the gate trench GT exposes the inner wall of the first gate spacer 30a, the inner wall of the second gate spacer 30b, the upper surface of the lowermost portion 11a of the channel 11, and the upper and lower surfaces of the other portions 11b to 11d of the channel 11.

[0088] Referring to Figure 3 The gate structure 20 can be formed in the gate trench GT. First, the interface layer 21, the ferroelectric layer 22, the stabilization layer 23, the oxygen diffusion barrier layer 24, and the silicon layer 50 are formed on each of the portions 11a to 11d of the channel 11 according to the method (1000) of manufacturing a semiconductor device described above with reference to Figure 5 and Figures 6A-6E (see Figure 6E ). Next, the ferroelectric layer 22 is annealed. Thereafter, the silicon layer 50 is removed (see Figure 6E ), and the threshold voltage control layer 25, the upper barrier layer 26, and the gate fill layer 27 can be sequentially formed on the oxygen diffusion barrier layer 24. In this way, the semiconductor device 100c shown in Figure 3 can be manufactured.

[0089] While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate, the substrate comprising a first region and a second region; A first gate structure is located on the first region of the substrate. The first gate structure includes a first interface layer, a first ferroelectric layer, a first stabilization layer, a first oxygen diffusion barrier layer, and a first threshold voltage control layer, which are sequentially stacked on the first region of the substrate. as well as A second gate structure is located on the second region of the substrate. The second gate structure includes a second interface layer, a second ferroelectric layer, a second stabilization layer, and a second threshold voltage control layer sequentially stacked on the second region of the substrate. The second threshold voltage control layer is directly located on the second stabilization layer. The first stabilization layer is configured to stabilize the ferroelectric phase of the first ferroelectric layer, thereby maintaining the ferroelectric properties of the first ferroelectric layer; and The second stabilization layer is configured to stabilize the ferroelectric phase of the second ferroelectric layer, thereby maintaining the ferroelectric properties of the second ferroelectric layer.

2. The semiconductor device according to claim 1, wherein, The thickness of the first interface layer is to Within the range.

3. The semiconductor device according to claim 1, wherein, The first stabilization layer and the first threshold voltage control layer comprise different materials.

4. The semiconductor device according to claim 3, wherein, The work function of the material included in the first stabilization layer is greater than the work function of the material included in the first threshold voltage control layer.

5. The semiconductor device according to claim 1, wherein, The first stabilization layer comprises at least one material selected from the group consisting of TiN, MoN, Mo, Al2O3, AlN, W, WN, WCN, La, LaO, LaN, TiAlN, and TiON.

6. The semiconductor device according to claim 1, wherein, The first oxygen diffusion barrier layer comprises at least one material selected from the group consisting of TiN, AlN, TaN, TiSiN, TiON, TiAlN, WCN, WN, and W.

7. The semiconductor device according to claim 1, wherein, The thickness of the first stabilizing layer is equal to the thickness of the second stabilizing layer.

8. The semiconductor device according to claim 1, wherein, The first stabilizing layer and the second stabilizing layer comprise the same material.

9. The semiconductor device according to claim 1, wherein, The first threshold voltage control layer includes a first lower threshold voltage control layer located on the first stabilization layer and a first upper threshold voltage control layer located on the first lower threshold voltage control layer; wherein, the second threshold voltage control layer includes a second lower threshold voltage control layer located on the second ferroelectric layer and a second upper threshold voltage control layer located on the second lower threshold voltage control layer.

10. The semiconductor device according to claim 9, wherein, The work function of the material included in the first stabilization layer is greater than the work function of the material included in the first upper threshold voltage control layer.

11. The semiconductor device according to claim 9, wherein, The work function of the material included in the first stabilization layer is greater than the work function of the material included in the first lower threshold voltage control layer.

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