Integrated circuit element and method for manufacturing the same

Abstract

An integrated circuit device and method for fabricating the same include a stack of RRAM cells formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep to allow the RRAM cells to be formed using a planarization process. The resulting RRAM cells may have a U-shaped profile. The area of ​​the RRAM cells includes contributions from the bottom of the RRAM cell layer parallel to the substrate and from the sides of the RRAM cell layer substantially perpendicular to the substrate. The combination of the curved sides and bottom of the RRAM cells provides an increased area compared to a flat cell stack, which reduces the formation voltage and set voltage of the RRAM cells.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit devices and methods of manufacturing the same. Background Art

[0002] RRAM boasts a simple structure, low operating voltage, high speed, excellent endurance, and CMOS process compatibility. It is highly anticipated as a smaller alternative to traditional flash memory and is finding widespread application in devices such as optical disks and non-volatile memory arrays.

[0003] RRAM cells store data in a material that can be induced to undergo a phase change. The phase change can be induced in all or part of a layer to switch between a high resistance state or a low resistance state. The resistance state can be queried and interpreted as "0" or "1". In a typical RRAM cell, the data storage layer comprises an amorphous metal oxide. Under the application of sufficient voltage, a metal bridge is induced to form on the data storage layer, resulting in a low resistance state. The metal bridge can be destroyed and the high resistance state restored by applying a short high current density pulse to melt or otherwise destroy all or part of the metal structure. The data storage layer quickly cools down and maintains the high resistance state until a low resistance state is induced again. Summary of the Invention

[0004] In some embodiments, an integrated circuit device includes a substrate, a metal interconnect structure, and a resistive random access memory (RRAM) cell. The substrate has a surface. The metal interconnect structure is formed on the surface. The RRAM cell is formed within the metal interconnect structure and includes a bottom electrode layer, a top electrode layer, and a conversion layer located between the bottom and top electrode layers. The top of the top electrode layer and the top of the bottom electrode layer have equal heights above the substrate.

[0005] In some embodiments, an integrated circuit device includes a substrate, a metal interconnect structure, and a resistive random access memory (RRAM) cell. The substrate has a surface. The metal interconnect structure is formed on the surface. The RRAM cell is formed within the metal interconnect structure, and the RRAM cell includes a bottom electrode layer, a top electrode layer, and a conversion layer located between the bottom and top electrode layers. The RRAM cell has multiple edges, including the bottom electrode layer, the conversion layer, and the top electrode layer. The RRAM cell is curved so that the edges all lie in a plane.

[0006] In some embodiments, a method for fabricating an integrated circuit device includes the following steps: forming a metal interconnect layer on a semiconductor substrate; forming a dielectric layer on the metal interconnect layer; forming an opening in the dielectric layer; forming a RRAM cell stack above the opening; and planarizing the RRAM cell stack within the opening to form a RRAM cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description, when read in conjunction with the accompanying drawings, will provide an understanding of the various aspects of the present disclosure. It should be noted that many features in the drawings are not drawn to scale according to standard practice in the field. In fact, the dimensions of the features described may be increased or decreased arbitrarily to facilitate clarity of discussion.

[0008] Figure 1 is a schematic cross-sectional view of an integrated circuit having a resistance random access memory cell according to some aspects of the present disclosure;

[0009] Figure 2 is another cross-sectional schematic diagram of an integrated circuit having a resistance random access memory cell according to some aspects of the present disclosure;

[0010] Figure 3 supply Figure 1 A schematic top view of a resistive random access memory cell in an integrated circuit device;

[0011] Figures 4 to 13 A schematic cross-sectional view illustrating a series of manufacturing processes of an integrated circuit chip according to some aspects of the present disclosure is shown;

[0012] Figure 14 is a flow chart of a manufacturing process according to some aspects of the present disclosure.

[0013]

Explanation of symbols

[0014] 101: Integrated Circuit Components

[0015] 102:Through hole

[0016] 103:Memory unit

[0017] 105: Width

[0018] 107: Height

[0019] 108: First metal interconnection layer

[0020] 109: Top electrode layer

[0021] 111: Active metal layer

[0022] 113: Conversion layer

[0023] 115: bottom electrode layer

[0024] 117: Bottom electrode through hole

[0025] 118: Second metal interconnection layer

[0026] 120: Angle

[0027] 121:Memory area

[0028] 123: Surrounding area

[0029] 125: Interlayer dielectric

[0030] 127: Metal Characteristics

[0031] 128:Metal inner connection layer

[0032] 129: Etch stop layer

[0033] 131: Interface layer

[0034] 133:Through hole

[0035] 135: interlayer dielectric layer

[0036] 137: Interlayer dielectric layer

[0037] 138:Metal inner connection layer

[0038] 139:Metal Characteristics

[0039] 141: Length

[0040] 200: Cross-sectional view

[0041] 202: Base material

[0042] 203:Through hole

[0043] 204: shallow trench isolation area

[0044] 206: word line transistor

[0045] 210: Gate

[0046] 212: word line dielectric layer

[0047] 214: Source / drain region

[0048] 216: Source / drain region

[0049] 217:Metal Characteristics

[0050] 218:Metal internal connection structure

[0051] 400: Cross-sectional view

[0052] 500: Cross-sectional view

[0053] 600: Cross-sectional view

[0054] 601: Opening

[0055] 603:Mask

[0056] 605: Width

[0057] 700: Cross-sectional view

[0058] 701: Materials

[0059] 800: Cross-sectional view

[0060] 900: Cross-sectional view

[0061] 1000: Cross-sectional view

[0062] 1001: Open

[0063] 1003:Mask

[0064] 1005: Width

[0065] 1100: Cross-sectional view

[0066] 1101: Resistive Random Access Memory Cell Stack

[0067] 1200: Cross-sectional view

[0068] 1300: Cross-sectional view

[0069] 1400:Process

[0070] 1401: Action

[0071] 1403: Action

[0072] 1405: Action

[0073] 1407: Action

[0074] 1409: Action

[0075] 1411: Action

[0076] 1413: Action

[0077] 1415: Action

[0078] 1417: Action

[0079] 1419: Action

[0080] 1421: Action

[0081] 1423: Action

[0082] 1425: Action DETAILED DESCRIPTION

[0083] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be definitive. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed so as to be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0084] Additionally, for simplicity of description, spatially relative terms, such as "below," "beneath," "below," "above," "above," and the like, may be used herein to describe the relationship of one element or feature relative to another (other) element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0085] As the area of ​​RRAM cells decreases, the formation and set voltages increase. The present disclosure provides RRAM geometries that can reduce the formation and set voltages without reducing device density. According to the present disclosure, RRAM cells are formed over openings in a dielectric layer. The dielectric layer is sufficiently thick and the openings are sufficiently deep relative to the thickness of the RRAM cells, allowing the RRAM cells to be formed using a planarization process to remove the portion of the RRAM cell stack that is located outside the dielectric layer openings.

[0086] The resulting RRAM cell may have a U-shaped profile and have an area that includes contributions from the bottom of the RRAM cell layers stacked parallel to the substrate and contributions from the sides of the RRAM cell, where the RRAM cell layers are stacked along a steep slope that is almost perpendicular to the substrate. For example, the bottom may be disk-shaped, and the sides may have the shape of a truncated cone that is almost cylindrical. In other embodiments, the bottom is rectangular, and the sides include four trapezoids with shared edges. The combination of the sides and bottom of the RRAM cell with a U-shaped profile provides a larger area than a planar RRAM cell with the same footprint. The increased area reduces the forming voltage and the set voltage. The proportion of ineffective cell area due to edge effects is reduced, which is conducive to size reduction.

[0087] The multiple layers of the RRAM cell stack according to the present disclosure are bent to form multiple edges that are all aligned in a plane. The plane is parallel to the surface of the substrate, so that the tops of the layers forming the RRAM cell stack are at the same height above the substrate. The order from "lower" to "higher" refers to the order of the layers through which electricity flows from the bottom electrode via directly below the RRAM cell stack to the top electrode via directly above the RRAM cell stack according to the present disclosure. Each lower layer can be bent to surround the layer above it. At least the bottom electrode layer and the resistive switching dielectric layer can have edges that are bent to form a closed loop in a plane.

[0088] In some of these teachings, the dielectric layer having an opening located above the RRAM cell stack is an interlevel dielectric layer. In some of these teachings, the interlevel dielectric layer is a low-k dielectric layer. In some of these teachings, the interlevel dielectric layer is an ultra-low-k dielectric layer. The RRAM cell stack may be formed between two adjacent metal interconnect layers. In some of these teachings, the depth of the opening in which the RRAM cell stack is formed is half the distance between the two metal interconnect layers or more.

[0089] Figure 1A schematic cross-sectional view of a portion of an integrated circuit device 101 including memory cells 103 according to some aspects of the present disclosure is shown. Each memory cell 103 includes a bottom electrode layer 115, a resistive switching layer 113, an active metal layer 111, and a top electrode layer 109. The RRAM cell 103 is surrounded by an interlayer dielectric layer 135. The top electrode layer 109 is coupled to a metal feature 139 in a metal interconnect layer 138 via a top electrode via 102. The metal feature 139 and the top electrode via 102 are surrounded by an interlayer dielectric layer 137. The interlayer dielectric layer 137 can be made of the same material as the interlayer dielectric layer 135. The bottom electrode layer 115 is coupled to a metal feature 127 in a metal interconnect layer 128 via a bottom electrode via 117. The bottom electrode via 117 is surrounded by an etch stop layer 129 and an interface layer 131. The etch stop layer 129 and the interface layer 131 may have a higher dielectric constant than the interlayer dielectric layer 135. The metal features 127 are surrounded by the matrix of the interlayer dielectric 125.

[0090] Metal interconnect layer 128 and metal interconnect layer 138 are part of a metal interconnect structure 218 disposed on substrate 202. Metal interconnect layer 128 may be the third metal interconnect layer disposed on substrate 202, and metal interconnect layer 138 may be the fourth metal interconnect layer. Metal interconnect structure 218 may also include first metal interconnect layer 108, second metal interconnect layer 118, and may include additional interconnect layers above those shown. In some of these teachings, as shown, memory cell 103 is located between third metal interconnect layer 128 and fourth metal interconnect layer 138. In some of these teachings, memory cell 103 is located between fourth metal interconnect layer 138 and a fifth metal interconnect layer. In general, memory cell 103 may be located between any adjacent pair of metal interconnect layers.

[0091] For example, substrate 202 may be a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate, or the like. One or more shallow trench isolation (STI) regions 204 or oxide-filled trenches may be disposed in or above substrate 202. A pair of word line transistors 206 may be located between STI regions 204. Word line transistors 206 may include gates 210 that operate as word lines. Gates 210 are separated from substrate 202 by a word line dielectric layer 212. Source / drain regions 214, 216 for word line transistors 206 may be formed in or above substrate 202. Metal features 217 in second metal interconnect layer 118 or elsewhere in metal interconnect structure 218 may be coupled to source / drain regions 216 and may operate as source lines. Bottom electrode layer 115 can be coupled to source / drain regions 214 via vias 203. Metal features 139 in fourth metal interconnect layer 138 or some other metal interconnect layer located above memory cell 103 can operate as bit lines. The illustrated control structure for the memory cell in integrated circuit device 101 is one of many possible control structures for connecting and operating memory cell 103. Integrated circuit devices according to the present disclosure are not limited in terms of control structure.

[0092] Metal interconnect structure 218 is a product of the back-end-of-line (BEOL) process. Metal features 139 and 217 of metal interconnect layers 108, 118, 128, and 138, as well as top electrode via 102, bottom electrode via 117, via 133, and via 203, can be formed from metals such as copper, aluminum, gold, tungsten, or the like. Interlayer dielectric layers 135 and 137 can be low-k or ultra-low-k. Low-k dielectrics are materials with a lower dielectric constant than silicon dioxide, which has a dielectric constant of approximately 3.9. Examples of low-k dielectrics include organosilicate glass (OSG), such as carbon-doped silicon dioxide, fluorinated silica glass (FSG), organic polymer low-k dielectrics, or porous silica glass. Ultra-low-k dielectrics are materials with a dielectric constant of approximately 2.1 or less. Ultra-low-k dielectrics are generally low-k dielectric materials formed into a porous structure. The porosity reduces the effective dielectric constant.

[0093] Figure 2A cross-sectional schematic diagram 200 illustrates another portion of integrated circuit device 101. Cross-sectional schematic diagram 200 includes a portion of memory region 121 and a portion of peripheral region 123 outside memory region 121. Memory region 121 includes two RRAM cells 103. Cross-sectional schematic diagram 200 focuses on the area between third metal interconnect layer 128 and fourth metal interconnect layer 138.

[0094] Figure 3 A schematic top view of memory cell 103 is shown. The layers of memory cell 103 are shown as square, however, the edges may be rounded. Memory cell 103 may be disk-shaped or have another shape consistent with the present teachings. Bottom electrode layer 115, conversion layer 113, active metal layer 111, and top electrode layer 109 are stacked and nested in order of size like an inverted set of Russian dolls. The nesting order of size is such that bottom electrode layer 115 surrounds conversion layer 113, conversion layer 113 surrounds active metal layer 111, and active metal layer 111 surrounds top electrode layer 109. Each surrounding layer curves to surround the layer it surrounds. The edges of these layers all terminate in a plane at the top of memory cell 103. This structure is the result of a planarization process that defines the edges.

[0095] The area of ​​the memory cell 103 includes contributions from the bottom and contributions from the sides. For a given footprint size, having steep sides of the memory cell 103 increases the overall area. Angle 120 (see Figure 2 ) may be greater than 45 degrees. In some of these teachings, angle 120 is greater than 60 degrees. In some of these teachings, angle 120 is greater than 75 degrees. In some of these teachings, angle 120 is greater than 90 degrees.

[0096] Memory cell 103 can have any suitable dimensions. In some of these teachings, width 105 and length 141 range from 25 nanometers to 1000 nanometers. In some of these teachings, width 105 and length 141 range from 50 nanometers to 500 nanometers. In some of these teachings, height 107 of memory cell 103 ranges from 25 nanometers to 1000 nanometers. In some of these teachings, height 107 ranges from 50 nanometers to 250 nanometers. In some of these teachings, height 107 ranges from 75 nanometers to 200 nanometers, for example, 100 nanometers. Height 107 can be much greater than the combined thickness of each etch stop layer 129 and interface layer 131.

[0097] The contribution of the sides to the overall area of ​​memory cell 103 is greater than or equal to the contribution of the bottom to the overall area of ​​memory cell 103. In some of these teachings, the contribution of the sides to the area is greater than the contribution of the bottom to the area. If angle 120 is close to 90 degrees and the bottom is square, the ratio of the contribution of the sides to the contribution of the bottom is about four times the ratio of height 107 to width 105. Thus, in some teachings, height 107 is at least one-quarter the width 105. In some of these teachings, height 107 is at least half the width 105.

[0098] The layers in each memory cell 103 may include multiple layers having various compositions. The bottom electrode via 117 may be made of titanium nitride or the like, or other suitable conductive materials. In some examples, the thickness of the bottom electrode via 117 ranges from 250 angstroms to 500 angstroms. A diffusion barrier layer may separate the bottom electrode via 117 from the metal feature 127. The diffusion barrier layer may be made of titanium nitride or the like, for example. In some examples, the thickness of the diffusion barrier layer ranges from 50 angstroms to 100 angstroms.

[0099] The bottom electrode layer 115 is a conductive material, such as titanium nitride, tantalum nitride, combinations thereof, or the like. The bottom electrode layer 115 may also be titanium, tantalum, platinum, gold, iridium, tungsten, nickel, ruthenium, copper, or the like. In some of these teachings, the bottom electrode layer 115 has a thickness of about 20 angstroms to about 200 angstroms. In some of these teachings, the bottom electrode layer 115 has a thickness of about 50 angstroms to about 150 angstroms. These exemplary thicknesses, as well as other exemplary dimensions given below, are applicable to a particular manufacturing node. The exemplary dimensions may be scaled proportionally for other manufacturing nodes.

[0100] The resistance switching layer 113 is a dielectric layer whose resistance can be changed through the hysteresis effect. The switching layer 113 can be a dielectric layer through which a conductive bridge can be reversibly formed. In some examples, the switching layer 113 is a metal oxide. In some examples, the switching layer 113 is a high-k dielectric. The switching layer 113 can be, for example, nickel oxide, tantalum oxide, hafnium tantalum oxide, tantalum aluminum oxide, hafnium oxide, tungsten oxide, zirconium oxide, aluminum oxide, strontium titanate, or the like. In some of these teachings, the thickness of the switching layer 113 ranges from about 20 angstroms to about 100 angstroms. In some of these teachings, the thickness of the switching layer 113 ranges from about 30 angstroms to about 40 angstroms.

[0101] Depending on the type of memory, the memory cell 103 may include an active metal layer 111 that contributes to the switching resistance. The active metal layer 111 may be a metal that alternately provides and absorbs ions to promote the switching resistance function. In some embodiments, the active metal layer 111 is a metal or a metal oxide with a relatively low oxygen concentration. For example, metals suitable for the active metal layer 111 are titanium, hafnium, platinum, aluminum, silver, gold, copper, or the like. In some of these teachings, the thickness of the active metal layer 111 is about 20 angstroms to about 100 angstroms. In some of these teachings, the thickness of the active metal layer 111 ranges from about 30 angstroms to about 70 angstroms.

[0102] A top electrode layer 109 is disposed on the conversion layer 113. The top electrode layer 109 may include a liner composed of tungsten or the like. The top electrode layer 109 may include one or more layers composed of a metal or metal compound, such as titanium, titanium nitride, tantalum, tantalum nitride, or the like. In some of these teachings, the thickness of the top electrode layer 109 ranges from approximately 100 angstroms to 400 angstroms. In some of these teachings, the thickness of the top electrode layer 109 ranges from approximately 150 angstroms to 350 angstroms. The top electrode layer 109 is thick enough to completely fill the opening formed therein of the memory cell 103.

[0103] During operation of the memory cell 103, a voltage may be applied between the top electrode layer 109 and the bottom electrode layer 115. Depending on the applied voltage, the voltage may be used to assess whether the memory cell 103 is in a low resistance state or a high resistance state, or to place the memory cell 103 in a high resistance state or a low resistance state. The memory cell 103 may be any type of RRAM cell. For example, types of RRAM cells include magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase-change memory (PCM), oxygen displacement memory (OxRAM), conductive bridging random access memory (CBRAM), carbon nanotube random access memory (NRAM), or the like. The number of layers, the thickness of the layers, and the composition of the layers of the memory cell 103 may vary.

[0104] Figures 4 to 13A series of cross-sectional views 400-1300 of an integrated circuit chip according to the present disclosure, manufactured according to the process of the present disclosure, are provided. Figures 4 to 13 Although described as a series of processes, the order of the processes may be changed in some cases and the series of processes may be applied to other structures not shown. In some embodiments, some of these processes may be omitted entirely or partially. Figures 4 to 13 Described as a series of processes, Figures 4 to 13 The structure shown is not intended to limit the method of manufacture, but can be used independently because the structure is separate from the method.

[0105] Figure 4 A schematic cross-sectional view 400 of an integrated circuit device after forming the third metal interconnect layer 128 is shown. The third metal interconnect layer 128 can be formed by any suitable process. For example, suitable processes may include a damascene process and a dual damascene process.

[0106] like Figure 5 As shown in cross-sectional schematic diagram 500 of , an etch stop layer 129 and an interface layer 131 are formed on the third metal interconnect layer 128. For example, the etch stop layer 129 can be silicon carbide. For example, the interface layer 131 can be silicon dioxide. These layers can also be or include other dielectrics, such as silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or the like. The combined thickness of the etch stop layer 129 and the interface layer 131 ranges from 150 angstroms to 600 angstroms. In some embodiments, the combined thickness of the etch stop layer 129 and the interface layer 131 ranges from 250 angstroms to 500 angstroms. In some embodiments, the combined thickness of the etch stop layer 129 and the interface layer 131 is less than 400 angstroms, for example, 300 angstroms. The etch stop layer 129 and the interface layer 131 can be formed by any suitable process or combination of processes.

[0107] like Figure 6As shown in cross-sectional schematic diagram 600 of FIG, a mask 603 may be formed over the etch stop layer 129 and the interface layer 131 to form an opening 601 through the etch stop layer 129 and the interface layer 131. The opening 601 is located above the metal feature 127 in the third metal interconnect layer 128. The mask 603 may be a photoresist mask patterned using photolithography. The opening 601 may be formed using any suitable etching process, such as plasma etching. The width 605 of the opening 601 may range from 10 nanometers to 100 nanometers. In some embodiments, the width 605 ranges from 45 nanometers to 100 nanometers, such as 50 nanometers. In some embodiments, the aspect ratio of the opening 601 (the ratio of the width 605 to the combined thickness of the etch stop layer 129 and the interface layer 131) ranges from 1:1 to 4:1. In some embodiments, the aspect ratio of the opening 601 ranges from 1.5:1 to 3:1, such as 5:3.

[0108] like Figure 7 As shown in the cross-sectional schematic diagram 700 of , the mask 603 may be stripped away and a layer of material 701 may be deposited to fill the opening 601 with a conductive material. Figure 8 As shown in the cross-sectional schematic diagram 800 of FIG, the layer of material 701 may be planarized to form the bottom electrode via 117. As previously described, the diffusion barrier layer may be deposited before the majority of the layer of material 701. The layer of material 701 may be formed using any suitable growth or deposition process. The planarization process may be chemical mechanical polishing (CMP) or any other suitable planarization process.

[0109] like Figure 9 As shown in cross-sectional schematic diagram 900 of FIG, an interlayer dielectric layer 135 is formed over the etch stop layer 129, the interface layer 131, and the bottom electrode via 117. The interlayer dielectric layer 135 can be a low-k or ultra-low-k dielectric formed using any suitable process. In some of these teachings, the thickness of the interlayer dielectric layer 135 ranges from 25 nanometers to 1000 nanometers. In some of these teachings, the thickness of the interlayer dielectric layer 135 ranges from 50 nanometers to 250 nanometers. In some of these teachings, the thickness of the interlayer dielectric layer 135 ranges from 75 nanometers to 200 nanometers, for example, approximately 100 nanometers. The thickness of the interlayer dielectric layer 135 can be much greater than the combined thickness of the etch stop layer 129 and the interface layer 131.

[0110] like Figure 10As shown in the cross-sectional schematic diagram 1000 of FIG, a mask 1003 can be formed in the interlayer dielectric layer 135 and used to form an opening 1001 through the interlayer dielectric layer 135. The opening 1001 is located above the bottom electrode via 117. The mask 1003 can be a photoresist mask patterned by photolithography. The opening 1001 can be formed using any suitable wet or dry etch, such as plasma etching. The plasma etching process can be used to provide the opening 1001 with steep sidewalls. The width 1005 of the opening 1001 can range from 25 nanometers to 1000 nanometers. In some of these teachings, the width 1005 of the opening 1001 ranges from 50 nanometers to 500 nanometers.

[0111] like Figure 11 As shown in the cross-sectional diagram 1100 of FIG. 1 , the mask 1003 can be peeled off and the layers of the RRAM cell stack 1101 can be conformally deposited on Figure 10 In this example, the RRAM cell stack 1101 includes a bottom electrode layer 115, a switching layer 113, an active metal layer 111, and a top electrode layer 109. The combined thickness of these layers, except for the topmost layer (i.e., the top electrode layer 109), is less than the opening 1001 (see FIG. 1 ). Figure 10 ) and the thickness of the interlayer dielectric layer 135, thereby Figure 12 The cross-sectional schematic 1200 is planarized to form a plurality of memory cells 103. In some of these teachings, the top electrode layer 109 is formed to a sufficient thickness so that the RRAM cell stack 1101 completely fills the opening 1001. The planarization process may be, for example, chemical mechanical polishing. The bottom electrode layer 115, the switching layer 113, the active metal layer 111, and the top electrode layer 109 may be formed by any suitable process or combination of processes. In some of these teachings, the switching layer 113 may be formed by an atomic layer deposition process, such as plasma enhanced atomic layer deposition, so that the switching layer 113 has a uniform thickness at the bottom and sides of the memory cell 103.

[0112] like Figure 13 As shown in the cross-sectional diagram 1300, the interlayer dielectric layer 137 is formed on Figure 12 1200 . ILD layer 137 can be the same material as ILD layer 135. In some of these teachings, ILD layer 137 has a thickness less than that of ILD layer 135. In some of these teachings, ILD layer 135 has a thickness that is half or more of the combined thickness of etch stop layer 129, interface layer 131, ILD layer 135, and ILD layer 137, or any combined thickness separating the metal interconnect layer directly below memory cell 103 and the metal interconnect layer directly above memory cell 103.

[0113] Figure 14 A flow chart of a process 1400 for producing some aspects of integrated circuit devices according to the present disclosure is provided. Although process 1400 is depicted and described herein as a series of acts or events, it is understood that the order of such acts or events as depicted should not be construed in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts or events than those depicted and / or described herein. Furthermore, not all depicted acts are required to implement one or more aspects or embodiments described herein. Furthermore, one or more acts described herein may be performed as one or more separate acts and / or stages.

[0114] The process 1400 begins with action 1401, a front-end-of-line (FEOL) process and the formation of a plurality of first metal interconnect layers to produce a Figure 4 The structure of the cross-sectional diagram 400 is shown. The process 1400 continues with action 1403, where an etch stop layer 129 and an interface layer 131 are deposited to produce the structure shown in FIG. Figure 5 A schematic cross-sectional view 500 is shown.

[0115] Action 1405 is to form and pattern a mask 603 to pattern the opening 601 in the etch stop layer 129 and the interface layer 131 to form Figure 6 The bottom electrode via 117 is shown in the cross-sectional view 600. Action 1407 is to pattern the opening 601 in the etch stop layer 129 and the interface layer 131, also shown in FIG. Figure 6 A cross-sectional schematic diagram 600 is provided.

[0116] Action 1409 is to deposit a layer of material 701 to fill the opening 601, such as Figure 7 Action 1411 is a planarization step to remove the layer of material 701 outside the opening 601, thereby forming a bottom electrode through hole 117, as shown in FIG. Figure 8 800 is a cross-sectional schematic diagram of the embodiment of the present invention.

[0117] Action 1413 is to deposit an interlayer dielectric layer 135 on the bottom electrode through hole 117, such as Figure 9 The cross-sectional view 900 of FIG. 1415 is shown. The operation 1415 is to form a mask 1003 on the interlayer dielectric layer 135 and etch an opening 1001 for the RRAM cell 103 through the interlayer dielectric layer 135. Figure 10 1000 is a cross-sectional schematic diagram of the embodiment of the present invention.

[0118] Action 1417 is to deposit a RRAM cell stack 1101 on the opening 1001, such as Figure 11The cross-sectional diagram 1100 of FIG. 1 shows a RRAM cell stack 1101 including a bottom electrode layer 115, a switching layer 113, an active metal layer 111 and a top electrode layer 109. Figure 11 As shown in the cross-sectional schematic diagram 1100 of , at least the bottom electrode layer 115 , the conversion layer 113 and the active metal layer 111 are conformally deposited along the shape of the opening 1001 .

[0119] Action 1419 is planarization to remove some portions of the RRAM cell stack 1101 outside the opening 1001, thereby forming a Figure 12 The cross-sectional diagram 1200 of FIG. 1200 shows the RRAM cell 103. As shown in the cross-sectional diagram 1200, the planarization process can define the edges of the RRAM cell 103 and align the edges of the RRAM cell 103 with a single plane.

[0120] Action 1421 is to deposit an interlayer dielectric layer 137 on the RRAM cell 103, such as Figure 13 1300. Action 1423 is to form an opening in and through the interlayer dielectric layer 137 in the memory region 121, and to form an opening in and through the interlayer dielectric layer 137 in the peripheral region 123, and fill these openings with metal to form a fourth metal interconnect layer 138 and vias 102 and 133 connecting the fourth metal interconnect layer 138 to the top electrode layer 109 and the third metal interconnect layer 128, as shown in FIG. Figure 2 Action 1425 is an additional process to complete the back-end process and the formation of the integrated circuit device 101.

[0121] Some aspects of the present disclosure relate to an integrated circuit device including a substrate, a metal interconnect structure formed on the substrate, and a resistive random access memory cell within the metal interconnect structure, wherein the resistive random access memory cell has a bottom electrode layer, a dielectric layer, and a top electrode. The bottom electrode layer is curved such that a top portion of the bottom electrode and a top portion of the top electrode are at equal heights above the substrate.

[0122] Some aspects of the present disclosure relate to a substrate, a metal interconnect structure formed on the substrate, and a RRAM cell within the metal interconnect structure, the RRAM cell having a bottom electrode layer, a dielectric layer, and a top electrode. The RRAM cell is curved such that edges of the RRAM cell are aligned with a plane parallel to a surface.

[0123] In some embodiments, the dielectric layer surrounds the top electrode layer.

[0124] In some embodiments, the bottom electrode layer is surrounded by a low-k dielectric layer.

[0125] In some embodiments, the bottom electrode layer is surrounded by an ultra-low-k dielectric layer.

[0126] In some embodiments, the RRAM cell has a width and a height, and the height is at least half of the width.

[0127] Some aspects of the present disclosure relate to a substrate, a metal interconnect structure formed on the substrate, and a RRAM cell formed in the metal interconnect structure. The RRAM cell has a bottom electrode layer, a dielectric layer, and a top electrode layer, and is bent so that edges of the RRAM cell lie in a plane parallel to a surface.

[0128] In some embodiments, the edge of the bottom electrode layer forms a closed loop in the plane.

[0129] In some embodiments, the bottom electrode layer surrounds the conversion layer and the top electrode layer.

[0130] In some embodiments, the bottom electrode layer is disposed in a matrix formed of a low-k dielectric.

[0131] In some embodiments, the RRAM cell has an area including a bottom area and a side area, and the side area is larger than the bottom area.

[0132] Some aspects of the present disclosure relate to a resistive random access memory (RRAM) cell comprising a substrate, a metal interconnect structure formed on the substrate, and a metal interconnect structure formed within the metal interconnect structure. The RRAM cell comprises a bottom electrode layer, a dielectric layer, and a top electrode. The layers are bent to terminate at the edge of a closed loop formed in a plane.

[0133] Some aspects of the present disclosure relate to a resistive random access memory (RRAM) cell including a substrate, a metal interconnect structure formed on the substrate, and a RRAM cell formed within the metal interconnect structure. The RRAM cell includes a bottom electrode layer, a dielectric layer, and a top electrode. The bottom electrode layer is curved to surround the RRAM dielectric layer.

[0134] Some aspects of the present disclosure relate to a method for fabricating an integrated circuit device. The method includes forming a metal interconnect layer on a semiconductor substrate, forming a dielectric layer on the metal interconnect layer, forming an opening in the dielectric layer, forming a RRAM cell stack on the opening, and planarizing the RRAM cell stack to form an RRAM cell in the opening.

[0135] In some embodiments, the dielectric layer is a low-k dielectric layer.

[0136] In some embodiments, the method further includes the following steps: forming an etch stop layer on the metal interconnect layer before forming the low-k dielectric layer; forming a via opening in the etch stop layer; and filling the via opening with metal to form a bottom electrode via for the RRAM cell.

[0137] In some embodiments, the opening has a width and a height, the height being at least half the width.

[0138] In some embodiments, forming a RRAM cell stack includes sequentially forming a bottom electrode layer, a switching layer, and a top electrode layer, forming the bottom electrode layer and the switching layer so that the opening is partially filled, and forming the top electrode layer to fill the opening.

Claims

1. An integrated circuit component, characterized in that: include: a substrate having a surface; a metal interconnect structure formed on the surface; a resistive random access memory cell formed within the metal interconnect structure, the resistive random access memory cell comprising a bottom electrode layer, a top electrode layer, and a conversion layer located between the bottom electrode layer and the top electrode layer; wherein a top portion of the top electrode layer and a top portion of the bottom electrode layer are at the same height above the substrate, a bottom portion of the bottom electrode layer is rectangular, and a side portion of the bottom electrode layer comprises four trapezoids having a shared edge; an etch stop layer below the bottom electrode layer and above the surface; and An interface layer is provided, wherein the etch stop layer and the bottom electrode layer are separated by the interface layer, and the interface layer contacts the etch stop layer and the bottom electrode layer.

2. The integrated circuit device according to claim 1, wherein: The RRAM cell has a plurality of edges, wherein the plurality of edges include the bottom electrode layer, the conversion layer and the top electrode layer; and The multiple edges are all located in a plane.

3. The integrated circuit element according to claim 2, wherein: The plane is parallel to the surface.

4. The integrated circuit element according to claim 1, wherein: The bottom electrode layer and the conversion layer are terminated at a plurality of edges, and the plurality of edges form a plurality of closed loops aligned in a plane.

5. The integrated circuit element according to claim 1, wherein: The bottom electrode layer surrounds the conversion layer.

6. The integrated circuit element according to claim 5, wherein: The conversion layer surrounds the top electrode layer.

7. The integrated circuit element according to claim 1, wherein: The bottom electrode layer is surrounded by a low dielectric constant layer.

8. The integrated circuit element according to claim 1, wherein: The bottom electrode layer is surrounded by an ultra-low dielectric constant layer.

9. The integrated circuit element according to claim 1, wherein: The RRAM cell has a width and a height; and The height is at least half the width.

10. An integrated circuit component, characterized in that: include: a substrate having a surface; a metal interconnect structure formed on the surface; a resistance random access memory cell formed in the metal interconnect structure, the resistance random access memory cell comprising a bottom electrode layer, a top electrode layer, and a conversion layer located between the bottom electrode layer and the top electrode layer; wherein the resistance random access memory cell has a plurality of edges, the plurality of edges including the bottom electrode layer, the conversion layer, and the top electrode layer; and an etch stop layer below the bottom electrode layer and above the surface, wherein the etch stop layer and the bottom electrode layer are separated by an interface layer, the interface layer contacting the etch stop layer and the bottom electrode layer; and The RRAM cell is curved so that the edges are all located in a plane.

11. The integrated circuit element according to claim 10, wherein: The plane is parallel to the surface.

12. The integrated circuit element according to claim 10, wherein: The edge of the bottom electrode layer forms a closed ring on the plane.

13. The integrated circuit element according to claim 10, wherein: The bottom electrode layer surrounds the conversion layer and the top electrode layer.

14. The integrated circuit element according to claim 10, wherein: The bottom electrode layer is arranged in a matrix formed by a low-k dielectric.

15. The integrated circuit device according to claim 10, wherein: The RRAM unit has an area including a bottom area and a side area; and The side area is larger than the bottom area.

16. A method for manufacturing an integrated circuit element, characterized in that: include: forming a metal interconnect layer on a semiconductor substrate; forming an etch stop layer on the metal interconnect layer; forming an interface layer on the etch stop layer; forming a dielectric layer on the metal interconnect layer, the etch stop layer, and the interface layer; forming an opening in the dielectric layer and the etch stop layer; forming a resistive random access memory cell stack on the opening, wherein forming the resistive random access memory cell stack includes sequentially forming a bottom electrode layer, a conversion layer, and a top electrode layer, the etch stop layer being located below the bottom electrode layer, a bottom portion of the bottom electrode layer being rectangular, a side portion of the bottom electrode layer including four trapezoids having a shared edge, the etch stop layer being separated from the bottom electrode layer by the interface layer, and the interface layer being in contact with the etch stop layer and the bottom electrode layer; and The RRAM cell stack within the opening is planarized to form a RRAM cell.

17. The method according to claim 16, characterized in that The dielectric layer is a low-k dielectric layer.

18. The method according to claim 16, characterized in that The opening has a width and a height; and The height is at least half the width.

19. The method according to claim 16, wherein forming the bottom electrode layer and the conversion layer so that the opening is partially filled; and The top electrode layer is formed to fill the opening.

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