boost circuit

Abstract

[Problem] This invention provides a boost circuit capable of adjusting power conversion capability according to input power and stably performing boost operation. [Solution] The boost circuit comprises: a first voltage detection circuit that outputs a first control signal as a result of comparing an input voltage and a first voltage obtained by dividing the output voltage; a first oscillation circuit that controls the operation by the first control signal; and a first switched-capacitor boost circuit that operates with a first clock signal output by the first oscillation circuit.

Description

Technical Field

[0001] This invention relates to boost circuits. Background Technology

[0002] Figure 4 A circuit diagram of a boost circuit 400, which is an example of an existing boost circuit, is shown.

[0003] The boost circuit 400 includes an oscillation circuit 401, a PMOS transistor 402, an NMOS transistor 403, diodes 404 and 406, and a capacitor 405. The output terminal of the solar cell 101 is connected to the input terminal of the boost circuit 400. A secondary battery 112 is connected to the output terminal of the boost circuit 400.

[0004] The boost circuit 400 uses the clock signal output by the oscillator circuit 401 to switch the PMOS transistor 402 and NMOS transistor 403 to conduct and cut off (ON / OFF), thereby boosting the input voltage.

[0005] In the boost circuit 400, the voltage output from the solar cell 101 is input to the input terminals of the boost circuit 400. The voltage input to the input terminals of the boost circuit 400 is the input voltage VIN. The input voltage VIN is boosted to approximately twice its original value by the boost circuit 400 and output as voltage VB from the output terminals. The boost circuit 400 supplies voltage VB to the secondary battery 112, thereby charging the secondary battery 112 (for example, see Patent Document 1).

[0006] [Existing Technical Documents]

[0007] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2001-183620. Summary of the Invention

[0009] [The problem the invention aims to solve]

[0010] However, since the oscillation circuit outputs a clock signal at a constant frequency, the power conversion capability of existing boost circuits is constant. Therefore, adjustments to the power conversion capability based on the power generated by solar cells, etc., i.e., the input power, are not considered. Furthermore, existing boost circuits suffer from voltage losses due to diodes, resulting in situations where the input voltage cannot be boosted to twice its original value.

[0011] The present invention was conceived in consideration of the above-mentioned circumstances, and its purpose is to provide a boost circuit that can adjust the power conversion capability according to the input power and can stably perform boost operation.

[0012] [Solutions for solving the problem]

[0013] One embodiment of the boost circuit of the present invention is characterized by comprising: a first voltage detection circuit that outputs a first control signal as a result of comparing an input voltage with a first voltage obtained by dividing the output voltage; a first oscillation circuit that controls operation by the first control signal; and a first switched capacitor boost circuit that operates with a first clock signal output by the first oscillation circuit.

[0014] Furthermore, one embodiment of the boost circuit of the present invention is characterized by comprising: a second voltage detection circuit that outputs a second control signal as a result of comparing the input voltage and a second voltage obtained by dividing the output voltage, wherein the second voltage is lower than the first voltage; a second oscillation circuit that controls its operation by the second control signal; and a second switched-capacitor boost circuit that operates with a second clock signal output by the second oscillation circuit, wherein the second switched-capacitor boost circuit outputs a voltage higher than the output voltage to the substrate of the PMOS transistor of the first switched-capacitor boost circuit for preventing reverse current.

[0015] [Invention Effects]

[0016] The boost circuit of the present invention is configured such that the first oscillation circuit operates according to the first control signal of the first voltage detection circuit, thus effectively boosting the voltage from a state with low input power to a state with high input power. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating a boost circuit according to an embodiment of the present invention.

[0018] Figure 2 This is a circuit diagram showing the first switched capacitor boost circuit of the boost circuit in this embodiment.

[0019] Figure 3 This is a circuit diagram showing the second switched capacitor boost circuit of the boost circuit in this embodiment.

[0020] Figure 4 This is a circuit diagram showing an existing boost circuit. Detailed Implementation

[0021] Figure 1 This is a block diagram illustrating a boost circuit 100 according to an embodiment of the present invention.

[0022] The boost circuit 100 of this embodiment is configured to boost the voltage input from the input terminal by 2 times and output it from the output terminal. A voltage source, such as a solar cell 101, is connected to the input terminal of the boost circuit 100. A secondary battery 112 is connected to the output terminal of the boost circuit 100. The boost circuit 100 receives the output voltage VIN of the solar cell 101 as input and outputs a voltage VB boosted to twice the voltage to the secondary battery 112. In the following description of this embodiment, the input voltage VIN will be set to the output voltage of a 1.5V series solar cell, and the voltage VB will be set to approximately twice the output voltage of the solar cell in its operating state, which will be described later, at 3.0V. For a 1.5V series solar cell with a three-cell structure, the output voltage in the operating state is approximately 1.5V, and the open-circuit voltage in the no-load state is approximately 1.8V.

[0023] The boost circuit 100 includes, for example, a first voltage detection circuit 102, a second voltage detection circuit 103, a first oscillation circuit 104, a second oscillation circuit 108, a delay circuit 105, a first switched capacitor boost circuit 106, a second switched capacitor boost circuit 107, and resistors 109, 110, and 111 constituting a voltage divider circuit.

[0024] The first voltage detection circuit 102 receives the input voltage VIN and the first voltage VREF1 output by the voltage divider circuit, and outputs a first control signal EN1 corresponding to their comparison result. The first voltage VREF1 is, for example, set to be approximately 0.1V added to half the voltage VB, i.e., the voltage of the secondary battery 112. The first control signal EN1 is such that when the input voltage VIN is higher than the first voltage VREF1, the first oscillation circuit 104 is activated, and when the input voltage VIN is lower than the first voltage VREF1, the first oscillation circuit 104 is deactivated.

[0025] The second voltage detection circuit 103 receives the input voltage VIN and the second voltage VREF2 output by the voltage divider circuit, and outputs a second control signal EN2 corresponding to their comparison result. The second voltage VREF2 is set to be lower than the first voltage VREF1. The second control signal EN2 is a signal that causes the second oscillation circuit 108 to operate when the input voltage VIN is higher than the second voltage VREF2, and stops the second oscillation circuit 108 when the input voltage VIN is lower than the second voltage VREF2. Furthermore, the second control signal EN2 is input to the first oscillation circuit 104 as a third control signal EN3 via the delay circuit 105. The third control signal EN3 is a signal that causes the first oscillation circuit 104 to operate when the input voltage VIN is higher than the second voltage VREF2, and stops the first oscillation circuit 104 when the input voltage VIN is lower than the second voltage VREF2. The first oscillation circuit 104 operates when both the first control signal EN1 and the third control signal EN3 are activated. Therefore, due to the third control signal EN3, the first oscillation circuit 104 will necessarily start operating later than the second oscillation circuit 108.

[0026] The operation of the first oscillation circuit 104 is controlled by the first control signal EN1 and the third control signal EN3. Based on the first control signal EN1 and the third control signal EN3, the first oscillation circuit 104 outputs a clock signal CLK1 as the first clock signal. The first switched-capacitor boost circuit 106 outputs a voltage VB that boosts the input voltage VIN to twice its original value according to the clock signal CLK1. Furthermore, the first switched-capacitor boost circuit 106 is input with the boosted voltage V1 output from the second switched-capacitor boost circuit 107 (described later).

[0027] The operation of the second oscillation circuit 108 is controlled by the second control signal EN2. Based on the second control signal EN2, the second oscillation circuit 108 outputs a clock signal CLK2 as a second clock signal.

[0028] The second switched capacitor boost circuit 107 outputs a boost voltage V1 higher than the voltage VB to the first switched capacitor boost circuit 106 according to the clock signal CLK2.

[0029] Figure 2 This is a circuit diagram showing the first switched capacitor boost circuit 106.

[0030] The first switched-capacitor boost circuit 106 includes: an NMOS transistor 201 for preventing reverse current, a PMOS transistor 205 for preventing reverse current, a switching PMOS transistor 202, a switching NMOS transistor 204, a boost capacitor 203, and a level shift circuit 206. The drains of the NMOS transistor 201 and the PMOS transistor 205 are connected to each other.

[0031] The first switched-capacitor boost circuit 106 uses an NMOS transistor 201 and a PMOS transistor 205 to prevent reverse current, thus eliminating voltage loss caused by the boost operation. Here, the drain voltage of the PMOS transistor 205 may exceed the substrate voltage; in this case, there is a concern that the parasitic bipolar transistor might conduct and cause latch-up. Therefore, from the viewpoint of preventing latch-up, the PMOS transistor 205 is configured to input a boost voltage V1 higher than the voltage VB to its substrate. With this structure, the parasitic bipolar transistor in the PMOS transistor 205 will not conduct, thus preventing latch-up.

[0032] Here, the clock signal CLK1 is a signal at the input voltage VIN level. The level shifting circuit 206 is powered by the voltage VB of the secondary battery 112. The level shifting circuit 206 shifts the clock signal CLK1 to a clock signal CLK1A at the voltage VB level.

[0033] Figure 3 This is a circuit diagram showing the second switched capacitor boost circuit 107.

[0034] The second switched capacitor boost circuit 107 includes: an NMOS transistor 301 for preventing reverse current, a depletion-type NMOS transistor 305 for preventing reverse current, a PMOS transistor 302 for switching, an NMOS transistor 304 for switching, a capacitor 303 for boosting voltage, a capacitor 306 for coupling, and a resistor 307.

[0035] The second switched-capacitor boost circuit 107 outputs a boost voltage V1 higher than VB by connecting the input voltage VIN in series with a capacitor 303 charged to voltage VB. A depletion-type NMOS transistor 305 is used as the switch for controlling the charging of capacitor 303. The gate of the NMOS transistor 305 is biased to voltage VB via resistor 307. Furthermore, a clock signal CLK2 is input to the gate of the NMOS transistor 305 via capacitor 306. Here, the clock signal CLK2 is a signal at the level of the input voltage VIN. The second switched-capacitor boost circuit 107 configured in this way can output a boost voltage V1 higher than VB. The boost voltage V1 is the voltage obtained by subtracting the threshold voltage of the NMOS transistor 301 from the voltage 3V added to the input voltage VIN.

[0036] Next, the operation of the boost circuit 100 configured as described above will be explained.

[0037] When the first switched-capacitor boost circuit 106 is charging the capacitor 203 used for boosting voltage, NMOS transistors 201 and 204 are turned on, while PMOS transistors 202 and 205 are turned off. During the charging of capacitor 203, the input voltage VIN becomes below the first voltage VREF1, therefore the first voltage detection circuit 102 outputs a first control signal EN1 that stops the first oscillation circuit 104.

[0038] If capacitor 203 is charged and the input voltage VIN is higher than the first voltage VREF1, the first voltage detection circuit 102 outputs a first control signal EN1 to activate the first oscillation circuit 104. If the first oscillation circuit 104 activates, the clock signal CLK1 is output to the first switched capacitor boost circuit 106. Then, NMOS transistors 201 and 204 are turned off, while PMOS transistors 202 and 205 are turned on, resulting in an output voltage VB. Furthermore, when the level of the clock signal CLK1 is reversed, NMOS transistors 201 and 204 are turned on, while PMOS transistors 202 and 205 are turned off. That is, capacitor 203 transitions to a charging state. In the charging state of capacitor 203, as described above, the first voltage detection circuit 102 outputs a first control signal EN1 to stop the first oscillation circuit 104.

[0039] The first switched capacitor boost circuit 106 repeats the above operation, thereby boosting the 1.5V input voltage VIN to a 3.0V voltage VB and outputting it from the output terminal.

[0040] The boost circuit 100 includes a first switched-capacitor boost circuit 106 configured such that when the power generated by the solar cell 101 is high, the charging period of the capacitor 203 is shortened, and therefore the switching frequency of the first switched-capacitor boost circuit 106 is increased. This reduces the operating time of the first oscillation circuit 104, i.e., the consumption (loss) of the power generated by the solar cell 101. Therefore, the boost circuit 100 can effectively boost the power generated by the solar cell 101. Furthermore, when the power generated by the solar cell 101 is low, the charging period of the capacitor 203 is longer, but since the first oscillation circuit 104 stops during this period, the boost circuit 100 is in a low-current consumption state, thus preventing the unnecessary consumption of the power generated by the solar cell 101.

[0041] Furthermore, the second oscillation circuit 108 starts operating with a second control signal EN2 corresponding to the comparison result between the second voltage VREF2 and the input voltage VIN. Therefore, the second switched-capacitor boost circuit 107 can output a boost voltage V1 before the first switched-capacitor boost circuit 106 starts operating. Furthermore, the second control signal EN2 is input to the first oscillation circuit 104 as a third control signal EN3 via the delay circuit 105, so the second switched-capacitor boost circuit 107 can output a boost voltage V1 before the first switched-capacitor boost circuit 106 starts operating. That is, the parasitic bipolar transistor of the first switched-capacitor boost circuit 106 will not conduct, thus preventing latch-up.

[0042] As explained above, the boost circuit 100 is configured to cause the first oscillation circuit 104 to operate according to the control signal of the first voltage detection circuit 102, thus enabling efficient voltage boosting from a state with low power generation to a state with high power generation. That is, it can effectively charge the power generated by a 1.5V series solar cell to a 3V series secondary battery. Furthermore, the PMOS transistor 205, which is configured to prevent reverse current, is configured to apply a voltage higher than voltage VB to its substrate, thus enabling stable voltage boosting without latch-up. In the boost circuit 100, which connects the illustrated solar cell 101 and secondary battery 112 respectively, it can stably output a voltage VB that boosts the 1.5V input voltage VIN to twice the input voltage VIN, i.e., 3.0V.

[0043] The embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the structure of the boost circuit 100 is not limited to... Figure 1 The structure is illustrated in the diagram. The boost circuit 100 may include at least a first voltage detection circuit 102, a first oscillation circuit 104, and a first switched capacitor boost circuit 106. That is, it may also be configured as a boost circuit 100 without the second voltage detection circuit 103, the delay circuit 105, the second switched capacitor boost circuit 107, and the second oscillation circuit 108.

[0044] [Label Explanation]

[0045] 100 Boost circuit; 102 First voltage detection circuit; 103 Second voltage detection circuit; 104 First oscillation circuit; 108 Second oscillation circuit; 106 First switched capacitor boost circuit; 107 Second switched capacitor boost circuit.

Claims

1. A boost circuit, characterized in that, have: The first voltage detection circuit outputs a first control signal by comparing the input voltage with the first voltage obtained by dividing the output voltage. The first oscillation circuit controls its operation through the first control signal; The first switched capacitor boost circuit operates with the first clock signal output by the first oscillation circuit. The second voltage detection circuit outputs a second control signal as the result of comparing the input voltage with the second voltage obtained by dividing the output voltage, wherein the voltage of the second voltage is lower than the first voltage. The second oscillation circuit controls its operation via the second control signal; and The second switched-capacitor boost circuit operates based on the second clock signal output by the second oscillation circuit. The second switched capacitor boost circuit outputs a voltage higher than the output voltage to the substrate of the PMOS transistor in the first switched capacitor boost circuit, which is used to prevent reverse current.

Images