Transimpedance amplifier circuit

Abstract

The present invention provides a transimpedance amplifier circuit. In the transimpedance amplifier circuit, a transconductance amplifier circuit generates a control current based on the differential integral signal via a first transconductance when the value of the differential integral signal is less than a threshold value, and generates a control current based on the differential integral signal via a second transconductance that is larger than the first transconductance when the value of the differential integral signal is greater than the threshold value. The control circuit controls a feedback current source such that a DC bypass current increases as the control current increases, and controls a variable resistance circuit such that an AC bypass current increases as the control current exceeds a bias current value.

Description

Technical Field

[0001] The present disclosure relates to a transimpedance amplifier circuit.

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2019-140075, Japanese Patent Application No. 2019-140077, and Japanese Patent Application No. 2019-140082, filed on July 30, 2019, and incorporates by reference all the contents disclosed in these Japanese patent applications. Background Art

[0003] In EPON (Ethernet (registered trademark) Passive Optical Network), which is an optical access system, a transimpedance amplifier circuit is used in the optical receiver of the central office device (OLT: Optical Line Terminal). The optical receiver of the OLT uses time division multiplexing (TDM) to receive burst optical signals from multiple home-side devices (ONU: Optical Network Unit). The transmission line loss from each ONU to the OLT varies depending on the distance from the OLT. Therefore, the signal strength from the ONU located closer to the OLT increases, and the signal strength from the ONU located farther from the OLT decreases. In this way, burst optical signals of various signal strengths are input to the optical receiver of the OLT. Therefore, the transimpedance amplifier circuit included in the optical receiver of the OLT has a feedback control circuit that extracts a bypass current from the current signal corresponding to the burst optical signal in order to be able to receive burst optical signals of various signal strengths (for example, refer to Japanese Patent Publication No. 2012-10107).

[0004] Japanese Patent Application Laid-Open No. 2012-10107 describes an amplifier circuit comprising an amplifier that converts an input current into an output voltage, a differential amplifier that converts the output voltage into a differential output signal, and a bypass circuit that extracts a bypass current from the photocurrent generated by a photodiode. This amplifier circuit has the following functions: During the initial phase of a burst signal (preamble), the time constant of the feedback control circuit is set to a small value to quickly activate automatic gain control; during the payload of the burst signal, the time constant of the feedback control circuit is set to a large value to improve robustness against continuous signals of the same symbol.

[0005] However, in the amplifier circuit described in Japanese Patent Application Publication No. 2012-10107, the forward voltage of the diode is controlled by an emitter follower circuit provided in the output portion of the bypass circuit, so the output voltage of the emitter follower circuit is divided and fed back by the on-resistance of the diode and the input impedance of the amplifier. Depending on the signal level (signal strength) of the burst optical signal, the on-resistance of the diode may change, so the time constant of the feedback control depends on the signal strength of the burst optical signal. For example, when a large signal with a large signal strength is input, the on-resistance of the diode decreases, so the open-loop transfer gain increases and the time constant of the feedback control decreases. It is expected that the time constant of the feedback control remains constant regardless of the signal strength of the burst optical signal. Summary of the Invention

[0006] In the present disclosure, a transimpedance amplifier circuit is described that can suppress variations in a control time constant caused by variations in the signal strength of a burst optical signal.

[0007] A transimpedance amplifier circuit according to one embodiment of the present disclosure is a circuit that generates a differential voltage signal based on an input current signal generated by a light-receiving element. The transimpedance amplifier circuit includes: an input terminal that receives an input current signal; a single-input amplifier circuit that converts the current signal into a voltage signal; a differential amplifier circuit that generates a differential voltage signal based on the difference between the voltage signal and a reference voltage signal; a control current generating circuit that generates a control current based on the difference; and a bypass circuit that generates a DC bypass current and an AC bypass current based on the control current. The current signal is generated by extracting the DC bypass current and the AC bypass current from the input current signal. The bypass circuit includes: a control circuit to which the control current is input; a feedback current source that generates a DC bypass current based on the control current; and a variable resistance circuit that generates an AC bypass current based on the control current. The control current generation circuit includes an integration circuit that integrates a difference to generate a differential integration signal; and a transconductance amplifier circuit that generates a control current based on the differential integration signal using a first transconductance when the value of the differential integration signal is less than a threshold value, and generates a control current based on the differential integration signal using a second transconductance that is larger than the first transconductance when the value of the differential integration signal is greater than the threshold value. The control circuit controls the feedback current source so that the DC bypass current increases as the control current increases, and controls the variable resistor circuit so that the AC bypass current increases as the control current exceeds a predetermined bias current value.

[0008] According to the present disclosure, it is possible to suppress fluctuations in the control time constant caused by changes in the signal intensity of the burst optical signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1This is a diagram schematically showing the configuration of an optical receiving device including a transimpedance amplifier circuit according to one embodiment.

[0010] Figure 2 Yes Figure 1 FIG. 1 is a diagram showing an example of a circuit configuration of an integrating circuit.

[0011] Figure 3 Yes Figure 2 Graph showing an example of DC (Direct Current) input-output characteristics of an integrating circuit.

[0012] Figure 4 It is a rough representation Figure 1 Figure 1 shows the structure of the OTA.

[0013] Figure 5 It is a rough representation Figure 1 The diagram shows the input-output current characteristics of the OTA.

[0014] Figure 6 Yes Figure 1 The graph of the transconductance characteristics of the OTA is shown.

[0015] Figure 7 Yes Figure 4 The diagram shows an example of the circuit structure of an OTA.

[0016] Figure 8 It means to Figure 1 Graph showing the relationship between the control current supplied by the control circuit and the current generated by the control circuit.

[0017] Figure 9 Yes Figure 1 FIG. 1 is a diagram showing an example of a circuit configuration of a control circuit.

[0018] Figure 10 Yes Figure 1 The diagram shows the DC bias characteristics and gain characteristics of the transimpedance amplifier circuit.

[0019] Figure 11A Yes Figure 1 A graph of the open-loop transfer function of the control loop in the transimpedance amplifier circuit shown.

[0020] Figure 11B Yes Figure 1 The closed-loop frequency characteristics of the transimpedance amplifier circuit are shown in FIG.

[0021] Figure 12A Graph showing an open-loop transfer function of a control loop in the transimpedance amplifier circuit of the first comparative example.

[0022] Figure 12BGraphs showing closed-loop frequency characteristics in the transimpedance amplifier circuit of the first comparative example.

[0023] Figure 13 This is a graph showing changes in transimpedance gain and low-frequency cutoff frequency relative to the optical input level.

[0024] Figure 14 This is a diagram showing changes in the control time constant relative to the light input level.

[0025] Figure 15 Yes Figure 1 A diagram showing the responses of each node in the optical receiving device.

[0026] Figure 16 This is a diagram schematically showing the configuration of an optical receiving device including a transimpedance amplifier circuit according to another embodiment.

[0027] Figure 17 Is used to illustrate Figure 16 A diagram showing the inter-terminal capacitance of a field effect transistor.

[0028] Figure 18 Yes Figure 17 The diagram shows an example of capacitance values ​​of the inter-terminal capacitance.

[0029] Figure 19A Yes Figure 16 A graph showing changes in total harmonic distortion relative to the average power of input light in the transimpedance amplifier circuit shown.

[0030] Figure 19B Yes Figure 16 Graph showing changes in the output amplitude of the TIA section relative to the average power of input light in the transimpedance amplifier circuit shown.

[0031] Figure 19C Yes Figure 16 Graph showing changes in amplitude at each terminal of a field effect transistor relative to the average power of input light in the transimpedance amplifier circuit shown.

[0032] Figure 20A Graphs showing changes in total harmonic distortion with respect to input light average power in a transimpedance amplifier circuit according to a second comparative example.

[0033] Figure 20B Graphs showing changes in the output amplitude of the TIA section relative to the average power of input light in the transimpedance amplifier circuit of the second comparative example.

[0034] Figure 20C Graphs showing changes in amplitude at each terminal of a field-effect transistor relative to the average power of input light in a transimpedance amplifier circuit according to the second comparative example.

[0035] Figure 21 This is a diagram schematically showing the configuration of an optical receiving device including a transimpedance amplifier circuit according to still another embodiment.

[0036] Figure 22 It means to Figure 21 Graph showing the relationship between the control current supplied by the control circuit and the current generated by the control circuit.

[0037] Figure 23 Yes Figure 21 FIG. 1 is a diagram showing an example of a circuit configuration of a control circuit.

[0038] Figure 24A Yes Figure 21 A graph showing changes in total harmonic distortion relative to the average power of input light in the transimpedance amplifier circuit shown.

[0039] Figure 24B Yes Figure 21 Graph showing changes in the output amplitude of the TIA section relative to the average power of input light in the transimpedance amplifier circuit shown.

[0040] Figure 25A Graphs showing changes in total harmonic distortion with respect to input light average power in the transimpedance amplifier circuit of the third comparative example.

[0041] Figure 25B Graphs showing changes in the output amplitude of the TIA portion relative to the average power of input light in the transimpedance amplifier circuit of the third comparative example. DETAILED DESCRIPTION

[0042] [Description of Embodiments of the Present Disclosure]

[0043] First, the contents of the embodiments of the present disclosure are listed and described.

[0044] A transimpedance amplifier circuit according to one embodiment of the present disclosure is a circuit that generates a differential voltage signal based on an input current signal generated by a light-receiving element. The transimpedance amplifier circuit includes: an input terminal that receives an input current signal; a single-input amplifier circuit that converts the current signal into a voltage signal; a differential amplifier circuit that generates a differential voltage signal based on the difference between the voltage signal and a reference voltage signal; a control current generating circuit that generates a control current based on the difference; and a bypass circuit that generates a DC bypass current and an AC bypass current based on the control current. The current signal is generated by extracting the DC bypass current and the AC bypass current from the input current signal. The bypass circuit includes: a control circuit to which the control current is input; a feedback current source that generates a DC bypass current based on the control current; and a variable resistance circuit that generates an AC bypass current based on the control current. The control current generation circuit includes an integration circuit that integrates a difference to generate a differential integration signal; and a transconductance amplifier circuit that generates a control current based on the differential integration signal using a first transconductance when the value of the differential integration signal is less than a threshold value, and generates a control current based on the differential integration signal using a second transconductance that is larger than the first transconductance when the value of the differential integration signal is greater than the threshold value. The control circuit controls the feedback current source so that the DC bypass current increases as the control current increases, and controls the variable resistor circuit so that the AC bypass current increases as the control current exceeds a predetermined bias current value.

[0045] This transimpedance amplifier circuit integrates the difference between a voltage signal and a reference voltage signal to generate a differential integrated signal. When the differential integrated signal is less than a threshold value, a control current is generated based on the differential integrated signal using a first transconductance. When the differential integrated signal is greater than the threshold value, a control current is generated based on the differential integrated signal using a second transconductance, which is larger than the first transconductance. Until the control current exceeds the bias current value, no AC bypass current is drawn, so the resistance value of the variable resistor circuit does not change. On the other hand, when the control current exceeds the bias current value, the variable resistor circuit is controlled so that the AC bypass current increases as the control current increases, thereby decreasing the resistance value of the variable resistor circuit. In the control current generation circuit, when the differential integrated signal exceeds the threshold value, the second transconductance, which is larger than the first transconductance, is used. This allows the increase in the transconductance of the control current generation circuit to compensate for the decrease in the resistance value of the variable resistor circuit. This suppresses the increase in the control time constant of the feedback control. Consequently, it is possible to suppress fluctuations in the control time constant caused by changes in the signal strength of the burst optical signal.

[0046] A transconductance amplifier circuit may include: a first transconductance circuit that generates a first output current based on a differential integrated signal; and a second transconductance circuit that generates a second output current based on the differential integrated signal. The transconductance amplifier circuit may generate a control current by adding the first output current to the second output current. The first transconductance circuit may operate such that the first output current decreases as the value of the differential integrated signal increases within a first range of differential integrated signal values. The second transconductance circuit may operate such that the second output current increases as the value of the differential integrated signal increases within a second range of differential integrated signal values. The upper limit of the second range may be lower than the upper limit of the first range, and the lower limit of the second range may be higher than the lower limit of the first range. In this case, the control current is generated by adding the first output current, which decreases as the value of the differential integrated signal increases within the first range, and the second output current, which increases as the value of the differential integrated signal increases within the second range. This simplifies the generation of the control current.

[0047] The integration circuit may include: a first output terminal for outputting the inverting component of the differential integrated signal; a second output terminal for outputting the non-inverting component of the differential integrated signal; and a diode disposed between the first and second output terminals. The differential may be the value obtained by subtracting the voltage signal from the reference voltage signal. The anode of the diode may be electrically connected to the first output terminal. The cathode of the diode may be electrically connected to the second output terminal. In the absence of a burst optical signal, the voltage signal may sometimes exceed the reference voltage signal due to, for example, variations in the characteristics of a single-input amplifier circuit. The feedback current source directs a DC bypass current in a direction drawn from the input current signal. Therefore, for example, when the voltage signal exceeds the reference voltage signal, the differential cannot be brought close to zero. In contrast, by electrically connecting the anode of the diode to the first output terminal and the cathode of the diode to the second output terminal, when the value obtained by subtracting the voltage signal from the reference voltage signal is negative, the absolute value of the value can be prevented from exceeding the diode's forward voltage. This can shorten the response time when a burst optical signal is input.

[0048] The control circuit can generate the first control current by amplifying the control current at a first amplification factor. The feedback current source can include: a first field-effect transistor having a first drain that receives the first control current, a first gate electrically connected to the first drain, and a first source electrically connected to a ground potential; and a second field-effect transistor having a second drain electrically connected to the input terminal, a second gate electrically connected to the first drain and the first gate, and a second source electrically connected to the first source. The feedback current source can cause a DC bypass current to flow from the second drain to the second source in response to the first control current. In this case, the first field-effect transistor is diode-connected, so when the first drain of the first field-effect transistor receives the first control current, a gate-source voltage is generated between the first gate and the first source. The first gate and the second gate are electrically connected to each other, and the first source and the second source are electrically connected to each other, so that the gate-source voltage of the second field-effect transistor becomes equal to the gate-source voltage of the first field-effect transistor. In the second field-effect transistor, the second source is electrically connected to the first source, i.e., the ground potential, and the second drain is electrically connected to the input terminal, so that the potential difference between the second source and the second drain increases. As a result, the second field-effect transistor operates in the saturation region. Therefore, the second field-effect transistor acts as a current source, and the output impedance of the second drain increases. Therefore, the AC component of the input current signal hardly flows into the second field-effect transistor, but the DC component of the input current signal may flow into the second field-effect transistor as a DC bypass current. In addition, as the control current increases, the gate-source voltage of the first field-effect transistor increases, so the DC component of the input current signal is extracted from the input current signal as a DC bypass current, and the DC component is appropriately removed from the input current signal.

[0049] The control circuit can generate a bias current set to a bias current value, and can amplify a difference current between a current generated by amplifying the control current and the bias current at a second amplification factor to generate a second control current. The variable resistor circuit can include: a third field-effect transistor having a third drain receiving the second control current, a third gate electrically connected to the third drain, and a third source supplied with a reference voltage signal; and a fourth field-effect transistor having a fourth drain electrically connected to the input terminal, a fourth gate electrically connected to the third drain and the third gate, and a fourth source electrically connected to the third source. The variable resistor circuit can extract an AC bypass current from the input current signal in response to the second control current. In this case, the third field-effect transistor is diode-connected, so when the third drain of the third field-effect transistor receives the second control current, a gate-source voltage is generated between the third gate and the third source. The third gate and the fourth gate are electrically connected to each other, and the reference voltage signal is supplied to the third source and the fourth source, so that the gate-source voltage of the fourth field-effect transistor becomes equal to the gate-source voltage of the third field-effect transistor. In the fourth field-effect transistor, a reference voltage signal is supplied to the fourth source, and the fourth drain is electrically connected to the input terminal, so there is almost no potential difference between the fourth drain and the fourth source. As a result, the fourth field-effect transistor operates within the (deeper) triode region (linear region). Therefore, the fourth field-effect transistor functions as a variable resistor, and the output impedance of the fourth drain becomes low. Since there is almost no potential difference between the fourth drain and the fourth source, the DC component of the input current signal hardly flows into the fourth field-effect transistor, but the AC component of the input current signal may flow into the fourth field-effect transistor as an AC bypass current. Furthermore, when the control current exceeds a predetermined bias current value, the gate-source voltage of the third field-effect transistor increases as the control current increases. Therefore, when the input current signal is relatively small, the extraction of the AC bypass current is suppressed, thereby avoiding attenuation of the AC component. When the input current signal is relatively large, the AC component of the input current signal is extracted from the input current signal as an AC bypass current, thereby attenuating the AC component of the input current signal. Therefore, the gain of the transimpedance amplifier is appropriately controlled by the variable resistance circuit.

[0050] The variable resistor circuit may further include a first resistor element. The third field-effect transistor may further include a first substrate terminal to which a reference voltage signal is supplied. The fourth field-effect transistor may further include a second substrate terminal to which a reference voltage signal is supplied. The fourth gate may be electrically connected to the third drain and the third gate via the first resistor element. The fourth field-effect transistor may be configured such that a first capacitance between the fourth gate and the fourth drain and a second capacitance between the fourth gate and the fourth source are equal to each other. The resistance value of the first resistor element may be greater than the impedance based on the first capacitance. In this structure, the fourth gate of the fourth field-effect transistor is electrically connected to the third gate of the third field-effect transistor via the first resistor element, and the third field-effect transistor is diode-connected. Therefore, the fourth gate is connected to the reference voltage signal via the first resistor element and the differential resistance of the third field-effect transistor. However, the resistance value of the first resistor element is greater than the impedance formed by the first capacitance between the fourth gate and the fourth drain, so the fourth gate and the third gate can be separated (insulated) at high frequency by the first resistor element. Therefore, the voltage between the fourth drain and the fourth source is divided by the first capacitor between the fourth gate and the fourth drain and the second capacitor between the fourth gate and the fourth source, and applied to the fourth gate. The fourth field-effect transistor is configured so that the first and second capacitors are equal, so a voltage approximately half the voltage between the fourth drain and the fourth source is applied to the fourth gate. This suppresses fluctuations in the differential resistance of the fourth field-effect transistor due to the voltage between the fourth drain and the fourth source. As a result, distortion is suppressed, thereby improving signal quality.

[0051] The variable resistor circuit may further include a second resistor element. A reference voltage signal may be supplied to the second substrate terminal via the second resistor element. The fourth field-effect transistor may be configured such that the third capacitance between the second substrate terminal and the fourth drain and the fourth capacitance between the second substrate terminal and the fourth source are equal to each other. The resistance value of the second resistor element may be greater than the impedance formed by the third capacitance. The second substrate terminal is electrically connected to the fourth gate via the inter-terminal capacitance, so the potential of the second substrate terminal may affect the fourth gate potential via the inter-terminal capacitance. In contrast, the reference voltage signal is supplied to the second substrate terminal via the second resistor element, and the resistance value of the second resistor element is greater than the impedance formed by the third capacitance. Therefore, the second substrate terminal can be isolated (insulated) from the outside of the fourth field-effect transistor at high frequency by the second resistor element. The fourth field-effect transistor is configured such that the third capacitance between the second substrate terminal and the fourth drain and the fourth capacitance between the second substrate terminal and the fourth source are equal to each other, so a voltage of half the voltage between the fourth drain and the fourth source is applied to the second substrate terminal. As a result, the potential of the second substrate terminal is the same as the fourth gate potential, thereby reducing the influence of the potential of the second substrate terminal on the fourth gate potential. As a result, the occurrence of distortion is further suppressed, and thus the signal quality can be further improved.

[0052] The bypass circuit may also generate another AC bypass current. The current signal may be generated by extracting another AC bypass current from the input current signal. The bypass circuit may further include another variable resistance circuit that generates another AC bypass current based on the control current. The control circuit may generate a third control current by amplifying the differential current at a second amplification factor. The other variable resistance circuit may include: a fifth field-effect transistor having a fifth drain that receives the third control current, a fifth gate electrically connected to the fifth drain, and a fifth source electrically connected to the input terminal; and a sixth field-effect transistor having a sixth drain that receives a reference voltage signal, a sixth gate electrically connected to the fifth drain and the fifth gate, and a sixth source electrically connected to the fifth source. The other variable resistance circuit may extract another AC bypass current from the input current signal based on the third control current. In this configuration, the differential resistance of the fourth field-effect transistor of the variable resistance circuit and the sixth field-effect transistor of the other variable resistance circuit each includes a component of the drain-source voltage and may therefore vary depending on the drain-source voltage. In the fourth field-effect transistor, a reference voltage signal is supplied to the fourth source, and the fourth drain is electrically connected to the input terminal. In contrast, in the sixth field-effect transistor, a reference voltage signal is supplied to the sixth drain, and the sixth source is electrically connected to the input terminal. Therefore, the polarity of the voltage between the fourth drain and the fourth source and the polarity of the voltage between the sixth drain and the sixth source are opposite to each other. Therefore, in the combined resistance formed by the variable resistance circuit and the other variable resistance circuit as viewed from the input terminal, the component of the voltage between the fourth drain and the fourth source and the component of the voltage between the sixth drain and the sixth source cancel each other out. Thus, the combined resistance of the variable resistance circuit and the other variable resistance circuit is suppressed from changing due to the voltage between the fourth drain and the fourth source and the voltage between the sixth drain and the sixth source. As a result, the occurrence of distortion is suppressed, thereby improving signal quality.

[0053] The DC bypass current can be set to include a third control current flowing from another variable resistor circuit. In the other variable resistor circuit, the third control current flows from the fifth drain to the fifth source of the fifth field-effect transistor. Since the fifth source is electrically connected to the input terminal, the third control current flows toward the input terminal, increasing the DC component of the input current signal. By setting the DC bypass current to include the third control current, the DC component based on the third control current can be removed from the input current signal.

[0054] The transimpedance amplifier circuit may further include a reference voltage generation circuit that generates a reference voltage signal. The reference voltage generation circuit may include an amplifier and a feedback resistor element electrically connected between the amplifier's input and output. In this case, the output impedance of the reference voltage generation circuit is low over a wide frequency range. In other words, the impedance of the variable resistor circuit as viewed from the input terminal of the single-input amplifier circuit is low over a wide frequency range. This makes it easier to extract an AC bypass current from the input current signal.

[0055] [Details of the embodiments of the present disclosure]

[0056] Specific examples of transimpedance amplifier circuits according to embodiments of the present disclosure are described below with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is defined by the claims and is intended to encompass all modifications within the meaning and scope of the claims.

[0057] Figure 1 This is a diagram schematically showing the configuration of an optical receiving device including a transimpedance amplifier circuit according to one embodiment. Figure 2 Yes Figure 1 FIG. 1 is a diagram showing an example of a circuit configuration of an integrating circuit. Figure 3 Yes Figure 2 Graph showing an example of DC input-output characteristics of an integrating circuit. Figure 4 It is a rough representation Figure 1 Figure 1 shows the structure of the OTA. Figure 5 Yes Figure 1 The diagram shows the input-output current characteristics of the OTA. Figure 6 Yes Figure 1 The graph of the transconductance characteristics of the OTA is shown. Figure 7 Yes Figure 4 The diagram shows an example of the circuit structure of an OTA. Figure 8 It means to Figure 1 Graph showing the relationship between the control current supplied by the control circuit and the current generated by the control circuit. Figure 9 Yes Figure 1 FIG. 1 is a diagram showing an example of a circuit configuration of a control circuit.

[0058] Figure 1The optical receiving device 1A shown receives an optical signal Pin sent from an optical transmitting device not shown. The optical receiving device 1A includes a light receiving element PD, a transimpedance amplifier circuit 10A, and a signal processing circuit 20. The optical receiving device 1A can be, for example, a receiving unit of an OLT. The light receiving element PD receives the optical signal Pin and generates a photocurrent (Photocurrent) Ipd (input current signal) corresponding to the optical signal Pin. The optical signal Pin is, for example, a burst optical signal. The photocurrent Ipd may include an alternating current component (AC (Alternating Current: alternating current) component) corresponding to the modulated signal and a direct current component (DC component) overlapping with the AC component. When the signal intensity (optical power) of the optical signal Pin increases, the AC component and DC component of the photocurrent Ipd increase, and when the signal intensity (optical power) of the optical signal Pin decreases, the AC component and DC component of the photocurrent Ipd decrease. Examples of the light receiving element PD include photodiodes and avalanche photodiodes. One terminal (e.g., cathode) of the photosensitive element PD is electrically connected to a predetermined bias voltage VPD, and the other terminal (e.g., anode) of the photosensitive element PD outputs a photocurrent Ipd. Usually, the photodiode is biased in the reverse direction for use. It should be noted that "electrically connected" (be electrically coupled) here means that, for example, the cathode of the photosensitive element PD is connected to the circuit that generates the bias voltage VPD via wire bonding, and the two electrically connected elements are connected in a state in which signal transmission, current and voltage supply can be performed. Therefore, "electrically connected" may include both direct connection through wiring and indirect connection via other electrical components. "Electrically connected" is also used in the same sense in the following description.

[0059] The transimpedance amplifier circuit 10A receives the photocurrent Ipd generated by the light-receiving element PD based on the optical signal Pin and generates differential voltage signals Vout and Voutb as voltage signals based on the photocurrent Ipd. The differential voltage signals Vout and Voutb are a pair of complementary signals. The transimpedance amplifier circuit 10A includes, for example, an input terminal 10a and output terminals 10b and 10c. The photocurrent Ipd is input to the input terminal 10a. The output terminal 10b outputs the positive-phase component Vout to the outside of the transimpedance amplifier circuit 10A. The output terminal 10c outputs the negative-phase component Vout to the outside of the transimpedance amplifier circuit 10A. For example, when the transimpedance amplifier circuit 10A is manufactured as a semiconductor integrated device (e.g., a semiconductor chip) using a semiconductor process, the input terminal 10a can be a bonding pad formed on the semiconductor chip. When the semiconductor chip forming the transimpedance amplifier circuit 10A is mounted in a package, the input terminal 10a can be an electrical terminal provided on the outer surface of the package. As with input terminal 10a, output terminals 10b and 10c may be bonding pads formed on a semiconductor chip or electrical terminals provided on the outer surface of a package. In other words, as an embodiment, transimpedance amplifier circuit 10A may be formed on a single semiconductor chip or mounted within a single package or on a substrate.

[0060] Output terminals 10b and 10c are electrically connected to the signal processing circuit 20 via capacitors 5a and 5b, respectively. Capacitors 5a and 5b are AC coupling capacitors. Capacitors 5a and 5b remove the DC component of the differential voltage signals Vout and Voutb in the transimpedance amplifier circuit 10A. By removing the DC component from the differential voltage signals Vout and Voutb, differential voltage signals Vc and Vcb are generated and supplied to the signal processing circuit 20. For example, the differential voltage signals Vc and Vcb are a pair of complementary signals. The positive-phase component Vc (positive-phase signal) of the differential voltage signals Vc and Vcb has a phase difference of 180° from the negative-phase component Vcb (negative-phase signal) of the differential voltage signals Vc and Vcb. For example, when the positive-phase signal Vc increases, the negative-phase signal Vcb decreases, and when the positive-phase signal Vc decreases, the negative-phase signal Vcb increases. When the positive-phase signal Vc reaches its maximum value (peak), the negative-phase signal Vcb reaches its minimum value (valley), and when the positive-phase signal Vc reaches its valley, the negative-phase signal Vcb reaches its peak. The positive-phase signal Vc and the negative-phase signal Vcb can have the same amplitude and the same time-averaged value. For example, assuming the output impedance of the transimpedance amplifier circuit 10A (output amplifier 13b described later) is a differential 100Ω, the input impedance of the signal processing circuit 20 is a differential 100Ω, and the capacitance values ​​of capacitors 5a and 5b are 1000pF, a time constant of 100nsec is generated by capacitors 5a and 5b in the input of the differential voltage signals Vc and Vcb to the signal processing circuit 20.

[0061] The transimpedance amplifier circuit 10A includes a TIA (Trans Impedance Amplifier) ​​section 11 (single-input amplifier circuit), a reference voltage generation circuit 12 , a differential amplifier circuit 13A, a control current generation circuit 14A, and a bypass circuit 15 .

[0062] The TIA unit 11 is a circuit that converts the current signal Iin into a voltage signal Vtia. Specifically, the TIA unit 11 includes a voltage amplifier 11a and a feedback resistor element 11b. The input terminal and the output terminal of the voltage amplifier 11a are electrically connected via the feedback resistor element 11b. That is, the feedback resistor element 11b is electrically connected between the input and the output of the voltage amplifier 11a. The current signal Iin is generated by extracting a DC bypass current Iaoc and an AC bypass current Iagc1 (a first AC bypass current) from the photocurrent Ipd. The DC bypass current Iaoc and the AC bypass current Iagc1 are controlled by the bypass circuit 15, and the details will be described later. The increase and decrease of the voltage signal Vtia are reversed relative to the increase and decrease of the current signal Iin. For example, when the magnitude of the current signal Iin increases, the voltage value of the voltage signal Vtia decreases (drops). The voltage amplifier 11a is, for example, an inverting amplifier circuit. The TIA unit 11 outputs the voltage signal Vtia to the differential amplifier circuit 13A and the control current generation circuit 14A. The gain of the TIA unit 11 (the ratio of the change in the voltage signal Vtia to the change in the current signal Iin) is determined by the resistance value (transimpedance) of the feedback resistor element 11b. The input impedance of the TIA unit 11 is, for example, approximately 10 to 100Ω.

[0063] The reference voltage generation circuit 12 is a circuit that generates a DC voltage signal, namely a reference voltage signal Vref. The reference voltage generation circuit 12 supplies the reference voltage signal Vref to the differential amplifier circuit 13A, the control current generation circuit 14A, and the bypass circuit 15. The reference voltage signal Vref has, for example, a predetermined voltage value (fixed value). The reference voltage generation circuit 12 can be configured so that the output impedance of the terminal supplying the reference voltage signal Vref is low impedance across a wide bandwidth. In this embodiment, the reference voltage generation circuit 12 includes, for example, a voltage amplifier 12a (amplifier) ​​and a feedback resistor element 12b, and is a virtual TIA having the same circuit structure as the TIA unit 11. Specifically, the input terminal and output terminal of the voltage amplifier 12a are electrically connected via the feedback resistor element 12b. In other words, the feedback resistor element 12b is electrically connected between the input and output of the voltage amplifier 12a. Since the reference voltage generation circuit 12 has the same circuit configuration as the TIA unit 11 , it can generate the reference voltage signal Vref so as to compensate (cancel) changes in the voltage signal Vtia caused by changes in the power supply voltage and temperature of the voltage amplifier 11 a .

[0064] The differential amplifier circuit 13A generates differential voltage signals Vout and Voutb based on the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref. In other words, the differential amplifier circuit 13A uses the reference voltage signal Vref to convert a single (single-phase) voltage signal Vtia into differential voltage signals Vout and Voutb. The differential amplifier circuit 13A includes, for example, a differential amplifier 13a and an output amplifier 13b. For example, when the differential amplifier 13a is an inverting amplifier and the output amplifier 13b is a non-inverting amplifier, the differential amplifier circuit 13A performs inverting amplification. For example, when the voltage value of the voltage signal Vtia is greater than the voltage value of the reference voltage signal Vref, the voltage value of the positive-phase component Vout of the differential voltage signals Vout and Voutb is smaller than the voltage value of the negative-phase component Voutb of the differential voltage signals Vout and Voutb. When the voltage value of the voltage signal Vtia is smaller than the voltage value of the reference voltage signal Vref, the voltage value of the positive phase component Vout of the differential voltage signals Vout, Voutb is larger than the voltage value of the negative phase component Voutb of the differential voltage signals Vout, Voutb.

[0065] The differential amplifier 13a amplifies the differential ΔVtia to generate differential voltage signals Va1 and Va1b. The differential amplifier 13a outputs the differential voltage signals Va1 and Va1b to the output amplifier 13b. The output amplifier 13b is a circuit that amplifies the differential voltage signals Va1 and Va1b. The output amplifier 13b amplifies the differential voltage signals Va1 and Va1b to generate differential voltage signals Vout and Voutb. The positive-phase component Vout (positive-phase signal) of the differential voltage signals Vout and Voutb is 180° out of phase with the negative-phase component Voutb (negative-phase signal) of the differential voltage signals Vout and Voutb. For example, when the positive-phase signal Vout increases, the negative-phase signal Voutb decreases, and when the positive-phase signal Vout decreases, the negative-phase signal Voutb increases. When the positive phase signal Vout reaches its maximum value (peak), the negative phase signal Voutb reaches its minimum value (valley), and when the positive phase signal Vout reaches its valley, the negative phase signal Voutb reaches its peak. The positive phase signal Vout and the negative phase signal Voutb can have the same amplitude and the same time average value. The difference between the time average value of the voltage of the positive phase component of the differential voltage signal and the time average value of the voltage of the negative phase component is called DC offset. For example, the difference between the time average value of the voltage of the positive phase signal Vout and the time average value of the voltage of the negative phase signal Voutb is DC offset. In the following description, when simply referred to as DC offset, it means the difference between the time average value of the voltage of the positive phase signal Vout and the time average value of the voltage of the negative phase signal Voutb. DC offset is preferably small during signal transmission. The output amplifier 13b outputs the differential voltage signals Vout and Voutb to the outside of the transimpedance amplifier circuit 10A via the output terminals 10b and 10c.

[0066] The control current generating circuit 14A generates the control current Icnt based on the integrated value of the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref. The difference ΔVtia is a signal (voltage value) obtained by subtracting the voltage signal Vtia from the reference voltage signal Vref. The control current generating circuit 14A includes an integrating circuit 41A and an OTA (operational transconductance amplifier) ​​42A (transconductance amplifier circuit).

[0067] The integration circuit 41A is a circuit that integrates the difference ΔVtia to generate a differential integration signal (voltage signal Vinp and voltage signal Vinn). Figure 2As shown, integration circuit 41A has input terminals 41a and 41b and output terminals 41c and 41d. Input terminal 41a is electrically connected to the output terminal of reference voltage generating circuit 12 (voltage amplifier 12a), and input terminal 41a receives reference voltage signal Vref. Input terminal 41b is electrically connected to the output terminal of TIA unit 11 (voltage amplifier 11a), and input terminal 41b receives voltage signal Vtia. Output terminal 41c (first output terminal) is electrically connected to input terminal 42b, the inverting input terminal of OTA 42A, and outputs voltage signal Vinn, the inverting component of the differential integration signal, to OTA 42A. Output terminal 41d (second output terminal) is electrically connected to input terminal 42a, the non-inverting input terminal of OTA 42A, and outputs voltage signal Vinp, the positive phase component of the differential integration signal, to OTA 42A. For example, when the voltage value of voltage signal Vtia is greater than the voltage value of reference voltage signal Vref, the voltage value of voltage signal Vinp is smaller than the voltage value of voltage signal Vinn.

[0068] Integrating circuit 41A includes an operational amplifier 43, resistors 44 and 45, capacitors 46 and 47, and a diode 48. Operational amplifier 43 has a non-inverting input terminal 43a, an inverting input terminal 43b, an inverting output terminal 43c, and a non-inverting output terminal 43d. Non-inverting input terminal 43a is electrically connected to input terminal 41a via resistor 44. Inverting input terminal 43b is electrically connected to input terminal 41b via resistor 45. Inverting output terminal 43c is electrically connected to output terminal 41c and to non-inverting input terminal 43a via capacitor 46. In other words, capacitor 46 is connected so that negative feedback is applied from inverting output terminal 43c to non-inverting input terminal 43a. Non-inverting output terminal 43d is electrically connected to output terminal 41d and to inverting input terminal 43b via capacitor 47. That is, the capacitor 47 is connected so as to apply negative feedback from the non-inverting output terminal 43d to the inverting input terminal 43b. Regarding the change in output relative to the change in input, for example, when the voltage value of the voltage signal Vtia is greater than the voltage value of the reference voltage signal Vref, the voltage value of the voltage signal Vinp is smaller than the voltage value of the voltage signal Vinn.

[0069] Here, it is assumed that the gain of operational amplifier 43 is, for example, 1000 times or greater, the resistance value R1 of resistor 44 and the resistance value R2 of resistor 45 are equal, and the capacitance value C1 of capacitor 46 and the capacitance value C2 of capacitor 47 are equal. In this case, the gain of operational amplifier 43 is considered infinite, and integrating circuit 41A operates as an integrator with a time constant of R1×C1.

[0070] The diode 48 is provided between the output terminal 41c and the output terminal 41d. The anode of the diode 48 is electrically connected to the output terminal 41c. The cathode of the diode 48 is electrically connected to the output terminal 41d. The on-state voltage (forward voltage) of the diode 48 is set to a low voltage from the perspective of high-speed operation of the control loop. Figure 3 In the example shown, the gain (voltage gain) of operational amplifier 43 is 10,000 times (80 dB), and the on-state voltage of diode 48 is 0.4 V. Integrating circuit 41A has a characteristic whereby a 1 μV change in differential ΔVtia causes a 10 mV change in differential ΔVin. Differential ΔVin is the signal (voltage value) obtained by subtracting voltage signal Vinn from voltage signal Vinp, and is the voltage amplitude of the differential integrated signal. In this example, when differential ΔVin is less than -0.4 V, diode 48 is in the on state. Thus, even if differential ΔVtia increases toward the negative side, differential ΔVin remains fixed at -0.4 V. On the other hand, when differential ΔVin increases toward the positive side, differential ΔVin saturates to 1.5 V or above and does not increase. Thus, integrating circuit 41A has an asymmetric characteristic centered on zero regarding differential ΔVin.

[0071] OTA42A is a circuit that converts the differential integrated signal (voltage signal Vinp and voltage signal Vinn) into a single current signal (error current), namely control current Icnt. OTA42A has an input-output characteristic where the transconductance increases when the differential ΔVin is positive.

[0072] like Figure 4 As shown, OTA 42A has input terminals 42a and 42b and an output terminal 42c. Input terminal 42a is electrically connected to output terminal 41d of integration circuit 41A, and voltage signal Vinp is input to input terminal 42a. Input terminal 42b is electrically connected to output terminal 41c of integration circuit 41A, and voltage signal Vinn is input to input terminal 42b. Output terminal 42c is electrically connected to input terminal 51a of control circuit 51, described later, and outputs control current Icnt to control circuit 51. OTA 42A includes transconductance circuit 21 (first transconductance circuit), transconductance circuit 22 (second transconductance circuit), and current source 23.

[0073] The transconductance circuit 21 generates an output current Iout1 (a first output current) based on the differential integrated signal (voltage signal Vinp and voltage signal Vinn). The non-inverting input terminal of the transconductance circuit 21 is electrically connected to the input terminal 42a and receives the voltage signal Vinp. The inverting input terminal of the transconductance circuit 21 is electrically connected to the input terminal 42b and receives the voltage signal Vinn. The output terminal of the transconductance circuit 21 outputs the output current Iout1.

[0074] like Figure 5 As shown, the transconductance circuit 21 operates in a range VR1 (first range) of the differential ΔVin such that the output current Iout1 decreases as the differential ΔVin increases. The transconductance circuit 21 has a transconductance -gm1 (second transconductance) in the range VR1. The transconductance -gm1 is equivalent to Figure 5 The gradient of the output current Iout1 within the range VR1 is shown in Figure 2. This gradient is a negative value, so for convenience, gm1 is expressed as -gm1, using a positive real value. When the differential ΔVin exceeds the upper limit of the range VR1, the transconductance circuit 21 maintains the output current Iout1 at the upper limit of the range VR1. When the differential ΔVin falls below the lower limit of the range VR1, the transconductance circuit 21 maintains the output current Iout1 at the lower limit of the range VR1.

[0075] The transconductance circuit 22 generates an output current Iout2 (a second output current) based on the differential integrated signal (voltage signal Vinp and voltage signal Vinn). The non-inverting input terminal of the transconductance circuit 22 is electrically connected to the input terminal 42b and receives the voltage signal Vinn. The inverting input terminal of the transconductance circuit 22 is electrically connected to the input terminal 42a and receives the voltage signal Vinp. The output terminal of the transconductance circuit 22 outputs the output current Iout2.

[0076] like Figure 5 As shown, the transconductance circuit 22 operates in a range VR2 (second range) of the differential ΔVin such that the output current Iout2 increases as the differential ΔVin increases. The transconductance circuit 22 has a transconductance gm2 in the range VR2. The transconductance gm2 is equivalent to Figure 5 The slope of output current Iout1 within range VR2 is shown in FIG. Here, gm2 is a positive real value. The magnitude (absolute value) of transconductance gm2 is different from the magnitude (absolute value) of transconductance -gm1 and is smaller than the magnitude (absolute value) of transconductance -gm1. Range VR2 is narrower than range VR1 and is included in range VR1. That is, the upper limit of range VR2 is smaller than the upper limit of range VR1, and the lower limit of range VR2 is larger than the lower limit of range VR1. When differential ΔVin exceeds the upper limit of range VR2, transconductance circuit 22 maintains the current value of output current Iout2 at the upper limit of range VR2. When differential ΔVin falls below the lower limit of range VR2, transconductance circuit 22 maintains the current value of output current Iout2 at the lower limit of range VR2. That is, the linear operating range (range VR2) of transconductance circuit 22 is narrower than the linear operating range (range VR1) of transconductance circuit 21.

[0077] The current source 23 supplies a constant current Inull. The constant current Inull has a current value (fixed value) obtained by adding the current value of the output current Iout1 when the difference ΔVin is 0 and the current value of the output current Iout2 when the difference ΔVin is 0.

[0078] OTA42A generates the control current Icnt by adding the output current Iout1 and the output current Iout2. More specifically, OTA42A adds the output current Iout1 and the output current Iout2, and subtracts the addition result from the constant current Inull to generate the control current Icnt. The control current Icnt is differentiated by the difference ΔVin to obtain Figure 6 The U-shaped transconductance characteristic shown has three flat portions. The transconductance (gm1-gm2) (first transconductance) of the central flat portion is smaller than the transconductance gm1 of the flat portions on both sides thereof, and the control current Icnt is nonlinear with respect to the differential ΔVin.

[0079] like Figure 6 As shown, the transconductance of OTA 42A is low near the differential ΔVin of 0V, and increases as the absolute value of the differential ΔVin increases. More specifically, when the absolute value of the differential ΔVin is less than the threshold value Vth1, the transconductance of OTA 42A is the value obtained by subtracting the transconductance gm2 from the transconductance gm1 (gm1-gm2). When the absolute value of the differential ΔVin is greater than the threshold value Vth2, the transconductance of OTA 42A is the transconductance gm1. When the absolute value of the differential ΔVin further increases and exceeds the linear operating range of the transconductance circuits 21 and 22, the transconductance of OTA 42A decreases again toward 0. This transconductance characteristic is line-symmetrical on the positive and negative sides about the vertical axis where ΔVin = 0. Therefore, the transconductance (gm1-gm2) of the flat portion near ΔVin = 0 is smaller than the transconductance gm1 of the two flat portions outside it.

[0080] According to this characteristic, OTA42A generates control current Icnt according to differential integral signals Vinp and Vinn through transconductance (gm1-gm2) when differential ΔVin is greater than threshold -Vth1 and less than threshold Vth1. OTA42A generates control current Icnt according to differential integral signals Vinp and Vinn through transconductance gm1 when differential ΔVin is less than threshold -Vth2 or greater than threshold Vth2. Transconductance gm1 is greater than transconductance (gm1-gm2). Figure 6 In the example shown, the threshold value Vth2 is larger than the threshold value Vth1 , but the threshold value Vth2 may be the same as the threshold value Vth1 .

[0081] The OTA 42A can operate in both directions: drawing the control current Icnt from the output terminal 42c into the OTA 42A, and discharging the control current Icnt from the output terminal 42c out of the OTA 42A. Therefore, even when the control current Icnt is near 0 A, the transconductance of the OTA 42A is maintained. By adjusting the transconductances gm1 and gm2 and the ranges VR1 and VR2, the U-shaped transconductance characteristics of the OTA 42A can be arbitrarily set.

[0082] Figure 7 The OTA42A shown has features for implementing Figure 4 The circuit structure of OTA42A is shown in FIG. Figure 7 As shown, OTA 42A includes input terminals 42a and 42b, an output terminal 42c, and a power supply terminal 42d. Power supply terminal 42d is electrically connected to a power supply line that supplies power supply voltage VCC, and power supply voltage VCC is supplied to power supply terminal 42d. OTA 42A includes, for example, transconductance circuits 21 and 22, and current source 23, as well as a bias circuit 24 and a synthesizing circuit 25.

[0083] Bias circuit 24 includes transistor 24a and current source 24b. Transistor 24a is, for example, a P-channel MOS (Metal-Oxide-Semiconductor) transistor. The source of transistor 24a is electrically connected to power supply terminal 42d. The gate and drain of transistor 24a are electrically connected to each other and to current source 24b. A reference current Ir is supplied to the drain of transistor 24a. Reference current Ir flows from the drain of transistor 24a to current source 24b. The value of reference current Ir is set by current source 24b.

[0084] Transconductance circuit 21 includes transistors 21a, 21b, 21c, and 21d, and a resistor 21e. Transistors 21a, 21b, 21c, and 21d are, for example, P-channel MOS transistors. The sources of transistors 21a and 21b are electrically connected to power supply terminal 42d via a power supply line. The gates of transistors 21a and 21b are electrically connected to the gate and drain of transistor 24a. The drain of transistor 21a is electrically connected to the source of transistor 21c. The drain of transistor 21b is electrically connected to the source of transistor 21d.

[0085] Transistor 24a and each of transistors 21a and 21b form a current mirror circuit. Transistor 24a functions as the input transistor of the current mirror circuit, while transistors 21a and 21b function as the output transistors of the current mirror circuit. For example, an output current (drain current Id1) proportional to the magnitude of the drain current (reference current Ir) of transistor 24a is output from the drain of transistor 21a. That is, when an input current (reference current Ir) is input to the input transistor, an output current (drain current Id1) proportional to the magnitude of the input current (reference current Ir) is output from the output transistor. Similarly, an output current (drain current Id2) proportional to the magnitude of the drain current (reference current Ir) of transistor 24a is output from the drain of transistor 21b. Thus, transistors 21a and 21b function as a current source for the transconductance circuit 21.

[0086] Transistors 21c and 21d form a differential pair. The gate of transistor 21c is electrically connected to input terminal 42a, and voltage signal Vinp is input to the gate of transistor 21c. The drain of transistor 21c is electrically connected to the drain and gate of transistor 25a, described later. The gate of transistor 21d is electrically connected to input terminal 42b, and voltage signal Vinn is input to the gate of transistor 21d. The drain of transistor 21d is electrically connected to ground potential GND. Transistor 21c can have electrical characteristics identical to those of transistor 21d. Resistor 21e is electrically connected between the source of transistor 21c and the source of transistor 21d. Resistor 21e has a resistance value of Rgm1. The sizes of transistors 21c and 21d are set so that the transconductance of transistors 21c and 21d is sufficiently greater than 1 / Rgm1. For example, by adjusting the gate length and gate width of the transistors 21 c and 21 d, the transconductance gm1 of the transconductance circuit 21 is made larger than 1 / Rgm1 . The output current Iout1 is output from the drain of the transistor 21 c .

[0087] Transconductance circuit 22 includes transistors 22a, 22b, 22c, and 22d, and a resistor 22e. Transistors 22a, 22b, 22c, and 22d are, for example, P-channel MOS transistors. The sources of transistors 22a and 22b are electrically connected to power supply terminal 42d. The gates of transistors 22a and 22b are electrically connected to the gate and drain of transistor 24a. The drain of transistor 22a is electrically connected to the source of transistor 22c. The drain of transistor 22b is electrically connected to the source of transistor 22d.

[0088] Transistor 24a and transistors 22a and 22b form a current mirror circuit. Transistor 24a functions as the input transistor of the current mirror circuit, while transistors 22a and 22b function as the output transistors of the current mirror circuit. An output current (drain current Id3) proportional to the drain current (reference current Ir) of transistor 24a is output from the drain of transistor 22a. Similarly, an output current (drain current Id4) proportional to the drain current (reference current Ir) of transistor 24a is output from the drain of transistor 22b. Thus, transistors 22a and 22b function as a current source for transconductance circuit 22.

[0089] Transistors 22c and 22d form a differential pair. The gate of transistor 22c is electrically connected to input terminal 42b, and a voltage signal Vinn is input to the gate of transistor 22c. The drain of transistor 22c is electrically connected to the drain and gate of transistor 25a, described later. The gate of transistor 22d is electrically connected to input terminal 42a, and a voltage signal Vinp is input to the gate of transistor 22d. The drain of transistor 22d is electrically connected to ground potential GND. Transistor 22c may have electrical characteristics identical to those of transistor 22d. Resistor 22e is electrically connected between the source of transistor 22c and the source of transistor 22d. Resistor 22e has a resistance value of Rgm2. The sizes of transistors 22c and 22d are set so that the transconductance of transistors 22c and 22d is sufficiently greater than 1 / Rgm2. For example, by adjusting the gate length and gate width of the transistors 22c and 22d, the transconductance gm2 of the transconductance circuit 22 is greater than 1 / Rgm2. The output current Iout2 is output from the drain of the transistor 22c.

[0090] Current source 23 includes transistor 23a. Transistor 23a is, for example, a P-channel MOS transistor. The source of transistor 23a is electrically connected to power supply terminal 42d. The gate of transistor 23a is electrically connected to the gate and drain of transistor 24a. The drain of transistor 23a is electrically connected to output terminal 42c. Transistor 24a and transistor 23a form a current mirror circuit. Transistor 24a functions as an input transistor of the current mirror circuit, and transistor 23a functions as an output transistor of the current mirror circuit. An output current (drain current) proportional to the drain current (reference current Ir) of transistor 24a is output from the drain of transistor 23a to output terminal 42c as a constant current Inull.

[0091] Synthesizing circuit 25 includes transistors 25a and 25b. Transistors 25a and 25b are, for example, N-channel MOS transistors. The sources of transistors 25a and 25b are electrically connected to ground potential GND. The gate and drain of transistor 25a are electrically connected to each other and to the drains of transistors 21c and 22c. The gate of transistor 25b is electrically connected to the gate of transistor 25a. The drain of transistor 25b is electrically connected to output terminal 42c.

[0092] The output current Iout1 output from the transconductance circuit 21 and the output current Iout2 output from the transconductance circuit 22 are synthesized in the synthesis circuit 25, and the synthesized current (Iout1+Iout2) flows to the transistor 25a connected by the diode. Transistors 25a and 25b constitute a current mirror circuit. Transistor 25a functions as an input transistor of the current mirror circuit, and transistor 25b functions as an output transistor of the current mirror circuit. An output current (drain current) proportional to the magnitude of the drain current (Iout1+Iout2) of transistor 25a is output from the drain of transistor 25b. Here, for example, the current mirror ratio is set to 1:1. It should be noted that transistor 25b can have the same electrical characteristics as those of transistor 25a.

[0093] The pull-in current Iout1 + Iout2 generated by the synthesizing circuit 25 is synthesized with the constant current Inull output from the current source 23. The synthesized current (Inull - (Iout1 + Iout2)) is output from the output terminal 42c as the control current Icnt. It should be noted that since the output terminal 42c is electrically connected to the transistor 23a and the transistor 25b, which function as current sources, the output impedance of the OTA 42A is very high, and the OTA 42A operates as a transconductance amplifier. It should be noted that when the transistor 23a functions as a current source, the transistor 23a can also operate in the saturation region of the drain current-voltage characteristic. The transistor 25b can also operate in the saturation region of the drain current-voltage characteristic, for example.

[0094] The range VR1 of differential ΔVin, where transconductance circuit 21 operates linearly, can be roughly expressed as Rgm1 × (Id1 + Id2) using the drain current Id1 of transistor 21a and the drain current Id2 of transistor 21b. That is, the maximum value of output current Iout1 is determined by (Id1 + Id2). Similarly, the range VR2 of differential ΔVin, where transconductance circuit 22 operates linearly, can be roughly expressed as Rgm2 × (Id3 + Id4) using the drain current Id3 of transistor 22a and the drain current Id4 of transistor 22b. That is, the maximum value of output current Iout2 is determined by (Id3 + Id4).

[0095] Figure 5The current characteristics shown can be achieved by satisfying the condition of equation (1). In this way, the desired current characteristics can be obtained by adjusting the drain currents Id1, Id2, Id3, and Id4 and the resistance values ​​Rgm1 and Rgm2.

[0096]

Mathematical formula 1

[0097]

[0098] The bypass circuit 15 generates a DC bypass current Iaoc and an AC bypass current Iagc1 based on the control current Icnt. The bypass circuit 15 includes, for example, a control circuit 51, a feedback current source 52, and a variable resistance circuit 53 (first variable resistance circuit).

[0099] A control current Icnt is input to the control circuit 51. The control circuit 51 controls the feedback current source 52 so that the DC bypass current Iaoc increases as the control current Icnt increases. When the control current Icnt exceeds the current value of the bias current Iofs, the control circuit 51 controls the variable resistor circuit 53 so that the AC bypass current Iagc1 increases as the control current Icnt increases. The bias current Iofs is a predetermined current value (fixed value), for example, set to the current value of the control current Icnt when the difference ΔVin is at the upper limit of the range VR1. Specifically, the control circuit 51 receives the control current Icnt from the control current generation circuit 14A (OTA 42A) and generates a control current Iaoccnt (a first control current) and a control current Iagc1cnt (a second control current) based on the control current Icnt. The control circuit 51 outputs the control current Iaoccnt to the feedback current source 52, thereby controlling the feedback current source 52 using the control current Iaoccnt. The control circuit 51 outputs the control current Iagc1cnt to the variable resistor circuit 53 , and controls the variable resistor circuit 53 by the control current Iagc1cnt.

[0100] like Figure 8As shown, the current value of the control current Iaoccnt is proportional to the current value of the control current Icnt. The current value of the control current Iaoccnt is α times the current value of the control current Icnt (Iaoccnt=α×Icnt). The amplification factor α is a real number greater than 1, for example. The control circuit 51 generates the control current Iaoccnt by amplifying the control current Icnt at the amplification factor α (first amplification factor). The current value of the control current Iagc1cnt is proportional to the current value of the control current Icnt when the current value of the control current Icnt is greater than the current value of the bias current Iofs. In other words, the current value of the control current Iagc1cnt is γ times the current value obtained by subtracting the current value of the bias current Iofs from the control current Icnt (Iagc1cnt=γ×(Icnt-Iofs)). The amplification factor γ is a real number greater than 1, for example. The control circuit 51 generates, for example, a bias current Iofs having a predetermined current value (bias current value) and amplifies the difference (differential current) between the current generated by amplifying the control current Icnt (here, the control current Icnt) and the bias current Iofs at an amplification factor γ (a second amplification factor) to generate the control current Iagc1cnt. In this manner, the amplification factor α is adjusted for the control current Iaoccnt. The bias current value, which determines the current at which automatic gain control (AGC) is initiated, and the amplification factor γ, which determines the control sensitivity of the AGC, are adjusted for the control current Iagc1cnt.

[0101] Figure 9 The control circuit 51 shown has a function for realizing Figure 8 The circuit structure of the control current Iaoccnt and the control current Iagc1cnt is shown in FIG. Figure 9 As shown, the control circuit 51 includes, for example, an input terminal 51a, output terminals 51b and 51c, and a power supply terminal 51d. Input terminal 51a is electrically connected to output terminal 42c of control current generating circuit 14A (OTA42A), and control current Icnt is input to input terminal 51a. Output terminal 51b is electrically connected to input terminal 52a of feedback current source 52, and control current Iaoccnt is supplied to feedback current source 52. Output terminal 51c is electrically connected to control terminal 53a of variable resistor circuit 53, and control current Iagc1cnt is supplied to variable resistor circuit 53. Power supply terminal 51d is electrically connected to a power supply line that supplies power supply voltage VCC, and power supply voltage VCC is supplied to power supply terminal 51d.

[0102] The control circuit 51 includes transistors 61 to 69 and a current source 70. The transistors 61 to 69 are, for example, field effect transistors (MOSFETs) having a MOS structure. Figure 9In the example shown, transistors 61 to 63 are N-channel MOS transistors (NMOS), and transistors 64 to 69 are P-channel MOS transistors (PMOS).

[0103] Transistors 61-63 form a current mirror circuit. Specifically, transistor 61 functions as the input transistor of the current mirror circuit, while transistors 62 and 63 each function as the output transistor of the current mirror circuit. The sources of transistors 61-63 are electrically connected to ground potential GND. The gate and drain of transistor 61 are electrically connected to each other and to input terminal 51a. The gates of transistors 62 and 63 are each electrically connected to the gate and drain of transistor 61. The drain of transistor 62 is electrically connected to the drain and gate of transistor 64. The drain of transistor 63 is electrically connected to the drain and gate of transistor 68 via node N1.

[0104] Transistors 61 and 62, and transistors 61 and 63, each form a current mirror circuit. Therefore, for example, an output current (drain current) proportional to the magnitude of the drain current (control current Icnt) of transistor 61 is output from the drains of transistors 62 and 63. Specifically, when an input current (control current Icnt) is input to the input transistor (transistor 61), an output current proportional to the magnitude of the input current (control current Icnt) is output from the output transistors (transistors 62 and 63). For ease of explanation, the current mirror ratio is assumed to be: input current: output current of transistor 62: output current of transistor 63 = 1:1:1. Therefore, the control current Icnt input to input terminal 51a is replicated by transistors 61 and 63, and the control current Icnt is output from the drains of transistors 62 and 63, respectively. It should be noted that the two replicated control currents Icnt flow from the drains to the sources of transistors 62 and 63, respectively. To achieve this current mirror ratio, transistors 61 and 63 may have identical electrical characteristics. It should be noted that the current mirror ratio can be appropriately changed according to the relationship between the control current Iaoccnt and the control current Iagc1cnt and the control current Icnt, such as by changing the sizes of the transistors 62 and 63 to the size of the transistor 61 .

[0105] Transistors 64 and 65 form a current mirror circuit. Transistor 64 functions as an input transistor of the current mirror circuit, and transistor 65 functions as an output transistor of the current mirror circuit. The sources of transistors 64 and 65 are electrically connected to power supply terminal 51d via a power supply line. The gate and drain of transistor 64 are electrically connected to each other and to the drain of transistor 62. The gate of transistor 65 is electrically connected to the gate and drain of transistor 64. The drain of transistor 65 is electrically connected to output terminal 51b.

[0106] The control current Icnt output from the drain of transistor 62 is input to the drain of transistor 64, and an output current (drain current) proportional to the magnitude of the drain current (control current Icnt) of transistor 64 is output from the drain of transistor 65 as control current Iaoccnt. Specifically, when the input current (control current Icnt) is input to the input transistor (transistor 64), an output current proportional to the magnitude of the input current (control current Icnt) is output from the output transistor (transistor 65). It should be noted that the actual input current flows from the source to the drain of transistor 64 and then flows into the drain of transistor 62. With this configuration, the output current of transistor 62 is equal to the input current of transistor 64. Here, the current mirror ratio of the current mirror circuit formed by transistors 64 and 65 is set to 1:α. That is, control current Iaoccnt is the current (α × Icnt) obtained by amplifying control current Icnt by α times. It should be noted that control current Iaoccnt flows from the drain of transistor 65 to output terminal 51b.

[0107] Transistors 66 and 67 form a current mirror circuit. Transistor 66 functions as an input transistor of the current mirror circuit, and transistor 67 functions as an output transistor of the current mirror circuit. The sources of transistors 66 and 67 are electrically connected to power supply terminal 51d via a power supply line. The gate and drain of transistor 66 are electrically connected to each other and to current source 70. The gate of transistor 67 is electrically connected to the gate and drain of transistor 66. The drain of transistor 67 is electrically connected to the drain and gate of transistor 68 via node N1.

[0108] The reference current Iref supplied from current source 70 is input to the drain of transistor 66. An output current (drain current) proportional to the magnitude of the drain current (reference current Iref) of transistor 66 is output from the drain of transistor 67 as bias current Iofs. The current mirror ratio of the current mirror circuit formed by transistors 66 and 67 is set to 1:m. That is, bias current Iofs is a current (m × Iref) obtained by amplifying the reference current Iref by a factor of m. In other words, when the input current (reference current Iref) is input to input transistor 66, output transistor 67 outputs an output current (m × Iref, the reference current amplified by a factor of m). It should be noted that bias current Iofs flows from the drain of transistor 67 toward node N1. The value of m is a real number, for example, greater than 1, and is arbitrarily selected based on the optical power required to activate the AGC. Since the current value of reference current Iref is fixed, the current value of bias current Iofs (bias current value) is also fixed.

[0109] Transistors 68 and 69 form a current mirror circuit. Transistor 68 functions as an input transistor of the current mirror circuit, and transistor 69 functions as an output transistor of the current mirror circuit. The sources of transistors 68 and 69 are electrically connected to power supply terminal 51d via a power supply line. The gate and drain of transistor 68 are electrically connected to each other and to the drain of transistor 63 and transistor 67 via node N1. The gate of transistor 69 is electrically connected to the gate and drain of transistor 68. The drain of transistor 69 is electrically connected to output terminal 51c.

[0110] The control current Icnt output from the drain of transistor 63 is combined at node N1 with the bias current Iofs output from the drain of transistor 67. Specifically, the bias current Iofs is deducted from the control current Icnt. At this point, only when the current value of the control current Icnt is greater than the current value of the bias current Iofs, does the difference current (Icnt - Iofs) flow to the drain of transistor 68, and an output current (drain current) proportional to the magnitude of the drain current (difference current) of transistor 68 is output from the drain of transistor 69 as control current Iagc1cnt. The current mirror ratio of the current mirror circuit formed by transistors 68 and 69 is set to 1:γ. In other words, control current Iagc1cnt is a current obtained by amplifying the difference current (Icnt - Iofs) by γ times (γ × (Icnt - Iofs)). That is, when the input current (difference current (Icnt-Iofs)) is input to the input transistor 68, the output transistor 69 outputs the output current (difference current γ×(Icnt-Iofs) amplified by γ times). Note that the control current Iagc1cnt flows from the drain of the transistor 69 toward the output terminal 51c.

[0111] On the other hand, when the current value of control current Icnt is less than the current value of bias current Iofs, current does not flow into transistor 68. Therefore, the potential of node N1 is pulled up toward power supply voltage VCC by a high resistance through diode-connected transistor 68. Furthermore, the drain-source voltage of transistor 67 decreases, so transistors 66 and 67 do not operate as a current mirror circuit. In this case, transistor 67 operates in a triode region (linear region), so the potential of node N1 is pulled up toward power supply voltage VCC by a low resistance. The triode region refers to a state in which, for example, the voltage obtained by subtracting the threshold voltage from the gate-source voltage of a transistor is greater than the drain-source voltage.

[0112] Since no gate-source voltage is applied to transistor 68, the resistance of transistor 67, to which the gate-source voltage is applied, is smaller than the resistance of transistor 68. Thus, since transistor 67 operates in the triode region, it is unable to supply bias current Iofs, and the entire control current Icnt from transistor 63 flows through transistor 67. Consequently, control current Iagc1cnt is output from output terminal 51c only when the current value of control current Icnt is greater than the current value of bias current Iofs (in the region where Icnt - Iofs > 0). For example, when the current value of control current Icnt is less than bias current Iofs, the gate-source voltage of transistor 69, a PMOS transistor, is approximately 0V, and the drain current (output current) of transistor 69 is zero.

[0113] It should be noted that through Figure 9 The control circuit 51 shown in FIG. Figure 8 The input-output characteristics of the current mirror ratio can be changed appropriately. As the circuit structure of the control circuit 51, it is also possible to adopt a circuit structure that can obtain Figure 8 Another circuit structure with input and output characteristics.

[0114] The feedback current source 52 is a current source used to form an automatic offset control (AOC) circuit. The feedback current source 52 is a circuit that generates a DC bypass current Iaoc based on the control current Icnt. More specifically, the feedback current source 52 generates the DC bypass current Iaoc based on the control current Iaoccnt. The feedback current source 52 has, for example, an input terminal 52a, an output terminal 52b, and a ground terminal 52c. The input terminal 52a is electrically connected to the output terminal 51b of the control circuit 51 and receives the control current Iaoccnt from the control circuit 51. The output terminal 52b is electrically connected to the input terminal 10a and outputs the DC bypass current Iaoc (specifically, it is introduced into the feedback current source 52). The ground terminal 52c is electrically connected to the ground potential GND. The feedback current source 52 includes a field effect transistor 54 (a first field effect transistor) and a field effect transistor 55 (a second field effect transistor).

[0115] Field effect transistors 54 and 55 are, for example, N-channel MOS transistors. The size of field effect transistor 54 and the size of field effect transistor 55 may be the same as or different from each other. The sources (first source, second source) of field effect transistors 54 and 55 are electrically connected to each other and electrically connected to ground potential GND via ground terminal 52c. The drain (first drain) of field effect transistor 54 is electrically connected to output terminal 51b of control circuit 51 via input terminal 52a, and receives control current Iaoccnt from control circuit 51. The gate (first gate) of field effect transistor 54 is electrically connected to the drain of field effect transistor 54. The drain (second drain) of field effect transistor 55 is electrically connected to input terminal 10a via output terminal 52b. The gate (second gate) of field effect transistor 55 is electrically connected to the drain and gate of field effect transistor 54.

[0116] In the feedback current source 52 thus configured, the control current Iaoccnt flowing from the input terminal 52a flows to the diode-connected field-effect transistor 54, thereby generating a gate-source voltage Vgs1 between the gate and source of the field-effect transistor 54. The gate of the field-effect transistor 54 is electrically connected to the gate of the field-effect transistor 55, and the source of the field-effect transistor 54 is electrically connected to the source of the field-effect transistor 55. Therefore, the gate-source voltage of the field-effect transistor 55 becomes equal to the gate-source voltage Vgs1. The source of the field-effect transistor 55 is electrically connected to the ground potential GND, so the source potential is approximately 0V. Meanwhile, the input potential of the TIA unit 11 (e.g., approximately 0.5 to 2V) is applied to the drain of the field-effect transistor 55. Therefore, the field-effect transistor 55 operates in the saturation region of its drain current-voltage characteristic. The saturation region refers to a state in which the voltage value obtained by subtracting the threshold voltage from the gate-source voltage of the transistor is less than the drain-source voltage. In the saturation region, even if the drain voltage of the field-effect transistor 55 increases, the relative increase in drain current is smaller than in the linear region. Therefore, the impedance (output impedance) of the output terminal 52b becomes relatively large. For example, by setting the impedance of the output terminal 52b to be larger than the input impedance of the TIA unit 11, it is possible to suppress the introduction of the DC bypass current Iaoc into the feedback current source 52 and to suppress the AC component of the photocurrent Ipd from flowing into the feedback current source 52.

[0117] That is, field-effect transistors 54 and 55 form a current mirror circuit, with control current Iaoccnt serving as the input current and a DC bypass current Iaoc proportional to control current Iaoccnt being output as the output current. In other words, feedback current source 52 causes DC bypass current Iaoc to flow from the drain of field-effect transistor 55 to the source of field-effect transistor 55 in response to control current Iaoccnt. This extracts DC bypass current Iaoc from photocurrent Ipd. As a result, the DC component and low-frequency components are removed from the differential ΔVtia, and the potential (average potential) of voltage signal Vtia becomes consistent with the potential of reference voltage signal Vref (DC bias control). This reduces the difference between the time-averaged voltage of positive-phase signal Vout and the time-averaged voltage of negative-phase signal Voutb, for example.

[0118] The variable resistor circuit 53 generates an AC bypass current Iagc1 based on the control current Icnt. More specifically, the variable resistor circuit 53 generates the AC bypass current Iagc1 based on the control current Iagc1cnt. The variable resistor circuit 53 includes, for example, a control terminal 53a, a resistance terminal 53b, and a resistance terminal 53c. The control terminal 53a is electrically connected to the output terminal 51c of the control circuit 51 and receives the control current Iagc1cnt from the control circuit 51. The resistance terminal 53b is electrically connected to the input terminal 10a. The resistance terminal 53c is electrically connected to the output terminal of the reference voltage generating circuit 12 (voltage amplifier 12a) and receives the reference voltage signal Vref from the reference voltage generating circuit 12. The variable resistor circuit 53 includes a field-effect transistor 56 (third field-effect transistor) and a field-effect transistor 57 (fourth field-effect transistor).

[0119] Field-effect transistors 56 and 57 are each, for example, N-channel MOS transistors. The size of field-effect transistor 56 and field-effect transistor 57 may be the same or different. The sources (third source and fourth source) of field-effect transistors 56 and 57 are electrically connected to each other and to the output terminal of reference voltage generating circuit 12 (voltage amplifier 12a) via resistor terminal 53c. A reference voltage signal Vref is input (supplied) to the sources of field-effect transistors 56 and 57. The drain (third drain) of field-effect transistor 56 is electrically connected to output terminal 51c of control circuit 51 via control terminal 53a, and receives control current Iagc1cnt from control circuit 51. The gate (third gate) of field-effect transistor 56 is electrically connected to the drain of field-effect transistor 56. The drain (fourth drain) of field-effect transistor 57 is electrically connected to input terminal 10a via resistor terminal 53b. The gate (fourth gate) of field-effect transistor 57 is electrically connected to the drain and gate of field-effect transistor 56.

[0120] In the variable resistor circuit 53 thus configured, control current Iagc1cnt flowing from control terminal 53a flows to diode-connected field-effect transistor 56, thereby generating a gate-source voltage Vgs2 between the gate and source of field-effect transistor 56. The gate of field-effect transistor 56 is electrically connected to the gate of field-effect transistor 57, and the source of field-effect transistor 56 is electrically connected to the source of field-effect transistor 57. Therefore, the gate-source voltage of field-effect transistor 57 is equal to gate-source voltage Vgs2. A reference voltage signal Vref is supplied to the source of field-effect transistor 57, and the input potential of TIA unit 11 is applied to the drain of field-effect transistor 57. Because reference voltage signal Vref is substantially the same as the input potential of TIA unit 11, field-effect transistor 57 operates in a deep triode region (linear region). The deeper triode region refers to a state in which the voltage value obtained by subtracting the threshold voltage from the gate-source voltage of the transistor is much larger than the drain-source voltage. In the linear region, when the drain voltage of the field effect transistor 57 increases, the drain current also increases accordingly. In particular, when the drain voltage is relatively small, the drain current can be considered to change in proportion to the drain voltage (linearly). The ratio of the drain voltage of the field effect transistor 57 to the drain current is expressed as the resistance value R AGC1 About the resistance value R AGC1 , described later.

[0121] The drain current Id of the field effect transistor 57 biased in the triode region (i.e., the AC bypass current Iagc1) can be expressed as Equation (2) using the intrinsic gain (gain coefficient) β of the field effect transistor 57 and the threshold voltage Vth of the field effect transistor 57. The intrinsic gain β is a value that depends on the semiconductor process and size of the field effect transistor 57.

[0122]

Mathematical formula 2

[0123]

[0124] In triodes, when the potential difference between the drain and source is small, the relationship between the drain and source potentials may be reversed. In this case, the terminal with the lowest voltage relative to the gate functions as the source. Transistor circuit symbols are used for convenience in circuit representation, so the transistor terminal representation in circuit diagrams may not match the actual transistor operation. Here, the terminals are appropriately replaced so that the drain-source voltage Vds is at least 0, and the terminal with the lower potential is always considered the source.

[0125] As shown in Formula (3), the gate-source voltage Vgs2 is expressed by adding the drain-source voltage Vds to the gate-source voltage Vgs0. The gate-source voltage Vgs0 is the gate-source voltage when the drain-source voltage Vds is 0V.

[0126]

Mathematical formula 3

[0127] Vgs2=Vgs0+Vds…(3)

[0128] Substituting equation (3) into equation (2) yields equation (4). As shown in equation (4), the drain current Id (AC bypass current Iagc1) is proportional to the square of the drain-source voltage Vds and therefore contains a nonlinear component.

[0129]

Mathematical formula 4

[0130]

[0131] As shown in equation (5), the differential resistance value Rd (resistance value Rd) is obtained by differentiating equation (4) with the drain-source voltage Vds and calculating the inverse of the result. AGC1 As shown in formula (5), the resistance value R AGC1 The resistance value R changes according to the drain-source voltage Vds. That is, as the gate-source voltage Vgs2 (= Vgs0 + Vds) increases, the resistance value R AGC1 The drain potential is modulated according to the photocurrent Ipd, so the resistance value R AGC1 Changes nonlinearly.

[0132]

Mathematical formula 5

[0133]

[0134] As shown in equation (6), the transconductance gm in the transistor region is obtained by differentiating equation (4) with the gate-source voltage Vgs0. In the transistor region, the drain-source voltage Vds is smaller than the voltage obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs2. In particular, in the deep transistor region, the drain-source voltage Vds is significantly smaller than the voltage obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs2. Therefore, the transconductance gm in the transistor region is negligibly small when compared with the transconductance (β×(Vgs-Vth)) in saturation operation.

[0135]

Mathematical formula 6

[0136]

[0137] That is, although variable resistor circuit 53 has the same circuit structure as feedback current source 52, it does not operate as a current mirror circuit. Instead, field-effect transistor 57 operates as a variable resistor controlled by gate-source voltage Vgs2. Specifically, field-effect transistor 57 is AC-grounded by reference voltage generator circuit 12, biasing field-effect transistor 57 in a deep triode region. The potentials of resistor terminal 53b and resistor terminal 53c are approximately the same, so the DC component of photocurrent Ipd barely flows into variable resistor circuit 53. Instead, a portion of the AC component of photocurrent Ipd flows into variable resistor circuit 53 (field-effect transistor 57) as AC bypass current Iagc1. In other words, variable resistor circuit 53 causes AC bypass current Iagc1 to flow between the drain and source of field-effect transistor 57 in response to control current Iagc1cnt. The AC bypass current Iagc1 is an AC component, so the AC bypass current Iagc1 sometimes flows from the drain to the source of the field effect transistor 57, and sometimes flows from the source to the drain of the field effect transistor 57, depending on the photocurrent Ipd. It should be noted that the AC bypass current Iagc1 also depends on the resistance value R of the field effect transistor 57 relative to the input impedance of the TIA unit 11. AGC1 When the resistance value R of the field effect transistor 57 is AGC1 When the input impedance is smaller than the TIA unit 11 , the AC bypass current Iagc1 increases. At this time, by suppressing the drain-source voltage Vds of the field effect transistor 57 to a low level, the DC component of the photocurrent Ipd can be suppressed from flowing into the variable resistor circuit 53 .

[0138] That is, the photocurrent Ipd increases and the difference ΔVtia increases. When the control current Icnt exceeds the current value of the bias current Iofs, the control current Iagc1cnt is supplied to the variable resistor circuit 53. As a result, the gate-source voltage Vgs2 is generated in the field effect transistors 56 and 57. As the gate-source voltage Vgs2 increases, the resistance value R of the field effect transistor 57 increases. AGC1To reduce the photocurrent Ipd's gain, a portion of the signal component (AC component) other than the DC component of the photocurrent Ipd is extracted from the photocurrent Ipd as AC bypass current Iagc1. This reduces the likelihood of the TIA unit 11 saturating due to large input signals. More specifically, when the gain (transimpedance) of the TIA unit 11 is set to a substantially constant value, if the photocurrent Ipd increases and the amplitude of the current signal Iin exceeds a predetermined value, the amplitude of the voltage signal Vtia saturates. Therefore, gain control is performed to suppress saturation of the amplitude of the voltage signal Vtia by extracting the AC bypass current Iagc1 from the photocurrent Ipd. When a burst optical signal is input as the optical signal Pin, the intensity of the optical signal Pin varies significantly before and after periods of no signal. Therefore, the AGC automatically adjusts the magnitude of the AC bypass current Iagc1 based on the magnitude of the voltage signal Vtia (actually, the magnitude of the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref). The AGC adjusts the magnitude of the signal component (AC component) of the current signal Iin. However, at this time, it is preferable that the DC component of the current signal Iin and the control of the DC component (DC offset control) are not affected.

[0139] As described above, a current proportional to the drain-source voltage flows between the drain and source of the field effect transistor 57 biased in the deep triode region (linear region). The reference voltage signal Vref is substantially the same potential as the input potential of the TIA unit 11, so no DC current flows, and the AC bypass current Iagc1 does not disturb the DC bias control. The resistance value R of the field effect transistor 57 is AGC1 The change of may not affect the AOC control, but only affect the gain control.

[0140] Next, the frequency characteristics of the control loop in the transimpedance amplifier circuit 10A will be described. The approximate expression of the transfer function of the control loop in the transimpedance amplifier circuit 10A uses the open loop gain A of the voltage amplifier 11a of the TIA unit 11. TIA , the input impedance R of the TIA unit 11 IN , the overall gain F(s) of the feedback circuit and the resistance value R of the field effect transistor 57 AGC1 It is expressed as formula (7). It should be noted that the gain F(s) is the product of the voltage gain of the integration circuit 41A, the transconductance of the OTA 42A, the gain of the control circuit 51, and the gain of the feedback current source 52 (field effect transistor 55). The gain F(s) has a frequency dependency as the integration circuit 41A at low frequencies. The open loop gain A TIA And the input impedance R IN At low frequencies, it is constant (fixed value) regardless of the frequency.

[0141]

Mathematical formula 7

[0142]

[0143] It should be noted that the resistance value R AGC1 Since the control is performed using the same control loop, the frequency characteristics of the control loop do not strictly follow the formula (7). The drain-source voltage of the field effect transistor 57 is set to be approximately 0V, so the transconductance of the field effect transistor 57 biased in the deeper triode region is small enough to be ignored compared to the transconductance of the field effect transistor 55. Therefore, there is almost no control gain in the field effect transistor 57, and the influence of the control gain of the field effect transistor 57 on the control is extremely small. On the other hand, the resistance value R of the field effect transistor 57 is AGC1 Controlled by gate-source voltage Vgs2 and input impedance R IN The parallel resistance circuit is formed, which can have a greater impact on the photocurrent Ipd and the DC bypass current Iaoc. As a result, the simplified formula (7) is obtained.

[0144] As described above, the OTA 42A can flow in either the direction of drawing in the control current Icnt or the direction of discharging the control current Icnt, depending on the polarity of the differential ΔVin. Figure 6 As shown, the transconductance of OTA 42A is constant when the differential ΔVin is near 0V. Meanwhile, the control circuit 51 and feedback current source 52 use a current mirror circuit to replicate the current. Therefore, the output current of the control circuit 51 and feedback current source 52 is rectified in one direction by the diode-connected MOS transistors that constitute the current mirror circuit. This rectification action reduces the transconductance in regions with very low output currents, but in other regions, the current is accurately replicated due to the transistor size ratio. Therefore, in the control circuit 51 and feedback current source 52, the transconductance is constant with respect to the input current except in regions with very low output currents.

[0145] If a configuration is used in which the DC bypass current Iaoc is generated by controlling the gate potential of the source-grounded amplifier rather than by controlling the current mirror circuit, the transconductance changes in proportion to the square root of the drain current. The DC bypass current Iaoc requires a dynamic range of at least 60dB (1μA to 1mA), so the transconductance changes by 30dB. As a result, the open-loop transfer function (also known as "open-loop transfer gain") changes significantly with respect to the feedback current. Furthermore, in a configuration in which the AC component is extracted from the photocurrent Ipd by controlling the cathode voltage of the diode, the diode's resistance component changes nonlinearly with respect to the control voltage, increasing the input level dependence of the control loop's open-loop transfer gain.

[0146] In contrast, in the transimpedance amplifier circuit 10A, the photocurrent Ipd is small, and when only the AOC is operating, the OTA42A operates linearly. Therefore, except for the region where the DC bypass current Iaoc is very small, the open-loop transfer function is constant regardless of the DC bypass current Iaoc. The transconductance of the OTA42A is designed to increase when the control current Icnt exceeds the current value of the bias current Iofs due to an increase in the photocurrent Ipd. When the control current Icnt exceeds the current value of the bias current Iofs, the AGC operates, and the resistance value R of the field effect transistor 57 is set to 0. AGC1 The transconductance of OTA 42A increases, thereby suppressing the decrease in open-loop transfer gain (i.e., the increase in control time constant).

[0147] As described above, except in regions where the photocurrent Ipd is very low, the open-loop transfer gain of the control loop is controlled to be substantially constant. Therefore, the time constant of the control loop remains substantially constant, independent of the photocurrent Ipd. This operation is suitable for situations where immediate DC bias and gain control is required, such as when a burst optical signal is input to the optical receiving device 1A as the optical signal Pin.

[0148] Next, the operation and effects of the transimpedance amplifier circuit 10A will be described. Figure 10 Yes Figure 1 The diagram shows the DC bias characteristics and gain characteristics of the transimpedance amplifier circuit. Figure 10 The horizontal axis represents the optical input level of the optical signal Pin (unit: dBm). Figure 10 The vertical axis represents the DC offset (unit: μV) and the transimpedance gain Zt (unit: dBohm). Figure 10 The dashed line shows the DC offset characteristic. The DC offset characteristic shows the dependency of the DC offset amount on the optical input level of the optical signal Pin. Figure 10 The solid line represents the gain characteristic. The gain characteristic represents the dependency of the transimpedance gain Zt of the transimpedance amplifier circuit 10A on the optical input level of the optical signal Pin.

[0149] As described above, when extracting current from the photocurrent Ipd, the DC component (DC bypass current Iaoc) and the AC component (AC bypass current Iagc1) can be separated and controlled. Therefore, for small signals between -30dBm and -15dBm, it is not necessary to extract the AC component from the photocurrent Ipd. Therefore, for small signals, only the DC bypass current Iaoc is extracted from the photocurrent Ipd, allowing only the DC bias to be controlled.

[0150] When the optical input level of the signal exceeds -15dBm, the control current Iagc1cnt starts to flow to the variable resistor circuit 53, and the resistance value R of the field effect transistor 57 is AGC1This decreases. As a result, the AC bypass current Iagc1 is extracted from the photocurrent Ipd, and the transimpedance gain Zt of the transimpedance amplifier circuit 10A begins to decrease. This decrease in transimpedance gain Zt reduces the open-loop transfer gain of the control loop, slightly reducing the amount of DC offset suppression. However, since this suppression amount is expressed in μV, the fluctuation in DC offset is negligible relative to the signal amplitude. Consequently, distortion caused by saturation of the transimpedance amplifier circuit 10A is suppressed over a wide range of optical input levels, achieving stable reception characteristics.

[0151] In the transimpedance amplifier circuit 10A, DC bias control and gain control can be implemented using a single control loop (a single integrator circuit 41A and a single control circuit 51), thereby suppressing an increase in circuit size. Furthermore, by adjusting the response of the control circuit 51 (such as the amplification factor α, the amplification factor γ, and the current value of the bias current Iofs), the optical input level can be arbitrarily controlled.

[0152] In the transimpedance amplifier circuit 10A, the control gain drop associated with AGC is compensated by the OTA 42A. This reduces the fluctuation of the control time constant caused by the magnitude of the photocurrent Ipd. This operation is particularly suitable when a burst optical signal is input as the optical signal Pin.

[0153] Figure 11A Yes Figure 1 A graph of the open-loop transfer function of the control loop in the transimpedance amplifier circuit shown. Figure 11B Yes Figure 1 The closed-loop frequency characteristics of the transimpedance amplifier circuit are shown in FIG. Figure 12A Graph showing an open-loop transfer function of a control loop in the transimpedance amplifier circuit of the first comparative example. Figure 12B This graph shows the closed-loop frequency characteristics of a transimpedance amplifier circuit according to a first comparative example. The transimpedance amplifier circuit according to the first comparative example differs from the transimpedance amplifier circuit 10A (first embodiment) primarily in that it includes a linear OTA in place of the OTA 42A. Specifically, the transimpedance amplifier circuit according to the first comparative example is configured to set the transconductance gm2 of the transconductance circuit 22 of the OTA 42A to zero. Figure 11A 、 Figure 11B 、 Figure 12A as well as Figure 12B The horizontal axis represents the frequency of the photocurrent Ipd (unit: Hz). Figure 11A as well as Figure 12A The vertical axis represents the open-loop transfer gain (unit: dB). Figure 11B as well as Figure 12B The vertical axis represents the transimpedance gain (unit: dB).

[0154] like Figure 11AAs shown, in the transimpedance amplifier circuit 10A, except when the optical input level of the optical signal Pin is low (the optical input level is -10 dBm or higher), the frequency at which the open-loop transfer gain is 0 is substantially constant. Figure 11B As shown in FIG, the variable resistor circuit 53 operates due to the increase in the photocurrent Ipd, and the closed loop transfer function (transimpedance gain) decreases accordingly, but the low-frequency cutoff frequency does not change. Figure 12A As shown, in the transimpedance amplifier circuit of the first comparative example, the frequency at which the open-loop transfer gain is 0 depends on the optical input level of the optical signal Pin. Figure 12B As shown, the closed-loop transfer function (transimpedance gain) decreases as the photocurrent Ipd increases, and the low-frequency cutoff frequency also decreases (the time constant becomes longer).

[0155] Figure 13 This is a graph showing changes in transimpedance gain and low-frequency cutoff frequency relative to the optical input level. Figure 14 This is a diagram showing changes in the control time constant relative to the light input level. Figure 13 as well as Figure 14 The horizontal axis represents the optical input level of the optical signal Pin (unit: dBm). Figure 13 The vertical axis represents the low-frequency cutoff frequency (unit: MHz) and the transimpedance gain Zt (unit: dBohm). Figure 14 The vertical axis represents the control time constant (unit: nsec). Figure 13 The solid line represents the low-frequency cutoff frequency of the transimpedance amplifier circuit 10A (non-linear OTA). Figure 13 The dotted line represents the low-frequency cutoff frequency of the transimpedance amplifier circuit (linear OTA) of the first comparative example. Figure 13 The single-dot chain line represents the transimpedance gain of the transimpedance amplifier circuit 10A (non-linear OTA). Figure 14 The solid line represents the control time constant of the transimpedance amplifier circuit 10A (non-linear OTA). Figure 14 The dashed line represents the control time constant of the transimpedance amplifier circuit (linear OTA) of the first comparative example. Note that the control characteristics of the transimpedance gain of the first comparative example with respect to the optical input level are the same as those of the transimpedance amplifier circuit 10A (nonlinear OTA) and are therefore not shown in the figure.

[0156] like Figure 13As shown, in the transimpedance amplifier circuit of the first comparative example, as the optical input level of the optical signal Pin increases, the transimpedance gain Zt decreases, and the low-frequency cutoff frequency also decreases. Specifically, the transimpedance gain Zt decreases by 8 dBohm (2 / 5) from its peak value (approximately 58 dBohm), and accordingly, the low-frequency cutoff frequency also decreases from its peak value to approximately 2 / 5. In contrast, in the transimpedance amplifier circuit 10A, even when the transimpedance gain Zt decreases as the optical input level of the optical signal Pin increases, the decrease in the low-frequency cutoff frequency is suppressed.

[0157] like Figure 14 As shown, in the transimpedance amplifier circuit of the first comparative example, the control time constant increases (becomes slower) as the optical input level of the optical signal Pin increases. In contrast, in the transimpedance amplifier circuit 10A, the increase in the control time constant is suppressed even when the optical input level of the optical signal Pin increases. In other words, the control time constant is suppressed from being dependent on the optical input level of the optical signal Pin, and fluctuations in the control time constant are suppressed over a wide range of optical input levels. This operation is suitable for receiving burst optical signals.

[0158] Figure 15 Yes Figure 1 The diagram shows the response of each node in the optical receiving device shown in FIG. Here, the response of the optical receiving device 1A when receiving a burst optical signal as the optical signal Pin is shown. Assuming that the burst optical signal starts at time t = 100nsec, the optical signal Pin increases from the no-input state to -5dBm, and when the burst optical signal ends at time t = 2μsec, the optical signal Pin decreases from -5dBm to -26dBm. Figure 15 As shown, the control time constant remains approximately constant except for small signal conditions. Therefore, the DC and AC components are extracted from the photocurrent Ipd in response to changes in the burst optical signal, converging to a stable state within several hundred nanoseconds. At the input of the signal processing circuit 20, the DC offset is removed within approximately 400 nanoseconds from the start and end of the burst optical signal. This operation is suitable for receiving burst optical signals.

[0159] As described above, in the transimpedance amplifier circuit 10A, the feedback current source 52 generates a DC bypass current Iaoc, and the variable resistor circuit 53 generates an AC bypass current Iagc1. These DC bypass current Iaoc and AC bypass current Iagc1 are extracted from the photocurrent Ipd generated by the light-receiving element PD to generate a current signal Iin. Furthermore, the TIA unit 11 converts the current signal Iin into a voltage signal Vtia, and the differential amplifier circuit 13A generates differential voltage signals Vout and Voutb based on the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref.

[0160] A control current Icnt is generated based on the integrated value of the difference ΔVtia, and the feedback current source 52 is controlled so that the DC bypass current Iaoc increases as the control current Icnt increases. Therefore, the DC component of the photocurrent Ipd is extracted from the photocurrent Ipd as the DC bypass current Iaoc, thereby removing the DC component from the photocurrent Ipd. On the other hand, when the control current Icnt exceeds the current value of the bias current Iofs, the variable resistor circuit 53 is controlled so that the AC bypass current Iagc1 increases as the control current Icnt increases. Therefore, when the photocurrent Ipd is relatively low, the DC component of the photocurrent Ipd is extracted as the DC bypass current Iaoc, but the extraction of the AC bypass current Iagc1 is suppressed. This allows the DC component of the photocurrent Ipd to be removed while preventing attenuation of the AC component of the photocurrent Ipd. When photocurrent Ipd is relatively large, the DC component of photocurrent Ipd is extracted as DC bypass current Iaoc, and the AC component of photocurrent Ipd is extracted from photocurrent Ipd as AC bypass current Iagc1. This removes the DC component of photocurrent Ipd and attenuates the AC component. Both feedback current source 52 and variable resistor circuit 53 are controlled by a single control circuit 51, enabling DC component removal control (DC bias control) and gain control to be performed using a single control loop. This results in DC bias control and gain control being implemented while minimizing circuit size.

[0161] The voltage signal Vinp and the voltage signal Vinn are generated by integrating the difference ΔVtia. When the difference ΔVin obtained by subtracting the voltage signal Vinn from the voltage signal Vinp is less than the threshold value Vth1, the control current Icnt is generated based on the voltage signal Vinp and the voltage signal Vinn via the transconductance (gm1-gm2). When the difference ΔVin is greater than the threshold value Vth2, the control current Icnt is generated based on the voltage signal Vinp and the voltage signal Vinn via the transconductance gm1. The AC bypass current Iagc1 is not extracted until the control current Icnt exceeds the current value of the bias current Iofs. Therefore, the resistance value R of the variable resistor circuit 53 (field effect transistor 57) is set to AGC1 On the other hand, when the control current Icnt exceeds the current value of the bias current Iofs, the variable resistor circuit 53 is controlled in such a way that the AC bypass current Iagc1 increases as the control current Icnt increases, so the resistance value R of the variable resistor circuit 53 (field effect transistor 57) is AGC1 In the control current generating circuit 14A, when the difference ΔVin is greater than the threshold value Vth1, a transconductance greater than the transconductance (gm1-gm2) is used. In this way, the increase in the transconductance of the control current generating circuit 14A can compensate for the increase in the resistance value RAGC1 The decrease in open-loop transfer gain caused by the decrease in the feedback signal intensity can be reduced. This can suppress the increase in the control time constant of the feedback control. Consequently, it is possible to suppress the fluctuation of the control time constant caused by changes in the signal intensity of the burst optical signal.

[0162] Within the differential ΔVin range VR1, transconductance circuit 21 operates so that output current Iout1 decreases as differential ΔVin increases. Within the differential ΔVin range VR2, transconductance circuit 22 operates so that output current Iout2 increases as differential ΔVin increases. Control current Icnt is generated by adding output currents Iout1 and Iout2. The upper limit of range VR2 is lower than the upper limit of range VR1. Therefore, when differential ΔVin is positive, OTA 42A achieves input-output characteristics such that transconductance increases as differential ΔVin increases. This simplifies the generation of control current Icnt.

[0163] Ideally, when the optical signal Pin is absent, the potential of the voltage signal Vtia should match the potential of the reference voltage signal Vref. However, due to variations in the characteristics of the TIA unit 11, variations in the characteristics between the TIA unit 11 and the reference voltage generation circuit 12, and external noise, the potential of the voltage signal Vtia and the reference voltage signal Vref may differ when the optical signal Pin is absent. Therefore, when the optical signal Pin is absent, the potential of the voltage signal Vtia may be greater than the potential of the reference voltage signal Vref. Since the increase and decrease of the voltage signal Vtia are opposite to the increase and decrease of the current signal Iin, the state where the potential of the voltage signal Vtia is greater than the potential of the reference voltage signal Vref indicates that the current signal Iin is decreasing. The feedback current source 52 causes the DC bypass current Iaoc to flow in a direction that draws from the photocurrent Ipd. Therefore, for example, when the voltage signal Vtia is greater than the reference voltage signal Vref, the difference ΔVtia cannot be brought close to zero. In this case, the differential ΔVtia is negative, and therefore the differential ΔVin is also negative, resulting in open-loop control. This results in a state with no control gain, slowing the control time constant. Consequently, even when the optical signal Pin is input, the control time constant is slow, preventing the control loop from responding immediately.

[0164] In contrast, the anode of diode 48 is electrically connected to output terminal 41c, and the cathode of diode 48 is electrically connected to output terminal 41d. Therefore, when differential ΔVtia has a negative value, the absolute value of differential ΔVtia can be prevented from exceeding the on-state voltage of diode 48. This shortens the recovery time from open-loop control to closed-loop control. Therefore, even when the optical signal Pin is input suddenly, DC bias control and gain control can be immediately performed. In other words, the response time when a burst optical signal is input can be shortened.

[0165] In feedback current source 52, field-effect transistor 54 is diode-connected. Therefore, when the drain of field-effect transistor 54 receives control current Iaoccnt, a gate-source voltage Vgs1 is generated between the gate and source of field-effect transistor 54. The gate of field-effect transistor 54 is electrically connected to the gate of field-effect transistor 55, and the source of field-effect transistor 54 is electrically connected to the source of field-effect transistor 55. Therefore, the gate-source voltage of field-effect transistor 55 becomes equal to gate-source voltage Vgs1. The source of field-effect transistor 55 is electrically connected to the source of field-effect transistor 54, i.e., ground potential GND, and the drain of field-effect transistor 55 is electrically connected to input terminal 10a. This increases the potential difference between the source and drain of field-effect transistor 55. Consequently, field-effect transistor 55 operates in a saturation region. Consequently, field-effect transistor 55 functions as a current source, and the output impedance of the drain of field-effect transistor 55 increases. Therefore, the AC component of the photocurrent Ipd barely flows into the field-effect transistor 55, but the DC component of the photocurrent Ipd can flow into the field-effect transistor 55 as a DC bypass current Iaoc. Furthermore, as the control current Icnt increases, the gate-source voltage Vgs1 of the field-effect transistor 54 increases, and accordingly, the drain current of the field-effect transistor 55 increases. Thus, the DC component of the photocurrent Ipd is extracted from the photocurrent Ipd as the DC bypass current Iaoc, appropriately removing the DC component from the photocurrent Ipd. It should be noted that the output impedance of the output terminal 52b should be determined by considering the input impedance of the TIA unit 11. For example, if the input impedance of the TIA unit 11 is Zin, the output impedance of the output terminal 52b can be set to 100×Zin or greater. The input impedance Zin and the output impedance of the output terminal 52b can have different frequency characteristics, so it is sufficient that this relationship is satisfied at least within a predetermined frequency range (band).

[0166] In variable resistor circuit 53, field-effect transistor 56 is diode-connected. Therefore, when the drain of field-effect transistor 56 receives control current Iagc1cnt, a gate-source voltage Vgs2 is generated between the gate and source of field-effect transistor 56. The gate of field-effect transistor 56 is electrically connected to the gate of field-effect transistor 57, and the source of field-effect transistor 56 is electrically connected to the source of field-effect transistor 57. Therefore, the gate-source voltage of field-effect transistor 57 becomes equal to gate-source voltage Vgs2. A reference voltage signal Vref is supplied to the source of field-effect transistor 57, and the drain of field-effect transistor 57 is electrically connected to input terminal 10a. Therefore, there is almost no potential difference between the drain and source of field-effect transistor 57. Consequently, field-effect transistor 57 operates in a (deeper) triode region. Consequently, field-effect transistor 57 functions as a variable resistor, and the output impedance of the drain of field-effect transistor 57 is reduced. Since there is almost no potential difference between the drain and source of field-effect transistor 57, the DC component of photocurrent Ipd hardly flows into field-effect transistor 57. However, the AC component of photocurrent Ipd can flow into field-effect transistor 57 as AC bypass current Iagc1. Furthermore, when control current Icnt exceeds the current value of bias current Iofs, gate-source voltage Vgs2 of field-effect transistor 56 increases as control current Icnt increases. Therefore, when photocurrent Ipd is relatively small, the extraction of AC bypass current Iagc1 is suppressed, thereby preventing attenuation of the AC component. When photocurrent Ipd is relatively large, the AC component of photocurrent Ipd is extracted from photocurrent Ipd as AC bypass current Iagc1, thereby attenuating the AC component of photocurrent Ipd. Therefore, the gain of transimpedance amplifier circuit 10A is controlled by variable resistor circuit 53.

[0167] It should be noted that the output impedance of the resistor terminal 53b can also be determined by taking into account the input impedance Zin of the TIA unit 11. For example, when the gain variable ratio of the TIA unit 11 is set to A (A is a real number greater than 1), the output impedance of the resistor terminal 53b is set to Zin / (A-1). Therefore, when the value of the current signal Iin of the TIA unit 11 when AGC is not performed is set to Iinoff, the value of the current signal Iin when AGC is performed, Iinon, becomes Iinon=Iinoff / A. For example, when A=2, the output impedance of the resistor terminal 53b is approximately equal to Zin, and when A is made larger than 2, the output impedance of the resistor terminal 53b becomes a value smaller than Zin. Therefore, when AOC and AGC are performed simultaneously, the output impedance of the output terminal 52b is set to be greater than the output impedance of the resistor terminal 53b. In addition, when AGC is not performed, the output impedance of the resistor terminal 53b can be set to be greater than 100×Zin. The output impedance of the resistor terminal 53b can be considered to be the same as the above-mentioned resistance value R AGC1 For example, the output impedance of the resistor terminal 53b is increased by making the gate voltage of the field-effect transistor 57 substantially equal to the threshold voltage of the field-effect transistor 57. The input impedance Zin and the output impedance of the resistor terminal 53b can have different frequency characteristics, and therefore, it is sufficient that the above relationship is satisfied at least within a predetermined frequency range (band).

[0168] The reference voltage generation circuit 12 includes a voltage amplifier 12a and a feedback resistor element 12b electrically connected between the input and output of the voltage amplifier 12a. With this configuration, the output impedance of the reference voltage generation circuit 12 is low over a wide frequency range. In other words, the impedance of the variable resistor circuit 53 as viewed from the input terminal of the TIA unit 11 is low over a wide frequency range. Consequently, the AC bypass current Iagc1 can be easily extracted from the photocurrent Ipd.

[0169] DC bias control is performed using the high-impedance feedback current source 52, so the AC component of the photocurrent Ipd is less affected (the AC component does not flow into the feedback current source 52). Meanwhile, gain control is performed by biasing the AC component of the photocurrent Ipd using the variable resistor circuit 53. Since the drain and source potentials of the field-effect transistor 57 are substantially equal, the DC component of the photocurrent Ipd is less affected (the DC component does not flow into the variable resistor circuit 53). As a result, interference between DC bias control and gain control can be avoided.

[0170] As described above, according to the transimpedance amplifier circuit 10A, control can be performed using a single control loop, without causing interference between the gain control of the transimpedance amplifier circuit 10A and the DC offset control for making the difference ΔVtia zero.

[0171] Next, refer to Figures 16 to 18 A transimpedance amplifier circuit according to another embodiment will be described. Figure 16 FIG1 schematically shows the structure of an optical receiving device including a transimpedance amplifier circuit according to another embodiment. Figure 17 Is used to illustrate Figure 16 A diagram showing the inter-terminal capacitance of a field effect transistor. Figure 18 Yes Figure 17 The diagram shows an example of capacitance values ​​of the inter-terminal capacitance.

[0172] like Figure 16 As shown, the optical receiving device 1B differs from the optical receiving device 1A primarily in that it includes a transimpedance amplifier circuit 10B instead of the transimpedance amplifier circuit 10A. The transimpedance amplifier circuit 10B differs from the transimpedance amplifier circuit 10A primarily in that it includes a bypass circuit 15B instead of the bypass circuit 15. The bypass circuit 15B differs from the bypass circuit 15 primarily in that it includes a variable resistance circuit 53B (first variable resistance circuit) instead of the variable resistance circuit 53. The variable resistance circuit 53B differs from the variable resistance circuit 53 primarily in that it further includes a resistance element 58 (first resistance element) and a resistance element 59 (second resistance element). In the variable resistance circuit 53B, the gate of the field-effect transistor 57 is electrically connected to the drain and gate of the field-effect transistor 56 via the resistance element 58.

[0173] Here, although it is not usually shown in the circuit diagram, the field effect transistor has a substrate terminal. The substrate terminal (first substrate terminal; Figure 16 53c) is electrically connected to the output terminal of the reference voltage generating circuit 12 (voltage amplifier 12a) via the resistor terminal 53c. A reference voltage signal Vref is input (supplied) to the substrate terminal of the field-effect transistor 56. The substrate terminal (second substrate terminal) of the field-effect transistor 57 is electrically connected to the output terminal of the reference voltage generating circuit 12 (voltage amplifier 12a) via the resistor element 59 and the resistor terminal 53c. The reference voltage signal Vref is input (supplied) to the substrate terminal of the field-effect transistor 57 via the resistor element 59. Since direct current does not flow through the substrate terminal of the field-effect transistor 57, the (direct current) potential of the substrate terminal of the field-effect transistor 57 is the same as the (direct current) potential of the substrate terminal of the field-effect transistor 56 and is set to the potential of the reference voltage signal Vref.

[0174] like Figure 17 As shown, the field effect transistor 57 has a capacitance component between each terminal of the gate (G), the source (S), the drain (D), and the substrate terminal (B). Figure 18 An example of the capacitance value of each capacitance component is shown in FIG. Figure 18The capacitance value shown is a typical capacitance value when the field effect transistor 57 is a 130nm CMOS process, the gate width (channel width) W of the field effect transistor 57 is 30μm, the gate length (channel length) L of the field effect transistor 57 is 0.13μm, and the field effect transistor 57 operates in a deeper transistor region.

[0175] The capacitance value of the capacitor Cgs (second capacitor) between the gate and the source and the capacitance value of the capacitor Cgd (first capacitor) between the gate and the drain are equal to each other and are 7.1fF. The capacitance value of the capacitor Cds between the drain and the source is 2.6fF. The capacitance value of the capacitor Cgb between the gate and the substrate terminal, the capacitance value of the capacitor Csb (fourth capacitor) between the source and the substrate terminal, and the capacitance value of the capacitor Cdb (third capacitor) between the drain and the substrate terminal are equal to each other and are 0.6fF. In this way, the field effect transistor 57 has symmetrical capacitance (capacitor Cgs and capacitor Cgd) on the source side and the drain side relative to the gate. In other words, the field effect transistor 57 is constructed in a way that the capacitance Cgd and the capacitance Cgs are equal to each other. Similarly, the field effect transistor 57 also has symmetrical capacitance (capacitor Csb and capacitor Cdb) on the source side and the drain side relative to the substrate terminal. In other words, the field effect transistor 57 is constructed in a way that the capacitance Cdb and the capacitance Csb are equal to each other.

[0176] It should be noted that when the number of gates of the field effect transistor is an odd number, by making the number of drains equal to the number of sources, a field effect transistor 57 is obtained in which the capacitance values ​​of capacitors Cgs and Cgd are equal, and the capacitance values ​​of capacitors Csb and Cdb are equal. For example, in the case of a MOS transistor with three gates, the structure can be drain D - gate G - source S - gate G - drain D - gate G - source S.

[0177] The capacitance of capacitor Csb is approximately one-tenth of that of capacitor Cgs, and the capacitance of capacitor Cdb is approximately one-tenth of that of capacitor Cgd. Capacitors Csb and Cdb primarily comprise the junction capacitance associated with the PN junction, while capacitors Cgs and Cgd primarily comprise the overlap capacitance due to the gate oxide film. Therefore, unless the source and drain areas are intentionally increased, capacitors Csb and Cdb are sufficiently smaller than capacitors Cgs and Cgd.

[0178] The resistance value Rg of the resistor element 58 is sufficiently larger than the impedance Zcgd formed by the capacitor Cgd and the impedance Zcgs formed by the capacitor Cgs at high frequencies. The resistance value Rb of the resistor element 59 is sufficiently larger than the impedance Zcdb formed by the capacitor Cdb and the impedance Zcsb formed by the capacitor Csb.

[0179] In the variable resistor circuit 53B thus configured, control current Iagc1cnt flowing from control terminal 53a flows to diode-connected field-effect transistor 56, generating a gate-source voltage Vgs2 between the gate and source of field-effect transistor 56. The gate of field-effect transistor 56 and the gate of field-effect transistor 57 are electrically connected to each other via resistor 58, and the source of field-effect transistor 56 and the source of field-effect transistor 57 are electrically connected to each other. Because the gate resistances of field-effect transistors 56 and 57 are significantly larger than the resistance value of resistor 58, the gate-source voltage of field-effect transistor 57 is equal to gate-source voltage Vgs2. A reference voltage signal Vref is supplied to the source of field-effect transistor 57, and the input potential of TIA unit 11 is applied to the drain of field-effect transistor 57. Because reference voltage signal Vref is substantially equal to the input potential of TIA unit 11, field-effect transistor 57 operates in a deep triode region (linear region). In the linear region, as the drain voltage of field-effect transistor 57 increases, the drain current also increases accordingly. Especially when the drain voltage is relatively low, the drain current can be considered to change proportionally (linearly) with the drain voltage. Specifically, field-effect transistors 56 and 57 of variable resistor circuit 53B are AC-grounded via reference voltage generator circuit 12, and field-effect transistor 57 is biased in a deep triode region.

[0180] Here, the field effect transistor 56 is diode-connected, so the gate of the field effect transistor 57 is electrically connected to the output terminal of the reference voltage generating circuit 12 (voltage amplifier 12a) through the resistor element 58 and the differential resistance of the field effect transistor 56 connected by the diode. The differential resistance value of the field effect transistor 56 connected by the diode is about several kΩ, which is quite small compared to the impedance Zcgd formed by the capacitor Cgd of the field effect transistor 57. The impedance Zcgd is 22 kΩ at 1 GHz, for example. Assuming that the resistance value Rg of the resistor element 58 is 0Ω, the gate potential of the field effect transistor 56 follows the low-impedance source potential (the potential of the reference voltage signal Vref). In this case, the gate-source voltage Vgs2 is expressed by adding the gate-source voltage Vgs0 to the drain-source voltage Vds as shown in the above formula (3).

[0181] Therefore, in the variable resistor circuit 53B, the drain current Id (i.e., the AC bypass current Iagc1) of the field effect transistor 57 biased in the triode region is also expressed by the above formula (4), and the resistance value R AGC1 It can be expressed by the above equation (5). Similarly, the transconductance gm in the triode region can be expressed by the above equation (6). Therefore, the transconductance gm in the triode region is negligibly small compared to the transconductance in saturation operation.

[0182] On the other hand, since the resistance value Rg of the resistor 58 is greater than the impedance Zcgd formed by the capacitor Cgd (Rg>>Zcgd), the gate of the field-effect transistor 57 is separated (insulated) from the gate of the field-effect transistor 56 at high frequency (AC). Since the capacitance values ​​of the capacitors Cgs and Cgd are equal, the drain-source voltage Vds is divided in half, and a voltage half of the drain-source voltage Vds (Vds / 2) is applied to the gate of the field-effect transistor 57.

[0183] The gate of field-effect transistor 57 can be electrically connected to the substrate terminal of field-effect transistor 57 at high frequencies via capacitor Cgb. Therefore, the potential of the substrate terminal of field-effect transistor 57 can slightly affect the gate potential of field-effect transistor 57 via capacitor Cgb. However, the resistance value Rb of resistor 59 is greater than the impedance Zcdb formed by capacitor Cdb (Rb>>Zcdb). Therefore, resistor 59 isolates (insulates) the substrate terminal of field-effect transistor 57 from the source of field-effect transistor 57 at high frequencies. The capacitance values ​​of capacitors Csb and Cdb are equal, so the drain-source voltage Vds is divided in half, and a voltage (Vds / 2) of half the drain-source voltage Vds is applied to the substrate terminal of field-effect transistor 57. This reduces the influence of the potential of the substrate terminal of field-effect transistor 57 on the gate potential of field-effect transistor 57.

[0184] In this case, as shown in Formula (8), the gate-source voltage Vgs2 is expressed by adding half of the drain-source voltage Vds to the gate-source voltage Vgs0.

[0185]

Mathematical formula 8

[0186]

[0187] Substituting equation (8) into equation (2) yields equation (9). As shown in equation (9), the drain current Id (AC bypass current Iagc1) is proportional to the drain-source voltage Vds and therefore contains no nonlinear components.

[0188]

Mathematical formula 9

[0189]

[0190] Then, as shown in equation (10), the differential resistance value Rd (resistance value Rd) is obtained by differentiating equation (9) using the drain-source voltage Vds and calculating the inverse of the result. AGC1 As shown in formula (10), the resistance value R AGC1It does not change due to the drain-source voltage Vds.

[0191]

Mathematical formula 10

[0192]

[0193] That is, by superimposing half of the drain-source voltage Vds (Vds / 2) on the gate voltage of the field effect transistor 57 operating in the triode region, the differential resistance value Rd (resistance value R AGC1 ) no longer depends on the drain-source voltage Vds, and the resistance value does not change from the time when the drain-source voltage Vds is 0V.

[0194] That is, although variable resistor circuit 53B has the same circuit structure as feedback current source 52, it does not operate as a current mirror circuit. Instead, field-effect transistor 57 operates as a linear variable resistor controlled by gate-source voltage Vgs2. The potentials of resistor terminal 53b and resistor terminal 53c are substantially the same, so the DC component of photocurrent Ipd barely flows into variable resistor circuit 53B. Instead, a portion of the AC component of photocurrent Ipd flows into variable resistor circuit 53B (field-effect transistor 57) as AC bypass current Iagc1. In other words, variable resistor circuit 53B causes AC bypass current Iagc1 to flow between the drain and source of field-effect transistor 57 in response to control current Iagc1cnt.

[0195] That is, the photocurrent Ipd increases and the difference ΔVtia increases. When the control current Icnt exceeds the current value of the bias current Iofs, the control current Iagc1cnt is supplied to the variable resistor circuit 53B. As a result, the gate-source voltage Vgs2 is generated in the field effect transistors 56 and 57. As the gate-source voltage Vgs2 increases, the resistance value R of the field effect transistor 57 increases. AGC1 Therefore, a portion of the signal component (AC component) other than the DC component of the photocurrent Ipd is extracted as the AC bypass current Iagc1. As a result, the possibility of saturation of the TIA unit 11 due to a large signal input is reduced.

[0196] As described above, a current proportional to the drain-source voltage flows between the drain and source of the field effect transistor 57 biased in the deep triode region (linear region). Since the reference voltage signal Vref is substantially the same potential as the input potential of the TIA unit 11, no DC current flows, and the AC bypass current Iagc1 does not disturb the DC bias control. AGC1 The change only affects the characteristics of the AOC control gain.

[0197] The resistance value R of the field effect transistor 57 AGC1 Since it does not depend on the drain-source voltage Vds, the AC bypass current Iagc1 is extracted from the photocurrent Ipd with low distortion. As a result, the occurrence of distortion is suppressed.

[0198] Next, the operation and effects of the transimpedance amplifier circuit 10B will be described. Figure 19A Yes Figure 16 A graph showing changes in total harmonic distortion relative to the average power of input light in the transimpedance amplifier circuit shown. Figure 19B Yes Figure 16 Graph showing changes in the output amplitude of the TIA section relative to the average power of input light in the transimpedance amplifier circuit shown. Figure 19C Yes Figure 16 Graph showing changes in amplitude at each terminal of a field effect transistor relative to the average power of input light in the transimpedance amplifier circuit shown. Figure 20A Graphs showing changes in total harmonic distortion with respect to input light average power in a transimpedance amplifier circuit according to a second comparative example. Figure 20B Graphs showing changes in the output amplitude of the TIA section relative to the average power of input light in the transimpedance amplifier circuit of the second comparative example. Figure 20C Graphs showing changes in amplitude at each terminal of a field-effect transistor relative to the average power of input light in a transimpedance amplifier circuit according to the second comparative example.

[0199] Figures 19A to 19C as well as Figures 20A to 20C The horizontal axis represents the average value of the optical input power of the optical signal Pin, that is, the input light average power Pin_ave (unit: dBm). Figure 19A as well as Figure 20A The vertical axis represents the total harmonic distortion (THD) (unit: %) of the output waveform (the waveform of the differential voltage signals Vout and Voutb). Figure 19B as well as Figure 20B The vertical axis represents the amplitude of the voltage signal Vtia (unit: mVpp). Figure 19C as well as Figure 20C The vertical axis represents the amplitudes (unit: mVpp) of the drain potential Vd, the gate potential Vg, and the source potential Vs of the field effect transistor 57 .

[0200] Figures 19A to 19C The calculation results shown are calculation results in the transimpedance amplifier circuit 10B (hereinafter referred to as “second embodiment”). Figures 20A to 20CThe calculation results shown are those of a transimpedance amplifier circuit according to a second comparative example (hereinafter referred to as the "second comparative example"). The transimpedance amplifier circuit according to the second comparative example differs from the transimpedance amplifier circuit 10B primarily in the resistance value Rg of the resistor element 58 and the resistance value Rb of the resistor element 59. In the transimpedance amplifier circuit according to the second embodiment, the resistance value Rg of the resistor element 58 is set to 200 kΩ, and the resistance value Rb of the resistor element 59 is set to 5 kΩ. In the transimpedance amplifier circuit according to the second comparative example, the resistance value Rg of the resistor element 58 and the resistance value Rb of the resistor element 59 are both set to 0Ω.

[0201] The current value of the bias current Iofs is set so that the AGC operates when the input light average power Pin_ave exceeds -1dBm. As the total harmonic distortion, the total harmonic distortion taking into account the 10th harmonic is calculated. In order to avoid distortion in the differential amplifier circuit 13A in the subsequent stage, the size of the field effect transistor 57 is determined so that the amplitude of the voltage signal Vtia does not exceed 500mVpp. The gain (voltage gain) of the TIA unit 11 is set to 10 times, and the resistance value of the feedback resistor element 11b is set to 550Ω. As the optical signal Pin, an optical signal obtained by intensity modulation with a 1GHz sine wave is used, and the amplitude of the optical signal Pin is set to be the same as the input light average power Pin_ave (extinction ratio is about 5dB). The photoelectric conversion gain of the light receiving element PD is set to 1.0A / W to simplify the calculation.

[0202] right Figure 19A and Figure 20A By comparison, it can be seen that when the average input optical power Pin_ave is 3dBm, the THD in the second comparative example is 5.2%, while the THD in the second embodiment is reduced to 4.1%. Figure 19B and Figure 20B Comparison shows that the amplitude of the voltage signal Vtia is controlled similarly in the second comparative example and the second embodiment. In other words, although the amount of AC bypass current Iagc1 drawn in the second embodiment is similar to that in the second comparative example, the THD of the second embodiment is improved compared to that of the second comparative example. Figure 20C , it can be seen that the gate-source voltage Vgs2 of the second comparative example is expressed by formula (3), so the amplitude of the gate potential Vg is approximately equal to the amplitude of the source potential Vs. Figure 19C , it can be seen that in the second embodiment, the amplitude of the gate potential Vg is approximately half of the amplitude of the drain potential Vd. This means that the drain-source voltage Vds of the field effect transistor 57 is divided by the capacitor Cgs and the capacitor Cgd, and the gate-source voltage Vgs2 is expressed by formula (8). Figure 19C as well as Figure 20CIn both the second comparative example and the second embodiment, the amplitude of the source potential Vs increases when the input light average power Pin_ave exceeds -1dB. This is because the output impedance of the reference voltage generation circuit 12 is not zero. Therefore, as the AC bypass current Iagc1 increases, the reference voltage signal Vref is modulated by the photocurrent Ipd. As described above, during gain control (AGC operation), the second embodiment can improve THD by approximately 1% compared to the second comparative example.

[0203] As described above, in the transimpedance amplifier circuit 10B, the bypass circuit 15B generates a DC bypass current Iaoc and an AC bypass current Iagc1. These are extracted from the photocurrent Ipd generated by the light-receiving element PD, thereby generating a current signal Iin. Furthermore, the TIA unit 11 converts the current signal Iin into a voltage signal Vtia. The differential amplifier circuit 13A generates differential voltage signals Vout and Voutb based on the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref. In the variable resistor circuit 53B, the field-effect transistor 56 is diode-connected. Therefore, when the drain of the field-effect transistor 56 receives the control current Iagc1cnt, a gate-source voltage Vgs2 is generated between the gate and source of the field-effect transistor 56. The gate of field-effect transistor 56 and the gate of field-effect transistor 57 are electrically connected to each other via resistor 58, and reference voltage signal Vref is supplied to the source of field-effect transistor 56 and the source of field-effect transistor 57. Since the gate resistances of field-effect transistors 56 and 57 are significantly larger than the resistance value Rg of resistor 58, the gate-source voltage of field-effect transistor 57 is equal to gate-source voltage Vgs2.

[0204] A reference voltage signal Vref is supplied to the source of field-effect transistor 57, and the drain of field-effect transistor 57 is electrically connected to input terminal 10a. Therefore, there is almost no potential difference between the drain and source of field-effect transistor 57. Consequently, field-effect transistor 57 operates in a (deeper) triode region. Consequently, field-effect transistor 57 functions as a variable resistor, and the output impedance of the drain of field-effect transistor 57 becomes low. Since there is almost no potential difference between the drain and source of field-effect transistor 57, the DC component of photocurrent Ipd hardly flows into field-effect transistor 57. However, the AC component of photocurrent Ipd can flow into field-effect transistor 57 as AC bypass current Iagc1. The difference (differential current) between the current generated by amplifying control current Icnt and bias current Iofs is amplified by amplification factor γ to obtain control current Iagc1cnt. Therefore, when the control current Icnt exceeds the current value of the bias current Iofs, the control current Iagc1cnt increases as the control current Icnt increases, and the gate-source voltage Vgs2 of the field-effect transistor 56 also increases. Therefore, when the photocurrent Ipd has a low or moderate signal strength, the extraction of the AC bypass current Iagc1 is suppressed, thereby preventing the AC component of the photocurrent Ipd from being attenuated. When the photocurrent Ipd has a high signal strength, the AC component of the photocurrent Ipd is extracted from the photocurrent Ipd as the AC bypass current Iagc1, thereby attenuating the AC component of the photocurrent Ipd. In this way, the gain of the transimpedance amplifier circuit 10B is controlled by the variable resistor circuit 53B.

[0205] The gate of the field effect transistor 57 is electrically connected to the gate of the field effect transistor 56 via the resistor element 58. The field effect transistor 56 is diode-connected, so the gate of the field effect transistor 57 is connected to the output terminal (reference voltage signal Vref) of the reference voltage generating circuit 12 via the resistor element 58 and the differential resistance of the field effect transistor 56. However, the resistance value Rg of the resistor element 58 is greater than the impedance Zcgd formed by the capacitor Cgd, so the gate of the field effect transistor 57 and the gate of the field effect transistor 56 can be separated (insulated) at high frequency by the resistor element 58. Therefore, the voltage obtained by dividing the drain-source voltage Vds by the capacitor Cgd and the capacitor Cgs is applied to the gate of the field effect transistor 57. The field effect transistor 57 is constructed in such a way that the capacitor Cgd and the capacitor Cgs are equal to each other, so a voltage of about half the drain-source voltage Vds is applied to the gate of the field effect transistor 57. As a result, the differential resistance value (resistance value Rg) of the field effect transistor 57 is suppressed. AGC1 ) varies due to the drain-source voltage Vds. As a result, the occurrence of distortion is suppressed, thereby improving signal quality.

[0206] Note that the output impedance of the resistance terminal 53 b of the variable resistance circuit 53B is similar to the output impedance of the resistance terminal 53 b of the variable resistance circuit 53 , and may be determined in consideration of the input impedance Zin of the TIA unit 11 .

[0207] The substrate terminal of field-effect transistor 57 is electrically connected to the gate of field-effect transistor 57 via capacitor Cgb. Therefore, the potential of the substrate terminal of field-effect transistor 57 may affect the gate potential of field-effect transistor 57 via capacitor Cgb. In contrast, a reference voltage signal Vref is supplied to the substrate terminal of field-effect transistor 57 via resistor 59. The resistance value Rb of resistor 59 is greater than the impedance Zcdb formed by capacitor Cdb (Rb>>Zcdb) and greater than the impedance Zcsb formed by capacitor Csb (Rb>>Zcsb). Therefore, resistor 59 isolates (insulates) the substrate terminal of field-effect transistor 57 from the outside of field-effect transistor 57 at high frequencies. Field-effect transistor 57 is configured so that capacitances Cdb and Csb are equal, so a voltage approximately half the drain-source voltage Vds is applied to the substrate terminal of field-effect transistor 57. As a result, the potential of the substrate terminal of the field effect transistor 57 is approximately the same as the gate potential of the field effect transistor 57, thereby reducing the influence of the potential of the substrate terminal of the field effect transistor 57 on the gate potential of the field effect transistor 57. As a result, the occurrence of distortion is further suppressed, thereby further improving signal quality.

[0208] The bypass circuit 15B includes a feedback current source 52 that generates a DC bypass current Iaoc based on the control current Icnt, and a variable resistor circuit 53B that generates an AC bypass current Iagc1 based on the control current Icnt. The control circuit 51 controls the feedback current source 52 so that the DC bypass current Iaoc increases as the control current Icnt increases. When the control current Icnt exceeds the current value of the bias current Iofs, the variable resistor circuit 53B is controlled so that the AC bypass current Iagc1 increases as the control current Icnt increases. This configuration allows both DC component removal and gain control of the transimpedance amplifier circuit 10B to be achieved using a single control loop, thereby minimizing increases in circuit size.

[0209] In feedback current source 52, field-effect transistor 54 is diode-connected. Therefore, when the drain of field-effect transistor 54 receives control current Iaoccnt, a gate-source voltage Vgs1 is generated between the gate and source of field-effect transistor 54. The gate of field-effect transistor 54 is electrically connected to the gate of field-effect transistor 55, and the source of field-effect transistor 54 is electrically connected to the source of field-effect transistor 55. Therefore, the gate-source voltage of field-effect transistor 55 is equal to gate-source voltage Vgs1. The source of field-effect transistor 55 is electrically connected to the source of field-effect transistor 54, i.e., ground potential GND, and the drain of field-effect transistor 55 is electrically connected to input terminal 10a. This increases the potential difference between the source and drain of field-effect transistor 55. Consequently, field-effect transistor 55 operates in a saturation region. Consequently, field-effect transistor 55 functions as a current source, and the output impedance of the drain of field-effect transistor 55 increases. Therefore, the AC component of the photocurrent Ipd barely flows into the field-effect transistor 55, but the DC component of the photocurrent Ipd can flow into the field-effect transistor 55 as a DC bypass current Iaoc. Furthermore, as the control current Icnt increases, the gate-source voltage Vgs1 of the field-effect transistor 54 increases, correspondingly increasing the drain current of the field-effect transistor 55. Thus, the DC component of the photocurrent Ipd is extracted from the photocurrent Ipd as a DC bypass current Iaoc, appropriately removing the DC component from the photocurrent Ipd. It should be noted that the output impedance of the output terminal 52b can be determined by considering the input impedance of the TIA unit 11. For example, if the input impedance of the TIA unit 11 is Zin, the output impedance of the output terminal 52b can be set to at least 100×Zin. The input impedance Zin and the output impedance of the output terminal 52b can have different frequency characteristics, so it is sufficient that this relationship is satisfied at least within a predetermined frequency range (band).

[0210] The reference voltage generation circuit 12 includes a voltage amplifier 12a and a feedback resistor element 12b electrically connected between the input and output of the voltage amplifier 12a. With this configuration, the output impedance of the reference voltage generation circuit 12 is low over a wide frequency range. In other words, the impedance of the variable resistor circuit 53B as viewed from the input terminal of the TIA unit 11 is low over a wide frequency range. Consequently, the AC bypass current Iagc1 can be easily extracted from the photocurrent Ipd.

[0211] Since the DC component is removed using the high-impedance feedback current source 52, the effect on the AC component of the photocurrent Ipd is minimal (the AC component does not flow into the feedback current source 52). Meanwhile, gain control is performed by biasing the AC component of the photocurrent Ipd using the variable resistor circuit 53B. Since the drain and source potentials of the field-effect transistor 57 are approximately equal, the effect on the DC component of the photocurrent Ipd is minimal (the DC component does not flow into the variable resistor circuit 53B). As a result, interference between the control of removing the DC component and the gain control can be avoided.

[0212] As described above, the transimpedance amplifier circuit 10B can be controlled using a single control loop without causing interference between gain control of the transimpedance amplifier circuit 10B and DC offset control for making the difference ΔVtia zero, and can perform gain control with low distortion.

[0213] Next, refer to Figures 21 to 23 A transimpedance amplifier circuit according to still another embodiment will be described. Figure 21 This is a diagram schematically showing the configuration of an optical receiving device including a transimpedance amplifier circuit according to still another embodiment. Figure 22 It means to Figure 21 Graph showing the relationship between the control current supplied by the control circuit and the current generated by the control circuit. Figure 23 Yes Figure 21 FIG. 1 is a diagram showing an example of a circuit configuration of a control circuit.

[0214] like Figure 21 As shown, the optical receiving device 1C differs from the optical receiving device 1A primarily in that it includes a transimpedance amplifier circuit 10C in place of the transimpedance amplifier circuit 10A. The transimpedance amplifier circuit 10C differs from the transimpedance amplifier circuit 10A primarily in that it includes a bypass circuit 15C in place of the bypass circuit 15. In the transimpedance amplifier circuit 10C, the current signal Iin is generated by extracting a DC bypass current Iaoc, an AC bypass current Iagc1, and an AC bypass current Iagc2 (another AC bypass current, a second AC bypass current) from the photocurrent Ipd.

[0215] Bypass circuit 15C differs from bypass circuit 15 primarily in that it generates DC bypass current Iaoc, AC bypass current Iagc1, and AC bypass current Iagc2 based on control current Icnt, includes control circuit 51C instead of control circuit 51, and further includes variable resistor circuit 80 (another variable resistor circuit, a second variable resistor circuit). Control circuit 51C differs from control circuit 51 primarily in that, when control current Icnt exceeds the current value of bias current Iofs, it controls variable resistor circuits 53 and 80 so that AC bypass currents Iagc1 and Iagc2 increase as control current Icnt increases.

[0216] Specifically, the control circuit 51C receives the control current Icnt from the control current generating circuit 14A (OTA 42A) and generates the control current Iaoccnt, the control current Iagc1cnt, and the control current Iagc2cnt (third control current) based on the control current Icnt. The control circuit 51C outputs the control current Iaoccnt to the feedback current source 52, thereby controlling the feedback current source 52 using the control current Iaoccnt. The control circuit 51C outputs the control current Iagc1cnt to the variable resistor circuit 53, thereby controlling the variable resistor circuit 53 using the control current Iagc1cnt. The control circuit 51C outputs the control current Iagc2cnt to the variable resistor circuit 80, thereby controlling the variable resistor circuit 80 using the control current Iagc2cnt.

[0217] like Figure 22 As shown, the current values ​​of control current Iagc1cnt and control current Iagc2cnt are proportional to the current value of control current Icnt when the current value of control current Icnt is greater than the current value of bias current Iofs. In other words, the current values ​​of control current Iagc1cnt and control current Iagc2cnt are γ times the current value obtained by subtracting the current value of bias current Iofs from control current Icnt (Iagc1cnt=Iagc2cnt=γ×(Icnt-Iofs)). Control circuit 51C generates bias current Iofs having a predetermined current value (bias current value), and amplifies the difference (differential current) between the current generated by amplifying control current Icnt (here, control current Icnt) and bias current Iofs by an amplification factor γ, thereby generating control current Iagc1cnt and control current Iagc2cnt.

[0218] The current value of control current Iaoccnt is the sum of α times the current value of control current Icnt and the current value of control current Iagc2cnt (Iaoccnt = α × Icnt + Iagc2cnt). For example, control circuit 51C generates control current Iaoccnt by adding the current generated by amplifying control current Icnt at an amplification factor α to control current Iagc2cnt. In this manner, amplification factor α is adjusted for control current Iaoccnt, while the bias current value used to determine the current for starting automatic gain control (AGC) and amplification factor γ, which determines the control sensitivity of AGC, are adjusted for control currents Iagc1cnt and Iagc2cnt.

[0219] Figure 23 The control circuit 51C shown has a function for implementing Figure 22The circuit structure of the control current Iaoccnt, the control current Iagc1cnt and the control current Iagc2cnt is shown. Figure 23 As shown, the circuit configuration of control circuit 51C differs from that of control circuit 51 mainly in that it further includes an output terminal 51e and transistors 71 and 72. Output terminal 51e is electrically connected to control terminal 80a of variable resistor circuit 80 and outputs control current Iagc2cnt to variable resistor circuit 80.

[0220] The transistors 71 and 72 are field effect transistors (MOSFETs) having a MOS structure, for example. Figure 23 In the example shown, transistors 71 and 72 are P-channel MOS transistors. Transistors 68 and 71, and transistors 68 and 72, respectively, form a current mirror circuit. Transistor 68 functions as an input transistor, and transistors 71 and 72 function as output transistors. The sources of transistors 71 and 72 are electrically connected to power supply terminal 51d. The gates and drains of transistors 71 and 72 are electrically connected to the gate and drain of transistor 68. The drain of transistor 71 is electrically connected to output terminal 51e. The drain of transistor 72 is electrically connected to output terminal 51b via node N2.

[0221] As described above, only when the current value of the control current Icnt is greater than the current value of the bias current Iofs, the differential current (Icnt-Iofs) flows to the drain of transistor 68, and the output current (drain current) of a magnitude proportional to the magnitude of the drain current (differential current) of transistor 68 is output from the drain of transistor 69 as the control current Iagc1cnt, and is output from the drains of transistors 71 and 72 as the control current Iagc2cnt, respectively.

[0222] Here, the current mirror ratio of the current mirror circuit formed by transistors 68, 69, 71, and 72 is set to 1:γ:γ:γ. That is, control currents Iagc1cnt and Iagc2cnt are currents of magnitude obtained by amplifying the difference current (Icnt-Iofs) by γ times (γ × (Icnt-Iofs)). It should be noted that control current Iagc1cnt generated by the current mirror circuit of transistors 68 and 69 flows from the drain of transistor 69 to output terminal 51c. Control current Iagc2cnt generated by the current mirror circuit of transistors 68 and 71 flows from the drain of transistor 71 to output terminal 51e. Control current Iagc2cnt generated by the current mirror circuit of transistors 68 and 72 flows from the drain of transistor 72 to node N2, where it is combined with the drain current output from the drain of transistor 65 at node N2. The drain current of transistor 65 is a current of magnitude obtained by amplifying control current Icnt by α times (α × Icnt). The drain current of transistor 65 flows toward node N2 from the drain of transistor 65. The drain current of transistor 65 is combined with control current Iagc2cnt to generate control current Iaoccnt, which flows from node N2 toward output terminal 51b.

[0223] On the other hand, when the current value of control current Icnt is less than the current value of bias current Iofs, no current flows into transistor 68. Therefore, the potential of node N1 is pulled up toward power supply voltage VCC by a high resistance through diode-connected transistor 68. Furthermore, the drain-source voltage of transistor 67 decreases, so transistors 66 and 67 do not operate as a current mirror circuit. In this case, transistor 67 operates in a triode region (linear region), so the potential of node N1 is pulled up toward power supply voltage VCC by a low resistance.

[0224] Since no gate-source voltage is applied to transistor 68, the resistance of transistor 67, to which the gate-source voltage is applied, is smaller than the resistance of transistor 68. Thus, by operating transistor 67 in the triode region, transistor 67 is unable to supply bias current Iofs, and all of control current Icnt from transistor 63 flows through transistor 67. Consequently, only when the current value of control current Icnt is greater than the current value of bias current Iofs (in the region of Icnt - Iofs > 0) is control current Iagc1cnt output from output terminal 51c, and control current Iagc2cnt is output from output terminal 51e and the drain of transistor 72.

[0225] Thus, the control current Iagc1cnt and the control current Iagc2cnt have the same current amount and flow in the same direction. In other words, the control currents Iagc1cnt and Iagc2cnt flow so as to be discharged from the power supply voltage VCC toward the ground potential GND.

[0226] It should be noted that through Figure 23 The control circuit 51C shown in FIG. Figure 22 The input-output characteristics of the current mirror ratio can be changed appropriately. As the circuit structure of the control circuit 51C, it is also possible to adopt a circuit structure that can obtain Figure 22 Another circuit structure with input and output characteristics.

[0227] The circuit configurations of the feedback current source 52 and the variable resistor circuit 53 in the bypass circuit 15C are the same as those of the feedback current source 52 and the variable resistor circuit 53 in the bypass circuit 15, and therefore their descriptions are omitted. As will be described later, the control current Iagc2cnt flows from the variable resistor circuit 80 toward the input terminal of the TIA unit 11, thereby increasing the DC component of the photocurrent Ipd. Therefore, the DC bypass current Iaoc generated by the feedback current source 52 is set to include the control current Iagc2cnt. Specifically, Figure 22 As shown, the control current Iaoccnt is generated by adding the current generated by amplifying the control current Icnt at an amplification factor α to the control current Iagc2cnt. This extracts the DC component and the control current Iagc2cnt from the photocurrent Ipd as the DC bypass current Iaoc. As a result, the DC component and low-frequency components are removed from the difference ΔVtia, and the potential of the voltage signal Vtia matches the potential of the reference voltage signal Vref (DC offset control).

[0228] The variable resistor circuit 80 is a circuit that generates an AC bypass current Iagc2 based on the control current Icnt. More specifically, the variable resistor circuit 80 generates the AC bypass current Iagc2 based on the control current Iagc2cnt. The variable resistor circuit 80 includes a control terminal 80a, a resistance terminal 80b, and a resistance terminal 80c. The control terminal 80a is electrically connected to the output terminal 51e of the control circuit 51C and receives the control current Iagc2cnt from the control circuit 51C. The resistance terminal 80b is electrically connected to the output terminal of the reference voltage generating circuit 12 (voltage amplifier 12a) and receives the reference voltage signal Vref from the reference voltage generating circuit 12. The resistance terminal 80c is electrically connected to the input terminal 10a. The variable resistor circuit 80 includes a field effect transistor 81 (fifth field effect transistor) and a field effect transistor 82 (sixth field effect transistor).

[0229] Field-effect transistors 81 and 82 are each, for example, N-channel MOS transistors. The size of field-effect transistor 81 and field-effect transistor 82 may be the same or different. The sources of field-effect transistors 81 and 82 are electrically connected to each other and to input terminal 10a via resistor terminal 80c. The drain of field-effect transistor 81 is electrically connected to output terminal 51e of control circuit 51C via control terminal 80a, and receives control current Iagc2cnt from control circuit 51C. The gate of field-effect transistor 81 is electrically connected to the drain of field-effect transistor 81. The gate of field-effect transistor 82 is electrically connected to the drain and gate of field-effect transistor 81. The drain of field-effect transistor 82 is electrically connected to the output terminal of reference voltage generating circuit 12 (voltage amplifier 12a) via resistor terminal 80b. A reference voltage signal Vref is input (supplied) to the drain of field-effect transistor 82. In other words, the relationship between the resistance terminal connected to the reference voltage generating circuit 12 and the resistance terminal connected to the input terminal 10 a is opposite in the variable resistance circuit 53 and the variable resistance circuit 80 .

[0230] In the variable resistor circuit 80 thus configured, control current Iagc2cnt flowing from control terminal 80a flows to diode-connected field-effect transistor 81, thereby generating a gate-source voltage Vgs3 between the gate and source of field-effect transistor 81. The gate of field-effect transistor 81 is electrically connected to the gate of field-effect transistor 82, and the source of field-effect transistor 81 is electrically connected to the source of field-effect transistor 82. Therefore, the gate-source voltage of field-effect transistor 82 is equal to gate-source voltage Vgs3. A reference voltage signal Vref is supplied to the drain of field-effect transistor 82, and the input potential of TIA section 11 is applied to the source of field-effect transistor 82. Because reference voltage signal Vref is approximately the same as the input potential of TIA section 11, field-effect transistor 82 operates in a deep triode region (linear region). In the linear region, as the drain voltage of field-effect transistor 82 increases, the drain current also increases accordingly. In particular, when the drain voltage is relatively small, the drain current can be considered to change in proportion to the drain voltage (linearly). The ratio of the drain voltage to the drain current of the field effect transistor 82 is expressed as the resistance value R. AGC2 .

[0231] As a result, the field effect transistor 82 operates as a variable resistor controlled by the gate-source voltage Vgs3, similarly to the field effect transistor 57. The resistance value R of the field effect transistor 82 is AGC2 With the resistance value R AGC1The same is expressed by formula (5). That is, through the reference voltage generating circuit 12, the field effect transistor 82 is AC grounded, and the field effect transistor 82 is biased in a deeper triode region. The potential of the resistance terminal 80b is approximately the same as the potential of the resistance terminal 80c, so the DC component of the photocurrent Ipd hardly flows into the variable resistance circuit 80, and a part of the AC component of the photocurrent Ipd flows into the variable resistance circuit 80 (field effect transistor 82) as the AC bypass current Iagc2. In other words, the variable resistance circuit 80 causes the AC bypass current Iagc2 to flow between the drain and source of the field effect transistor 82 according to the control current Iagc2cnt. The AC bypass current Iagc2 is an AC component, so the AC bypass current Iagc2 sometimes flows from the source to the drain of the field effect transistor 82, and sometimes flows from the drain to the source of the field effect transistor 82 according to the photocurrent Ipd.

[0232] That is, the photocurrent Ipd increases and the difference ΔVtia increases. When the control current Icnt exceeds the current value of the bias current Iofs, the control current Iagc2cnt is supplied to the variable resistor circuit 80. As a result, the gate-source voltage Vgs3 is generated in the field effect transistors 81 and 82. As the gate-source voltage Vgs3 increases, the resistance value R of the field effect transistor 82 increases. AGC2 Therefore, a portion of the signal component (AC component) other than the DC component of the photocurrent Ipd is extracted as the AC bypass current Iagc2. As a result, the possibility of saturation of the TIA unit 11 due to a large signal input is reduced.

[0233] A current proportional to the drain-source voltage flows between the drain and source of the field effect transistor 82 biased in the deep triode region (linear region). Since the reference voltage signal Vref is substantially the same as the input potential of the TIA unit 11, no DC current flows, and the AC bypass current Iagc2 does not disturb the DC bias control. AGC2 The change only affects the characteristics of the AOC control gain.

[0234] It should be noted that in variable resistor circuit 80, control current Iagc2cnt flowing from control terminal 80a flows through diode-connected field-effect transistor 81 and outflows from resistor terminal 80c toward the input terminal of TIA unit 11, thereby increasing the DC component of photocurrent Ipd. As described above, control current Iagc2cnt is extracted as part of DC bypass current Iaoc via feedback current source 52. This suppresses the generation of a DC offset in the potential of voltage signal Vtia caused by control current Iagc2cnt.

[0235] Next, the relationship between the variable resistor circuit 53 and the variable resistor circuit 80 will be described. At the input terminal of the TIA unit 11, an amplitude of up to about 100 mV is generated by the current signal Iin. As a result of this potential fluctuation, the drain-source voltage Vds of the field-effect transistors 57 and 82 may fluctuate. As described above, the drain of the field-effect transistor 57 and the source of the field-effect transistor 82 are commonly connected to the input terminal 10a (the input terminal of the TIA unit 11), and the source of the field-effect transistor 57 and the drain of the field-effect transistor 82 are commonly connected to the output terminal of the reference voltage generating circuit 12 (voltage amplifier 12a). Therefore, as a result of the above-mentioned potential fluctuation, the drain-source voltage Vds of the field-effect transistor 57 and the field-effect transistor 82 are generated in opposite directions (opposite polarity).

[0236] The variable resistor circuit 53 and the variable resistor circuit 80 are connected in parallel between the input terminal 10a and the output terminal of the reference voltage generating circuit 12. Therefore, the combined resistance value R of the variable resistor circuit 53 and the variable resistor circuit 80 viewed from the input terminal 10a (the input of the TIA unit 11) is AGCT , resistance value R AGC1 and resistance value R AGC2 The relationship of formula (11) is satisfied. Here, the field effect transistor 57 and the field effect transistor 82 are transistors of the same structure, have the same size, and have the same electrical characteristics. That is, the inherent gain β, gate-source voltage Vgs0, and threshold voltage Vth of the field effect transistor 57 are equal to the inherent gain β, gate-source voltage Vgs0, and threshold voltage Vth of the field effect transistor 82. In this case, the resistance value R AGC1 And the resistance value R AGC2 Both are expressed by formula (5), but the drain-source voltage Vds of opposite polarity is generated in the field effect transistor 57 and the field effect transistor 82, so the drain-source voltage Vds generated in the field effect transistor 57 is set to "+Vds", and the drain-source voltage Vds generated in the field effect transistor 82 is set to "-Vds".

[0237]

Mathematical formula 11

[0238]

[0239] By rearranging equation (11), we can obtain equation (12). As shown in equation (12), the synthetic resistance value R AGCT It does not contain the drain-source voltage Vds component, so it does not change due to the drain-source voltage Vds. Therefore, the combined resistance value R AGCTThe resistance value no longer depends on the drain-source voltage Vds, and does not fluctuate from the value when the drain-source voltage Vds is 0 V. This allows the AC component to be extracted from the photocurrent Ipd with low distortion.

[0240]

Mathematical formula 12

[0241]

[0242] For example, when the potential at the input terminal of the TIA unit 11 fluctuates and the potential of the input terminal 10a increases by a voltage Δvds compared to the reference voltage signal Vref, the drain-source voltage Vds of the field effect transistor 57 becomes +Δvds, and the drain-source voltage Vds of the field effect transistor 82 becomes -Δvds. At this time, in the variable resistor circuit 53, the current Δids based on the voltage Δvds flows from the resistor terminal 53b to the resistor terminal 53c. On the other hand, in the variable resistor circuit 80, the current Δids based on the voltage Δvds flows from the resistor terminal 80b to the resistor terminal 80c. These currents Δids flow in opposite directions relative to the reference voltage generating circuit 12 and cancel each other out. Therefore, the reference voltage signal Vref of the reference voltage generating circuit 12 is substantially constant regardless of the photocurrent Ipd. As a result, the reference voltage signal Vref is stabilized, and the drain-source voltage Vds gives the combined resistance value R AGCT That is, the variable resistance circuit 53 and the variable resistance circuit 80 are in a relationship of compensating for nonlinearity. Therefore, in the transimpedance amplifier circuit 10C, the current signal Iin can be amplified without distorting the current signal Iin.

[0243] Next, the operation and effects of the transimpedance amplifier circuit 10C will be described. Figure 24A Yes Figure 21 A graph showing changes in total harmonic distortion relative to the average power of input light in the transimpedance amplifier circuit shown. Figure 24B Yes Figure 21 Graph showing changes in the output amplitude of the TIA section relative to the average power of input light in the transimpedance amplifier circuit shown. Figure 25A Graphs showing changes in total harmonic distortion with respect to input light average power in the transimpedance amplifier circuit of the third comparative example. Figure 25B Graphs showing changes in the output amplitude of the TIA portion relative to the average power of input light in the transimpedance amplifier circuit of the third comparative example.

[0244] Figure 24A 、 Figure 24B 、 Figure 25A as well as Figure 25B The horizontal axis represents the average value of the optical input power of the optical signal Pin, that is, the input light average power Pin_ave (unit: dBm). Figure 24A as well as Figure 25A The vertical axis represents the total harmonic distortion (THD) (unit: %) of the output waveform (the waveform of the differential voltage signals Vout and Voutb). Figure 24B as well as Figure 25B The vertical axis represents the amplitude of the voltage signal Vtia (unit: mVpp).

[0245] Figure 24A as well as Figure 24B The calculation results shown are calculation results in the transimpedance amplifier circuit 10C (hereinafter referred to as “third embodiment”). Figure 25A as well as Figure 25B The calculation results shown are the calculation results of the transimpedance amplifier circuit of the third comparative example (hereinafter referred to as the "third comparative example"). The transimpedance amplifier circuit of the third comparative example is different from the transimpedance amplifier circuit 10C mainly in that it does not include the variable resistor circuit 80 and that the resistance value R of the field effect transistor 57 is set to AGC1 The difference is that the configuration of the transimpedance amplifier circuit of the third comparative example is half that of the transimpedance amplifier circuit 10C. That is, the configuration of the transimpedance amplifier circuit of the third comparative example is the same as that of the transimpedance amplifier circuit of the second comparative example.

[0246] The current value of the bias current Iofs is set so that the AGC operates when the input light average power Pin_ave exceeds -1dBm. As the total harmonic distortion, the total harmonic distortion taking into account the 10th harmonic is calculated. In order to avoid distortion in the differential amplifier circuit 13A in the subsequent stage, the size of the field effect transistor 57 is determined so that the amplitude of the voltage signal Vtia does not exceed 500mVpp. The gain (voltage gain) of the TIA unit 11 is set to 10 times, and the resistance value of the feedback resistor element 11b is set to 550Ω. As the optical signal Pin, an optical signal obtained by intensity modulation with a 1GHz sine wave is used, and the amplitude of the optical signal Pin is set to be the same as the input light average power Pin_ave (extinction ratio is about 5dB). The photoelectric conversion gain of the light receiving element PD is set to 1.0A / W to simplify the calculation.

[0247] right Figure 24A and Figure 25A By comparison, it can be seen that when the average power of the input light Pin_ave is 3dBm, the THD in the third comparative example is 5.2%, while the THD in the third embodiment is reduced to 4.1%. Figure 24B and Figure 25BComparison shows that the amplitude of the voltage signal Vtia is controlled similarly in the third comparative example and the third embodiment. In other words, while the amount of AC bypass current Iagc1 extracted in the third embodiment is similar to that in the third comparative example, the THD of the third embodiment is improved compared to that of the third comparative example.

[0248] In the third embodiment, the drain-source voltage Vds in the variable resistor circuit 53 and the drain-source voltage Vds in the variable resistor circuit 80 change complementarily, so the resistance value R of the field effect transistor 57 changes. AGC1 The distortion is controlled by the resistance value R of the field effect transistor 82 AGC2 That is, the connection point of the drain and source of the field effect transistor 82 is reversed (exchanged) with the connection point of the drain and source of the variable resistance circuit 53. Therefore, when the drain-source voltage Vds in the variable resistance circuit 53 is a positive value, the drain-source voltage Vds in the field effect transistor 82 is a negative value. Therefore, as shown in equations (11) and (12), the variable resistance circuits 53 and 80 are connected with the resistance value R of the field effect transistor 57. AGC1 The distortion and resistance value R of field effect transistor 82 AGC2 The distortions cancel each other out.

[0249] As described above, in the transimpedance amplifier circuit 10C, the bypass circuit 15C generates a DC bypass current Iaoc, an AC bypass current Iagc1, and an AC bypass current Iagc2. These DC bypass current Iaoc, AC bypass current Iagc1, and AC bypass current Iagc2 are extracted from the photocurrent Ipd generated by the light-receiving element PD, thereby generating a current signal Iin. Furthermore, the TIA unit 11 converts the current signal Iin into a voltage signal Vtia, and the differential amplifier circuit 13A generates differential voltage signals Vout and Voutb based on the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref.

[0250] In variable resistor circuit 53, field-effect transistor 56 is diode-connected. Therefore, when the drain of field-effect transistor 56 receives control current Iagc1cnt, a gate-source voltage Vgs2 is generated between the gate and source of field-effect transistor 56. The gate of field-effect transistor 56 is electrically connected to the gate of field-effect transistor 57, and the source of field-effect transistor 56 is electrically connected to the source of field-effect transistor 57. Therefore, the gate-source voltage of field-effect transistor 57 is equal to gate-source voltage Vgs2. A reference voltage signal Vref is supplied to the source of field-effect transistor 57, and the drain of field-effect transistor 57 is electrically connected to input terminal 10a. Therefore, there is almost no potential difference between the drain and source of field-effect transistor 57. Consequently, field-effect transistor 57 operates in a (deeper) triode region. Consequently, field-effect transistor 57 functions as a variable resistor, and the output impedance of the drain of field-effect transistor 57 is reduced.

[0251] Similarly, in variable resistor circuit 80, field-effect transistor 81 is diode-connected. Therefore, when the drain of field-effect transistor 81 receives control current Iagc2cnt, a gate-source voltage Vgs3 is generated between the gate and source of field-effect transistor 81. The gate of field-effect transistor 81 is electrically connected to the gate of field-effect transistor 82, and the source of field-effect transistor 81 is electrically connected to the source of field-effect transistor 82. Therefore, the gate-source voltage of field-effect transistor 82 is equal to gate-source voltage Vgs3. A reference voltage signal Vref is supplied to the drain of field-effect transistor 82, and the source of field-effect transistor 82 is electrically connected to input terminal 10a. Therefore, there is almost no potential difference between the drain and source of field-effect transistor 82. As a result, field-effect transistor 82 operates in the (deeper) triode region. Therefore, field-effect transistor 82 functions as a variable resistor, and the output impedance of the source of field-effect transistor 82 becomes low.

[0252] There is almost no potential difference between the drain and source of field-effect transistor 57, and there is almost no potential difference between the drain and source of field-effect transistor 82. Therefore, the DC component of photocurrent Ipd hardly flows into field-effect transistors 57 and 82, but the AC component of photocurrent Ipd can flow into field-effect transistors 57 and 82 as AC bypass currents Iagc1 and Iagc2. The difference (differential current) between the current generated by amplifying control current Icnt and bias current Iofs is amplified by an amplification factor γ to obtain control currents Iagc1cnt and Iagc2cnt. Therefore, when control current Icnt exceeds the current value of bias current Iofs, control currents Iagc1cnt and Iagc2cnt increase as control current Icnt increases, and gate-source voltages Vgs2 and Vgs3 also increase. Therefore, when the photocurrent Ipd has a low or moderate signal strength, the extraction of the AC bypass currents Iagc1 and Iagc2 is suppressed, thereby preventing attenuation of the AC component of the photocurrent Ipd. When the photocurrent Ipd has a high signal strength, the AC component of the photocurrent Ipd is extracted from the photocurrent Ipd as the AC bypass currents Iagc1 and Iagc2, thereby attenuating the AC component of the photocurrent Ipd. In this manner, the gain of the transimpedance amplifier circuit 10C is controlled by the variable resistor circuits 53 and 80.

[0253] The resistance value R of the field effect transistor 57 AGC1 and the resistance value R of the field effect transistor 82 of the variable resistance circuit 80 AGC2 The voltage Vds between the drain and source is included, and therefore may vary depending on the voltage Vds between the drain and source. In the field effect transistor 57, the reference voltage signal Vref is supplied to the source, and the drain is electrically connected to the input terminal 10a. In contrast, in the field effect transistor 82, the reference voltage signal Vref is supplied to the drain, and the source is electrically connected to the input terminal 10a. Therefore, the polarity of the voltage Vds between the drain and source of the field effect transistor 57 and the polarity of the voltage Vds between the drain and source of the field effect transistor 82 are opposite to each other. Therefore, the combined resistance value R of the variable resistance circuit 53 and the variable resistance circuit 80 observed from the input terminal 10a is AGCT In the embodiment, the component of the drain-source voltage Vds of the field effect transistor 57 and the component of the drain-source voltage Vds of the field effect transistor 82 cancel each other. AGCT The signal fluctuates due to the drain-source voltage Vds of the field effect transistor 57 and the drain-source voltage Vds of the field effect transistor 82. As a result, the occurrence of distortion is suppressed, and thus the signal quality can be improved.

[0254] It should be noted that the gain of the transimpedance amplifier circuit 10C changes based on the combined output impedance of the output impedance of the resistor terminal 53b and the output impedance of the resistor terminal 80c. This combined output impedance, like the output impedance of the resistor terminal 53b of the variable resistor circuits 53 and 53B, can be determined by considering the input impedance Zin of the TIA unit 11. For example, when the gain variable ratio of the TIA unit 11 is set to A (A is a real number greater than 1), the combined output impedance is set to Zin / (A-1). Therefore, when the value of the current signal Iin of the TIA unit 11 when AGC is not being performed is set to Iinoff, the value of the current signal Iin when AGC is being performed is Iinon = Iinoff / A. For example, when A = 2, the combined output impedance is approximately equal to Zin. When A is greater than 2, the combined output impedance is smaller than Zin. Therefore, when AGC and AGC are performed simultaneously, the output impedance of the output terminal 52b is set to be greater than the combined output impedance. Furthermore, when AGC is not being performed, the combined output impedance can be set to be greater than 100×Zin. The combined output impedance can be considered to be the same as the combined resistance value R AGCT The input impedance Zin and the combined output impedance can have frequency characteristics different from each other, and therefore it is sufficient that the above relationship is satisfied at least within a predetermined frequency range (frequency band).

[0255] The bypass circuit 15C includes a feedback current source 52 that generates a DC bypass current Iaoc based on a control current Icnt, a variable resistor circuit 53 that generates an AC bypass current Iagc1 based on the control current Icnt, and a variable resistor circuit 80 that generates an AC bypass current Iagc2 based on the control current Icnt. The control circuit 51C controls the feedback current source 52 so that the DC bypass current Iaoc increases as the control current Icnt increases. When the control current Icnt exceeds the current value of the bias current Iofs, the variable resistor circuits 53 and 80 are controlled so that the AC bypass currents Iagc1 and Iagc2 increase as the control current Icnt increases. This configuration allows control to remove the DC component (DC offset control) and gain control of the transimpedance amplifier circuit 10C to be achieved using a single control loop, thereby suppressing an increase in circuit size.

[0256] In feedback current source 52, field-effect transistor 54 is diode-connected. Therefore, when the drain of field-effect transistor 54 receives control current Iaoccnt, a gate-source voltage Vgs1 is generated between the gate and source of field-effect transistor 54. The gate of field-effect transistor 54 is electrically connected to the gate of field-effect transistor 55, and the source of field-effect transistor 54 is electrically connected to the source of field-effect transistor 55. Therefore, the gate-source voltage of field-effect transistor 55 is equal to gate-source voltage Vgs1. The source of field-effect transistor 55 is electrically connected to the source of field-effect transistor 54, i.e., ground potential GND, and the drain of field-effect transistor 55 is electrically connected to input terminal 10a. This increases the potential difference between the source and drain of field-effect transistor 55. Consequently, field-effect transistor 55 operates in a saturation region. Consequently, field-effect transistor 55 functions as a current source, and the output impedance of the drain of field-effect transistor 55 increases. Therefore, the AC component of the photocurrent Ipd barely flows into the field-effect transistor 55, but the DC component of the photocurrent Ipd can flow into the field-effect transistor 55 as a DC bypass current Iaoc. Furthermore, as the control current Icnt increases, the gate-source voltage Vgs1 of the field-effect transistor 54 increases, correspondingly increasing the drain current of the field-effect transistor 55. Thus, the DC component of the photocurrent Ipd is extracted from the photocurrent Ipd as a DC bypass current Iaoc, appropriately removing the DC component from the photocurrent Ipd. It should be noted that the output impedance of the output terminal 52b can be determined by considering the input impedance of the TIA unit 11. For example, if the input impedance of the TIA unit 11 is Zin, the output impedance of the output terminal 52b can be set to be greater than 100×Zin. The input impedance Zin and the output impedance of the output terminal 52b can have different frequency characteristics, so it is sufficient that this relationship is satisfied at least within a predetermined frequency range (band).

[0257] In variable resistor circuit 80, control current Iagc2cnt flows from the drain to the source of field-effect transistor 81. Since the source of field-effect transistor 81 is electrically connected to input terminal 10a, control current Iagc2cnt flows toward input terminal 10a (the input terminal of TIA unit 11), increasing the DC component of photocurrent Ipd. In contrast, DC bypass current Iaoc is set to include control current Iagc2cnt, thereby removing the DC component caused by control current Iagc2cnt from photocurrent Ipd. As a result, a DC offset in the potential of voltage signal Vtia caused by control current Iagc2cnt can be suppressed.

[0258] The reference voltage generation circuit 12 includes a voltage amplifier 12a and a feedback resistor element 12b electrically connected between the input and output of the voltage amplifier 12a. With this configuration, the output impedance of the reference voltage generation circuit 12 is low over a wide frequency range. In other words, the impedance of the variable resistor circuits 53 and 80 as viewed from the input terminals of the TIA unit 11 is low over a wide frequency range. Consequently, the AC bypass currents Iagc1 and Iagc2 can be easily extracted from the photocurrent Ipd.

[0259] Since DC bias control is performed using the high-impedance feedback current source 52, the effect on the AC component of the photocurrent Ipd is minimal (the AC component does not flow into the feedback current source 52). Meanwhile, gain control is performed by biasing the AC component of the photocurrent Ipd using the variable resistor circuits 53 and 80. Since the drain and source potentials of the field-effect transistors 57 and 82 are substantially equal, the effect on the DC component of the photocurrent Ipd is minimal (the DC component does not flow into the variable resistor circuits 53 and 80). As a result, interference between the control for removing the DC component and the gain control can be avoided.

[0260] As described above, the transimpedance amplifier circuit 10C can be controlled using a single control loop without causing interference between the gain control of the transimpedance amplifier circuit 10C and the DC offset control for making the difference ΔVtia zero, and can perform gain control with low distortion.

[0261] It should be noted that the transimpedance amplifier circuit disclosed herein is not limited to the above-mentioned embodiments.

[0262] The circuit configuration of the TIA unit 11, reference voltage generation circuit 12, differential amplifier circuit 13A, control current generation circuit 14A, and bypass circuits 15, 15B, and 15C is not limited to that shown in the above embodiment. For example, the TIA unit 11 can be configured to convert the current signal Iin into the voltage signal Vtia. The reference voltage generation circuit 12 can be configured to supply the reference voltage signal Vref. The differential amplifier circuit 13A does not need to include the output amplifier 13b.

[0263] The control current generating circuit 14A may not include the diode 48. In this case, the variation of the control time constant caused by the variation of the signal strength of the burst optical signal can also be suppressed. The control current generating circuit 14A may also include another circuit element for fixing the difference ΔVin so as to prevent the difference ΔVin from falling below a predetermined negative value instead of the diode 48. OTA42A is not limited to Figure 4 as well as Figure 7 The circuit structure shown can generate Figure 5 The control current Icnt shown is sufficient. OTA42A can also generate Figure 5 The portion of the control current Icnt shown as being 0 or greater is the control current Icnt.

[0264] The control circuit 51 is not limited to Figure 9 The circuit structure shown can generate Figure 8 The control circuit 51C is not limited to the control current Iaoccnt and the control current Iagc1cnt shown. Figure 23 The circuit structure shown can generate Figure 22 The control currents Iaoccnt, Iagc1cnt, and Iagc2cnt shown in the figure are sufficient.

[0265] The feedback current source 52 only needs to be configured to generate the DC bypass current Iaoc so that the DC bypass current Iaoc increases as the control current Iaoccnt increases. For example, the feedback current source 52 may include a resistor element configured to change the gate-source voltage of the field-effect transistor 55 according to the control current Iaoccnt, instead of the diode-connected field-effect transistor 54. The source of the field-effect transistor 55 does not need to be electrically connected to the ground potential GND; the source potential of the field-effect transistor 55 can be set so that the field-effect transistor 55 operates in the saturation region. In other words, the source potential of the field-effect transistor 55 is set so that the drain potential of the field-effect transistor 55 is greater than the source potential of the field-effect transistor 55.

[0266] The variable resistor circuit 53 only needs to be configured to generate the AC bypass current Iagc1 so that the AC bypass current Iagc1 increases as the control current Iagc1cnt increases. Instead of the diode-connected field-effect transistor 56, the variable resistor circuit 53 can include a resistor element configured to change the gate-source voltage of the field-effect transistor 57 according to the control current Iagc1cnt. The source of the field-effect transistor 57 does not need to be electrically connected to the output terminal of the reference voltage generation circuit 12. The source potential of the field-effect transistor 57 can be set so that the field-effect transistor 57 operates in the triode region. In other words, the source potential of the field-effect transistor 57 is set so that the drain potential of the field-effect transistor 57 is approximately equal to the source potential of the field-effect transistor 57.

[0267] The transimpedance amplifier circuits 10A, 10B, and 10C do not need to include the reference voltage generating circuit 12 . The transimpedance amplifier circuits 10A, 10B, and 10C may be supplied with the reference voltage signal Vref from an external reference voltage generating circuit.

[0268] In the above embodiment, the magnitude of the control current Iaoccnt (DC bypass current Iaoc) is adjusted by the amplification factor α. However, it may be adjusted by the current mirror ratio of transistors 61 and 62 instead, or by both the amplification factor α and the current mirror ratio of transistors 61 and 62. Similarly, the magnitude of the DC bypass current Iaoc may also be adjusted by the current mirror ratio of field-effect transistors 54 and 55.

[0269] In the above embodiment, the magnitude of the control current Iagc1cnt (AC bypass current Iagc1) is adjusted by the amplification factor γ and the current value of the bias current Iofs. However, instead of the amplification factor γ, the magnitude of the control current Iagc1cnt (AC bypass current Iagc1) can be adjusted by the current mirror ratio of the transistors 61 and 63. Alternatively, the magnitude of the control current Iagc1 can be adjusted by the amplification factor γ, the current mirror ratio of the transistors 61 and 63, and the current value of the bias current Iofs. Similarly, the magnitude of the AC bypass current Iagc1 can be adjusted by the size of the field-effect transistor 56 and the size of the field-effect transistor 57, etc.

[0270] In the above embodiment, field effect transistors are used as the field effect transistors 54 and 55 and the transistors 21a to 21d, 22a to 22d, 23a, 24a, 25a, 25b, 61 to 69, 71, and 72. However, the field effect transistors 54 and 55 and the transistors 21a to 21d, 22a to 22d, 23a, 24a, 25a, 25b, 61 to 69, 71, and 72 may be bipolar transistors. When the field effect transistors 54 and 55 and the transistors 21a to 21d, 22a to 22d, 23a, 24a, 25a, 25b, 61 to 69, 71, and 72 are bipolar transistors, the gate, source, and drain of the field effect transistors are referred to as the base, emitter, and collector, respectively.

[0271] Bypass circuit 15 does not need to use a single control loop to control feedback current source 52 and variable resistor circuit 53. Bypass circuit 15B does not need to use a single control loop to control feedback current source 52 and variable resistor circuit 53B. Bypass circuit 15C does not need to use a single control loop to control feedback current source 52, variable resistor circuit 53, and variable resistor circuit 80.

[0272] The potential of the substrate terminal of the field effect transistor 57 does not have such a significant influence on the gate potential. Therefore, the variable resistor circuit 53B may not include the resistor element 59 (i.e., the resistance value Rb=0), and the field effect transistor 57 may not be configured so that the capacitance Cdb and the capacitance Csb are equal to each other. In this case, the differential resistance value (resistance value R AGC1) varies due to the drain-source voltage Vds. As a result, the occurrence of distortion is suppressed, thereby improving signal quality.

[0273] Typically, the input impedance of the dummy TIA is approximately 10 to 100 Ω, similar to the input impedance of the TIA unit 11, and the output impedance of the dummy TIA is approximately several Ω. Both the input and output terminals of the dummy TIA generate a reference voltage signal Vref of approximately the same potential, so either terminal can be used as the output terminal of the reference voltage generation circuit 12. The output impedance of the dummy TIA is lower than the input impedance, so by using the output terminal of the dummy TIA as the output terminal of the reference voltage generation circuit 12, the resistance value R can be increased. AGC1 And the resistance value R AGC2 , it is possible to reduce the size of the field effect transistors 57 and 82. In other words, it is possible to reduce the parasitic capacitance of the field effect transistors 57 and 82, and to improve the high frequency characteristics of the transimpedance amplifier circuit 10C.

[0274] In the transimpedance amplifier circuit 10C, the field effect transistor 57 and the field effect transistor 82 are transistors of the same structure, have the same size, and have the same electrical characteristics. However, the electrical characteristics of the field effect transistor 57 may not be consistent with the electrical characteristics of the field effect transistor 82. In this case, the influence of the drain-source voltage Vds can be reduced by the variable resistance circuits 53 and 80, and the combined resistance value R can be compensated. AGCT Nonlinearity.

Claims

1. A transimpedance amplifier circuit that generates a differential voltage signal based on an input current signal generated by a light-receiving element. The transimpedance amplifier circuit has: An input terminal, receiving the input current signal; Single-input amplifier circuit, converting current signal into voltage signal; a differential amplifier circuit for generating the differential voltage signal according to a difference between the voltage signal and a reference voltage signal; a control current generating circuit for generating a control current based on the difference; as well as a bypass circuit that generates a DC bypass current and an AC bypass current according to the control current, The current signal is generated by extracting the DC bypass current and the AC bypass current from the input current signal. The bypass circuit comprises: a control circuit into which the control current is input; a feedback current source, generating the DC bypass current according to the control current; and a variable resistance circuit, generating the AC bypass current according to the control current, The control current generating circuit comprises: an integrating circuit for integrating the difference to generate a differential integrated signal; as well as a transconductance amplifier circuit that generates the control current according to the differential integration signal through a first transconductance when the value of the differential integration signal is less than a threshold value, and generates the control current according to the differential integration signal through a second transconductance greater than the first transconductance when the value of the differential integration signal is greater than the threshold value, The control circuit controls the feedback current source so that the DC bypass current increases as the control current increases, and controls the variable resistance circuit so that the AC bypass current increases as the control current increases when the control current exceeds a predetermined bias current value.

2. The transimpedance amplifier circuit according to claim 1, wherein: The transconductance amplifier circuit has: a first transconductance circuit generating a first output current based on the differential integrated signal; as well as a second transconductance circuit that generates a second output current based on the differential integrated signal; The transconductance amplifier circuit generates the control current by adding the first output current and the second output current. The first transconductance circuit operates in a first range of values ​​of the differential integrated signal such that the first output current decreases as the value of the differential integrated signal increases. The second transconductance circuit operates in a second range of values ​​of the differential integrated signal such that the second output current increases as the value of the differential integrated signal increases. The upper limit value of the second range is smaller than the upper limit value of the first range, and the lower limit value of the second range is larger than the lower limit value of the first range.

3. The transimpedance amplifier circuit according to claim 1 or 2, wherein: The integrating circuit comprises: a first output terminal for outputting an inverted component of the differential integrated signal; a second output terminal for outputting a positive phase component of the differential integral signal; as well as a diode provided between the first output terminal and the second output terminal, The difference is a value obtained by subtracting the voltage signal from the reference voltage signal. The anode of the diode is electrically connected to the first output terminal, A cathode of the diode is electrically connected to the second output terminal.

4. The transimpedance amplifier circuit according to claim 1 or 2, wherein: The control circuit generates a first control current by amplifying the control current at a first amplification ratio, The feedback current source has: a first field effect transistor having a first drain receiving the first control current, a first gate electrically connected to the first drain, and a first source electrically connected to a ground potential; and a second field effect transistor having a second drain electrically connected to the input terminal, a second gate electrically connected to the first drain and the first gate, and a second source electrically connected to the first source; The feedback current source causes the DC bypass current to flow from the second drain to the second source according to the first control current.

5. The transimpedance amplifier circuit according to claim 1 or 2, wherein: The control circuit generates a bias current set to the bias current value, and amplifies a difference current between a current generated by amplifying the control current and the bias current at a second amplification factor to generate a second control current. The variable resistance circuit comprises: a third field effect transistor having a third drain receiving the second control current, a third gate electrically connected to the third drain, and a third source supplied with the reference voltage signal; as well as a fourth field effect transistor having a fourth drain electrically connected to the input terminal, a fourth gate electrically connected to the third drain and the third gate, and a fourth source electrically connected to the third source, The variable resistance circuit extracts the AC bypass current from the input current signal according to the second control current.

6. The transimpedance amplifier circuit according to claim 5, wherein: The variable resistance circuit further includes a first resistance element, The third field effect transistor further includes a first substrate terminal to which the reference voltage signal is supplied. The fourth field effect transistor further includes a second substrate terminal to which the reference voltage signal is supplied. The fourth gate is electrically connected to the third drain and the third gate via the first resistor. The fourth field effect transistor is configured such that a first capacitance between the fourth gate and the fourth drain and a second capacitance between the fourth gate and the fourth source are equal to each other. The resistance value of the first resistance element is greater than the impedance formed by the first capacitor.

7. The transimpedance amplifier circuit according to claim 6, wherein: The variable resistance circuit further includes a second resistance element, supplying the reference voltage signal to the second substrate terminal via the second resistor element, The fourth field effect transistor is configured such that a third capacitance between the second substrate terminal and the fourth drain and a fourth capacitance between the second substrate terminal and the fourth source are equal to each other. The resistance value of the second resistance element is greater than the impedance formed by the third capacitor.

8. The transimpedance amplifier circuit according to claim 5, wherein: The bypass circuit also generates another AC bypass current, The current signal is generated by also extracting the further AC bypass current from the input current signal, The bypass circuit further includes another variable resistance circuit for generating the another AC bypass current according to a third control current. The control circuit generates the third control current by amplifying the difference current at the second amplification rate, The other variable resistance circuit comprises: a fifth field effect transistor having a fifth drain receiving the third control current, a fifth gate electrically connected to the fifth drain, and a fifth source electrically connected to the input terminal; as well as a sixth field effect transistor having a sixth drain to which the reference voltage signal is supplied, a sixth gate electrically connected to the fifth drain and the fifth gate, and a sixth source electrically connected to the fifth source; The another variable resistance circuit extracts the another AC bypass current from the input current signal according to the third control current.

9. The transimpedance amplifier circuit according to claim 8, wherein: The DC bypass current is set to include the third control current flowing from the other variable resistance circuit.

10. The transimpedance amplifier circuit according to claim 1 or 2, wherein: The transimpedance amplifier circuit further includes a reference voltage generating circuit for generating the reference voltage signal. The reference voltage generation circuit includes an amplifier and a feedback resistance element electrically connected between an input and an output of the amplifier.

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