Gain control circuit and method for instrument amplifier

Abstract

An instrumentation amplifier with electronically adjustable gain is disclosed. The gain is adjusted by electronically controlling a resistor coupled to a feedback portion of the instrumentation amplifier. The resistor is adjusted by a switch controlled by a resistor-controlled signal referenced by a common-mode voltage present at the input of the instrumentation amplifier. Thus, the instrumentation amplifier can accommodate a high range of common-mode voltages while still providing controllable gain.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 16 / 668,557, filed October 30, 2019, which claims the benefit of U.S. Provisional Application No. 62 / 882,090, filed August 2, 2019. The entire contents of these patent applications are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to instrumentation amplifiers, and more particularly to gain control circuits and methods for instrumentation amplifiers. Background Art

[0004] The instrumentation amplifier amplifies two input signals (for example, V IN+ 、V IN- ) while rejecting signals common to both inputs (e.g., common-mode voltage V CM The output of the instrument amplifier (V OUT ) is relative to the reference (V REF ) and can therefore be a single-ended output (e.g., V REF = ground) or a differential output with a common mode offset from the reference. For example, the formula for an instrumentation amplifier with a gain (G) is given by:

[0005] V OUT =G×(V IN+ -V IN- )+V REF

[0006] High-voltage (HV) instrumentation amplifiers can have large (>100) gains and can reject large common-mode voltages (e.g., >12V). Instrumentation amplifiers can have gains that can be set to a desired value but, once set, cannot be easily controlled to other values. Therefore, a gain control circuit for the instrumentation amplifier is required to electronically control the gain of the instrumentation amplifier. Summary of the Invention

[0007] In at least one aspect, the present disclosure generally describes a circuit including an instrumentation amplifier and a gain control circuit. The gain control circuit is coupled to the instrumentation amplifier and configured to control the gain of the instrumentation amplifier to one of a plurality of possible gain values. The control is based on: (i) gain select signals received at a plurality of gain select inputs; and (ii) a common-mode voltage corresponding to input signals received at the positive and negative inputs of the instrumentation amplifier.

[0008] In another aspect, the present disclosure generally describes a method for adjusting the gain of an instrumentation amplifier. The method includes extracting a common-mode voltage from an input of the instrumentation amplifier. The method also includes receiving a gain select signal and then generating a plurality of resistor control signals using a gain decoder circuit based on the gain select signal and the common-mode voltage. The resistance of an internal controlled resistor is then set based on the plurality of resistor control signals, and the gain of the instrumentation amplifier is adjusted based on the resistance of the internal controlled resistor circuit.

[0009] In another aspect, the present disclosure generally describes an adjustable-gain instrumentation amplifier. The adjustable-gain instrumentation amplifier includes a dual-stage opamp instrumentation amplifier or a triple-stage opamp instrumentation amplifier (i.e., a dual-stage or triple-stage opamp instrumentation amplifier). The adjustable-gain instrumentation amplifier also includes an internal controlled resistor coupled to the dual-stage or triple-stage opamp instrumentation amplifier, and the gain of the dual-stage or triple-stage opamp instrumentation amplifier is based on the resistance of the internal controlled resistor. The adjustable-gain instrumentation amplifier also includes a gain decoder coupled to the internal controlled resistor. The gain decoder is configured to control the resistance of the internal controlled resistor based on a gain select signal received at a first gain select input and a second gain select input of the gain decoder. The adjustable-gain instrumentation amplifier also includes a common-mode extractor coupled to the dual-stage or triple-stage opamp instrumentation amplifier. The common-mode extractor is configured to determine a common-mode voltage based on the inputs of the dual-stage or triple-stage opamp instrumentation amplifier. The common-mode voltage is transmitted to the gain decoder, which is configured to shift the resistor control signal provided to the internal controlled resistor by the common-mode voltage.

[0010] The foregoing illustrative summary, as well as other exemplary objects and / or advantages of the present disclosure, and implementations are further explained in the following detailed description and its accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A block diagram of a possible adjustable gain instrumentation amplifier circuit according to an embodiment of the present disclosure is shown.

[0012] Figure 2A Schematically shows the Figure 1 The adjustable gain instrumentation amplifier circuit is used together with the first instrumentation amplifier implementation.

[0013] Figure 2B Schematically shows the Figure 1 A second instrumentation amplifier implementation is used in conjunction with an adjustable gain instrumentation amplifier circuit.

[0014] Figure 3 Shown for Figure 1 Block diagram of the gain control circuit of an adjustable gain instrumentation amplifier circuit.

[0015] Figure 4 Shown for Figure 3 Detailed schematic diagram of the gain decoder circuit of the gain control circuit.

[0016] Figure 5A According to a first possible embodiment, Figure 1 Detailed schematic of an adjustable-gain instrumentation amplifier.

[0017] Figure 5B According to a second possible embodiment Figure 1 Detailed schematic of an adjustable-gain instrumentation amplifier.

[0018] Figure 6 is a flow chart of a method for adjusting the gain of an instrumentation amplifier according to a possible implementation of the present disclosure.

[0019] Like reference numerals designate corresponding parts throughout the several views of the drawings. DETAILED DESCRIPTION

[0020] The present disclosure includes an adjustable gain instrumentation amplifier circuit, wherein the gain of the instrumentation amplifier can be electronically adjusted to one of a plurality of gain values ​​via a gain control circuit. The adjustable gain instrumentation amplifier can accurately amplify the input differential mode voltage (V DM ), while ignoring (i.e., rejecting) the input common-mode voltage (V CM ). The disclosed circuit can operate at high voltages and is very versatile for the user due to the gain that can be set or adjusted via the gain select input.

[0021] Figure 1 1 is a block diagram of an adjustable gain instrumentation amplifier circuit 10. The adjustable gain amplifier circuit includes an instrumentation amplifier 100 that receives a first (i.e., positive) input signal (V IN+ ) and the second (ie, negative) input signal (V IN- ) is limited between the input differential mode voltage (V DM )(i.e., V DM =V IN+ -V IN- In some cases, the positive and negative input signals may share a non-zero common-mode voltage (V CM ), the non-zero common-mode voltage can be defined as the average value of the first signal and the second signal (ie, V CM =(V IN+ +VIN- ) / 2). In a high voltage (HV) embodiment, V CM Can be much higher than V DM For example, for a supply voltage of 36 volts (V), V DM can be in the range of -0.75V to +0.75V, and V CM The adjustable gain instrumentation amplifier circuit 10 is configured to amplify V DM and suppress V CM .

[0022] The adjustable gain instrumentation amplifier circuit 10 includes an instrumentation amplifier circuit (ie, instrumentation amplifier) ​​100 configured to amplify V by a gain (G). DM , to generate a reference signal (V REF ) (e.g., a reference input signal) output signal (V OUT ). The gain (G) of the instrumentation amplifier 100 can be adjusted by a plurality of gain select signals (GS1, GS2) at a plurality of gain select inputs 25, 30. The adjustable gain instrumentation amplifier circuit 10 is driven by a high rail (i.e., positive supply) voltage (V DD ) and the low rail (ie, negative supply) voltage (V SS ) power supply. The difference between the positive voltage and the negative voltage (i.e., V DD -V SS ) is the supply voltage and, for embodiments of the adjustable gain instrumentation amplifier circuit, can be in the range of 4 volts to 36 volts.

[0023] In some embodiments, adjustable gain instrumentation amplifier circuit 10 is included in a discrete package. For these embodiments, the input, output, and reference terminals described above may be embodied as pins of the discrete package to serve as physical electrical connection points for other circuits and components.

[0024] As mentioned, the specific gain of adjustable-gain instrumentation amplifier circuit 10 may depend on a specific combination of gain select signals (GS1, GS2). In other words, the instrumentation amplifier may have discrete gain values ​​that are determined (i.e., selected) by the gain select combination of the gain select signals at the gain selector pins of adjustable-gain instrumentation amplifier circuit 10. Thus, the number of selectable gain values ​​may correspond to the unique combinations of gain select signals at the gain select inputs: 2 n, where n is the number of gain select inputs; in the circuit of the present invention, n=2. Adjustable gain instrumentation amplifier circuit 10 includes gain control circuit 200, which receives and interprets the gain select signal and provides a resistor between first node 110 and second node 120 of instrumentation amplifier 100 to control the gain of the instrumentation amplifier.

[0025] like Figure 1 As shown, the adjustable gain instrumentation amplifier circuit 10 includes a first gain select input 25 and a second gain select input 30. Each gain select input receives a corresponding gain select signal. The gain select signal at each gain select input is a multi-level signal. For example, each gain select signal can have a voltage corresponding to one of two possible levels. In other words, each gain select signal can be a voltage corresponding to a logic high or a voltage corresponding to a logic low. The voltage corresponding to a logic high can be a positive supply voltage (V DD ), and the voltage corresponding to logic low can be the negative supply voltage (V SS ). The two gain select signals GS1 and GS2 provide four possible gain select combinations of voltages (e.g., low-low, low-high, high-low, and high-high). Gain control circuit 200 can interpret a particular gain select combination as corresponding to a particular gain value. Based on this interpretation, gain control circuit 200 can provide a specific resistor to instrumentation amplifier 100 to adjust the gain (G) of the instrumentation amplifier to a specific gain value. Thus, the gain (G) can be electronically adjusted to one of four discrete values. For example, the circuit disclosed in the present invention can be configured to provide possible gain values ​​within a range between 20 and 200 (including 20 and 200) (e.g., 20, 50, 100, and 200). The present disclosure is not limited to four possible gain values; variations may exist to facilitate more (or fewer) selectable gain values. For example, more (or fewer) gain select inputs may be provided. Additionally or alternatively, the gain select signal may have more (or fewer) possible values.

[0026] Figure 2A A first possible instrumentation amplifier for an adjustable gain instrumentation amplifier circuit is schematically shown. The instrumentation amplifier 100 is a two-stage opamp instrumentation amplifier including a first operational amplifier (i.e., opamp) OA1 and a second opamp OA2. The non-inverting terminal of the first opamp OA1 receives a negative input signal V IN- , while the non-inverting terminal of the second opamp OA2 receives the positive input signal V IN+ The reference voltage V applied to the reference terminal 55 of the instrumentation amplifier 100 REFThe output terminal 50 of the instrumentation amplifier is coupled to the inverting terminal of the first opamp OA1 via the resistor R2. The output terminal 50 of the instrumentation amplifier is coupled to the second opamp OA2. The gain of the instrumentation amplifier 100 is controlled by the resistors R1 and R2. Figure 2A For the embodiment shown, the gain (G) is given by the following formula.

[0027]

[0028] The gain can be adjusted by applying a resistor (i.e., internal resistor R3) between the first node 110 and the second node 120 of the instrumentation amplifier 100. In this configuration, the internal resistor R3 is placed in parallel with the two R1 resistors (i.e., resistor R1 with matched resistance), or in other words, half of R3 is connected to R1 (i.e., as shown in FIG. Figure 2A The upper R1 shown in FIG3 is connected in parallel, and half of R3 is connected in parallel with R1 (ie, Figure 2A When the internal resistors are added, the gain (G) is given by the following formula.

[0029]

[0030] Therefore, a specific internal resistor R3 can be coupled between first node 110 and second node 120 of instrumentation amplifier 100 to set the gain to a specific value corresponding to specific internal resistor R3. However, once the gain is set, this approach does not provide a convenient means for adjusting the gain. In contrast, the disclosed method utilizes gain control circuit 200 to provide an adjustable resistance (i.e., an adjustable internal controlled resistor) between first node 110 and second node 120 to adjust the gain of instrumentation amplifier 100. In other words, gain control circuit 200 can be configured to provide an electronically adjustable resistance R3.

[0031] Figure 2B A second possible instrumentation amplifier for an adjustable gain instrumentation amplifier circuit is schematically shown. The instrumentation amplifier 100 is a three-stage opamp instrumentation amplifier including a first operational amplifier (i.e., opamp) OA1 and a second opamp OA2. The non-inverting terminal of the first opamp receives a negative input signal V IN- , while the non-inverting terminal of the second opamp OA2 receives the positive input signal V IN+ The reference voltage V applied to the reference terminal 55 of the instrumentation amplifier 100 REFThe output terminal 50 of the instrumentation amplifier is coupled to the non-inverting terminal of the third opamp OA6 via resistor R7. The output terminal 50 of the instrumentation amplifier is coupled to the output of the third opamp OA6. Similar to the two-stage opamp instrumentation amplifier, the gain of the three-stage opamp instrumentation amplifier 100 can be controlled by the resistance between the first node 110 and the second node 120 of the instrumentation amplifier.

[0032] Figure 3 FIG. 1 is a block diagram of a gain control circuit 200 for an adjustable gain instrumentation amplifier circuit 10. The gain control circuit includes a common-mode extractor circuit portion (ie, common-mode extractor) 210. The common-mode extractor 210 receives a positive input signal (V IN+ ) and the negative input signal at the negative input (V IN- ) as input. Based on the input signal, the common mode extractor 210 outputs the common mode voltage (V CM ). The common mode voltage is coupled to a gain decoder circuit portion (ie, gain decoder) 400. Additionally, the gain decoder 400 receives a first gain select signal (GS1) at a first gain select input 25 and a second gain select signal (GS2) at a second gain select input 30.

[0033] The gain decoder 400 is configured to determine a gain value based on a combination of gain selection signals. Based on the determined gain value, a resistor control signal (e.g., G ) may be presented at one or more resistor control outputs 410, 420, 430, each corresponding to a gain value. 50 , G 100 , G 200 For example, if a gain value of 200 is determined based on GS1 and GS2, a resistor control signal (eg, a voltage) G may be provided at the resistor control output 430 corresponding to the gain of 200. 200 Similarly, the GS1 and GS2 voltages corresponding to gain values ​​of 100 and 50 can cause the resistor control signal G 100 and G 50 Each resistor control signal (G 50 , G 100 , G 200 ) are based on (i.e., relative to) the common-mode voltage (V CM ). To facilitate understanding, the following table 1 provides Figure 3 An exemplary table of signal values ​​for possible gain decoder implementations.

[0034] Table 1: Example signals associated with gain values ​​(G)

[0035] G <![CDATA[GS1]]> <![CDATA[GS2]]> <![CDATA[G 50 ]]> <![CDATA[G 100 ]]> <![CDATA[G 200 ]]> 20 <![CDATA[Low (V SS )]]> <![CDATA[Low (V SS )]]> <![CDATA[Low (V CM )]]> <![CDATA[Low (V CM )]]> <![CDATA[Low (V CM )]]> 50 <![CDATA[High (V DD )]]> <![CDATA[Low (V SS )]]> <![CDATA[High (V CM + ΔV)]]> <![CDATA[Low (V CM )]]> <![CDATA[Low (V CM )]]> 100 <![CDATA[Low (V SS )]]> <![CDATA[High (V DD )]]> <![CDATA[Low (V CM )]]> <![CDATA[High (V CM + ΔV)]]> <![CDATA[Low (V CM )]]> 200 <![CDATA[High (V DD )]]> <![CDATA[High (V DD )]]> <![CDATA[High (V CM + ΔV)]]> <![CDATA[High (V CM + ΔV)]]> <![CDATA[High (V CM + ΔV)]]>

[0036] As shown in Table 1, each gain selection signal (i.e., GS1 or GS2) is generated at the lower rail voltage (V SS ) is considered low, while at the high rail voltage (V DD ) is considered high. The gain select signal on each (i.e., both) gain select inputs forms a (high / low) combination corresponding to a specific gain value. Although any possible combination can correspond to any possible gain value, the possible gain values ​​(G) for the example shown in Table 1 are 20, 50, 100, and 200.

[0037] As shown in Table 1, each resistor control signal (G 50 , G 100 , G 200 ) are both at the common mode voltage (V CM ) is considered low, while the common-mode voltage plus the switch voltage (V CM +ΔV) is considered high. The resistor control signal can be used to switch the transistor to an on state (e.g., high = on) or an off state (e.g., low = off). The resistor control signal is offset by V CM Can help to provide a range of V CM Provide appropriate switching levels.

[0038] As with gain selection, the resistor control signals at multiple (e.g., three) resistor control outputs 410, 420, and 430 can be combined to form an input to the internal controlled resistor 220. A specific combination of resistor control signals can set the resistance between the first node 110 and the second node 120. As shown in Table 1, when all three resistor control signals are low (e.g., the default state), the internal controlled resistor can be controlled to provide a resistance corresponding to a gain value of 20. A high at the first resistor control output 410 configures the internal controlled resistor 220 to provide a resistance corresponding to a gain of 50. Similarly, a high at the second resistor control output 420 configures the internal controlled resistor 220 to provide a resistance corresponding to a gain of 100. Similarly, a high at the third resistor control output 430 configures the internal controlled resistor 220 to provide a resistance corresponding to a gain of 200.

[0039] In some embodiments, when a particular resistor control output is high, all other resistor control outputs are low. In other embodiments, when a particular resistor control output is high, one or more of the other resistor control outputs may be high. For example, in Table 1, when the third resistor control output 430 is high, then the first resistor control output 410 and the second resistor control output 420 are also high. In different embodiments, the gain values ​​and signals of Table 1 may vary. Therefore, while the values ​​and relationships listed in Table 1 are helpful in describing the circuits and methods of the present disclosure, they are not intended to be limiting.

[0040] Figure 4 Shown Figure 3 FIG. 4 is a detailed schematic diagram of the gain decoder 400 of the gain control circuit 200 of FIG. 1 . The output of the first resistor control output 410 is coupled to a pair of diode-connected transistors M16 and M17 and a switch transistor M26. When the switch transistor M26 is in an on state (i.e., conducting), the first resistor control output 410 is coupled to the common mode voltage input (i.e., G 50 =V CM When the switch transistor M26 is in the off state, the first resistor control output 410 is coupled to V via the pair of diode-connected transistors M16, M17. CM The pair of diode-connected transistors M16, M17 act as voltage sources because they are coupled to a current mirror (e.g., M7+M8, M9+M10, M11, M12, or M3) that provides them with a bias current (I 偏置 ). In this case, the first resistor control output 410 is V CM Add the voltage drop across the pair of diode-connected transistors (ie, the switching voltage ΔV).

[0041] The output of the second resistor control output 420 is coupled to a pair of diode-connected transistors M18, M19 and a switch transistor M32. When the switch transistor M32 is in an on condition (i.e., conducting), the second resistor control output 420 is coupled to the common mode voltage input (i.e., G 100 =V CM When the switch transistor M32 is in the off state, the second resistor control output 420 is coupled to V via the pair of diode-connected transistors M18, M19. CM The pair of diode-connected transistors M18, M19 act as voltage sources because they are coupled to a current mirror that provides them with a bias current (I 偏置 ). In this case, the second resistor control output 420 is V CM Add the voltage drop across the pair of diode-connected transistors (ie, the switching voltage ΔV).

[0042] Switching transistors M26 and M32 are controlled by voltages corresponding to the first gain select signal (GS1) and the second gain select signal (GS2), respectively. These voltages are generated by a first gain decoder input circuit 440 and a second gain decoder input circuit 450. Because both circuits operate similarly, only the first gain decoder input circuit 440 will be described in detail.

[0043] The first gain decoder input circuit 440 includes a large input resistor R5 to prevent the load circuit from providing the first gain select signal (GS1) and to help bias the diode-connected transistors M22 and M23 when receiving a high signal. In addition, the first gain input circuit includes a diode device (e.g., a Zener diode) DZ1 for overvoltage protection. The first gain input circuit also includes an inverter formed by transistors M24 and M25. When GS1 is high, the input of the inverter is pulled high, and the first gain input circuit outputs a low voltage. When GS1 is low, the input of the inverter is pulled low, and the first gain input circuit outputs a high voltage.

[0044] The output of the third resistor control output 430 is coupled to a pair of diode-connected transistors M20 and M21 and a first switch transistor M27 and a second switch transistor M33. When the first switch transistor M27 or the second switch transistor M33 is in an on state (i.e., conducting), the third resistor control output 430 is coupled to the common mode voltage input (i.e., G 200 =V CM When the first switching transistor M27 and the second switching transistor M33 are both in the off state, the third resistor control output 430 is coupled to V via the pair of diode-connected transistors M20 and M21. CM The pair of diode-connected transistors M20, M21 act as voltage sources because they are coupled to a current mirror that provides them with a bias current (I 偏置 ). In this case, the third resistor controls the output 430 to be V CM Add the voltage drop across the pair of diode-connected transistors (ie, the switching voltage ΔV).

[0045] exist Figure 4 In the operation of the gain decoder, low GS1 configures M26 and M27 to the on condition, and high GS1 configures M26 and M27 to the off condition. Similarly, low GS2 configures M32 and M33 to the on condition, and high GS2 configures M32 and M33 to the off condition. When M26 is in the off condition, G 50 is high (i.e., V CM +ΔV), when M32 is in the off state, G 100When M27 and M33 are both in the off state, G 200 is high level.

[0046] Figure 5A According to a first possible embodiment, Figure 1 Detailed schematic diagram of the adjustable gain instrumentation amplifier 10. The instrumentation amplifier 100, the common-mode extractor 210, the gain decoder 400, and the portion of the internal controlled resistor 220 of the adjustable gain instrumentation amplifier 10 are separated by dashed lines. In addition, the portions included in the gain control circuit 200 are depicted with solid outlines. As shown, the common-mode extractor is coupled to the positive input (IN+) of the instrumentation amplifier and the negative input (IN-) of the instrumentation amplifier. The input signal (e.g., voltage) is buffered by opamps OA3, OA4 and develops a voltage across a pair of matched resistors R4. The pair of matched resistors forms a voltage divider that produces a common-mode voltage (V CM ), the resistor pair can be in the range of 100 kΩ to 500 kΩ. V CM is buffered by opamp OA5 and coupled to gain decoder 400. This circuit senses V CM and use it as the resistor control signal G 50 , G 100 and G 200 virtual ground, making V CM can be changed without adversely affecting the operation of the circuit.

[0047] The resistor control signal from the gain decoder is coupled to the internal controlled resistor 220. The internal controlled resistor includes a plurality of resistors connected in series and a plurality of switches. The series-connected resistors are coupled between the first node 110 and the second node 120 to provide a resistor (R3) that sets the gain of the instrumentation amplifier. Each switch acts as a single-pole single-throw (SPST) switch, and each switch is connected in parallel to one or more resistors in the series-connected resistors so that when a particular switch is closed (i.e., in the on state), a portion of the plurality of resistors is short-circuited by the switch. In this way, the resistance between the first node 110 and the second node 120 can be electronically adjusted by adjusting the on / off state of the switch. The present disclosure is not limited to any particular number of resistors or switches, and the resistors and switches can be arranged in different ways.

[0048] Figure 5AThe internal controlled resistor 220 is one possible implementation in which each switch is embodied as a pair of metal oxide semiconductor field effect transistors (MOSFETs). The gate terminals and source terminals of the two MOSFETs are coupled together to form a dual MOSFET bidirectional switch. For example, the first resistor switch may include transistors M1 and M2, which may be controlled by the resistor control signal G. 50 The second resistor switch may include transistors M3 and M4, which may be controlled by the resistor control signal G 100 The third resistor switch may include transistors M5 and M6, which may be controlled by the resistor control signal G 200 Control is open (off) or short circuit (on) condition.

[0049] The resistors in the plurality of series-connected resistors may be arranged symmetrically around the central resistor, such that the central resistor R3A is coupled to a resistor R3B of equal value at each outer side. Resistor R3B is coupled to a resistor R3C of equal value at each outer side. Resistor R3C is coupled to a resistor R3D of equal value at each outer side. In the default condition, all switches may be turned off, such that R3=R3A+2R3B+2R3C+2R3D, which may correspond to a minimum gain value (e.g., G=20). In other words, the maximum internal resistance (R3) may correspond to the minimum gain of the instrumentation amplifier. To aid understanding, an exemplary table of resistance values ​​for possible internal controlled resistor implementations is provided in Table 2 below.

[0050] Table 2: Example internal resistance associated with gain values

[0051] Gain (G) G50 G100 G200 Internal resistance (R3) 20 <![CDATA[Low (V CM )]]> <![CDATA[Low (V CM )]]> <![CDATA[Low (V CM )]]> R3A+2R3B+2R3C+2R3D 50 <![CDATA[High (V CM + ΔV)]]> <![CDATA[Low (V CM )]]> <![CDATA[Low (V CM )]]> 2R3B+2R3C+2R3D 100 <![CDATA[Low (V CM )]]> <![CDATA[High (V CM + ΔV)]]> <![CDATA[Low (V CM )]]> 2R3C+2R3D 200 <![CDATA[High (V CM + ΔV)]]> <![CDATA[High (V CM + ΔV)]]> <![CDATA[High (V CM + ΔV)]]> 2R3D

[0052] The resistor switches in the internal controlled resistor 220 are arranged so that the second resistor switch and the first resistor switch are short-circuited when the third resistor switch is closed (i.e., turned on). Therefore, in the example shown in Table 2, when the third resistor switch is turned on, the (on / off) state of the first resistor switch and the (on / off) state of the second resistor switch do not significantly affect the internal resistance (i.e., 2R3D). Therefore, in Table 2, for G=200, G50 and G100 can be low (V CM ) without loss of functionality, and variations such as these are within the scope of the present disclosure. Additionally, more or fewer possible gain values ​​are possible. For example, the plurality of possible gain values ​​may be four or more discrete gain values ​​in the range of approximately 20 to 200.

[0053] Gain control circuit 200 advantageously consumes very little power. For example, gain control circuit 200 may consume 10% or less of the total power consumed by adjustable gain instrumentation amplifier circuit 10.

[0054] The values ​​of resistors R1, R2, and subsequently R3, are selected based on the input noise voltage specification of the high voltage instrumentation amplifier. One possible value for R1 is 4 kilo-ohms, which is large enough to be accurately implemented in the layout but still low in terms of white noise voltage contribution.

[0055] The resistance of the switch in the "on" state is related to the transistor's transconductance, which is in strong opposition. Considering k N is the intrinsic transconductance of the MOSFET (e.g., HV NMOS) transistor, W and L are the channel dimensions, and V TP is the overload provided by the circuit (i.e., an overload equal to the threshold voltage of the HV PMOS transistor). The switching of M1 and M2 can be described by the following equation:

[0056]

[0057] The fact that the switches are built as symmetrical pairs (with source and p-well connected together) allows them to handle the (+ / -) differential voltage appearing across R3 (i.e., the voltage that is proportional to the differential input voltage V IN+ -V IN- Almost the same voltage). In addition, by using this connection, the switch can handle negative voltages close to the threshold voltage of a "pn" diode (e.g., a parasitic p-well / source-drain diode). This voltage is less than 400mV and greater than 375mV over temperature. This allows the maximum differential voltage across R3 to be equal to ±0.75V, which corresponds to a maximum ±15V or 30V peak-to-peak output swing for a gain of 20 over a large temperature range (-40°C to +125°C). Therefore, instrumentation amplifier 100 is configured to amplify the differential-mode voltage (V DM ).

[0058] Figure 5B According to a second possible embodiment Figure 1 Detailed schematic diagram of the adjustable gain instrumentation amplifier 10. In addition to the instrumentation amplifier 100, Figure 5B The embodiment shown is similar to Figure 5A The same embodiment is shown. Figure 5A In the embodiment of FIG. 1 , the instrumentation amplifier 100 is implemented as a two-stage opamp instrumentation amplifier. Figure 5BIn the embodiment, the instrumentation amplifier 100 is implemented as a three-stage opamp instrumentation amplifier. The three-stage opamp embodiment can be used for amplifiers that require a large common-mode rejection ratio (CMRR) and a high V CM Applications requiring good (e.g., fast) transient response to changes (step changes). In some cases, a three-stage op amp instrumentation amplifier provides greater CMRR and better (e.g., faster) transient response than a two-stage op amp instrumentation amplifier.

[0059] The three-stage opamp implementation of the instrumentation amplifier differs from the two-stage opamp implementation of the instrumentation amplifier in several ways. The three-stage opamp instrumentation amplifier includes one additional opamp (OA6) and four additional resistors (R7), all of which have the same resistance. The additional opamp and resistors are sized and arranged so that the gain values ​​G (e.g., 20, 50, 100, and 200) correspond to the internal resistance values ​​in the same manner as described for the two-stage opamp instrumentation amplifier implementation (e.g., see Table 2).

[0060] Figure 6 1 is a flow chart of a method for adjusting the gain of an instrument amplifier according to a possible embodiment of the present disclosure. The method includes adjusting the gain of an instrument amplifier from an input (eg, V IN+ 、V IN- ) extracts the 610 common-mode voltage (V CM ). The extraction can be implemented using a common mode extractor circuit 210 including a voltage divider. The method also includes receiving 620 a gain select signal (e.g., GS1, GS2). In some embodiments, the gain select signal can be provided by a user, a sensor, or a processor controlled circuit and provided according to a lookup table of gain values ​​based on the gain select signal (or vice versa). The method also includes generating 630 a plurality of resistor control signals (G) based on the gain select signal and the common mode voltage using a gain decoder circuit. 50 , G 100 , G 200). In a possible embodiment, the resistor control signal may be a high voltage or a low voltage offset by a common mode voltage. The method also includes setting 640 the resistance of an internal controller resistor circuit based on a plurality of resistor control signals. In a possible embodiment, the internal controlled resistor circuit includes a resistor group connected in series, portions of which may be short-circuited by a switch to set or adjust the resistance. Finally, the method includes adjusting 650 the gain of an instrumentation amplifier based on the resistance of the internal controlled resistor circuit. In one possible embodiment, the instrumentation amplifier is a two-stage opamp instrumentation amplifier, and the resistance of the internal controlled resistor is coupled between the inverting inputs of the two opamps. In another possible embodiment, the instrumentation amplifier is a three-stage opamp instrumentation amplifier, and the resistance of the internal controlled resistor is coupled between the inverting inputs of two of the three opamps (i.e., OA1, OA2), wherein the three opamps include a first opamp (OA1), a second opamp (OA2), and a third opamp (OA6).

[0061] The present disclosure may be implemented as a circuit including an instrumentation amplifier and a gain control circuit. The gain control circuit may be coupled to the instrumentation amplifier and configured to control gain to one of a plurality of possible gain values ​​based on: (i) a gain select signal received at a plurality of gain select inputs; and (ii) a common-mode voltage corresponding to input signals received at a positive input of the instrumentation amplifier and at a negative input of the instrumentation amplifier.

[0062] In one possible implementation of the circuit, for a supply voltage of 36 volts, the common mode voltage (V CM ) in the range of approximately 1.5 volts to 34.5 volts.

[0063] In another possible implementation of the circuit, the gain control circuit consumes 10% or less of the total power consumed by the circuit.

[0064] In another possible implementation of the circuit, the instrument amplifier is configured to amplify the differential model voltage (V DM ), the input signal has a voltage difference in the range of -0.75 volts to +0.75 volts.

[0065] In another possible implementation of the circuit, the plurality of possible gain values ​​is four or more discrete gain values ​​in the range of approximately 20 to 200.

[0066] The circuit can be configured as an adjustable gain instrumentation amplifier, which, in a possible embodiment, can be configured to provide a gain of 20, 50, 100, or 200 based on four possible combinations of gain select signals at the first gain select input and the second gain select input.

[0067] In the specification and / or drawings, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. For example, the techniques and methods of the present disclosure can be applied to low voltages, which are almost the same as the techniques and methods described herein for high voltages. The use of the term "and / or" includes any and all combinations of one or more associated listed items. The accompanying drawings are schematic representations and are therefore not necessarily drawn to scale. Unless otherwise specified, specific terms have been used in a general and descriptive sense and not for limiting purposes.

[0068] Some embodiments may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0069] Although certain features of the described embodiments have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of a specific implementation. It should be understood that these modifications and variations are presented by way of example only and not limitation, and that various changes in form and detail may be made. Except for mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A circuit, comprising: Instrument amplifier; and a gain control circuit coupled to the instrumentation amplifier, the gain control circuit comprising: A common-mode extractor circuit is coupled to the positive and negative inputs of the instrumentation amplifier and is configured to output a common-mode voltage (V CM ); a gain decoder circuit configured to output a plurality of resistor control signals based in part on the common-mode voltage from the common-mode extractor circuit; and An internal controlled resistor circuit is configured to generate a resistance based on the plurality of resistor control signals from the gain decoder circuit, the resistor being coupled to the instrumentation amplifier.

2. The circuit according to claim 1, wherein: The instrument amplifier is powered by a negative supply voltage (V SS ) and the positive supply voltage (V DD ) is powered, and wherein: The internal controlled resistor circuit includes a resistor bank, the gain of the instrumentation amplifier corresponding to the resistance of the resistor bank; and the gain decoder circuit being configured to output a plurality of resistor control signals based on the common-mode voltage from the common-mode extractor circuit and gain select signals at a plurality of gain select inputs to the gain decoder circuit; and wherein: Each of the plurality of gain selection inputs receives a negative supply voltage (V SS ) or positive supply voltage (V DD ) to define a particular gain select combination of voltages on the plurality of gain select inputs; and wherein: The gain decoder circuit is configured to output a particular combination of resistor control signals on a plurality of resistor control outputs, the particular combination corresponding to a particular gain select combination of voltages on the plurality of gain select inputs.

3. The circuit of claim 2, wherein: the internal controlled resistor circuit comprising a plurality of switches, each coupled in parallel to a different set of resistors in the resistor bank such that when one or more of the plurality of switches is in an on condition, a portion of the resistor bank is shorted and a resistance of the resistor bank corresponds to a non-short-circuited portion of the resistor bank; and Each switch of the plurality of switches is coupled to one of the plurality of resistor control outputs such that the conduction condition of the plurality of switches corresponds to a particular combination of resistor control signals on the plurality of resistor control outputs.

4. The circuit of claim 2, wherein: Each resistor control signal in a particular combination of resistor control signals is offset by the common mode voltage (V CM ).

5. The circuit of claim 2 , wherein the common-mode extractor circuit comprises: A voltage divider circuit is coupled to the positive input and the negative input of the instrumentation amplifier, wherein the output of the voltage divider circuit corresponds to the common-mode voltage (V CM ).

6. The circuit of claim 2, wherein: The instrumentation amplifier is a dual operational amplifier instrumentation amplifier including a first operational amplifier and a second operational amplifier, and The resistor bank of the internal controlled resistor circuit is coupled between the inverting input of the first operational amplifier and the inverting input of the second operational amplifier.

7. The circuit of claim 2, wherein: The instrumentation amplifier is a three-op-amp instrumentation amplifier including a first op-amp, a second op-amp, and a third op-amp, and The resistor bank of the internal controlled resistor circuit is coupled between the inverting input of the first operational amplifier and the inverting input of the second operational amplifier.

8. A method for adjusting the gain of an instrumentation amplifier, the method comprising: extracting a common-mode voltage from an input of the instrumentation amplifier; receiving a gain selection signal; generating a plurality of resistor control signals based on the gain select signal and the common mode voltage using a gain decoder circuit; setting a resistance of an internal controlled resistor circuit based on the plurality of resistor control signals; as well as The gain of the instrumentation amplifier is adjusted based on the resistance of the internal controlled resistor circuit.

9. The method of claim 8, wherein the instrumentation amplifier is a dual operational amplifier instrumentation amplifier.

10. The method of claim 8, wherein the instrumentation amplifier is a three operational amplifier instrumentation amplifier.

11. The method according to claim 8, wherein: The internal controlled resistor circuit includes a plurality of resistors connected in series and a plurality of switches, each switch of the plurality of switches being connected in parallel to one or more resistors of the plurality of resistors connected in series; And among them: Setting the resistance of the internal controlled resistor circuit based on the plurality of resistor control signals includes: controlling one or more of the switches to be in an on condition based on the resistor control signal; and A portion of the series-connected resistors is short-circuited using the one or more switches in the on-state such that the resistance of the internal controlled resistor circuit corresponds to resistors of the plurality of series-connected resistors that are not short-circuited by the one or more switches in the on-state.

12. The method of claim 8, wherein extracting a common-mode voltage from an input of the instrumentation amplifier comprises: applying the positive input terminal and the negative input terminal of the instrumentation amplifier to a voltage divider; as well as The voltage divider is tapped to obtain the common mode voltage. 13 . The method of claim 8 , wherein each of the plurality of resistor control signals is a high voltage or a low voltage, the high voltage and the low voltage being offset by the common mode voltage.

14. An adjustable gain instrument amplifier, comprising: dual or triple op-amp instrumentation amplifiers; an internal controlled resistor coupled to the dual or triple op-amp instrumentation amplifier, the gain of the dual or triple op-amp instrumentation amplifier being based on the resistance of the internal controlled resistor; a gain decoder coupled to the internal controlled resistor and configured to provide a resistor control signal to the internal controlled resistor to control the resistance of the internal controlled resistor based on gain select signals received at first and second gain select inputs of the gain decoder; and a common-mode extractor coupled to the dual or triple op-amp instrumentation amplifier and configured to determine a common-mode voltage from an input of the dual or triple op-amp instrumentation amplifier, the common-mode voltage being transmitted to the gain decoder, the gain decoder being configured to offset the resistor control signal provided to the internal controlled resistor by the common-mode voltage.

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