Computational Optimization of Low-Precision Machine Learning Operations

Abstract

The title of the present invention is "Computational Optimization for Low-Precision Machine Learning Operations". One embodiment provides a general-purpose graphics processing unit including a dynamic precision floating-point unit, the dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track the available number of precision bits of computational data related to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Description

Technical Field

[0001] Embodiments generally relate to data processing, and more particularly to data processing via a general purpose graphics processing unit. Background Art

[0002] Current parallel graphics data processing involves developing systems and methods for performing specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed function computing units to process graphics data; however, recently, parts of the graphics processor have been made programmable, enabling such processors to support a wide variety of operations for processing vertex and fragment data.

[0003] To further increase performance, graphics processors typically implement processing techniques such as pipelined operations that attempt to parallel process as much graphics data as possible across different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to synchronously execute program instructions together as often as possible to increase processing efficiency. A general overview of the software and hardware for the SIMT architecture can be found in Shane Cook's CUDA Programming, Chapter 3, pages 37 - 51 (2013) and / or Nicholas Wilt's CUDA Handbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2 to 3.1.2 (June 2013). Brief Description of the Drawings

[0004] A more particular description of the invention can be had by reference to the embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the drawings only illustrate typical embodiments and are not to be considered limiting of the scope of all embodiments.

[0005] Figure 1 is a block diagram of a computer system configured to implement one or more aspects of the embodiments described herein.

[0006] Figures 2A - 2D illustrates a parallel processor component according to an embodiment.

[0007] Figures 3A - 3B is a block diagram of a graphics multiprocessor according to an embodiment.

[0008] Figures 4A - 4F illustrates an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi - core processors.

[0009] Figure 5 Shows a graphics processing pipeline according to an embodiment.

[0010] Figure 6 Shows a machine learning software stack according to an embodiment.

[0011] Figure 7 Shows a highly parallel general-purpose graphics processing unit according to an embodiment.

[0012] Figure 8 Shows a multi-GPU computing system according to an embodiment.

[0013] Figures 9A - 9B Shows the layers of a exemplary deep neural network.

[0014] Figure 10 Shows an exemplary recurrent neural network.

[0015] Figure 11 Shows the training and deployment of a deep neural network.

[0016] Figure 12 Is a block diagram showing distributed learning.

[0017] Figure 13 Shows an exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model.

[0018] Figure 14 Shows the components of a dynamic precision floating-point unit according to an embodiment.

[0019] Figure 15 Provides additional details regarding the dynamic precision floating-point unit according to an embodiment.

[0020] Figure 16 Shows the thread assignment of a dynamic precision processing system according to an embodiment.

[0021] Figure 17 Shows the logic for performing numerical operations at a precision lower than required according to an embodiment.

[0022] Figure 18 Shows the loop vectorization of a SIMD unit according to an embodiment.

[0023] Figure 19 Shows a thread processing system according to an embodiment.

[0024] Figure 20 Shows the logic for assigning threads for computation according to an embodiment.

[0025] Figure 21 Shows a deep neural network 2100 that can be processed using the computing logic provided by the embodiments described herein.

[0026] Figure 22 It is a block diagram of logic 2200 that prevents errors or significant precision loss when performing low-precision operations for machine learning according to an embodiment.

[0027] Figure 23 It is a block diagram of a processing system according to an embodiment.

[0028] Figure 24 It is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.

[0029] Figure 25 It is a block diagram of a graphics processor that can be a discrete graphics processing unit or can be a graphics processor integrated with multiple processing cores.

[0030] Figure 26 It is a block diagram of a graphics processing engine of a graphics processor according to some embodiments.

[0031] Figure 27 It is a block diagram of a graphics processor provided by additional embodiments.

[0032] Figure 28 It shows thread execution logic including an array of processing elements employed in some embodiments.

[0033] Figure 29 It is a block diagram showing a graphics processor instruction format according to some embodiments.

[0034] Figure 30 It is a block diagram of a graphics processor according to another embodiment.

[0035] Figures 31A - 31B It shows a graphics processor command format and command sequence according to some embodiments.

[0036] Figure 32 It shows a exemplary graphics software architecture for a data processing system according to some embodiments.

[0037] Figure 33 It is a block diagram showing an IP core development system according to an embodiment.

[0038] Figure 34 It is a block diagram showing an exemplary system-on-chip integrated circuit according to an embodiment.

[0039] Figure 35 It is a block diagram showing an additional graphics processor according to an embodiment.

[0040] Figure 36 It is a block diagram showing an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. Detailed Implementation Manner

[0041] In some embodiments, a Graphics Processing Unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various General-Purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic for efficiently processing these commands / instructions.

[0042] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of ordinary skill in the art that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the embodiments of the present invention.

[0043] System Overview

[0044] Figure 1 is a block diagram showing a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 that communicate via an interconnect path that can include a memory hub 105. The memory hub 105 can be a separate component within a chipset component or can be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that can enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 can enable a display controller to provide output to one or more display devices 110A, which can be included in the one or more processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 can include local, internal, or embedded display devices.

[0045] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, and the one or more parallel processors 112 are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as but not limited to PCI Express), or can be a vendor-specific communication interface or communication fabric. In one embodiment, the one or more parallel processors 112 form a parallel or vector processing system in a computing cluster, and the system includes a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem, and the graphics processing subsystem can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable a direct connection to one or more display devices 110B.

[0046] Within the I / O subsystem 111, the system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components that can be integrated into the platform (such as the network adapter 118 and / or the wireless network adapter 119) and various other devices that can be added via one or more plug-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0047] The computing system 100 may include other components not explicitly shown, and the other components include USB or other port connections, optical storage drives, video capture devices, etc., and can also be connected to the I / O hub 107. Any suitable protocol can be used, such as a PCI (Peripheral Component Interconnect)-based protocol (for example, PCI-Express), or any other bus or point-to-point communication interface and / or (multiple) protocols, such as the NV-Link high-speed interconnect or an interconnect protocol known in the art, to implement the communication paths that interconnect the various components Figure 1 in.

[0048] In one embodiment, the one or more parallel processors 112 are coupled with circuitry optimized for graphics and video processing, the circuitry including, for example, video output circuitry, and form a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 are coupled with circuitry optimized for general-purpose processing while maintaining the underlying computational architecture described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, the memory hub 105, the processor(s) 102, and the I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0049] It will be appreciated that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connection topology may be modified as desired, including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112. For example, in some embodiments, system memory 104 is connected directly to the processor(s) 102 rather than through a bridge, while other devices communicate with system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102 rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of the processor(s) 102 attached via multiple sockets, which may be coupled with two or more instances of the parallel processor(s) 112.

[0050] Some of the specific components shown herein are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripheral devices may be supported, or some components may be eliminated. Additionally, some architectures may use different terms for components similar to those shown Figure 1 herein. For example, in some architectures the memory hub 105 may be referred to as a north bridge, while the I / O hub 107 may be referred to as a south bridge.

[0051] Figure 2AFIG. 200 shows a parallel processor in accordance with an embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In accordance with an embodiment, the illustrated parallel processor 200 is Figure 1 a variant of the one or more parallel processors 112 shown in FIG. 1.

[0052] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface such as memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, where the host interface 206 receives commands related to the execution of processing operations and the memory crossbar 216 receives commands related to the execution of memory operations.

[0053] When the host interface 206 receives a command buffer via the I / O unit 204, the host interface 206 may direct the work operations for the execution of those commands to a front end 208. In one embodiment, the front end 208 is coupled to a scheduler 210 that is configured to distribute commands or other work items to an array of processing clusters 212. In one embodiment, the scheduler 210 ensures that the array of processing clusters 212 is properly configured and in an active state before distributing tasks to the processing clusters of the array of processing clusters 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 may be configured to perform complex scheduling and work distribution operations at both a coarse and fine granularity, enabling context switching and rapid preemption of threads executing on the processing array 212. In one embodiment, host software may check the workload for scheduling on the processing array 212 via one of a plurality of graphics processing doorbells. The workload may then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0054] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B to cluster 214N). Each of the clusters 214A - 214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to the clusters 214A - 214N of the processing cluster array 212, and the algorithms may vary according to the workload generated by each type of program or calculation. Scheduling may be handled dynamically by the scheduler 210, or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the processing cluster array 212. In one embodiment, different clusters 214A - 214N of the processing cluster array 212 may be assigned to process different types of programs or to perform different types of calculations.

[0055] The processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general - purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks, the processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformation.

[0056] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, tessellation logic, and other vertex processing logic. Additionally, the processing cluster array 212 may be configured to execute graphics - processing - related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transfer data from the system memory via the I / O unit 204 for processing. During processing, the transferred data may be stored to on - chip memory (e.g., parallel processor memory 222) during processing and then written back to the system memory.

[0057] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable the graphics processing operations to be distributed to the multiple clusters 214A - 214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A - 214N may be stored in a buffer to allow the intermediate data to be transferred between the clusters 214A - 214N for further processing.

[0058] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include data to be processed and indices of status parameters and commands defining how the data is to be processed (e.g., what program is to be executed), such as surface (patch) data, primitive data, vertex data, and / or pixel data. The scheduler 210 may be configured to obtain the index corresponding to the task or may receive the index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured in a valid state before the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0059] Each of one or more instances of the parallel processing unit 202 may be coupled to the parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar 216 that may receive memory requests from the array of processing clusters 212 as well as the I / O unit 204. The memory crossbar 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partitioning units (e.g., partitioning unit 220A, partitioning units 220B through 220N), each of which may be coupled to a portion (e.g., a memory unit) of the parallel processor memory 222. In one implementation, the number of partitioning units 220A - 220N is configured to be equal to the number of memory units such that the first partitioning unit 220A has a corresponding first memory unit 224A, the second partitioning unit 220B has a corresponding memory unit 224B, and the Nth partitioning unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partitioning units 220A - 220N may not be equal to the number of memory devices.

[0060] In various embodiments, the memory units 224A - 224N may include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A - 224N may also include 3D stacked memory including, but not limited to, high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A - 224N may vary and may be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps may be stored across the memory units 224A - 224N, allowing the partitioning units 220A - 220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 222. In some embodiments, a local instance of the parallel processor memory 222 may be excluded to support a unified memory design that utilizes system memory along with local caches.

[0061] In one embodiment, any one of clusters 214A - 214N of processing cluster array 212 can process any data to be written into memory cells 224A - 224N within parallel processor memory 222. Memory crossbar 216 can be configured to transfer the output of each cluster 214A - 214N to any partition unit 220A - 220N or another cluster 214A - 214N, which can perform additional processing operations on the output. Each cluster 214A - 214N can communicate with memory interface 218 through memory crossbar 216 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has a connection to memory interface 218 for communicating with I / O unit 204, and a connection to a local instance of parallel processor memory 222, such that processing units within different processing clusters 214A - 214N can communicate with system memory or other memory that is non - local to parallel processing unit 202. In one embodiment, memory crossbar 216 can use virtual channels to separate the traffic flow between clusters 214A - 214N and partition units 220A - 220N.

[0062] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 can be included. For example, multiple instances of parallel processing unit 202 can be provided on a single plug - in card, or multiple plug - in cards can be interconnected. Even if different instances of parallel processing unit 202 have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences, the different instances can be configured to interoperate. For example and in one embodiment, some instances of parallel processing unit 202 can include floating - point units with higher precision relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0063] Figure 2B is a block diagram of partition unit 220 according to an embodiment. In one embodiment, partition unit 220 is Figure 2AAn example of one of the partition units 220A - 220N. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. The L2 cache 221 outputs read misses and urgent write-back requests to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as the memory units 224A - 224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0064] In a graphics application, the ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. The ROP 226 then outputs the processed graphics data, which is stored in the graphics memory. In some embodiments, the ROP 226 includes compression logic for compressing depth or color data written to the memory and decompressing depth or color data read from the memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by the ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0065] In some embodiments, the ROP 226 is included within each processing cluster (e.g., clusters 214A - 214N of FIG. 2) rather than within the partition unit 220. In such embodiments, read and write requests for pixel data are transmitted through the memory crossbar 216, rather than pixel fragment data. The processed graphics data can be displayed on a display device (such as Figure 1 one of the one or more display devices 110), routed for further processing by the (multiple) processors 102, or routed for further processing by Figure 2A one of the processing entities within the parallel processor 200.

[0066] Figure 2CIt is a block diagram of the processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A - 214N in FIG. 2. The processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific set of input data. In some embodiments, without providing multiple independent instruction units, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads. In other embodiments, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronous threads using a common instruction unit, which is configured to issue instructions to a set of processing engines within each of the processing clusters. Different from the SIMD execution regime in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0067] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 in FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is a demonstrative example of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and a data crossbar 240 can be used to distribute the processed data to one of a plurality of possible destinations including other shader units. The pipeline manager 232 can facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

[0068] Each graphics multiprocessor 234 within the processing cluster 214 can include a set of identical functional execution logics (e.g., arithmetic logic units, load - store units, etc.). The functional execution logics can be configured in a pipelined manner, where new instructions can be issued before the completion of previous instructions. The functional execution logics support a variety of operations, including integer and floating - point arithmetic, comparison operations, boolean operations, shifts, and the calculation of various algebraic functions. In one embodiment, the same functional unit hardware can be utilized to perform different operations, and there can be any combination of functional units.

[0069] Instructions transmitted to processing cluster 214 constitute a thread. A collection of threads executed across a collection of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycles in which the thread group is processed. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed in consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 234.

[0070] In one embodiment, graphics multiprocessor 234 includes an internal cache for performing load and store operations. In one embodiment, graphics multiprocessor 234 can forego the internal cache and instead use the cache within processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 is also capable of accessing the L2 cache within a partition unit (e.g., partition units 220A - 220N of FIG. 2) that is shared among all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 can also access off - chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data that can be stored in L1 cache 308.

[0071] Each processing cluster 214 can include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 can reside within memory interface 218 of FIG. 2. MMU 245 includes a set of page table entries (PTEs) that are used to map virtual addresses to the physical addresses of tiles (more on tiling) and optionally to cache line indices. MMU 245 can include a translation lookaside buffer (TLB) or cache, which can reside within graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to allow for efficient request interleaving between partition units. Cache line indices can be used to determine whether a request to a cache line is a hit or a miss.

[0072] In graphics and computing applications, processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. As needed, texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within graphics multiprocessor 234 and fetched from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs a processed task to data crossbar 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via memory crossbar 216. preROP 242 (pre-raster operation unit) is configured to receive data from graphics multiprocessor 234 and direct the data to ROP units, which may be collocated with partition units (e.g., partition units 220A - 220N of FIG. 2) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0073] It will be appreciated that the core architectures described herein are illustrative and variations and modifications are possible. Any number of processing units, such as graphics multiprocessor 234, texture unit 236, preROP 242, etc., may be included within processing cluster 214. Further, although only one processing cluster 214 is shown, the parallel processing units as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0074] Figure 2D A graphics multiprocessor 234 is shown in accordance with one embodiment. In such embodiments, graphics multiprocessor 234 is coupled to a pipeline manager 232 of processing cluster 214. Graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0075] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 may dispatch instructions as thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions may access any address space in the local, shared, or global address space by specifying an address within the unified address space. The address mapping unit 256 may be used to translate an address in the unified address space into a different memory address accessible by the load / store unit 266.

[0076] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands of the data paths connected to the functional units (e.g., GPGPU core 262, load / store unit 266) of the graphics multiprocessor 324. In one embodiment, the register file 258 is partitioned among each of the functional units such that each functional unit is assigned a dedicated portion of the register file 258. In one embodiment, the register file 258 is partitioned among different warps being executed by the graphics multiprocessor 324.

[0077] Each GPGPU core 262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of the graphics multiprocessor 324. According to embodiments, the GPGPU cores 262 may be similar in architecture or may be different in architecture. For example and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units for performing specific functions such as copy rectangle or pixel blend operations. In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0078] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time or can be automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0079] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfer between the GPGPU core 262 and the register file 258 has a very low latency. The shared memory 270 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data transferred between the functional units and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0080] Figures 3A - 3B An additional graphics multiprocessor is shown according to an embodiment. The shown graphics multiprocessors 325, 350 are Figure 2C variants of the graphics multiprocessor 234. The shown graphics multiprocessors 325, 350 can be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0081] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes the same as Figure 2DMultiple additional instances of execution resource units associated with the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A - 332B, register files 334A - 334B, and (multiple) texture units 344A - 344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A - 336B, GPGPU cores 337A - 337B, GPGPU cores 338A - 338B) and multiple sets of load / store units 340A - 340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346.

[0082] Various components may communicate via the interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbars to enable communication between various components of the graphics multiprocessor 325. In one embodiment, the interconnect structure 327 is a separate high - speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the GPGPU cores 336A - 336B, 337A - 337B, and 338A - 338B may each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 may arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0083] Figure 3B Illustrates a graphics multiprocessor 350 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A - 356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load - store units, as Figure 2D and Figure 3A shown. The execution resources 356A - 356D may work in concert with (multiple) texture units 360A - 360D for texture operations while sharing an instruction cache 354 and a shared memory 362. In one embodiment, the execution resources 356A - 356D may share the instruction cache 354 and the shared memory 362 as well as multiple instances of texture and / or data cache memories 358A - 358B. Various components may communicate via an interconnect structure 352 similar to the Figure 3A interconnect structure 327.

[0084] Those skilled in the art will understand, Figure 1 、 2AThe architectures described in 2D and 3A-3B are descriptive and not restrictive with respect to the scope of embodiments of the present invention. Thus, the techniques described herein may be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as the parallel processing unit 202 of FIG. 2), and one or more graphics processors or specialized processing units, without departing from the scope of the embodiments described herein.

[0085] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or die as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or die). Regardless of how the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses specialized circuitry / logic for efficiently processing these commands / instructions.

[0086] Techniques for GPU - to - Host Processor Interconnection

[0087] Figure 4A A exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440-443 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s or higher, depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the present invention are not limited to any particular communication protocol or throughput.

[0088] Additionally, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as those used for the high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via a high-speed link 433, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively,Figure 4A All communication between the various system components shown can be accomplished using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the present invention are not limited to any particular type of interconnect technology.

[0089] In one embodiment, each multi-core processor 405 - 406 is communicatively coupled to a processor memory 401 - 402 via a memory interconnect 430 - 431, respectively, and each GPU 410 - 413 is communicatively coupled to a GPU memory 420 - 423 via a GPU memory interconnect 450 - 453, respectively. The memory interconnects 430 - 431 and 450 - 453 may utilize the same or different memory access technologies. By way of example and not limitation, the processor memories 401 - 402 and the GPU memories 420 - 423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0090] As described below, although the various processors 405 - 406 and GPUs 410 - 413 may be physically coupled to specific memories 401 - 402, 420 - 423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among all the various physical memories. For example, each of the processor memories 401 - 402 may include 64GB of system memory address space, and each of the GPU memories 420 - 423 may include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0091] Figure 4B Additional details of the interconnect between a multi-core processor 407 and a graphics acceleration module 446 in accordance with one embodiment are shown. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0092] The illustrated processor 407 includes a plurality of cores 460A - 460D, each having a translation lookaside buffer 461A - 461D and one or more caches 462A - 462D. The cores may include various other components for executing instructions and processing data (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.), which are not shown to avoid obscuring the basic principles of the present invention. The caches 462A - 462D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by a set of cores 460A - 460D. For example, one embodiment of processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 caches and one of the L3 caches are shared by two adjacent cores. Processor 407 and graphics accelerator integration module 446 are connected to system memory 441, which may include processor memories 401 - 402.

[0093] Consistency is maintained for data and instructions stored in the various caches 462A - 462D, 456, and system memory 441 through inter - core communication via coherence bus 464. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles of the present invention.

[0094] In one embodiment, proxy circuit 425 communicatively couples graphics acceleration module 446 to coherence bus 464, thereby allowing graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the cores. Specifically, interface 435 provides connectivity to proxy circuit 425 via high - speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to high - speed link 440.

[0095] In one implementation, the accelerator integrated circuit 436 represents multiple graphics processing engines 431, 432, N of the graphics acceleration module 446 and provides cache management, memory access, context management, and interrupt management services. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431 - 432, N, or the graphics processing engines 431 - 432, N may be separate GPUs integrated on a common package, line card, or chip.

[0096] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual - to - physical memory translation (also known as effective - to - real memory translation) and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective - to - physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431 - 432, N. In one embodiment, the data stored in the cache 438 and the graphics memories 433 - 434, N is kept consistent with the core caches 462A - 462D, 456 and the system memory 411. As mentioned, this can be done via the proxy circuit 425, which represents the cache 438 and the memories 433 - 434, N in the cache coherence mechanism (e.g., sending updates related to the modification / access of cache lines on the processor caches 462A - 462D, 456 to the cache 438 and receiving updates from the cache 438).

[0097] A set of registers 445 stores context data for the threads executed by the graphics processing engines 431 - 432, N, and the context management circuit 448 manages the thread contexts. For example, the context management circuit 448 may perform save and restore operations to save and restore the contexts of various threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 448 may store the current register values into a specified area in memory (e.g., identified by a context pointer). It may then restore the register values when returning to that context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0098] In one implementation, the MMU 439 converts virtual / valid addresses from the graphics processing engine 431 into real / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executing on the processor 407 or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 431 - 432, N are shared among multiple applications or virtual machines (VMs). The resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0099] Accordingly, the accelerator integrated circuit acts as a bridge to the system of the graphics accelerator module 446 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage the virtualization of the graphics processing engine, interrupts, and memory management.

[0100] Since the hardware resources of the graphics processing engines 431 - 432, N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431 - 432, N such that they appear as independent units to the system.

[0101] As mentioned, in the illustrated embodiment, one or more graphics memories 433 - 434, M are coupled to each of the graphics processing engines 431 - 432, N, respectively. The graphics memories 433 - 434, M store the instructions and data being processed by each of the graphics processing engines 431 - 432, N. The graphics memories 433 - 434, M can be volatile memories such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-Ram.

[0102] In one embodiment, to reduce data traffic on the high-speed link 440, a biasing technique is used to ensure that the data stored in the graphics memories 433-434, M is the data that will be most frequently used by the graphics processing engines 431-432, N and preferably not used (or at least not frequently used) by the cores 460A-460D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not the graphics processing engines 431-432, N) within the caches 462A-462D, 456 of the cores and the system memory 411.

[0103] Figure 4C Another embodiment is shown in which the accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via the interface 437 and the interface 435 (again, which can utilize any form of bus or interface protocol) over the high-speed link 440. The accelerator integrated circuit 436 can perform the same operations as those described with respect to Figure 4B but may perform the operations with higher throughput considering its proximity to the coherence bus 462 and the caches 462A-462D, 426.

[0104] One embodiment supports different programming models, which include a dedicated process programming model (without virtualization of the graphics acceleration module) and a shared programming model (with virtualization). The shared programming model can include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0105] In one embodiment of the dedicated process model, the graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. This single application can aggregate other application requests to the graphics engines 431-432, N, thus providing virtualization within the VM / partition.

[0106] In the dedicated process programming model, the graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires the hypervisor to virtualize the graphics processing engines 431-432, N to allow access by each operating system. For a single-partition system without a hypervisor, the graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431-432, N to provide access to each process or application.

[0107] For a shared programming model, the graphics acceleration module 446 or a separate graphics processing engine 431-432, N uses a process handle to select process elements. In one embodiment, the process elements are stored in the system memory 411 and can be addressed using the effective address to physical address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when it registers its context with the graphics processing engine 431-432, N (i.e., calls the system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0108] Figure 4D A exemplary accelerator integration slice 490 is shown. As used herein, "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to a GPU call 481 from an application 480 executing on the processor 407. The process element 483 contains the process state for the corresponding application 480. The work descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to a job request queue within the application's address space 482.

[0109] The graphics acceleration module 446 and / or a separate graphics processing engine 431-432, N can be shared by all or a subset of the processes in the system. Embodiments of the present invention include infrastructure for establishing process state and sending the WD 484 to the graphics acceleration module 446 to start a job in a virtualized environment.

[0110] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owned partition, and the operating system initializes the accelerator integrated circuit 436 for the owned process when the graphics acceleration module 446 is assigned.

[0111] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be done by one of the graphics processing engines in the graphics acceleration module 446. Data from the WD 484 can be stored in the register 445 and used by the MMU 439, interrupt management circuit 447, and / or context management circuit 448 as shown. For example, one embodiment of the MMU 439 includes segment / page walk circuitry for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt events 492 received from the graphics acceleration module 446. When performing a graphics operation, the MMU 439 converts the virtual addresses 493 generated by the graphics processing engines 431 - 432, N into physical addresses.

[0112] In one embodiment, the same set of registers 445 is replicated for each of the graphics processing engines 431 - 432, N and / or the graphics acceleration module 446, and the same set of registers 445 can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integrated slice 490. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0113] Table 1 - Hypervisor Initialized Registers

[0114] 1 Slice Control Register 2 Actual Address (RA) Scheduled Process Region Pointer 3 Permission Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Actual Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0115] Table 2 shows exemplary registers that can be initialized by the operating system.

[0116] Table 2 - Operating System Initialized Registers

[0117] 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Resume Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Permission Mask 6 Work Descriptor

[0118] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431 - 432, N. It contains all the information required for the graphics processing engine 431 - 432, N to do its work, or it can be a pointer to a memory location in a command queue where the application has established the work to be done.

[0119] Figure 4E Additional details of one embodiment of the shared model are shown. This embodiment includes the hypervisor physical address space 498 in which the process element list 499 is stored. The hypervisor physical address space 498 can be accessed via the hypervisor 496, which virtualizes the graphics acceleration module engines for the operating system 495.

[0120] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time slice sharing and graphics-directed sharing.

[0121] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) The job requests of the application must be autonomous (i.e., do not require maintaining state between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees to complete the job requests of the application within a specified time period, including any translation faults, or the graphics acceleration module 446 provides the ability to preempt the processing of jobs. 3) When operating in the directed sharing programming model, fairness of the graphics acceleration module 446 must be guaranteed between processes.

[0122] In one embodiment, for the shared model, the application 480 is required to make an operating system 495 system call using the graphics acceleration module 446 type, work descriptor (WD), permission mask register (AMR) value, and context save / restore area pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the following forms: a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure used to describe the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the user authority mask override register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current authority mask override register (AMOR) value before placing the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the valid address of a region in the application's address space 482 for the graphics acceleration module 446 to save and restore the context state. If it is not required to save state between jobs or when a job is preempted, this pointer is optional. The context save / restore area can be pinned system memory.

[0123] Upon receiving a system call, the operating system 495 may verify that the application 480 is registered and has been granted permission to use the graphics acceleration module 446. The operating system 495 then utilizes the information shown in Table 3 to call the hypervisor 496.

[0124] Table 3 - OS Hypervisor Call Parameters

[0125] 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) Value (May be Masked) 3 Effective Address (EA) Context Save / Resume Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0126] Upon receiving a hypervisor call, the hypervisor 496 verifies that the operating system 495 is registered and has been granted permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a linked list of process elements for the corresponding type of graphics acceleration module 446. The process element may include the information shown in Table 4.

[0127] Table 4 - Process Element Information

[0128] 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) Value (May be Masked) 3 Effective Address (EA) Context Save / Resume Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table Derived from Hypervisor Call Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Actual Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0129] In one embodiment, the hypervisor initializes the registers 445 of multiple accelerator integrated slices 490.

[0130] As Figure 4F shown, one embodiment of the present invention employs a unified memory that can be addressed via a common virtual memory address space for accessing the physical processor memories 401 - 402 and the GPU memories 420 - 423. In this implementation, operations executed on the GPUs 410 - 413 utilize the same virtual / effective memory address space to access the processor memories 401 - 402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 401, a second portion is allocated to the second processor memory 402, a third portion is allocated to the GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memories 401 - 402 and the GPU memories 420 - 423, allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0131] In one embodiment, the bias / coherency management circuits 494A - 494E within one or more of the MMUs 439A - 439E ensure cache coherency between the host processor (e.g., 405) and the caches of the GPUs 410 - 413, and implement a bias technique for indicating the physical memory in which certain types of data should be stored. Although in Figure 4FMultiple instances of bias / coherence management circuits 494A - 494E are shown, but the bias / coherence circuits may be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0132] One embodiment allows the GPU - attached memories 420 - 423 to be mapped as portions of system memory and accessed using shared virtual memory (SVM) techniques without suffering the typical performance penalties associated with full - system cache coherence. The ability to access the GPU - attached memories 420 - 423 as system memory without the heavy cache - coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory - mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access the GPU - attached memories 420 - 423 without cache - coherence overhead can be critical to the execution time of offloaded computations. For example, in the case of a large number of streaming write - to - memory transactions, the cache - coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 410 - 413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offloading.

[0133] In one implementation, the choice between GPU bias and host - processor bias is driven by a bias - tracker data structure. For example, a bias table may be used, which may be a page - granularity structure (i.e., controlled at the granularity of memory pages) that includes 1 or 2 bits per GPU - attached memory page. The bias table may be implemented in the stolen - memory ranges of one or more GPU - attached memories 420 - 423, with or without a bias cache in the GPUs 410 - 413 (e.g., to cache frequently / most - recently - used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0134] In one implementation, before an actual access to the GPU memory, the bias table entries associated with each access to the GPU-attached memories 420-423 are accessed, which causes the following operations. First, local requests from the GPUs 410-413 that find their pages in the GPU bias are directly forwarded to the corresponding GPU memories 420-423. (For example, via the high-speed link discussed above) Local requests from the GPUs that find their pages in the host bias are forwarded to the processor 405. In one embodiment, requests from the processor 405 that find the requested page in the host processor bias complete the requests like normal memory reads. Alternatively, requests involving GPU bias pages can be forwarded to the GPUs 410-413. If the GPU is not currently using the page, the GPU can then convert the page to the host processor bias.

[0135] The bias state of a page can be changed via a software-based mechanism, a software mechanism assisted by hardware, or a pure hardware mechanism for a limited set of cases.

[0136] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or enqueues a command descriptor) to the GPU to guide it to change the bias state, and for certain conversions, a cache dump purge operation is performed in the host. The cache dump purge operation is required for the conversion from the host processor 405 bias to the GPU bias, but not for the reverse conversion.

[0137] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages non-cacheable by the host processor 405. To access these pages, the processor 405 can request access from the GPU 410, which may or may not immediately grant access, depending on the implementation. Therefore, to reduce communication between the processor 405 and the GPU 410, it is beneficial to ensure that the GPU bias pages are those that are required by the GPU but not by the host processor 405, and vice versa.

[0138] Graphics Processing Pipeline

[0139] Figure 5 A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor can implement the shown graphics processing pipeline 500. The graphics processor can be included within a parallel processing subsystem as described herein (such as the parallel processor 200 of FIG. 2), which in one embodiment is Figure 1Variants of the (multiple) parallel processors 112. Various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of parallel processing units (e.g., the parallel processing unit 202 of FIG. 2) as described herein. For example, shader units (e.g., the graphics multiprocessor 234 of FIG. 3) can be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 can also be performed by other processing engines and corresponding partitioning units (e.g., the partitioning units 220A-220N of FIG. 2) within a processing cluster (e.g., the processing cluster 214 of FIG. 3). The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 can be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 can access on-chip memory (e.g., the parallel processor memory 222 as in FIG. 2) via the memory interface 528, which can be an instance of the memory interface 218 of FIG. 2.

[0140] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs vertex data including vertex attributes to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to light and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data and can be programmed to transform the vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0141] A first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0142] The tessellation control processing unit 508 treats the input vertices as control points for geometric patches. The control points are transformed from an input representation (e.g., the basis of the patch) to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patches. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edges. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and subdivide the patch into a plurality of geometric primitives such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate vertex attributes and surface representations for each vertex associated with the geometric primitives.

[0143] A second instance of the primitive assembler 514 receives the vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphics primitives into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0144] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying the new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scale, cull, and clip unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometric data. The viewport scale, cull, and clip unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0145] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to the raster operations unit 526. The fragment / pixel processing unit 524 can read data stored in the parallel processor memory or the system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity according to the sampling rate configured for the processing unit.

[0146] The raster operations unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in a graphics memory (e.g., the parallel processor memory 222 as shown in FIG. 2, and / or the system memory 104 as shown in Figure 1 ), for display on one or more display devices 110 or for further processing by one of the one or more processors 102 or (multiple) parallel processors 112. In some embodiments, the raster operations unit 526 is configured to compress z or color data written to the memory and decompress z or color data read from the memory.

[0147] Machine Learning Overview

[0148] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0149] One exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph where nodes are arranged in layers. Generally, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating an output in the output layer. Network nodes are fully connected via edges to nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at the nodes of the input layer of a feedforward network is propagated (i.e., "fed forward") via an activation function to the nodes of the output layer, which calculates the state of the nodes in each successive layer of the network based on coefficients ("weights") associated respectively with each of the edges connecting the layers. Depending on the particular model represented by the algorithm being executed, the output from a neural network algorithm can take various forms.

[0150] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a set of training data representing the problem to be modeled by the network, and adjusting the weights until the network model exhibits minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output produced by the network in response to an input representing an instance in the training data set is compared with the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted to minimize the error as the error signal is propagated backward through the layers of the network. When the error for each output generated based on an instance of the training data set is minimized, the network is considered to be "trained".

[0151] The accuracy of a machine learning algorithm can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and may take a large amount of time on a conventional general-purpose processor. Accordingly, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks because the computations performed when adjusting the coefficients in a neural network inherently lend themselves to parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0152] Figure 6It is a generalized diagram of a machine learning software stack 600. The machine learning application 602 can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 602 can include specialized software that can be used to train a neural network before deployment and / or the training and inference functions of a neural network. The machine learning application 602 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0153] Hardware acceleration for the machine learning application 602 can be enabled via the machine learning block rack 604. The machine learning block rack 604 can provide a machine learning primitive library. Machine learning primitives are the basic operations that machine learning algorithms typically perform. Without the machine learning block rack 604, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm and then re-optimize that computational logic when a new parallel processor is developed. Instead, the machine learning application can be configured to perform the necessary computations using the primitives provided by the machine learning block rack 604. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning block rack 604 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0154] The machine learning block rack 604 can process the input data received from the machine learning application 602 and generate appropriate inputs to the computational block rack 606. The computational block rack 606 can abstract the basic instructions provided to the GPGPU driver 608 so that the machine learning block rack 604 can utilize hardware acceleration via the GPGPU hardware 610 without requiring the machine learning block rack 604 to be very familiar with the architecture of the GPGPU hardware 610. Additionally, the computational block rack 606 can enable hardware acceleration for the machine learning block rack 604 across multiple types and generations of GPGPU hardware 610.

[0155] GPGPU Machine Learning Acceleration

[0156] Figure 7 Illustrated is a highly parallel general-purpose graphics processing unit 700 according to an embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 700 can be configured to be particularly efficient when processing computational workloads of the type associated with training deep neural networks. Additionally, the GPGPU 700 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster to improve the training speed of particularly deep neural networks.

[0157] The GPGPU 700 includes a host interface 702 for enabling connection with a host processor. In one embodiment, the host interface 702 is a PCI Express interface. However, the host interface can also be a vendor - specific communication interface or communication fabric. The GPGPU 700 receives commands from the host processor and distributes execution threads associated with those commands to a set of compute clusters 706A - 706H using a global scheduler 704. The compute clusters 706A - 706H share a cache memory 708. The cache memory 708 can act as a cache - of - caches within the compute clusters 706A - 706H.

[0158] The GPGPU 700 includes memories 714A - 714B that are coupled to the compute clusters 706A - H via a set of memory controllers 712A - 712B. In various embodiments, the memories 714A - 714B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM) (including graphics double data rate (GDDR) memory) or 3D stacked memory (including but not limited to high - bandwidth memory (HBM)).

[0159] In one embodiment, each compute cluster 706A - 706H includes a set of graphics multiprocessors, such as Figure 4A the graphics multiprocessor 400. The graphics multiprocessors of the compute clusters include multiple types of integer and floating - point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine - learning computations. For example and in one embodiment, at least one subset of the floating - point units in each of the compute clusters 706A - H can be configured to perform 16 - bit or 32 - bit floating - point operations, while a different subset of the floating - point units can be configured to perform 64 - bit floating - point operations.

[0160] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate via host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 700 to GPU link 710, which enables direct connection to other instances of the GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect to transfer data to and receive data from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 are located in separate data processing systems and communicate via a network device that can be accessed via host interface 702. In one embodiment, in addition to or as an alternative to host interface 702, GPU link 710 can be configured to enable connection to a host processor.

[0161] Although the illustrated configuration of GPGPU 700 can be configured to train neural networks, one embodiment provides an alternative configuration of GPGPU 700 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 700 includes fewer computing clusters 706A-H relative to the training configuration. Additionally, the memory technology associated with memories 714A-714B may differ between the inference configuration and the training configuration. In one embodiment, the inference configuration of GPGPU 700 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations for deployed neural networks.

[0162] Figure 8 A multi-GPU computing system 800 according to an embodiment is illustrated. The multi-GPU computing system 800 can include a processor 802 that is coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI express switch device that couples the processor 802 to a PCI express bus through which the processor 802 can communicate with the set of GPGPUs 806A-D. Each of the plurality of GPGPUs 806A-806D can be Figure 7An example of the GPGPU 700. The GPGPU 806A-D can be interconnected via a set of high-speed point-to-point GPU-to-GPU links 816. The high-speed GPU-to-GPU links can be connected to each of the GPGPU 806A-806D via dedicated GPU links (such as the GPU link 710 in Figure 7 ). The P2P GPU link 816 enables direct communication between each of the GPGPU 806A-806D without requiring communication through the host interface bus connected to by the processor 802. In the case where GPU-to-GPU traffic involves the P2P GPU link, the host interface bus can still be used for system memory access or communication with other instances of the multi-GPU computing system 800 via, for example, one or more network devices. Although in the illustrated embodiment the GPGPU 806A-806D are connected to the processor 802 via the host interface switch 804, in one embodiment the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPU 806A-806D.

[0163] Machine Learning Neural Network Implementation

[0164] The computing architecture provided by the embodiments described herein can be configured to perform a type of parallel processing particularly suitable for training and deploying neural networks for machine learning. A neural network can be generally characterized as a network of functions with graphical relationships. As is well known in the art, there are multiple types of neural network implementations used in machine learning. A demonstration type of neural network is the feedforward network described previously.

[0165] A second demonstration type of neural network is the convolutional neural network (CNN). A CNN is a specialized feedforward neural network for processing data with a known grid-like topology (such as image data). Thus, CNNs are commonly used in computer vision and image recognition applications, but they can also be used in other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to the nodes in the successive layers of the network. The computations for a CNN include applying the convolutional mathematical operation to each filter to produce the output of that filter. Convolution is a specialized kind of mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be referred to as the input, and the second function can be referred to as the convolution kernel. The output can be referred to as the feature map. For example, the input to a convolutional layer can be a multi-dimensional data array that defines the various color components of the input image. The convolution kernel can be a multi-dimensional parameter array, where the parameters are adapted through the training process for the neural network.

[0166] A Recurrent Neural Network (RNN) is a type of feedforward neural network that includes feedback connections between layers. RNN enables modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes a loop. The loop represents the influence of the current value of a variable on its own value at a future time, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. Due to the variable nature that language data can include, this feature makes RNN particularly useful for language processing.

[0167] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe the general processes for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non - limiting with respect to any particular embodiments described herein, and in general, the concepts illustrated can be generally applied to deep neural networks and machine learning techniques.

[0168] The exemplary neural networks described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. Contrary to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Training deeper neural networks is generally more computationally intensive. However, the additional hidden layers of the network enable multi - step pattern recognition, which results in reduced output error relative to shallow machine learning techniques.

[0169] The deep neural networks used in deep learning typically include a front - end network to perform feature recognition coupled to a back - end network representing a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables performing machine learning without requiring hand - crafted feature engineering for the model. Instead, the deep neural network can learn features based on the statistical structure or correlations within the input data. The learned features can be provided to the mathematical model, which can map the detected features into an output. The mathematical model used by the network is generally specialized for the particular task to be performed, and different models will be used to perform different tasks.

[0170] Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backpropagation of errors is a commonly used method for training neural networks. An input vector is presented to the network for processing. A loss function is used to compare the output of the network with the desired output, and an error value is calculated for each neuron in the output layer. The error value is then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm such as the stochastic gradient descent algorithm to update the weights of the neural network.

[0171] Figures 9A - 9B A exemplary convolutional neural network is illustrated. Figure 9A Illustrates the various layers within the CNN. As Figure 9A shown, an exemplary CNN for modeling image processing can receive an input 902 that describes the red, green, and blue (RGB) components of an input image. The input 902 can be processed by a plurality of convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The output from the plurality of convolutional layers can optionally be processed by a set of fully connected layers 908. Neurons in the fully connected layers have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layers 908 can be used to generate an output result from the network. Matrix multiplication rather than convolution can be used to calculate the activations within the fully connected layers 908. Not all CNN implementations use the fully connected layers 908. For example, in some implementations, the convolutional layer 906 can generate the output of the CNN.

[0172] Convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layers 908. Traditional neural network layers are fully connected such that each output unit interacts with each input unit. However, convolutional layers are sparsely connected because the output of the convolution of the domain (rather than the corresponding state value of each node in the domain) is input to the nodes of the subsequent layer, as illustrated. The kernel associated with the convolutional layer performs a convolution operation, and the output of the convolution operation is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables the CNN to scale to handle large images.

[0173] Figure 9B Illustrates an exemplary computational stage within the convolutional layer of a CNN. The input 912 to the convolutional layer of the CNN can be processed in three stages of the convolutional layer 914. These three stages can include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 can then output the data to a successive convolutional layer. The last convolutional layer of the network can generate output feature map data or provide an input to the fully connected layer, e.g., to generate classification values for the input to the CNN.

[0174] In the convolution stage 916, a number of convolutions are performed in parallel to produce a set of linear activations. The convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function (e.g., a neuron) connected to a specific region in the input, and the specific region can be determined as the local region associated with the neuron. The neuron computes the dot product between the weights of the neuron and the region in the local input to which the neuron is connected. The output from the convolution stage 916 defines a set of linear activations processed by successive stages of the convolutional layer 914.

[0175] The linear activations can be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a non-linear activation function. The non-linear activation function increases the non-linear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation functions can be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max( 0 , x ) such that the activation is thresholded at zero.

[0176] The pooling stage 920 uses a pooling function that replaces the output of the convolutional layer 906 with summary statistics of nearby outputs. The pooling function can be used to introduce translational invariance into the neural network so that small translations of the input do not change the pooled output. Invariance to local translations can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 920, including max pooling, average pooling, and l2-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations replace it with an additional convolutional stage that has an increased stride relative to the previous convolutional stage.

[0177] The output from the convolutional layer 914 can then be processed by the next layer 922. The next layer 922 can be either an additional convolutional layer or one of the fully connected layers 908. For example, Figure 9A the first convolutional layer 904 can output to the second convolutional layer 906, and the second convolutional layer can output to the first layer of the fully connected layer 908.

[0178] Figure 10FIG. illustrates a exemplary recurrent neural network 1000. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. The RNN can be built in a variety of ways using a variety of functions. The use of RNN generally revolves around using a mathematical model to predict the future based on a previous input sequence. For example, an RNN can be used to perform statistical language modeling to predict the upcoming word given a previous sequence of words. The illustrated RNN 1000 can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 for implementing a recurrent function, a feedback mechanism 1005 for enabling the 'memory' of the previous state, and an output layer 1006 for outputting the result. The RNN 1000 operates based on time steps. The state of the RNN at a given time step is affected by the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x 1 ) at the first time step can be processed by the hidden layer 1004. The second input (x 2 ) can be processed by the hidden layer 1004 using the state information determined during the processing of the initial input (x 1 ). A given state can be calculated as s t = f ( Ux t + Ws t-1 ), where U and W are parameter matrices. The function f is generally non-linear, such as the hyperbolic tangent function (Tanh) or a variant of the rectifier function f (x) = max( 0 , x ). However, the specific mathematical function used in the hidden layer 1004 can vary according to the specific implementation details of the RNN 1000.

[0179] In addition to the basic CNN and RNN networks described, variations of those networks can also be enabled. An example RNN variant is the long short-term memory (LSTM) RNN. The LSTM RNN is capable of learning long-term dependencies that may be necessary for processing longer language sequences. A variant of the CNN is the convolutional deep belief network, which has a structure similar to the CNN and is trained in a manner similar to the deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of stochastic (random) variables. Greedy unsupervised learning can be used to train the DBN layer by layer. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0180] Figure 11 Illustrated is the training and deployment of a deep neural network. Once a given network has been structured for a task, a training data set 1102 is used to train the neural network. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 the machine learning framework 604 can be configured as a training framework 604. The training framework 604 can be hooked up to an untrained neural network 1106 and enable the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1108.

[0181] To initiate the training process, initial weights can be selected randomly or by pre-training using a deep belief network. The training loop is then performed in a supervised or unsupervised manner.

[0182] Supervised learning is a learning method in which training is performed as a mediation operation, such as when the training data set 1102 includes the input paired with the desired output of the input, or when the training data set includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the input and compares the resulting output with a set of expected or desired outputs. The error is then backpropagated through the system. The training framework 1104 can be adjusted to adjust the weights that control the untrained neural network 1106. The training framework 1104 can provide tools to monitor how well the untrained neural network 1106 converges towards a model suitable for generating correct answers based on the known input data. The training process occurs repeatedly as the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to perform any number of machine learning operations.

[0183] Unsupervised learning is a learning method in which the network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training dataset 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled input and can determine how individual inputs relate to the overall dataset. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1107 capable of performing operations useful in reducing data dimensionality. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input dataset that deviate from the normal data pattern.

[0184] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1102 includes a mixture of labeled and unlabeled data from the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used to further train the model. Incremental learning enables the trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge instilled within the network during initial training.

[0185] Regardless of whether supervised or unsupervised, the training process for particularly deep neural networks can be computationally intensive for a single computing node. A distributed network of computing nodes can be used instead of a single computing node to accelerate the training process.

[0186] Figure 12 is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. Each distributed computing node can include one or more host processors and one or more of general-purpose processing nodes, such as the highly parallel general-purpose graphics processing unit 700 as in Figure 7 As illustrated, distributed learning can perform model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1204.

[0187] In model parallelism 1202, different computing nodes in the distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes of the distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of the neural network enables training of very large neural networks where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0188] In data parallelism 1204, different nodes of a distributed network have a complete instance of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. Although different methods for data parallelism are possible, data parallel training methods all require techniques for combining the results and synchronizing the model parameters across the nodes. Demonstrative methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are communicated instead of the parameters from the nodes to the parameter server. Additionally, update-based data parallelism can be performed in a decentralized manner where the updates are compressed and communicated between the nodes.

[0189] For example, the combined model and data parallelism 1206 can be implemented in a distributed system in which each computing node includes multiple GPUs. Each node can have a complete instance of the model, where individual GPUs within each node are used to train different parts of the model.

[0190] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques for reducing the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

[0191] Demonstration Machine Learning Application

[0192] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The scope of applications for computer vision ranges from replicating human visual capabilities such as face recognition to creating new categories of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced by objects visible in a video. Machine learning accelerated by parallel processors enables the use of training datasets that are significantly larger than previously feasible for training computer vision applications and enables the deployment of inference systems using low-power parallel processors.

[0193] Machine learning accelerated by a parallel processor has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. The accelerated machine learning techniques can be used to train a driving model based on a data set that defines appropriate responses to specific training inputs. The parallel processors described herein can enable the rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0194] Parallel-processor-accelerated deep neural networks have enabled machine learning methods for automatic speech recognition (ASR). ASR includes creating a function that computes the most likely language sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled replacing the previously used hidden Markov models (HMMs) and Gaussian mixture models (GMMs) for ASR.

[0195] Parallel-processor-accelerated machine learning can also be used to accelerate natural language processing. Automated learning programs can use statistical inference algorithms to produce models that are robust to incorrect or unfamiliar inputs. Demonstrative natural language processor applications include automatic machine translation between human languages.

[0196] The parallel processing platforms for machine learning can be divided into a training platform and a deployment platform. The training platform is generally highly parallel and includes optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Demonstrative parallel processors suitable for training include Figure 7 the highly parallel general-purpose graphics processing unit 700 and Figure 8 the multi-GPU computing system 800. In contrast, deployed machine learning platforms generally include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0197] Figure 13Illustrated is an exemplary inference system-on-a-chip (SOC) 1300 suitable for performing inference using a trained model. The SOC 1300 can integrate processing components, which include a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. The SOC 1300 can additionally include on-chip memory 1305, which can enable a shared on-chip data pool accessible by each of the processing components. The processing components can be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1300 can be used as part of the main control system for an autonomous vehicle. In the case where the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards for the deployment jurisdiction.

[0198] During operation, the media processor 1302 and the vision processor 1304 can work in concert to accelerate computer vision operations. The media processor 1302 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The vision processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames of the decoded video using a trained image recognition model. For example, the vision processor 1304 can accelerate the convolutional operations for a CNN used to perform image recognition on high-resolution video data, and the backend model computations are performed by the GPGPU 1306.

[0199] The multi-core processor 1308 can include control logic to assist in the ordering and synchronization of shared memory operations and data transfers performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 can also act as an application processor to execute software applications that can utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of the navigation and driving logic can be implemented in software executed on the multi-core processor 1308. Such software can directly issue computational workloads to the GPGPU 1306, or can issue computational workloads to the multi-core processor 1308, which can offload at least a portion of those operations to the GPGPU 1306.

[0200] The GPGPU 1306 may include a compute cluster, such as a low-power configuration of compute clusters 706A-706H within the highly parallel general-purpose graphics processing unit 700. The compute clusters within the GPGPU 1306 may support instructions that are specifically optimized to perform inference computations on a trained neural network. For example, the GPGPU 1306 may support instructions for performing low-precision computations, such as 8-bit and 4-bit integer vector operations.

[0201] Dynamic Floating - Point Unit Accuracy Reduction for Machine Learning Operations

[0202] The IEEE 754 single-precision binary floating-point format specifies a 32-bit binary representation with 1 bit for the sign, 8 bits for the exponent, and 24 bits for the significand, where 23 bits are explicitly stored. The IEEE 754 half-precision binary floating-point format specifies a 16-bit binary representation with 1 bit for the sign, 5 bits for the exponent, and 11 bits for the significand, where 10 bits are explicitly stored. For non-zero exponent values, the implicit significand bit is defined as 1, and is defined as 0 when all exponent bits are zero. Floating-point units capable of performing arithmetic operations in single and half precision are known in the art. For example, existing floating-point units may perform 32-bit single-precision floating-point operations (FP32) or dual 16-bit half-precision floating-point operations (FP16).

[0203] The embodiments described herein extend this capability by providing support for instructions and associated logic to enable variable-precision operations. Floating-point instructions that allow variable-precision operations may dynamically increase throughput by performing operations at a lower precision when possible. In one embodiment, associated logic and a set of instructions are provided, where throughput is increased by performing floating-point operations at the lowest possible precision without significant data loss. In one embodiment, associated logic and a set of instructions are provided, where the floating-point logic will verify the lower-precision result against the result of performing the operation at a higher precision to determine if any significant data loss has occurred.

[0204] Figure 14 Components of a dynamic-precision floating-point unit 1400 according to an embodiment are shown. In one embodiment of the dynamic-precision floating-point unit 1400, the dynamic-precision floating-point unit 1400 includes a control unit 1402, a set of internal registers 1404, an exponent block 1406, and a significand block 1408. In addition to the floating-point control logic known in the art, in one embodiment, the control unit 1402 additionally includes precision tracking logic 1412 and a numeric transformation unit 1422.

[0205] In one embodiment, the precision tracking logic 1412 is hardware logic configured to track the available number of precision bits of computational data related to a target precision. The precision tracking logic 1412 may track precision registers within the exponent block 1406 and the significand block 1408 to track precision metrics, such as the minimum number of precision bits required to store the computed values generated by the exponent block 1406 and the significand block 1408. In one embodiment, the precision metric includes a running average representing the numerical precision required for data over a set of computations. In one embodiment, the precision metric includes the maximum required precision within a given data set. In one embodiment, the dynamic precision floating point unit 1400 supports instructions to read or reset the register data used by the precision tracking logic 1412 to generate the precision metrics described herein. In one embodiment, the computational unit housing the dynamic precision floating point unit supports instructions to set or reset the register data used by the precision tracking logic 1412. In one embodiment, the precision tracking logic 1412 monitors an error accumulator 1434 in the set of internal registers 1404. The error accumulator may be used to track the accumulated error (e.g., rounding error) over a set of floating point operations. In one embodiment, the dynamic precision floating point unit 1400 supports a set of instructions including an instruction to reset the error accumulator 1434 and an instruction to read the error accumulator 1434. In one embodiment, the error accumulator may be reset in response to bits or flags supplied as operands to an instruction.

[0206] In one embodiment, the numerical transformation unit 1422 may be used to perform intermediate numerical transformations on data when performing lower precision operations to prevent or mitigate the likelihood of overflow or underflow when performing the operations. For example, when approaching the precision limit of a given data type, the numerical transformation unit 1422 may perform multiplication or division operations using logarithms and transform the resulting values via exponentiation. Further details regarding the precision tracking logic 1412 and the numerical transformation unit 1422 are provided in Figure 22 provided.

[0207] The internal register 1404 includes a set of operand registers 1414 that store input values for the dynamic precision floating point unit 1400. In one embodiment, the operand registers 1414 include two operands (A, B). For floating point input data, the input data values can be divided into an exponent part (EXA, EXB) and a significand part (SIGA, SIGB). In various embodiments, the operand registers 1414 are not limited to supporting two floating point inputs. In one embodiment, the operand registers 1414 include three input operands, for example to support fused multiply-add, multiply-subtract, multiply-accumulate, or related operations. In one embodiment, the operand registers 1414 can also store integer values, such as in one embodiment the dynamic precision floating point unit supports 32-bit, 16-bit, and 8-bit integer operations. In one embodiment, the specific data type and baseline precision are configurable via an input to the control unit 1402.

[0208] In one embodiment, an exponent block 1406 and a significand block 1408 are used to perform floating point operations with dynamic precision. In one embodiment, integer operations can be performed via the significand block 1408. In one embodiment, double 8-bit integer operations can be performed using the exponent block 1406 and the significand block 1408.

[0209] In one embodiment, the exponent block 1406 includes a comparator 1416 and a dynamic precision exponent adder 1426. The comparator determines the difference between the exponents and determines the smaller of the two exponents. During floating point addition, the exponent of the smaller number is adjusted to match the exponent of the larger number. The dynamic precision exponent adder 1426 can be used to add the exponent values for FP16 or FP32 values. The significand block 1408 includes a dynamic precision multiplier 1418, a shift unit 1428, a dynamic precision significand adder 1438, and an accumulator register 1448.

[0210] In one embodiment, an FP16 or FP32 data type may be specified for an operation. In the case where FP16 is specified, the dynamic precision floating-point unit 1400 may power gate elements that are not necessary for performing FP32 operations while maintaining logic to track precision loss or error (e.g., via the error accumulator 1434). For example and in one embodiment, the error accumulator 1434 may be used to track multiple rounding operations within an instruction cycle. In one embodiment, the error accumulator maintains a value of the total accumulated rounding error over a set of instructions. The dynamic precision floating-point unit 1400 may enable support for instructions to clear or read the error accumulator 1434 from software. In the case where FP32 is specified, the dynamic precision floating-point unit 1400 may attempt to perform FP32 operations at FP16 precision while powering gate elements and components that are gated beyond those required to perform operations at FP16 precision. Based on input or intermediate values, in the case where the dynamic precision floating-point unit 1400 is requested to perform an operation at FP32, the dynamic precision floating-point unit 1400 may initially attempt to perform the operation at FP16 and extend the precision to FP32 as needed. In cases where FP32 operations can be performed at FP16 precision, the power consumption requirement per operation is reduced, allowing a greater number of compute elements to be enabled simultaneously. For example, dynamic capacitance and / or power budget limitations for a given configuration (such as a battery-powered configuration or a passive-only cooling configuration) may not allow all floating-point units or other compute elements within a GPGPU to be enabled simultaneously. By enabling dynamically lower precision computations to reduce the dynamic power of a set of floating-point units, the overall throughput of the compute units of the GPGPU within a given power envelope can be increased because a greater number of threads can be processed on a per-cycle basis without exceeding the dynamic power limit.

[0211] Figure 15 Additional details of the dynamic precision floating-point unit 1400 according to an embodiment are provided with respect to Figure 14 In one embodiment, the dynamic precision multiplier 1418 includes a set of input buffers 1302 to store significand data. In one embodiment, the set of input buffers includes two buffers to store two input values for a multiplication or division operation. For fused operations (e.g., multiply-add, multiply-subtract), the product of the operation may be added to a third input via an adder and / or stored in an accumulator register.

[0212] In one embodiment, some configurations of the dynamic precision multiplier 1418 include an input buffer that is a 24-bit input (which can explicitly store 24-bit mantissa data for single-precision floating-point inputs or 11-bit mantissa data for half-precision floating-point values). In some configurations, the input buffer 1302 can also be a 32-bit buffer to enable multiplication of 32-bit integer values. In one embodiment, there is a single configuration of the input buffer 1302 that is selectable or configurable between 32 bits and 24 bits. In one embodiment, the output buffer 1310 is similarly configurable or selectable between 24 bits and 32 bits to selectively enable storage of 24-bit and / or 11-bit mantissa values of 32-bit or 16-bit floating-point numbers or full-precision 32-bit integers.

[0213] In one embodiment, the dynamic precision multiplier 1418 includes a multiplier 1306 and an overflow multiplier 1304. The multiplier 1306 is configurable to perform multiplication or division operations in half precision for a data type. For example, the multiplier 1306 can perform an 11-bit multiplication operation on the mantissa of an FP16 floating-point value and / or a 16-bit multiplication operation on 16-bit integer operations. The multiplier 1306 can also perform an 8-bit multiplication operation on INT8 integer values. For 32-bit floating-point values or 32-bit integer values, the multiplier 1306 can perform a multiplication operation on 24-bit mantissas in 11 bits (e.g., FP16 precision). If needed, the multiplier 1306 can perform multiplication values in 16-bit mantissa precision on 24-bit FP16 mantissas. In one embodiment, the precision required and obtained for operations on a given set of inputs can be tracked via a precision register 1308. In one embodiment, the required and obtained precision can be represented in the precision register 1308 via the precision loss incurred if the output of the multiplier 1306 is output via the output buffer 1310. In such embodiments, the precision register 1308 can track the precision loss associated with the use of lower-precision data types and the precision loss associated with performing operations at a precision lower than the requested precision.

[0214] In one embodiment, the control logic associated with the dynamic precision multiplier 1418 (e.g., within the control unit 1402 of Figure 14 ) can monitor the precision loss associated with operations that perform higher-precision (e.g., FP32, INT32) operations at a lower precision (e.g., FP16, INT16, INT8). If the precision loss would be significant, the control logic can cause the overflow multiplier 1304 to perform an operation on additional precision bits. Additionally, if the control logic determines that an overflow or underflow will occur based on the current inputs, the overflow multiplier 1304 is enabled and the multiplication operation is performed using the overflow multiplier 1304 and the multiplier 1306.

[0215] Similar control operations are performed on the dynamic precision exponent adder 1426 and the dynamic precision significand adder 1438. The dynamic precision exponent adder 1426 includes a set of 8-bit input buffers that can store exponent data for FP32 (8 bits) and FP16 (5 bits). The 8-bit input buffer 1312 can also store a set of INT-8 inputs. The output buffer 1320 for the dynamic precision exponent adder 1426 can be configured similarly. The dynamic precision significand adder 1438 includes a set of input buffers 1322 that can be selected from a set of 24-bit and 32-bit buffers or can be dynamically configurable to store 24-bit or 32-bit input data. In one embodiment, the input buffer 1322 is just a 32-bit buffer that can also store 24-bit input data. The output buffer 1330 for the dynamic precision significand adder 1438 can be configured similarly. The precision registers 1318 within the dynamic precision exponent adder 1426 and the precision registers 1328 within the dynamic precision significand adder 1438 can be configured to track the precision loss of the operations performed. The control logic can enable the overflow adder 1314 and / or the overflow adder 1324 as needed to prevent overflow or underflow conditions or to prevent the precision loss from exceeding a threshold.

[0216] Return Figure 14 , in one embodiment, the dynamic precision floating-point unit 1400 can use the dynamic precision exponent adder 1426 and the dynamic precision significand adder 1438 to perform double INT8 operations. For example, instead of disabling the exponent block 1406 during integer operations, the exponent block 1406 can be configured to perform operations on a first set of 8-bit integer operands, while the significand block 1408 can be configured to perform operations on a second set of 8-bit operands. To enable support for double 8-bit multiplication, double fused multiply-add, double fused multiply-subtract, and / or other multiplication-based operations, in one embodiment, the exponent block 1406 can include an additional multiplier 1436. The multiplier can be a fixed 8-bit multiplier to enable simultaneous double 8-bit multiplication operations using the exponent block 1406 and the significand block 1408.

[0217] Figure 16Illustrates thread assignment of a dynamic precision processing system 1600 according to an embodiment. In one embodiment, the dynamic precision processing system 1600 includes a set of dynamic floating-point units 1608A - 1608D. The dynamic floating-point units 1608A - 1608D can execute a set of operation threads 1606A - 1606D, which can perform mixed-precision operations and generate output data with variable precision. In one embodiment, a first operation (e.g., addition, subtraction, multiplication, division, etc.) can be executed by a first operation thread 1606A on a first dynamic floating-point unit 1608A, where the first operation thread 1606A accepts two 16-bit floating-point values 1602A - 1602B as inputs and outputs a 16-bit floating-point value FP16. The first operation can be executed as a dual operation, where a single instruction executed by the GPGPU allows a mixed-precision FP16 / FP32 dual operation. The second operation of the dual operation can be executed by a second operation thread 1606B, which is executed by a second dynamic floating-point unit 1608B, and the second dynamic floating-point unit 1608B can generate a second output 1612 as a 32-bit floating-point output. The second operation thread 1606B configures the second dynamic floating-point unit 1608B to receive two 32-bit floating-point input values 1603A - 1603B. In one embodiment, if an operation can be executed without excessive precision loss, underflow, or overflow by performing the operation at a lower precision, the operation on two 32-bit floating-point operations can be executed at 16-bit precision.

[0218] In one embodiment, the dynamic precision processing system 1600 can execute a single instruction with 16-bit operand 1604A and 32-bit operand 1604B. The operation thread 1606C can be executed on the dynamic floating-point unit 1608C. The dynamic floating-point unit 1608C will attempt to execute the mixed-precision 16-bit / 32-bit operation at 16-bit precision unless significant precision loss or error will occur. In one embodiment, the dynamic precision processing system 1600 can also be configured to execute integer operations. For example, operations on a pair of 8-bit integer inputs 1605A - 1605B can be executed via the operation thread 1606D by means of the dynamic floating-point unit 1608D to generate an 8-bit integer output 1616. In one embodiment, the dynamic floating-point unit 1608D can be configured to execute dual 8-bit integer operations, where two 8-bit integer operations can be executed in a single cycle.

[0219] Figure 17 Illustrates logic 1700 for performing a numerical operation at less than the requested precision according to an embodiment. In one embodiment, the logic 1700 is implemented via hardware integrated within Figure 14 the dynamic precision floating-point unit 1400. In one embodiment, the logic 1700 is partially via Figure 14It is executed by the control unit 1402 within the dynamic precision floating-point unit 1400.

[0220] In one embodiment, the logic 1700 may receive a request to perform a numerical operation at a first precision, as shown at block 1702. The numerical operation may be a floating-point operation or an integer operation. The first precision may be, for example, 32-bit precision. In one embodiment, the numerical operation may be an operation at the first precision that is performed on an operation with mixed precision. The logic 1700 may then perform the numerical operation using a plurality of bits associated with a second precision that is lower than the first precision, as shown at block 1704. For example and in one embodiment, the number of bits used to perform the operation may be a plurality of bits associated with a 16-bit operation, while the first precision is 32-bit precision. At block 1706, the logic 1700 may generate an intermediate result at the second precision. The logic 1700 may then determine the precision loss of the intermediate result associated with the first precision. The precision loss may be read from a register that stores a precision loss indicator stored during the operation.

[0221] At block 1709, the logic 1700 may determine whether the precision loss is less than a threshold. In one embodiment, the threshold associated with the precision loss may be software-configurable, although in some embodiments a hardware default threshold is used. In one embodiment, the degree of precision loss may also be determined by parallelly performing a full-precision operation on an unused computing unit. The reduced-precision result may then be compared with the full-precision result. If the precision loss is less than the threshold, the logic 1700 may output the result at the second precision, as shown at block 1712. If the precision loss is not less than the threshold at block 1709, at block 1710 the logic 1700 may calculate the remaining bits of the result and output the result at the first precision, as shown at block 1714. In one embodiment, the remaining bits of the calculated result may be performed at block 1710 via an overflow logic unit (such as the overflow multiplier 1304, overflow adder 1314, and / or overflow adder 1324 as in Figure 15 ).

[0222] Vertical Stacking Operation for 16 - Bit Floating - Point Operations

[0223] When performing single-instruction multiple-thread (SIMT) operations at a lower precision, in some cases, it may be difficult to maintain full utilization of the underlying single-instruction multiple-data (SIMD) logic because filling all SIMD lanes requires a large number of elements. For example, a SIMD logic unit configured for FP32 operations on a 128-bit input register can perform a single operation on four sets of input data. If the logic unit is configured to perform FP16 operations on the same four sets of input data, the underlying throughput of the operation may increase due to the lower operation precision, but the SIMD utilization is halved. One solution for underutilized SIMD is to perform operations on eight sets of input data. However, the software executed on the logic unit may not require as much parallelism as the underlying hardware can provide.

[0224] For example, a loop that performs iterative operations on an input array can be vectorized such that each iteration of the array is executed in parallel as a separate SIMT thread. Separate SIMT threads can execute on the underlying SIMD / vector logic within a compute unit in a single operation. When executing parallel instructions derived via compiler loop vectorization logic, loops shorter than 8 iterations will not fill all eight SIMD lanes available for executing the threads generated for those operations, reducing the overall utilization of the compute unit. Additionally, in the case where the underlying hardware has N SIMD lanes, any number of vectorized iterations that are not a multiple of N will require the remaining iterations to be executed on less than a full SIMD unit. Additionally, vectorization may require a separate peel loop to be executed before the body of the vectorized operation.

[0225] Some embodiments described herein can increase SIMD utilization by stacking multiple unrelated FP16 operations into a single SIMD unit for execution. In the case where the SIMD unit has 8 lanes available for execution, the thread scheduling logic can dispatch threads in units of N / 2 or N / 4 and allow unrelated sets of threads that are to perform the same or compatible operations to share a single SIMD unit. Additionally, one embodiment enables SIMD lane scheduling, which allows a dynamically assembled group of SIMT threads to be mixed with vector SIMD threads.

[0226] Figure 18Shows loop vectorization for a SIMD unit according to an embodiment. In one embodiment, the software logic may include loops automatically vectorized by compiler software executed on a data processing system. The loop may include a strip loop 1802, a vectorized main loop 1804, and a remainder loop 1806. In some configurations, loop vectorization is most effective when performed on data accessing aligned memory. For example, a GPGPU may be configured such that vector memory access can be most effectively performed in 64-byte chunks 1801A - 1801F. In such a configuration, the strip loop 1802 includes a subset of loop iterations stripped from the main loop to separate unaligned memory accesses from the main loop. The vectorized main loop 1804 includes most of the iterations of the loop. Each iteration of the vectorized main loop can be executed in parallel, and memory accesses to each element are aligned at a specific memory boundary. The remainder loop 1806 includes a set of iterations after the vectorized main loop 1804. Iterations in the remainder loop 1806 generally may not be executed in parallel as effectively as the main loop.

[0227] In one embodiment, the strip loop 1802 and the remainder loop 1806 may also be vectorized. In one embodiment, each of the strip loop 1802, the main loop 1804, and the remainder loop 1806 may be executed on an FP16 SIMD8 unit, where eight instances of the same operation can be executed in parallel. Loop iterations can be executed in parallel on SIMD hardware (e.g., FP16 SIMD8 units 1801A - 1808C) using execution masks 1812, 1814, and 1816 (each enabling and disabling SIMD lanes for an operation cycle). For the shown strip loop 1802 and remainder loop 1806, a subset of elements is selected in execution masks 1812 and 1816. All lanes are selected in the execution mask 1814 of the vectorized main loop 1804.

[0228] In one embodiment, a SIMD unit with inactive lanes can be configured to perform other operations on those inactive lanes. For a given cycle, where the scheduling logic configures a set of inactive lanes for a SIMD unit (e.g., FP16 SIMD8 1808A, FP16 SIMD8 108C) instead of idling those lanes during the cycle, the scheduler can stack other multi-element SIMD threads or assign SIMT threads to SIMD lanes that would otherwise be idle.

[0229] Figure 19FIG. 1900 shows a thread processing system 1900 according to an embodiment. In one embodiment, the thread processing system 1900 includes a SIMD computing unit, such as a SIMD8 floating-point unit 1920 that includes a plurality of dynamic floating-point units 1922A - 1922H. Depending on the operation, the SIMD8 floating-point unit 1920 can execute eight or more identical or similar operations in a single cycle. For example and in one embodiment, each of the eight dynamic floating-point units 1922A - 1922H can execute a single operation with FP16 precision. In one embodiment, each of the eight dynamic floating-point units 1922A - 1922H can execute two paired INT8 operations in a single cycle.

[0230] In some cases, such as with a peeling or remainder loop as shown in Figure 18 not all channels of the SIMD floating-point unit will be active during a cycle. To increase utilization, SIMD slots can be assigned at a smaller granularity to enable additional unused SIMD channels to be utilized. For example, the SIMD8 floating-point unit 1920 will generally be assigned threads or operations at an eight-operation granularity, where fewer than eight operations present a potential loss of computational efficiency. In one embodiment, a SIMD channel can be occupied by a single vector SIMD thread, which includes an execution mask that selects at least eight elements or a group of SIMT threads having at least eight elements.

[0231] To increase SIMD utilization, one embodiment divides the eight SIMD channels into two SIMD4 slots (e.g., SIMD4 slot 1910, SIMD4 slot 1912). The SIMD4 slots can be filled in a variety of ways. In one embodiment, two separate SIMD threads (SIMD thread 1902, SIMD thread 1904) that together cover a total of four SIMD channels are assigned to a SIMD4 slot (e.g., SIMD4 slot 1910). In one embodiment, a SIMT thread group 1906 can be assigned to SIMD4 slot 1912. The SIMT thread group 1906 can include any number of threads that are a multiple of four threads (e.g., 4, 8, 12, 16, etc.). The threads within the SIMT thread group 1906 can be processed four at a time, where the number of cycles required to process all the threads within the SIMT thread group 1906 depends on the number of threads in the group.

[0232] Figure 20 FIG. 2000 shows logic 2000 for assigning threads for computation according to an embodiment. In one embodiment, the logic 2000 is via as shown in Figure 19executed by the thread processing system 1900 therein. In one embodiment, the logic 2000 may receive a first set of threads at a SIMD unit having a first number of lanes, as shown at block 2002. The logic 2000 may then determine whether the first set of threads fills all of the SIMD lanes of the SIMD unit, as shown at block 2003. If the first set of threads includes a sufficient number of SIMT threads or the threads of the first set of threads include a sufficient number of SIMD vector elements to fill all of the SIMD lanes, the logic 2000 may assign the first set of threads to the SIMD unit, as shown at block 2004.

[0233] As determined at block 2003, if the first set of threads does not fill all of the SIMD lanes, at block 2006 the logic 2000 may assign the first set of threads to a second number of lanes, the second number of lanes being less than the first number of lanes. The assignment may be performed by assigning SIMD threads to the SIMD unit and masking out the inactive lanes. The assignment may also be performed by assigning a set of SIMT threads to the SIMD unit. As shown at block 2008, the logic may then stack one or more additional sets of threads to fill all of the SIMD lanes. The additional sets of threads may specify active SIMD lanes that occupy the lanes not occupied by the initial threads.

[0234] System Enabling Normalization and Transformation of Low - Precision Data

[0235] When performing operations with low-precision data types, care must be taken to avoid overflow or underflow of data during numerical operations. This responsibility typically falls on the data scientist developing the low-precision algorithms. Due to the limitations of low-precision arithmetic, many neural networks have adapted to use binary and / or ternary values (occupying only one or two bits per element). However, there is a need for integer and floating-point arithmetic logic units that can enable N-bit low-precision arithmetic with protection logic to warn or attempt to prevent significant loss of precision during arithmetic operations. In one embodiment, the dynamic precision floating-point unit described herein includes logic that warns when numerical calculations approach the low-precision calculation limit.

[0236] As Figure 14As shown, the dynamic precision floating point unit 1400 may include precision tracking logic 1412 and a numerical transformation unit 1422. In one embodiment, the precision tracking logic 1412 tracks the available bits of precision retained for the computed data related to the target precision. The available bits of precision may be tracked for intermediate data to determine whether an intermediate value (which is computed at a higher precision related to the input data or output data in one embodiment) can be stored at the output precision without significant loss of precision or rounding error. For example and in one embodiment, certain low precision operations may be efficiently performed at a higher precision, and the precision tracking logic 1412 may determine whether the result of the computation will overflow a given output precision. In one embodiment, the logic units described herein may output status information indicating the degree of precision loss due to rounding error. In one embodiment, the logic unit may perform intermediate numerical transformations on the data to prevent significant data loss. The logic unit may then output the transformed value. In one embodiment, a full precision or near full precision output value may be programmatically derived based on the output and status information provided with the output.

[0237] Figure 21 Shown is a deep neural network 2100 that may be processed using the computational logic provided by the embodiments described herein. A deep neural network (DNN) is an artificial neural network that includes multiple neural network layers 2102A - 2102N. Each layer represents a set of non - linear computational operations to perform feature extraction and transformation in a manner consistent with the machine learning neural networks described herein. Each successive layer uses the output from the previous layer as input. In the case of a convolutional neural network, fused multiply - add logic (e.g., FMA logic 2104A, 2104B) may be used to compute the dot product between the feature map and the filter data to generate activation map data provided as input to the successive layer.

[0238] Low - precision neural networks may be implemented using binary, ternary, or N - bit feature maps in combination with binary or ternary weights. Some neural networks may still benefit from the added computational precision of using N - bit feature maps and N - bit filters. In some implementations, the N - bit features and weights of a neural network may be processed at low precision without significantly reducing the output error. However, data scientists implementing low - precision N - bit neural networks (e.g., FP16, INT8) should generally be aware of the rounding errors or out - of - bounds data that may occur due to successive computations at low precision. If the precision tracking logic in the FMA logic 2104A - 2106B (e.g., Figure 14If the precision tracking logic 1412 determines that the weight or feature map data is approaching the limit of the available precision of the data type, the status bit can be set by the FMA logic 2104A - 2015B. The status bit can act as an indicator to the data scientist who is developing the neural network model existing within the neural network layers 2102A - 2012N, and the model can be alerted that optimization or higher numerical precision may be required.

[0239] In one embodiment, before providing the feature map data to the next neural network layer for input, the normalization and transformation logic 2106A - 2106B can be enabled to perform weight normalization or numerical transformation on the feature map data. The application of the normalization and transformation logic 2106A - 2106B is optional at each stage and can be performed only when significant precision loss, overflow, or underflow conditions are likely during the processing of the upcoming layer. In one embodiment, the weights or feature maps output from the layers of the neural network can be automatically normalized via an instance of the normalization and transformation logic 2106A - 2106B.

[0240] In one embodiment, the normalization and transformation logic 2106A - 2016B can use Figure 14 the numerical transformation unit 1422 to transform the feature map data or weight data. The feature map data output from the neural layer can be based on the data set output from the functional set. In such embodiments, a specific set of low - precision instructions is provided, which enables the automatic adjustment of N - bit neural network data to prevent catastrophic precision loss. Exemplary transformations or normalizations that can be performed by the normalization and transformation logic 2106A - 2016B include weight normalization for a set of continuous and reversible feature data transformation sets or value ranges. In one embodiment, weight normalization can be performed to compress the dynamic range of the filter weight set into a predetermined range. The weight data can be normalized, for example, within the range of [-1, 1], which can preserve the relative differences between the weight values while reducing the overall magnitude of the weight values. In one embodiment, the neural network weights or feature map data can be normalized by means of the average value of the data set.

[0241] In one embodiment, neural network computations using data that is close to the range limit of the data type can be transformed before the data is used in the computation. For example, a multiplication operation using large values that may cause overflow can be performed as an addition of logarithms instead of a multiplication operation. Although such a transformation may cause a certain degree of precision loss, the computation will be able to execute without overflowing the number of bits allocated to perform the operation. For example, a series of operations can be presented as in Equation (1).

[0242]

[0243] If the precision tracking logic within the computational unit determines that such an operation may overflow or underflow, then the operation may be transformed into equation (2).

[0244]

[0245] Equation (2) may be executed to produce a result without triggering overflow of the data type. In one embodiment, normalization and transformation logic 2106A-2016B may transform the output values ​​into logarithmic values ​​for storage and transform the values ​​by exponentiation before using the values ​​for machine learning calculations described herein.

[0246] Figure 22 2200 is a flow chart of logic 2200 for preventing errors or significant precision loss when performing low-precision operations for machine learning according to an embodiment. In one embodiment, the logic 2200 may be implemented as follows: Figure 14 This is achieved by the numerical conversion unit 1422 and the precision tracking logic 1412 within the dynamic precision floating point unit 1400.

[0247] In one embodiment, the logic 2200 may calculate activation maps based on filters and feature map data associated with a layer of a neural network, as shown at block 2202. The logic 2200 may then track the loss of precision that occurs during the calculation of the activation map for the neural network layer. The logic 2200 may then determine at block 2205 whether the loss of precision is approaching a threshold. If the loss of precision is not approaching a default or configured threshold at block 2205, the logic 2200 may continue to calculate activation maps (and apply activation functions) for successive layers until and unless a loss of precision approaches the threshold at block 2205. When the loss of precision approaches the threshold, the logic 2200 may determine at block 2207 whether automatic numerical transformation is enabled. If automatic transformation is enabled at block 2207, such as via instructions for performing a set of numerical operations, the logic 2200 may transform the neural network data to reduce errors due to the loss of precision at block 2208. The logic 2200 may perform any numerical transformation described herein, including normalization of data by means of an average or range. Regardless of whether automatic conversion is enabled at block 2207, the logic 2200 may output a status indicating that the loss of precision is approaching a threshold at block 2210. The status may be output as a status flag output from the computing unit as a result of the executed operation. The programmer may configure the software logic to respond to such status by performing algorithmic adjustments to the executing program or adjusting the neural network model used to perform machine learning.

[0248] Additional Demonstration Graphics Processing System

[0249] Details of the embodiments described above may be incorporated into the graphics processing systems and devices described below. Figures 23 through 36The graphics processing systems and devices shown can implement alternative systems and graphics processing hardware that can implement any and all of the technologies described above.

[0250] Additional Demonstration Graphics Processing System Overview

[0251] Figure 23 is a block diagram of a processing system 2300 according to an embodiment. In various embodiments, system 2300 includes one or more processors 2302 and one or more graphics processors 2308, and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2302 or processor cores 2307. In one embodiment, system 2300 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile devices, handheld devices, or embedded devices.

[0252] Embodiments of system 2300 can include a server-based game platform, a game console, which includes a game and media console, a mobile game console, a handheld game console, or an online game console, or be incorporated within them. In some embodiments, system 2300 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. The data processing system 2300 can also include a wearable device (such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), be coupled to, or integrated within, the wearable device. In some embodiments, the data processing system 2300 is a television or set-top box device having one or more processors 2302 and a graphical interface generated by one or more graphics processors 2308.

[0253] In some embodiments, each of the one or more processors 2302 includes one or more processor cores 2307 for processing instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 2307 is configured to process a particular instruction set 2309. In some embodiments, the instruction set 2309 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 2307 can each process a different instruction set 2309, which can include instructions for facilitating the emulation of other instruction sets. The processor cores 2307 can also include other processing devices, such as a digital signal processor (DSP).

[0254] In some embodiments, the processor 2302 includes a cache memory 2304. Depending on the architecture, the processor 2302 may have a single internal cache or multiple internal cache levels. In some embodiments, the cache memory is shared among various components of the processor 2302. In some embodiments, the processor 2302 also uses an external cache (e.g., a level 3 (L3) cache or a last-level cache (LLC)) (not shown), and the external cache can be shared among the processor cores 2307 using known cache coherence techniques. A register file 2306 is additionally included in the processor 2302, which may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor 2302.

[0255] In some embodiments, the processor 2302 is coupled to a processor bus 2310 to transfer communication signals, such as address, data, or control signals, between the processor 2302 and other components in the system 2300. In one embodiment, the system 2300 uses a exemplary 'hub' system architecture, including a memory controller hub 2316 and an input / output (I / O) controller hub 2330. The memory controller hub 2316 facilitates communication between the memory device and other components of the system 2300, while the I / O controller hub (ICH) 2330 provides a connection to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 2316 is integrated within the processor.

[0256] The memory device 2320 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance to act as a process memory. In one embodiment, the memory device 2320 may operate as the system memory of the system 2300 to store data 2322 and instructions 2321 for use when the one or more processors 2302 execute an application or a process. The memory controller hub 2316 is also coupled to an optional external graphics processor 2312, and the optional external graphics processor 2312 may communicate with the one or more graphics processors 2308 in the processor 2302 to perform graphics and media operations.

[0257] In some embodiments, the ICH 2330 enables peripheral devices to be connected to the memory device 2320 and the processor 2302 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 2346, a firmware interface 2328, a wireless transceiver 2326 (e.g., Wi-Fi, Bluetooth), a data storage device 2324 (e.g., a hard disk drive, a flash memory, etc.), and a legacy I / O controller 2340 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 2342 connect input devices, such as a keyboard and mouse 2344 combination. A network controller 2334 may also be coupled to the ICH 2330. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 2310. It will be appreciated that the system 2300 shown is exemplary and not restrictive, as other types of data processing systems configured differently may also be used. For example, the I / O controller hub 2330 may be integrated within the one or more processors 2302, or the memory controller hub 2316 and the I / O controller hub 2330 may be integrated into a discrete external graphics processor (such as the external graphics processor 2312).

[0258] Figure 24 is a block diagram of an embodiment of a processor 2400 that has one or more processor cores 2402A - 2402N, an integrated memory controller 2414, and an integrated graphics processor 2408. Figure 24 Those elements of having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto. The processor 2400 may include additional cores up to and including the additional core 2402N represented by the dashed block. Each of the processor cores 2402A - 2402N includes one or more internal cache units 2404A - 2404N. In some embodiments, each processor core is also capable of accessing one or more shared cache units 2406.

[0259] The internal cache units 2404A - 2404N and the shared cache units 2406 represent the cache memory hierarchy within the processor 2400. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level of cache, where the highest level of cache before the external memory is classified as the LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 2406 and 2404A - 2404N.

[0260] In some embodiments, the processor 2400 may further include a system agent core 2410 and a set of one or more bus controller units 2416. The one or more bus controller units 2416 manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express). The system agent core 2410 provides management functions for various processor components. In some embodiments, the system agent core 2410 includes one or more integrated memory controllers 2414 for managing access to various external memory devices (not shown).

[0261] In some embodiments, one or more of the processor cores 2402A - 2402N include support for simultaneous multithreading. In such embodiments, the system agent core 2410 includes components for coordinating and operating the processor cores 2402A - 2402N during multithreaded processing. The system agent core 2410 may additionally include a Power Control Unit (PCU) that includes logic and components for adjusting the power states of the processor cores 2402A - 2402N as well as the graphics processor 2408.

[0262] In some embodiments, the processor 2400 additionally includes a graphics processor 2408 for performing graphics processing operations. In some embodiments, the graphics processor 2408 is coupled to a set of shared cache units 2406 and the system agent core 2410, which includes the one or more integrated memory controllers 2414. In some embodiments, a display controller 2411 is coupled to the graphics processor 2408 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 2411 may be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within the graphics processor 2408 or the system agent core 2410.

[0263] In some embodiments, a ring - based interconnect unit 2412 is used to couple the internal components of the processor 2400. However, alternative interconnect units may be used, such as point - to - point interconnects, switched interconnects, or other techniques, including those well - known in the art. In some embodiments, the graphics processor 2408 is coupled to the ring interconnect 2412 via an I / O link 2413.

[0264] The exemplary I / O link 2413 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2418, such as an eDRAM module. In some embodiments, each of the processor cores 2402A - 2402N and the graphics processor 2408 uses the embedded memory module 2418 as a shared last-level cache.

[0265] In some embodiments, the processor cores 2402A - 2402N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 2402A - 2402N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 2402A - 2402N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 2402A - 2402N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more power-efficient cores. Additionally, the processor 2400 can be implemented on one or more chips or as a SoC integrated circuit that also has the shown components among other components.

[0266] Figure 25 is a block diagram of a graphics processor 2500, which can be a discrete graphics processing unit or can be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and using commands placed in the processor memory. In some embodiments, the graphics processor 2500 includes a memory interface 2514 for accessing memory. The memory interface 2514 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0267] In some embodiments, the graphics processor 2500 also includes a display controller 2502 for driving display output data to a display device 2520. The display controller 2502 includes hardware for one or more overlapping planes of the display and the composition of multi-layer video or user interface elements. In some embodiments, the graphics processor 2500 includes a video codec engine 2506 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, the one or more media coding formats including but not limited to Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1 and Joint Photographic Experts Group (JPEG) formats (such as JPEG, and Motion JPEG (MJPEG) formats).

[0268] In some embodiments, the graphics processor 2500 includes a block image transfer (BLIT) engine 2504 for performing two-dimensional (2D) rasterizer operations including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of the Graphics Processing Engine (GPE) 2510. In some embodiments, the GPE 2510 is a computing engine for performing graphics operations, the graphics operations including three-dimensional (3D) graphics operations and media operations.

[0269] In some embodiments, the GPE 310 includes a 3D pipeline 2512 for performing 3D operations such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2512 includes programmable and fixed function elements that perform various tasks within the element and / or generate a large number of execution threads to the 3D / media subsystem 2515. Although the 3D pipeline 2512 can be used to perform media operations, embodiments of the GPE 2510 also include a media pipeline 2516 that is specifically used to perform media operations such as video post-processing and image enhancement.

[0270] In some embodiments, media pipeline 2516 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encode acceleration, in place of, or on behalf of, video codec engine 2506. In some embodiments, media pipeline 2516 additionally includes a thread spawning unit to spawn threads for execution on 3D / media subsystem 2515. The spawned threads perform computations for media operations on one or more graphics execution units included in 3D / media subsystem 2515.

[0271] In some embodiments, 3D / media subsystem 2515 includes logic for executing threads spawned by 3D pipeline 2512 and media pipeline 2516. In one embodiment, the pipelines send thread execution requests to 3D / media subsystem 2515, which includes thread dispatch logic for arbitrating various requests and dispatching the various requests to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, 3D / media subsystem 2515 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0272] Demonstration Additional Graphics Processing Engine

[0273] Figure 26 is a block diagram of graphics processing engine 2610 of a graphics processor in accordance with some embodiments. In one embodiment, graphics processing engine (GPE) 2610 is Figure 25 a version of GPE 2510 shown in Figure 26 Elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the manner described elsewhere herein, but are not limited thereto. For example, 3D pipeline 2512 and media pipeline 2516 are shown in Figure 25 Media pipeline 2516 is optional in some embodiments of GPE 2610 and may not be explicitly included within GPE 2610. For example and in at least one embodiment, a separate media and / or image processor is coupled to GPE 2610.

[0274] In some embodiments, the GPE 2610 is coupled to or includes a command streamer 2603 that provides a command stream to the 3D pipeline 2512 and / or the media pipeline 2516. In some embodiments, the command streamer 2603 is coupled to a memory, which can be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 2603 receives commands from the memory and sends the commands to the 3D pipeline 2512 and / or the media pipeline 2516. The commands are indications fetched from a ring buffer that stores commands for the 3D pipeline 2512 and the media pipeline 2516. In one embodiment, the ring buffer can additionally include a batch command buffer that stores batches of multiple commands. Commands for the 3D pipeline 2512 can also include references to data stored in the memory, such as but not limited to vertex and geometry data for the 3D pipeline 2512 and / or image data and memory objects for the media pipeline 2516. The 3D pipeline 2512 and the media pipeline 2516 process commands and data by performing operations via logic within the respective pipeline or by dispatching one or more execution threads to the graphics core array 2614.

[0275] In various embodiments, the 3D pipeline 2512 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2614. The graphics core array 2614 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution units) within the graphics core array 2614 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

[0276] In some embodiments, the graphics core array 2614 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution units additionally include general-purpose logic programmable to perform parallel general-purpose computing operations. The general-purpose logic can perform processing operations in parallel with or in combination with the (one or more) processor cores 2307 as in Figure 23 or the processor cores 2402A - 2402N as in Figure 24 or the general-purpose logic within any of the processors described herein.

[0277] Output data generated by threads executing on the graphics core array 2614 can output data to memory in the unified return buffer (URB) 2618. The URB 2618 can store data for multiple threads. In some embodiments, the URB 2618 can be used to send data between different threads executing on the graphics core array 2614. In some embodiments, the URB 2618 can additionally be used for synchronization between fixed function logic within the shared function logic 2620 and threads on the graphics core array.

[0278] In some embodiments, the graphics core array 2614 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of the GPE 2610. In one embodiment, the execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0279] The graphics core array 2614 is coupled to shared function logic 2620, which includes multiple resources shared among the graphics cores in the graphics core array. The shared functions within the shared function logic 2620 are hardware logic units that provide specialized complementary functions to the graphics core array 2614. In various embodiments, the shared function logic 2620 includes, but is not limited to, sampler 2621, math 2622, and inter-thread communication (ITC) 2623 logic. Additionally, some embodiments implement one or more caches 2625 within the shared function logic 2620. The shared function is implemented in cases where the demand for a given specialized function is not sufficient to be included within the graphics core array 2614. Alternatively, a single instance of the specialized function is implemented as an independent entity within the shared function logic 2620 and shared among the execution resources within the graphics core array 2614. The exact set of functions shared among and included within the graphics core array 2614 varies between embodiments.

[0280] Figure 27 is a block diagram of another embodiment of the graphics processor 2700. Figure 27 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited to such.

[0281] In some embodiments, graphics processor 2700 includes a ring interconnect 2702, a pipeline front end 2704, a media engine 2737, and graphics cores 2780A-2780N. In some embodiments, ring interconnect 2702 couples the graphics processor to other processing units, which may include other graphics processors or one or more general processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system.

[0282] In some embodiments, graphics processor 2700 receives batches of commands via ring interconnect 2702. The incoming commands are interpreted by command streamer 2703 in pipeline front end 2704. In some embodiments, graphics processor 2700 includes scalable execution logic for performing 3D geometry processing and media processing via (a plurality of) graphics cores 2780A-2780N. For 3D geometry processing commands, command streamer 2703 supplies the commands to geometry pipeline 2736. For at least some media processing commands, command streamer 2703 supplies the commands to video front end 2734, which is coupled to media engine 2737. In some embodiments, media engine 2737 includes a video quality engine (VQE) 2730 for video and image post-processing and a multi-format encode / decode (MFX) 2733 engine for providing hardware-accelerated encoding and decoding of media data. In some embodiments, geometry pipeline 2736 and media engine 2737 each generate execution threads for execution resources provided by at least one of graphics cores 2780A.

[0283] In some embodiments, the graphics processor 2700 includes scalable thread execution resources featuring modular cores 2780A - 2780N (sometimes referred to as core slices), each of the modular cores 2780A - 2780N having multiple sub - cores 2750A - 2750N, 2760A - 2760N (sometimes referred to as corelets). In some embodiments, the graphics processor 2700 can have any number of graphics cores 2780A through 2780N. In some embodiments, the graphics processor 2700 includes a graphics core 2780A that has at least a first sub - core 2750A and a second sub - core 2760A. In other embodiments, the graphics processor is a low - power processor having a single sub - core (e.g., 2750A). In some embodiments, the graphics processor 2700 includes multiple graphics cores 2780A - 2780N, each including a set of first sub - cores 2750A - 2750N and a set of second sub - cores 2760A - 2760N. Each sub - core in the set of first sub - cores 2750A - 2750N includes at least a first set of execution units 2752A - 2752N and media / texture samplers 2754A - 2754N. Each sub - core in the set of second sub - cores 2760A - 2760N includes at least a second set of execution units 2762A - 2762N and samplers 2764A - 2764N. In some embodiments, each sub - core 2750A - 2750N, 2760A - 2760N shares a set of shared resources 2770A - 2770N. In some embodiments, the shared resources include a shared cache memory and pixel operation logic. Other shared resources can also be included in various embodiments of the graphics processor.

[0284] Demonstration additional execution unit

[0285] Figure 28 Thread execution logic 2800 is shown, which includes an array of processing elements employed in some embodiments of the GPE. Figure 28 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited to such.

[0286] In some embodiments, the thread execution logic 2800 includes a shader processor 2802, a thread dispatcher 2804, an instruction cache 2806, a scalable execution unit array including a plurality of execution units 2808A - 2808N, a sampler 2810, a data cache 2812, and a data port 2814. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 2808A, 2808B, 2808C, 2808D through 2808N - 1 and 2808N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, the thread execution logic 2800 includes one or more connections to memory (such as system memory or a cache) via the instruction cache 2806, the data port 2814, the sampler 2810, and one or more of the execution units 2808A - 2808N. In some embodiments, each execution unit (e.g., 2808A) is an independent programmable general - purpose computing unit capable of executing multiple simultaneous hardware threads and processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2808A - 2808N is scalable to include any number of individual execution units.

[0287] In some embodiments, the execution units 2808A - 2808N are primarily used to execute shader programs. The shader processor 2802 can process various shader programs and dispatch execution threads associated with the shader programs via the thread dispatcher 2804. In one embodiment, the thread dispatcher includes logic for arbitrating requests to initiate threads from the graphics and media pipelines and instantiating the requested threads on one or more of the execution units 2808A - 2808N. For example, a geometry pipeline (e.g., Figure 27 2736) can dispatch vertex, tessellation, or geometry shaders to the thread execution logic 2800 ( Figure 28 ) for processing. In some embodiments, the thread dispatcher 2804 can also handle runtime thread spawning requests from executing shader programs.

[0288] In some embodiments, execution units 2808A - 2808N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs from graphics libraries (e.g., Direct 3D and OpenGL) to be executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general - purpose processing (e.g., compute and media shaders). Each of the execution units 2808A - 2808N has the ability for multi - issue single - instruction multiple - data (SIMD) execution, and multi - threading operations enable an efficient execution environment in the face of higher - latency memory accesses. Each hardware thread within each execution unit has a dedicated high - bandwidth register file and associated independent thread state. For pipelines with integer, single - and double - precision floating - point operations, SIMD branch capabilities, logical operations, transcendental operations, and other miscellaneous operation capabilities, execution is multi - issue per clock. When waiting for data from one of memory or a shared function, the dependency logic within execution units 2808A - 2808N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during the latency associated with vertex shader operations, the execution unit can perform operations of pixel shaders, fragment shaders, or another type of shader program including a different vertex shader.

[0289] Each execution unit among execution units 2808A - 2808N operates on an array of data elements. The number of data elements is the "execution size", or the number of lanes for an instruction. Execution lanes are logical units for data - element access, masking, and flow control within an instruction. The number of lanes can be independent of the number of physical arithmetic - logic units (ALUs) or floating - point units (FPUs) for a particular graphics processor. In some embodiments, execution units 2808A - 2808N support integer and floating - point data types.

[0290] The execution - unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256 - bit - wide vector, the 256 - bit vector is stored in a register and the execution unit operates on the vector as four separate 64 - bit compressed data elements (quad - word (QW) - sized data elements), eight separate 32 - bit compressed data elements (double - word (DW) - sized data elements), sixteen separate 16 - bit compressed data elements (word (W) - sized data elements), or thirty - two separate 8 - bit data elements (byte (B) - sized data elements). However, different vector widths and register sizes are possible.

[0291] One or more internal instruction caches (e.g., 2806) are included in the thread execution logic 2800 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 2812) are included to cache thread data during thread execution. In some embodiments, a sampler 2810 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2810 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0292] During execution, the graphics and media pipeline sends thread launch requests to the thread execution logic 2800 via the thread spawning and dispatching logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2802 is called to further compute the output information and cause the results to be written to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader computes the values of various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 2802 then executes pixel or fragment shader programs supplied by an application programming interface (API). To execute the shader programs, the shader processor 2802 dispatches threads to the execution units (e.g., 2808A) via the thread dispatcher 2804. In some embodiments, the pixel shader 2802 uses the texture sampling logic in the sampler 2810 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and the input geometric data compute the pixel color data for each geometric fragment, or discard one or more pixels from further processing.

[0293] In some embodiments, the data port 2814 provides a memory access mechanism for the thread execution logic 2800 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 2814 includes or is coupled to one or more caches (e.g., the data cache 2812) to cache data for memory access via the data port.

[0294] Figure 29is a block diagram showing a graphics processor instruction format 2900 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set with instructions having multiple formats. The solid blocks show components generally included in the execution unit instructions, while the dashed lines include optional or components included only in a subset of the instructions. In some embodiments, the described and shown instruction format 2900 is a macro-instruction as they are the instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decoding once the instruction is processed.

[0295] In some embodiments, a graphics processor execution unit natively supports instructions in a 128-bit instruction format 2910. Based on the selected instruction, instruction options, and number of operands, a 64-bit compressed instruction format 2930 can be used for some instructions. The native 128-bit instruction format 2910 provides access to all instruction options, while some options and operations are limited in the 64-bit format 2930. The native instructions available in the 64-bit format 2930 vary by embodiment. In some embodiments, a set of index values in an index field 2913 is used to partially compress the instruction. The execution unit hardware references a set of compression tables based on the index values and uses the compressed table output to reconstruct the native instruction in the 128-bit instruction format 2910.

[0296] For each format, an instruction opcode 2912 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel, where each color channel represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, an instruction control field 2914 enables control of certain execution options, such as channel selection (e.g., predication) and data channel ordering (e.g., swizzling). For instructions in the 128-bit instruction format 2910, an execution size field 2916 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 2916 is not available for use in the 64-bit compressed instruction format 2930.

[0297] Some execution unit instructions have up to three operands, including two source operands - src0 2920, src1 2922, and one destination 2918. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions can have a third source operand (e.g., SRC2 2924), where the instruction opcode 2912 determines the number of source operands. The last source operand of the instruction can be an immediate (e.g., hard-coded) value passed with the instruction.

[0298] In some embodiments, the 128-bit instruction format 2910 includes an access / addressing mode field 2926 that specifies, for example, whether a direct register addressing mode or an indirect register addressing mode is used. When the direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

[0299] In some embodiments, the 128-bit instruction format 2910 includes an access / addressing mode field 2926 that specifies the addressing mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte alignment access mode and a 1-byte alignment access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands.

[0300] In one embodiment, the addressing mode portion of the access / addressing mode field 2926 determines whether the instruction is to use direct addressing or indirect addressing. When the direct register addressing mode is used, bits in the instruction directly provide the register addresses of one or more operands. When the indirect register addressing mode is used, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0301] In some embodiments, instructions are grouped based on the 2912-bit opcode field to simplify opcode decoding 2940. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is merely exemplary. In some embodiments, the move and logic opcode group 2942 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2942 shares the five most significant bits (MSB), where the move (mov) instruction takes the form 0000xxxxb and the logic instruction takes the form 0001xxxxb. The flow control instruction group 2944 (e.g., call, jump (jmp)) includes instructions that take the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2946 includes a mix of instructions, including synchronization instructions (e.g., wait, send) that take the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 2948 includes arithmetic instructions (e.g., add, multiply (mul)) in the component aspect that take the form 0100xxxxb (e.g., 0x40). The parallel math group 2948 performs arithmetic operations in parallel across data channels. The vector math group 2950 includes arithmetic instructions (e.g., dp4) that take the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations.

[0302] Demonstration additional graphics pipeline

[0303] Figure 30 is a block diagram of another embodiment of the graphics processor 3000. Figure 30 Elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited to such.

[0304] In some embodiments, the graphics processor 3000 includes a graphics pipeline 3020, a media pipeline 3030, a display engine 3040, thread execution logic 3050, and a render output pipeline 3070. In some embodiments, the graphics processor 3000 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued through the ring interconnect 3002 to the graphics processor 3000. In some embodiments, the ring interconnect 3002 couples the graphics processor 3000 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 3002 are interpreted by a command streamer 3003, which supplies instructions to individual components of the graphics pipeline 3020 or the media pipeline 3030.

[0305] In some embodiments, the command streamer 3003 directs the operation of the vertex fetcher 3005, which reads vertex data from memory and executes vertex processing commands provided by the command streamer 3003. In some embodiments, the vertex fetcher 3005 provides vertex data to the vertex shader 3007, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 3005 and the vertex shader 3007 execute vertex processing instructions by dispatching execution threads to the execution units 3052A - 3052B via the thread dispatcher 3031.

[0306] In some embodiments, the execution units 3052A - 3052B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, the execution units 3052A - 3052B have attached L1 caches 3051, which are specific to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0307] In some embodiments, the graphics pipeline 3020 includes a tessellation component for performing hardware - accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operation. The programmable domain shader 817 provides a backend evaluation of the tessellation output. The tessellator 3013 operates in the direction of the hull shader 3011 and includes dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model, which are provided as input to the graphics pipeline 3020. In some embodiments, if tessellation is not used, the tessellation component (e.g., the hull shader 3011, the tessellator 3013, and the domain shader 3017) can be bypassed.

[0308] In some embodiments, the complete geometric object can be processed by the geometry shader 3019 via one or more threads dispatched to the execution units 3052A - 3052B, or can proceed directly to the clipper 3029. In some embodiments, the geometry shader operates on the entire geometric object rather than on vertices or vertex patches as in the previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 3019 receives input from the vertex shader 3007. In some embodiments, the geometry shader 3019 can be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0309] Before rasterization, the clipper 3029 processes vertex data. The clipper 3029 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader capabilities. In some embodiments, the rasterizer and depth test component 3073 in the render output pipeline 3070 dispatches pixel shaders to convert geometric objects into their per-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 3050. In some embodiments, an application can bypass the rasterizer and depth test component 3073 and access the un-rasterized vertex data via the issue unit 3023.

[0310] The graphics processor 3000 has an interconnect bus, an interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed between the major components of the processor. In some embodiments, the execution units 3052A - 3052B and the associated caches 3051, the texture and media sampler 3054, and the texture / sampler cache 3058 are interconnected via the data port 3056 to perform memory accesses and communicate with the render output pipeline components of the processor. In some embodiments, the sampler 3054, the caches 3051, 3058, and the execution units 3052A - 3052B each have separate memory access paths.

[0311] In some embodiments, the render output pipeline 3070 includes a rasterizer and depth test component 3073 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. The associated render cache 3078 and depth cache 3079 are also available in some embodiments. The pixel operation component 3077 performs pixel-based operations on the data, however, in some instances, pixel operations associated with 2D operations (e.g., bit-block blitting with blending) are performed by the 2D engine 3041, or at display time, the display controller 3043 uses an overlay display plane instead. In some embodiments, a shared L3 cache 3075 is available for all graphics components, allowing data to be shared without using the main system memory.

[0312] In some embodiments, the graphics processor media pipeline 3030 includes a media engine 3037 and a video front end 3034. In some embodiments, the video front end 3034 receives pipeline commands from the command streamer 3003. In some embodiments, the media pipeline 3030 includes a separate command streamer. In some embodiments, the video front end 3034 processes the commands before sending the media commands to the media engine 3037. In some embodiments, the media engine 3037 includes a thread spawning function to spawn threads for dispatch to the thread execution logic 3050 via the thread dispatcher 3031.

[0313] In some embodiments, the graphics processor 3000 includes a display engine 3040. In some embodiments, the display engine 3040 is external to the processor 3000 and is coupled to the graphics processor via the ring interconnect 3002 or some other interconnect bus or fabric. In some embodiments, the display engine 3040 includes a 2D engine 3041 and a display controller 3043. In some embodiments, the display engine 3040 contains dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 3043 is coupled to a display device (not shown), which may be a system integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0314] In some embodiments, the graphics pipeline 3020 and the media pipeline 3030 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the driver software for the graphics processor converts API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and compute APIs, all from the Khronos Group. In some embodiments, support can also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, combinations of these libraries can be supported. Support can also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with a compatible 3D pipeline will also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

[0315] Graphics pipeline programming

[0316] Figure 31A is a block diagram showing a graphics processor command format 3100 according to some embodiments. Figure 31B is a block diagram showing a graphics processor command sequence 3110 according to an embodiment. Figure 31AThe solid blocks therein illustrate components that are generally included in a graphics command, while the dashed lines include optional components or components that are only included in a subset of the graphics command. Figure 31A A exemplary graphics processor command format 3100 includes data fields for identifying a target client 3102 of the command, a command operation code (opcode) 3104, and associated data 3106 of the command. Some commands also include a sub-opcode 3105 and a command size 3108.

[0317] In some embodiments, the client 3102 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition further processing of the command and route the command data to an appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 3104 and the sub-opcode 3105 (if present) to determine the operation to be performed. The client unit uses the information in the data field 3106 to execute the command. For some commands, an explicit command size 3108 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands in the command based on the command opcode. In some embodiments, commands are aligned by a multiple of a double word.

[0318] Figure 31B The flow therein illustrates an exemplary graphics processor command sequence 3110. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the illustrated command sequence to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described only for purposes of example, as embodiments are not limited to these particular commands or this command sequence. Moreover, the commands may be issued as a batch of commands in a command sequence such that the graphics processor will process the sequence of commands at least partially concurrently.

[0319] In some embodiments, the graphics processor command sequence 3110 may begin with a pipeline dump clear command 3112 to cause any active graphics pipeline to complete the current outstanding commands for that pipeline. In some embodiments, the 3D pipeline 3122 and the media pipeline 3124 do not operate simultaneously. A pipeline dump clear is performed to cause the active graphics pipeline to complete any outstanding commands. In response to the pipeline dump clear, the command parser for the graphics processor will suspend command processing until the active rendering engine has completed the outstanding operations and the associated read caches are invalidated. Optionally, any data marked as 'dirty' in the render cache may be dumped to memory. In some embodiments, the pipeline dump clear command 3112 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0320] In some embodiments, a pipeline select command 3113 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, only one pipeline select command 3113 is required within an execution context before issuing pipeline commands, unless the context is to issue commands for both pipelines. In some embodiments, a pipeline dump clear command 3112 is required immediately before a pipeline switch via the pipeline select command 3113.

[0321] In some embodiments, the pipeline control command 3114 configures the graphics pipeline for operation and programs the 3D pipeline 3122 and the media pipeline 3124. In some embodiments, the pipeline control command 3114 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command 3114 is used for pipeline synchronization and for clearing data from one or more caches within the active pipeline before processing a batch of commands.

[0322] In some embodiments, the return buffer status command 3116 is used to configure a set of return buffers for enabling the corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer status 3116 includes selecting the size and number of return buffers to be used for a set of pipeline operations.

[0323] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on the pipeline determination 3120, the command sequence is suitable for the 3D pipeline 3122 starting with the 3D pipeline state 3130 or the media pipeline 3124 starting in the media pipeline state 3140.

[0324] Commands for configuring the 3D pipeline state 3130 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured prior to processing 3D primitive commands. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, the 3D pipeline state 3130 commands are also capable of selectively disabling or bypassing certain pipeline elements if those elements will not be used.

[0325] In some embodiments, 3D primitive 3132 commands are used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters passed to the graphics processor via 3D primitive 3132 commands are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 3132 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 3132 commands are used to perform vertex operations on 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 3122 dispatches shader execution threads to the graphics processor execution units.

[0326] In some embodiments, the 3D pipeline 3122 is triggered via an execution 3134 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to flush a clear command sequence through the graphics pipeline. The 3D pipeline will perform geometric processing on the 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0327] In some embodiments, when performing media operations, the graphics processor command sequence 3110 follows the media pipeline 3124 path. Generally, the particular use and manner of programming for the media pipeline 3124 depends on the media or compute operation to be performed. During media decoding, specific media decoding operations may be offloaded to the media pipeline. In some embodiments, the media pipeline may also be bypassed and resources provided by one or more general-purpose processing cores may be used to perform media decoding, either in whole or in part. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs not explicitly related to rendering graphics primitives.

[0328] In some embodiments, the media pipeline 3124 is configured in a manner similar to the 3D pipeline 3122. A set of commands for configuring the media pipeline state 3140 is dispatched or placed into a command queue, before the media object commands 3142. In some embodiments, the media pipeline state commands 3140 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state commands 3140 also support the use of one or more pointers to "indirect" state elements that point to a batch of state settings.

[0329] In some embodiments, the media object commands 3142 supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers that contain video data to be processed. In some embodiments, all media pipeline states must be valid before the media object commands 3142 are issued. Once the pipeline state is configured and the media object commands 3142 are queued, the media pipeline 3124 is triggered via an execute command 3144 or an equivalent execution event (e.g., a register write). The output from the media pipeline 3124 can then be post-processed by operations provided by the 3D pipeline 3122 or the media pipeline 3124. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0330] Graphics software architecture

[0331] Figure 32 A exemplary graphics software architecture of a data processing system 3200 is shown according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 3210, an operating system 3220, and at least one processor 3230. In some embodiments, the processor 3230 includes a graphics processor 3232 and one or more general-purpose processor cores 3234. The graphics application 3210 and the operating system 3220 each execute in the system memory 3250 of the data processing system.

[0332] In some embodiments, the 3D graphics application 3210 includes one or more shader programs that include shader instructions 3212. The shader language instructions can be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 3214 in machine language suitable for execution by the general-purpose processor cores 3234. The application also includes graphics objects 3216 defined by vertex data.

[0333] In some embodiments, the operating system 3220 is the Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open-source UNIX-like operating system using a variant of the Linux kernel. The operating system 3220 may support a graphics API 3222, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 3220 uses a front-end shader compiler 3224 to compile any shader instructions 3212 in HLSL into a lower-level shader language. The compilation may be just-in-time (JIT) compilation, or the application may perform shader pre-compilation. In some embodiments, during the compilation of the 3D graphics application 3210, high-level shaders are compiled into low-level shaders. In some embodiments, the shader instructions 3212 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0334] In some embodiments, the user-mode graphics driver 3226 includes a backend shader compiler 3227 for converting the shader instructions 3212 into a hardware-specific representation. When the OpenGL API is in use, the shader instructions 3212 in the GLSL high-level language are passed to the user-mode graphics driver 3226 for compilation. In some embodiments, the user-mode graphics driver 3226 uses the operating system kernel-mode functionality 3228 to communicate with the kernel-mode graphics driver 3229. In some embodiments, the kernel-mode graphics driver 3229 communicates with the graphics processor 3232 to dispatch commands and instructions.

[0335] IP core implementation

[0336] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions representing various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate logic for performing the techniques described herein. Such representations (referred to as “IP cores”) are reusable units of logic for an integrated circuit, which may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to various consumers or manufacturing facilities that load the hardware model on a manufacturing machine for fabricating the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

[0337] Figure 33FIG. 3300 is a block diagram showing an IP core development system 3300 that can be used to fabricate integrated circuits to perform operations. The IP core development system 3300 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build an entire integrated circuit (e.g., a SOC integrated circuit). A design facility 3330 can generate a software simulation 3310 of an IP core design in a high-level programming language (e.g., C / C++). The software simulation 3310 can be used to design, test, and verify the behavior of the IP core using a simulation model 3312. The simulation model 3312 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 3315 can then be created or synthesized from the simulation model 3312. The RTL design 3315 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers and includes the associated logic executed using the modeled digital signals. In addition to the RTL design 3315, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

[0338] The RTL design 3315 or equivalent can be further synthesized by the design facility into a hardware model 3320, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. A non-volatile memory 3340 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 3365. Alternatively, the IP core design can be transmitted (e.g., via the Internet) over a wired connection 3350 or a wireless connection 3360. The manufacturing facility 3365 can then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0339] Demonstration system-on-chip integrated circuit

[0340] Figures 34 - 36 FIG. shows exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores in accordance with various embodiments described herein. In addition to the things shown, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0341] Figure 34is a block diagram showing an exemplary system-on-chip integrated circuit 3400 that can be fabricated using one or more IP cores. The exemplary integrated circuit 3400 includes one or more application processors 3405 (e.g., CPUs), at least one graphics processor 3410, and additionally may include an image processor 3415 and / or a video processor 3420, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 3400 includes peripheral or bus logic that includes a USB controller 3425, a UART controller 3430, an SPI / SDIO controller 3435, and an I 2 S / I 2 C controller 3440. Additionally, the integrated circuit may include a display device 3445 that is coupled to one or more of a high-definition multimedia interface (HDMI) controller 3450 and a mobile industry processor interface (MIPI) display interface 3455. Storage may be provided by a flash memory subsystem 3460 that includes a flash memory and a flash memory controller. A memory interface may be provided via a memory controller 3465 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 3470.

[0342] Figure 35 is a block diagram showing an exemplary graphics processor 3510 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores. The graphics processor 3510 may be Figure 34 a variant of the graphics processor 3410. The graphics processor 3510 includes a vertex processor 3505 and one or more fragment processors 3515A - 3515N (e.g., 3515A, 3515B, 3515C, 3515D to 3515N - 1, and 3515N). The graphics processor 3510 may execute different shader programs via separate logic such that the vertex processor 3505 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 3515A - 3515N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 3505 executes the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. The (multiple) fragment processors 3515A - 3515N use the primitives and vertex data generated by the vertex processor 3505 to produce a frame buffer that is displayed on a display device. In one embodiment, the (multiple) fragment processors 3515A - 3515N are optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs as provided in the Direct3D API.

[0343] The graphics processor 3510 additionally includes one or more memory management units (MMUs) 3520A - 3520B, caches 3525A - 3525B, and circuit interconnects 3530A - 3530B. The one or more MMUs 3520A - 3520B provide a virtual - to - physical address mapping for the image processor 3510, including the vertex processor 3505 and / or the fragment processors 3515A - 3515N, and the virtual - to - physical address mapping can reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in the one or more caches 3525A - 3525B. In one embodiment, the one or more MMUs 3520A - 3520B can be synchronized with other MMUs within the system, the other MMUs including one or more MMUs associated with Figure 34 the one or more application processors 3405, image processors 3415, and / or video processors 3420 such that each processor 3405 - 3420 can participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 3530A - 3530B enable the graphics processor 3510 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0344] Figure 36 is a block diagram showing an additional exemplary graphics processor 3610 of a system - on - chip integrated circuit that can be fabricated using one or more IP cores. The graphics processor 3610 can be Figure 34 a variant of the graphics processor 3410. The graphics processor 3610 includes Figure 35 the one or more MMUs 3520A - 3520B, caches 3525A - 3525B, and circuit interconnects 3530A - 3530B of the integrated circuit 3500.

[0345] The graphics processing unit 3610 includes one or more shader cores 3615A - 3615N (e.g., 3615A, 3615B, 3615C, 3615D, 3615E, 3615F to 3615N - 1, and 3615N), which provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, and the programmable shader code includes shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present can vary among embodiments and implementations. Additionally, the graphics processing unit 3610 includes an inter - core task manager 3605, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 3615A - 3615N, and a tiling unit 3618 for accelerating tiled operations for tile - based rendering, where the rendering operations for a scene are subdivided in the image space, e.g., for taking advantage of local spatial coherence within the scene or for optimizing the use of internal caches.

[0346] The present invention also provides a set of technical solutions as follows:

[0347] 1. A general - purpose graphics processing unit, comprising:

[0348] A dynamic - precision floating - point unit including a control unit, the control unit having precision - tracking hardware logic to track the available number of precision bits of computational data related to a target precision, wherein the dynamic - precision floating - point unit includes computational logic to output data in multiple precisions.

[0349] 2. The general - purpose graphics processing unit according to technical solution 1, wherein the dynamic - precision floating - point unit includes a register set to store input data and intermediate data in multiple precisions.

[0350] 3. The general - purpose graphics processing unit according to technical solution 2, wherein the register set includes an error accumulator to track the accumulated error on a set of floating - point operations.

[0351] 4. The general - purpose graphics processing unit according to technical solution 1, the dynamic - precision floating - point unit includes a significand block to perform the significand part of a floating - point calculation, the significand block including a dynamic - precision adder configurable to add or subtract input data in multiple precisions.

[0352] 5. The general - purpose graphics processing unit according to technical solution 4, the significand block includes a dynamic - precision multiplier configurable to add or multiply or divide input data in multiple precisions.

[0353] 6. The general - purpose graphics processing unit as described in technical solution 5, wherein the dynamic - precision floating - point unit includes an exponent block to perform the exponent part of floating - point calculations, the exponent block includes a dynamic - precision adder, and the dynamic - precision adder is configurable to add or subtract the exponents of input data with multiple precisions.

[0354] 7. The general - purpose graphics processing unit as described in technical solution 6, wherein the exponent block and the mantissa block are used to perform a first floating - point operation to output a first output value with 16 - bit precision.

[0355] 8. The general - purpose graphics processing unit as described in technical solution 7, wherein the exponent block and the mantissa block are used to perform a second operation to output a second output value with 32 - bit precision.

[0356] 9. The general - purpose graphics processing unit as described in technical solution 8, wherein the exponent block and the mantissa block are used to perform a third floating - point operation on input data with a 32 - bit value to output a third output value with a 32 - bit data type, and the third output value is generated with 16 - bit precision.

[0357] 10. The general - purpose graphics processing unit as described in technical solution 9, wherein the exponent block includes an 8 - bit multiplier, and wherein the exponent block and the mantissa block are configurable to perform a double 8 - bit integer operation.

[0358] 11. A method for performing variable - precision operations within the hardware of a general - purpose graphics processing unit, the method comprising:

[0359] Receiving a request to perform a numerical operation with a first precision;

[0360] Performing the numerical operation using multiple bits associated with a second precision lower than the first precision;

[0361] Generating an intermediate result with the second precision;

[0362] Determining a precision loss of the intermediate result; and

[0363] When the precision loss of the intermediate result is lower than a threshold, outputting the result with the second precision.

[0364] 12. The method as described in technical solution 11, wherein the threshold is configurable via software logic.

[0365] 13. The method as described in technical solution 11, wherein the threshold is a default hardware value.

[0366] 14. The method as described in technical solution 11, additionally comprising:

[0367] compute the remaining bits of the result when the precision loss of the intermediate result is greater than the threshold; and

[0368] output the result with the first precision.

[0369] 15. The method according to claim 14, wherein performing the numerical operation using a plurality of bits associated with a second precision lower than the first precision includes performing the numerical operation using a first set of logic units and computing the remaining bits of the result, and when the precision loss of the intermediate result is greater than the threshold, includes computing the remaining bits of the result using a second set of logic units.

[0370] 16. A data processing system, comprising:

[0371] a non-transitory machine-readable medium for storing instructions for execution by one or more processors of the data processing system; and

[0372] a general-purpose graphics processing unit including a dynamic precision floating-point unit, the dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track the available number of precision bits of computed data related to a target precision, wherein the dynamic precision floating-point unit includes computation logic to output data in a plurality of precisions.

[0373] 17. The data processing system according to claim 16, wherein the dynamic precision floating-point unit includes a register set to store input data and intermediate data in a plurality of precisions.

[0374] 18. The data processing system according to claim 17, wherein the register set includes an error accumulator to track the accumulated error on a set of floating-point operations.

[0375] 19. The data processing system according to claim 16, the dynamic precision floating-point unit includes a significand block to perform the significand part of a floating-point computation, the significand block including a dynamic precision adder configurable to add or subtract input data in a plurality of precisions.

[0376] 20. The data processing system according to claim 19, the significand block includes a dynamic precision multiplier configurable to add or multiply or divide input data in a plurality of precisions.

[0377] The following clauses and / or examples relate to specific embodiments or examples thereof. The specific details in the examples may be used anywhere in one or more embodiments. The various features of different embodiments or examples may be combined in various ways with some of the features included and other features excluded to apply to a wide variety of different applications. The examples may include a subject matter such as a method, components for performing the actions of the method, and at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of the method or the device or system according to the embodiments and examples described herein. The various components may be components for performing the described operations or functions.

[0378] The embodiments described herein refer to a specific configuration of hardware (e.g., an application specific integrated circuit (ASIC)) configured to perform certain operations or having a predetermined functionality. Such an electronic device typically includes a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., a keyboard, a touch screen, and / or a display), and a network connection. The coupling of the set of processors and its other components is typically through one or more buses and bridges (also referred to as bus controllers). The storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the storage devices of a given electronic device typically store code and / or data for execution on the set of one or more processors of the electronic device.

[0379] Of course, one or more portions of the embodiments may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the embodiments may be practiced without some of these specific details. In some instances, well-known structures and functions have not been described in exhaustive detail to avoid obscuring the inventive subject matter of the embodiments. Accordingly, the scope and spirit of the present invention should be judged according to the following claims.

Claims

1. A processing device, comprising: an interconnect structure including one or more switches; a memory interface coupled to the interconnect structure; an input / output interface coupled to the interconnect structure; an array of processing clusters coupled to the interconnect structure, the array of processing clusters for processing mixed-precision instructions, wherein at least one processing cluster includes: a plurality of registers for storing a plurality of compressed data elements in a first precision; and an execution unit for executing mixed-precision dot product instructions, the execution unit for performing a plurality of multiplications of different pairs of the plurality of compressed data elements to generate corresponding plural products, and for adding the corresponding plural products to an accumulation value stored in a second precision greater than the first precision.

2. The device according to claim 1, further comprising: a parallel processing unit including the interconnect structure, the memory interface, the input / output unit, and the array of processing clusters, wherein the memory interface includes a plurality of partitioning units, each of the plurality of partitioning units independently coupled to respective ones of a plurality of 3D stacked memory cells.

3. The device according to claim 1, wherein the plurality of compressed data elements include data elements of various data sizes.

4. The device according to claim 1, wherein the mixed-precision dot product instruction is a primitive of a machine learning framework.

5. The device according to claim 4, wherein matrix multiplication is performed by a convolutional layer of the machine learning framework.

6. The device according to claim 4, wherein the machine learning framework includes a neural network.

7. The device according to claim 6, wherein the neural network includes a recurrent neural network.

8. The device according to any one of claims 1-6, wherein the array of processing clusters is to be shared among a plurality of virtual machines in a virtualized graphics execution environment.

9. The device according to claim 8, wherein the virtualized graphics execution environment includes multiple sets of registers for storing valid address pointers to memory locations.

10. The device according to claim 2, wherein, the memory interface is for coupling the interconnect structure to access the 3D stacked memory cells, and the memory interface uses virtual channels to separate traffic flows.

11. The device according to any one of claims 1 to 7, further comprising: a level 1 (L1) cache and a level 2 (L2) cache for storing data of the array of processing clusters, the level 1 (L1) cache and the level 2 (L2) cache to be shared among all processing clusters.

12. The device according to claim 2, further comprising: a memory management unit coupled to the interconnect structure, the memory management unit including a translation lookaside buffer for caching virtual-to-physical address translations.

13. The device according to claim 12, wherein the memory management unit is to use a shared virtual system address space allocated to the 3D stacked memory cells.

14. The apparatus according to claim 2, wherein the 3D stacked memory cells include high bandwidth memory.

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