Display panel and display device

Abstract

The present application discloses a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, a data writing module, and a light-emitting control module. The driving module is configured to provide a driving current for the light-emitting element, and the driving module includes a driving transistor. The data writing module is configured to selectively provide a data signal for the driving transistor. The light-emitting control module is configured to selectively allow the light-emitting element to enter a light-emitting stage. One end of the light-emitting control module is connected to a first power signal terminal for receiving a first power signal. The pixel circuit further includes a latching module and a first scan signal line for receiving a first scan signal. The latching module is connected between the gate of the driving transistor and the first scan signal line. This application helps to achieve the regulation of the gate potential of the driving transistor.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device including the display panel. Background Art

[0002] In a display panel, a pixel circuit provides a driving current required for display for a light-emitting element of the display panel and controls whether the light-emitting element enters a light-emitting stage, and is an indispensable component in most self-luminous display panels.

[0003] However, in an existing display panel, as the usage time increases, the internal characteristics of a driving transistor in the pixel circuit change slowly, resulting in a drift of the threshold voltage of the driving transistor; or, the gate potential of the driving transistor in the pixel circuit is affected during the operation of the pixel circuit and may be unstable. The above problems will affect the comprehensive characteristics of the driving transistor, and further affect the display uniformity. Summary of the Invention

[0004] In view of this, the present invention provides a display panel and a display device, which can help to weaken the problem of threshold voltage shift of a driving transistor, or improve the stability of the gate potential of the driving transistor.

[0005] One aspect of an embodiment of the present application provides a display panel, which includes

[0006] a pixel circuit and a light-emitting element;

[0007] The pixel circuit includes a driving module, a data writing module, and a light-emitting control module;

[0008] The driving module is configured to provide a driving current for the light-emitting element, and the driving module includes a driving transistor;

[0009] The data writing module is configured to selectively provide a data signal for the driving transistor;

[0010] The light-emitting control module is configured to selectively allow the light-emitting element to enter a light-emitting stage, and one end of the light-emitting control module is connected to a first power signal terminal for receiving a first power signal; wherein,

[0011] The pixel circuit further includes a latching module and a first scan signal line for receiving a first scan signal;

[0012] The latching module is connected between the gate of the driving transistor and the first scan signal line.

[0013] Another aspect of an embodiment of the present application provides another display panel, which is characterized by including a pixel circuit and a light-emitting element;

[0014] The pixel circuit includes a driving module, a data writing module, a light emitting control module, a compensation module, and a reset module;

[0015] The driving module is configured to provide a driving current for the light emitting element, and the driving module includes a driving transistor;

[0016] The data writing module is configured to selectively provide a data signal for the driving transistor;

[0017] The light emitting control module is configured to selectively allow the light emitting element to enter a light emitting stage, and one end of the light emitting control module is connected to a first power signal terminal for receiving a first power signal;

[0018] The compensation module is connected between the gate and the drain of the driving transistor for compensating the threshold voltage of the driving transistor;

[0019] The reset module is connected between the drain of the driving transistor and a reset signal terminal for providing a reset signal for the gate of the driving transistor; wherein,

[0020] The reset module is multiplexed as a bias module;

[0021] The operation process of the pixel circuit includes a reset stage and a bias stage. In the reset stage, the compensation module and the reset module are turned on, and the reset signal terminal provides the reset signal for the gate of the driving transistor;

[0022] In the bias stage, the compensation module is turned off, the reset module is turned on, and the reset signal terminal provides a bias signal for the drain of the driving transistor;

[0023] The pixel circuit further includes a latching module and a reset signal line. The reset signal line is configured to provide the reset signal or the bias signal for the reset signal terminal, and the latching module is connected between the gate of the driving transistor and the reset signal line.

[0024] The present invention also provides a display device, including the display panel in any of the above embodiments.

[0025] In an embodiment of the present invention, a latching module is provided. The latching module is connected between the gate of the driving transistor and the first scanning line or the reset signal line, so as to realize the function of regulating the gate potential of the driving transistor through the signal on the first scanning signal line or the reset signal line. Since the gate potential of the driving transistor plays a very important role in the normal operation of the pixel circuit, and in different stages, the gate potential of the driving transistor is likely to change. Therefore, through the signal on the first scanning signal line or the reset signal line and the function of the latching module, the present invention can effectively maintain and regulate the gate potential of the driving transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of a pixel circuit of a display panel provided by an embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a pixel circuit of another display panel provided by an embodiment of the present invention;

[0028] Figure 3 is Figure 1 one of the working timing diagrams of the pixel circuit shown;

[0029] Figure 4 is Figure 1 two of the working timing diagrams of the pixel circuit shown;

[0030] Figure 5 is Figure 1 three of the working timing diagrams of the pixel circuit shown;

[0031] Figure 6 is a schematic diagram of a pixel circuit of a display panel provided by another embodiment of the present invention;

[0032] Figure 7 is Figure 6 one of the working timing schematic diagrams of the pixel circuit shown;

[0033] Figure 8 is Figure 6 two of the working timing schematic diagrams of the pixel circuit shown;

[0034] Figure 9 is Figure 6 three of the working timing schematic diagrams of the pixel circuit shown;

[0035] Figure 10 is a partial cross-sectional schematic diagram of the pixel circuit;

[0036] Figure 11 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0038] It should be noted that specific details are set forth in the following description to facilitate a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0039] Reference Figure 1 , Figure 1 is a schematic diagram of a pixel circuit of a display panel provided by an embodiment of the present invention. Among them, the display panel includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes a driving module 11, a data writing module 12, and a light-emitting control module 13. The driving module 11 is used to provide a driving current for the light-emitting element 20, and the driving module 11 includes a driving transistor T0. The data writing module 12 is used to selectively provide a data signal Vdata for the driving transistor T0. The light-emitting control module 13 is used to selectively allow the light-emitting element to enter the light-emitting stage. One end of the light-emitting control module 13 is connected to the first power signal terminal for receiving the first power signal PVDD. Among them, the pixel circuit 10 further includes a latching module 16 and a first scan signal line, and the first scan signal line is used to receive the first scan signal S1. The latching module 16 is connected between the gate of the driving transistor T0 and the first scan signal line for controlling the gate potential of the driving transistor T0 according to the first scan signal S1.

[0040] Optionally, in this embodiment, the input end of the driving module 11 is connected to the source of the driving transistor T0, and the output end of the driving module 11 is connected to the drain of the driving transistor T0. Optionally, as Figure 1 shown in the pixel circuit, the driving transistor T0 is a PMOS transistor; further, the driving transistor T0 can be a low-temperature polysilicon transistor.

[0041] Optionally, in this embodiment, the control end of the data writing module 12 is connected to the second scan signal line for receiving the second scan signal S2, and the second scan signal S2 controls the opening and closing of the data writing module 12. The first end of the data writing module 12 is connected to the data signal input terminal for receiving the data signal Vdata, and the second end of the data writing module 12 is connected to the input end of the driving module 11. Optionally, the data writing module 12 includes a fifth transistor T5, the source of the fifth transistor T5 is connected to the first end of the data writing module 12, and the drain of the fifth transistor T5 is connected to the second end of the data writing module 12.

[0042] Optionally, in this embodiment, the light emission control module 13 includes a first light emission control module 13a and a second light emission control module 13b. The first end of the first light emission control module 13a is connected to the first power signal terminal for receiving the first power signal PVDD, and the second end of the first light emission control module 13a is connected to the input end of the driving module 11; the first end of the second light emission control module 13b is connected to the output end of the driving module 11, and the second end is connected to the light emitting element 20. The control ends of the first light emission control module 13a and the second light emission control module 13b can be connected to the same light emission control signal line for receiving the light emission control signal EM, as Figure 1 shown; in other alternative embodiments, the control ends of the first light emission control module 13a and the second light emission control module 13b can also be connected to different light emission control signal lines for receiving different light emission control signals. Optionally, the first light emission control module 13a includes a second transistor T2, the source of the second transistor T2 is connected to the first end of the first light emission control module 13a, and the drain is connected to the second end of the first light emission control module 13a; the second light emission control module 13a includes a third transistor T3, the source of the third transistor T3 is connected to the first end of the second light emission control module 13b, and the drain is connected to the second end of the second light emission control module 13b.

[0043] Refer to Figure 2 , Figure 2 is a schematic diagram of a pixel circuit of another display panel provided by an embodiment of the present invention. Among them, the display panel includes a pixel circuit 10 and a light emitting element 20. The pixel circuit 10 includes a driving module 11, a data writing module 12, and a light emission control module 13; the driving module 11 is used to provide a driving current for the light emitting element 20, and the driving module 11 includes a driving transistor T0; the data writing module 12 is used to selectively provide a data signal Vdata for the driving transistor T0; the light emission control module 13 is used to selectively allow the light emitting element to enter the light emission stage, and one end of the light emission control module 13 is connected to the first power signal terminal for receiving the first power signal PVDD; wherein, the pixel circuit 10 further includes a latching module 16 and a first scan signal line, and the first scan signal line is used to receive the first scan signal S1; the latching module 16 is connected between the gate of the driving transistor T0 and the first scan signal line for controlling the gate potential of the driving transistor T0 according to the first scan signal S1.

[0044] Optionally, in this embodiment, the input end of the driving module 11 is connected to the source of the driving transistor T0, and the output end of the driving module 11 is connected to the drain of the driving transistor T0. Optionally, as Figure 1 shown in the pixel circuit, the driving transistor T0 is an NMOS transistor; further, the driving transistor T0 can be an oxide semiconductor type transistor.

[0045] Optionally, in this embodiment, the control terminal of the data writing module 12 is connected to the second scanning signal line for receiving the second scanning signal S2, and the second scanning signal S2 controls the turning on and off of the data writing module 12; the first terminal of the data writing module 12 is connected to the data signal input terminal for receiving the data signal Vdata, and the second terminal of the data writing module 12 is connected to the input terminal of the driving module 11; optionally, the data writing module 12 includes a fifth transistor T5, the source of the fifth transistor T5 is connected to the first terminal of the data writing module 12, and the drain of the fifth transistor T5 is connected to the second terminal of the data writing module 12.

[0046] Optionally, in this embodiment, the light emitting control module 13 includes a first light emitting control module 13a and a second light emitting control module 13b. The first terminal of the first light emitting control module 13a is connected to the first power signal terminal for receiving the first power signal PVDD, and the second terminal of the first light emitting control module 13a is connected to the output terminal of the driving module 11; the first terminal of the second light emitting control module 13b is connected to the input terminal of the driving module 11, and the second terminal is connected to the light emitting element 20. The control terminals of the first light emitting control module 13a and the second light emitting control module 13b may be connected to the same light emitting control signal line for receiving the light emitting control signal EM, as Figure 2 shown; in other alternative embodiments, the control terminals of the first light emitting control module 13a and the second light emitting control module 13b may also be connected to different light emitting control signal lines for receiving different light emitting control signals. Optionally, the first light emitting control module 13a includes a second transistor T2, the source of the second transistor T2 is connected to the first terminal of the first light emitting control module 13a, and the drain is connected to the second terminal of the first light emitting control module 13a; the second light emitting control module 13a includes a third transistor T3, the source of the third transistor T3 is connected to the first terminal of the second light emitting control module 13b, and the drain is connected to the second terminal of the second light emitting control module 13b.

[0047] In the embodiment of the present invention, a latching module is provided. The latching module is connected between the gate of the driving transistor and the first scanning line, so that the gate potential of the driving transistor can be regulated by the first scanning signal. Since the gate potential of the driving transistor is very important for the normal operation of the pixel circuit, and in different stages, the gate potential of the driving transistor is likely to change. Therefore, through the action of the first scanning signal and the latching module, the present invention can effectively maintain and regulate the gate potential of the driving transistor.

[0048] Optionally, in this embodiment, as Figure 1As shown, the pixel circuit 10 further includes a reset module 15 and a compensation module 14. The reset module 15 is connected between the reset signal terminal and the drain of the driving transistor T0, and is configured to provide a reset signal for the gate of the driving transistor T0. The reset signal includes a first transistor T1. The compensation module 14 is connected between the gate and the drain of the driving transistor T0, and is configured to compensate for the threshold voltage of the driving transistor T0. An initialization module 17 is connected between the initialization signal terminal and the light-emitting element 20, and is configured to selectively provide an initialization signal Vini for the light-emitting element 20.

[0049] Optionally, the source of the first transistor T1 is connected to the reset signal terminal, and the drain is connected to the drain of the driving transistor T0.

[0050] Optionally, the control terminal of the compensation module 14 is connected to the third scanning signal line for receiving a third scanning signal S3. The third scanning signal S3 controls the turning on and off of the compensation module 14. The compensation module 14 includes a fourth transistor T4. The source of the fourth transistor T4 is connected to the drain of the driving transistor T0, and the drain is connected to the gate of the driving transistor T0. Optionally, the fourth transistor T4 can be a PMOS transistor or an NMOS transistor. When the fourth transistor T4 is a PMOS transistor, the fourth transistor T4 is turned on when the third scanning signal S3 is a low-level signal. The fourth transistor T4 can be a low-temperature polysilicon transistor. When the fourth transistor T4 is an NMOS transistor, the fourth transistor T4 is turned on when the third scanning signal S3 is a high-level signal. The fourth transistor T4 can be an oxide semiconductor transistor. Hereinafter, the fourth transistor T4 being an NMOS-type oxide semiconductor transistor is taken as an example for description.

[0051] Optionally, the initialization module Vini includes a sixth transistor T6. The source of the sixth transistor T6 is connected to the initialization signal terminal, and the drain is connected to the light-emitting element 20.

[0052] Figure 2 In, the connection manners of the reset module 15, the compensation module 14, and the initialization module 17 are the same as those described in the previous paragraph. For the same description, it will not be repeated here. It should be noted that Figure 1 and Figure 2 In, the source and the drain of the driving transistor T0 are interchanged, and the end of the driving transistor T0 connected to the data writing module 11 is the source of the driving transistor T0.

[0053] In this embodiment, in some embodiments, the control terminal of the reset module 15 is connected to the first scan signal line. That is, when the first scan signal S1 controls the reset module 15 to turn on, under the action of the first scan signal S1 and the latch module 16, the gate potential of the driving transistor T0 is regulated to reach the first state; when the first scan signal line S1 controls the reset module 15 to turn off, under the action of the first scan signal S1 and the latch module 16, the gate potential of the driving transistor T0 is regulated to reach the second state. The first state and the second state can be a state of raising the potential or a state of pulling down the potential. For example, when the first scan signal S1 is at a low level and the reset module 15 is turned on, the first state is a state of pulling down the potential; when the first scan signal S1 is at a high level and the reset module 15 is turned off, the second state is a state of raising the potential. For another example, when the first scan signal S1 is at a high level and the reset module 15 is turned on, the first state is a state of raising the potential; when the first scan signal S1 is at a low level and the reset module 15 is turned off, the second state is a state of pulling down the potential.

[0054] In this embodiment, in some other embodiments, the control terminal of the initialization module 17 is connected to the first scan signal line. That is, when the first scan signal S1 controls the initialization module 17 to turn on, under the action of the first scan signal S1 and the latch module 16, the gate potential of the driving transistor T0 is regulated to reach the third state; when the first scan signal line S1 controls the initialization module 17 to turn off, under the action of the first scan signal S1 and the latch module 16, the gate potential of the driving transistor T0 is regulated to reach the fourth state. The third state and the fourth state can be a state of raising the potential or a state of pulling down the potential. For example, when the first scan signal S1 is at a low level and the initialization module 17 is turned on, the third state is a state of pulling down the potential; when the first scan signal S1 is at a high level and the initialization module 17 is turned off, the fourth state is a state of raising the potential. For another example, when the first scan signal S1 is at a high level and the initialization module 17 is turned on, the third state is a state of raising the potential; when the first scan signal S1 is at a low level and the initialization module 17 is turned off, the fourth state is a state of pulling down the potential.

[0055] In this embodiment, in some other embodiments, the control terminals of the reset module 15 and the initialization module 17 are both used to receive the first scan signal S1, and the latch module 16 is connected to any one of the first scan signal lines connected to the control terminal of the reset module 15 and the first scan signal line connected to the control terminal of the initialization module 17. In this embodiment, both the reset module 15 and the initialization module 16 receive the first scan signal S1. When the transistors in both of them are PMOS transistors or NMOS transistors at the same time, the reset module 15 and the initialization module 16 are turned on or off simultaneously. This is allowed in the panel because the reset stage and the initialization stage of the pixel circuit are independent of each other. Therefore, they can be performed simultaneously or not simultaneously. In this embodiment, they are performed simultaneously. At this time, the first scan signal S1 can be shared for control. Therefore, only one set of shift register circuits for generating the first scan signal S1 needs to be provided in the panel to meet the requirements, thus simplifying the panel structure and process.

[0056] In this embodiment, optionally, the working process of the pixel circuit includes a reset stage and a bias stage. In the reset stage, the reset module 15 and the compensation module 14 are turned on, and the reset signal terminal provides a reset signal Vref for the gate of the driving transistor T0; in the bias stage, the reset module 15 is turned on, the compensation module 14 is turned off, and the reset signal terminal provides a bias signal Vobs for the drain of the driving transistor T0; that is, the reset module 15 is multiplexed as a bias module and functions to provide the bias signal Vobs in the bias stage.

[0057] During non - bias stages such as the light - emitting stage of the display panel, the source of the driving transistor T0 receives the first power signal PVDD, and the gate of the driving transistor T0 is the signal written during the data - writing stage. Therefore, for the case where the driving transistor is a PMOS transistor, during the light - emitting stage, there may be a situation where the gate potential of the driving transistor T0 is higher than the drain potential, and at this time, the driving transistor is in an on state. If this situation persists for a long time, it will cause the Id - Vg curve of the driving transistor T0 to shift, thereby causing the threshold voltage of the driving transistor T0 to shift; for the case where the driving transistor is an NMOS transistor, during the light - emitting stage, since the drain of the driving transistor T0 receives the first power signal PVDD, and the first power signal PVDD is usually a high - level signal, there may be a situation where the gate potential of the driving transistor T0 is lower than the drain potential, and at this time, the driving transistor is in an on state. If this situation persists for a long time, it will cause the Id - Vg curve of the driving transistor T0 to shift, thereby causing the threshold voltage of the driving transistor T0 to shift. Therefore, in order to improve this situation, a bias stage needs to be added. During the bias stage, the potential difference between the gate potential and the drain potential of the driving transistor T0 is adjusted to weaken the problem existing in the above - mentioned non - bias stage, that is, the problem of the threshold - voltage shift of the driving transistor T0, and to ensure display uniformity.

[0058] During the reset stage, the gate of the driving transistor T0 receives the reset signal, and the gate potential of the driving transistor T0 before the reset stage is cleared to the reset signal, in order to re - set the gate potential of the driving transistor T0 before the next operation, and to avoid the influence of the residual potential of the gate on the next operation. For example, before the data - writing stage, a reset stage is required to ensure that the signal written during the data - writing stage is not interfered by other signals.

[0059] Optionally, in this embodiment, both the driving transistor T0 and the first transistor T1 are PMOS transistors, and during the bias stage, the voltage of the first scan signal S1 is lower than the voltage of the bias signal Vobs; or, both the driving transistor T0 and the first transistor T1 are NMOS transistors, and during the bias stage, the voltage of the first scan signal S1 is higher than the voltage of the bias signal Vobs.

[0060] Taking the control end of the reset module 15 being connected to the first scan signal line as an example, the specific principle of other situations is the same as this situation and can be referred to. Figure 1, when both the driving transistor T0 and the first transistor T1 are PMOS transistors, during the biasing stage, the first scan signal S1 is a low-level signal. Under the action of the first scan signal S1, the reset module 15 is turned on, and the bias signal Vobs is written to the drain of the driving transistor T0. As described above, the purpose of the biasing stage is to adjust the potential difference between the gate potential and the drain potential of the driving transistor during the non-biasing stage. For example, the potential difference can be reduced or even reversed. Therefore, a higher potential is required for the drain potential, and a lower potential is required for the gate potential to achieve this purpose. Thus, in this embodiment, the bias signal Vobs is a high-level signal, the first scan signal S1 is a low-level signal, the bias signal Vobs raises the drain potential of the driving transistor T0, and the first scan signal S1, through the action of the latch module 16, pulls down the gate potential of the driving transistor T0, thereby realizing the adjustment of both the gate potential and the drain potential of the driving transistor T0, which is beneficial to improving the biasing effect.

[0061] Taking the control end of the reset module 15 connected to the first scan signal line as an example, the specific principle in other cases is the same as this case and can be referred to. Figure 2 , when both the driving transistor T0 and the first transistor T1 are NMOS transistors, during the biasing stage, the first scan signal S1 is a high-level signal. Under the action of the first scan signal S1, the reset module 15 is turned on, and the bias signal Vobs is written to the drain of the driving transistor T0. As described above, the purpose of the biasing stage is to adjust the potential difference between the gate potential and the drain potential of the driving transistor during the non-biasing stage. For example, the potential difference can be reduced or even reversed. Therefore, a lower potential is required for the drain potential, and a higher potential is required for the gate potential to achieve this purpose. Thus, in this embodiment, the bias signal Vobs is a low-level signal, the first scan signal S1 is a high-level signal, the bias signal Vobs pulls down the drain potential of the driving transistor T0, and the first scan signal S1, through the action of the latch module 16, raises the gate potential of the driving transistor T0, thereby realizing the adjustment of both the gate potential and the drain potential of the driving transistor T0, which is beneficial to improving the biasing effect.

[0062] Optionally, in this embodiment, the driving transistor is a PMOS transistor, and during the biasing stage, the drain voltage of the driving transistor T0 is greater than the gate voltage of the driving transistor T0; or, the driving transistor is an NMOS transistor, and during the biasing stage, the drain voltage of the driving transistor T0 is less than the gate voltage of the driving transistor T0.

[0063] As described above, for the case where the driving transistor is a PMOS transistor, in non-biased stages such as the light-emitting stage, when the driving transistor T0 is turned on, there may be a situation where the gate potential of the driving transistor T0 is greater than the drain potential, resulting in a threshold voltage shift of the driving transistor T0. Therefore, if the drain voltage of the driving transistor is set to be greater than the gate voltage in the biasing stage, the above problems in the non-biased stage can be effectively offset. Similarly, for the case where the driving transistor is an NMOS transistor, in non-biased stages such as the light-emitting stage, when the driving transistor T0 is turned on, there may be a situation where the gate potential of the driving transistor T0 is lower than the drain potential, resulting in a threshold voltage shift of the driving transistor T0. Therefore, if the drain voltage of the driving transistor is set to be less than the gate voltage in the biasing stage, the above problems in the non-biased stage can be effectively offset.

[0064] The following embodiments take Figure 1 the case where the driving transistor shown in Figure 2 is a PMOS transistor as an example to illustrate the operation timing of the pixel circuit. It should be noted that for other embodiments, such as the case where the driving transistor shown in

[0065] is an NMOS transistor, the relationships of the respective stage times in the pre-stage also satisfy the various cases in the example, and the same content will not be repeatedly described in this embodiment. Figures 3 - 5 Figure 3 is Figure 1 one of the operation timing diagrams of the pixel circuit shown in Figure 4 is Figure 1 another operation timing diagram of the pixel circuit shown in Figure 5 is Figure 1 the third operation timing diagram of the pixel circuit shown in. Among them, within one frame time of the display panel, the operation process of the pixel circuit includes a pre-stage and a light-emitting stage; among them, within at least one frame time, the pre-stage of the pixel circuit includes a biasing stage. For convenience of description, in this embodiment, the signals received at the reset signal terminal are collectively referred to as V0.

[0066] As Figure 3As shown, the pre-stage further includes a reset stage; after the reset stage ends, the pixel circuit enters the bias stage. At the beginning of the bias stage, the gate potential of the driving transistor T0 is the reset signal Vref. In this case, at the beginning of the bias stage, the gate potential of the driving transistor T0 has been reset. If the driving transistor T0 is a PMOS transistor, the gate potential is reset to a low-level signal. Then, in the bias stage, the drain of the driving transistor T0 receives the high-level bias signal Vobs, achieving the dual adjustment of the gate potential and the drain potential. If the driving transistor T0 is an NMOS transistor, the gate potential is reset to a high-level signal. Then, in the bias stage, the drain of the driving transistor T0 receives the low-level bias signal Vobs, achieving the dual adjustment of the gate potential and the drain potential.

[0067] In some other embodiments, before the bias stage starts, the gate potential of the driving transistor T0 is not equal to the reset signal Vref.

[0068] As Figure 4 shown, after the light-emitting stage of the pixel circuit ends and it enters the pre-stage, the reset module 15 is turned on, the compensation module 14 remains off, and it enters the bias stage. At this time, after the light-emitting stage ends and it enters the pre-stage, it directly enters the bias stage without going through the reset stage, and the gate potential of the driving transistor T0 is not equal to the reset signal Vref. Generally speaking, for a PMOS transistor, the reset signal is a low-level signal. When the gate potential of the driving transistor T0 is not equal to the reset signal, the gate potential is higher than the reset signal. Then, when entering the bias stage at this time, it will cause the gate potential to be high, making it difficult to reduce the potential difference between the gate and the drain, or reverse the potential difference between the gate and the drain. Then, at this time, after setting the latch module 16, since the first transistor T1 is also a PMOS transistor, the first transistor T1 is turned on in the bias stage, and the first scan signal S1 is a low-level signal. Under the action of the first scan signal S1 and the latch module 16, the potential of the gate of the driving transistor is pulled down, so that while adjusting the drain voltage of the driving transistor in the bias stage, the gate voltage is also adjusted, achieving the purpose of dual adjustment and helping to improve the bias effect.

[0069] As Figure 4 and 5As shown, the pre-stage also includes a data writing stage. During the data writing stage, the data writing module 12, the driving module 11, and the compensation module 14 are all turned on, and the data signal Vdata is written to the gate of the driving transistor T0. At least one biasing stage of the pre-stage is performed after the data writing stage. During the data writing stage, the data signal Vdata is written to the gate of the driving transistor T0, resulting in a relatively high gate potential of the driving transistor T0. After that, during the biasing stage, because the gate potential is high, it is also difficult to reduce the potential difference between the gate and the drain, or reverse the potential difference between the gate and the drain. At this time, after setting the latch module 16, since the first transistor T1 is also a PMOS transistor, the first transistor T1 is turned on during the biasing stage, and the first scan signal S1 is a low-level signal. Under the action of the first scan signal S1 and the latch module 16, the potential of the gate of the driving transistor is pulled down, so that while adjusting the drain voltage of the driving transistor during the biasing stage, the gate voltage is also adjusted, achieving the purpose of two-way adjustment and helping to improve the biasing effect.

[0070] As Figure 4 shown, the pre-stage may include N biasing stages, where N≥1; Figure 4 Two biasing stages are shown in the figure, but it can also be one or three, or more than three cases. Figure 4 In the figure, the pre-stage includes a first biasing stage and a second biasing stage; the first biasing stage is performed before the data writing stage, and the second biasing stage is performed after the data writing stage; among them, the time length of the first biasing stage is longer than that of the second biasing stage. Among them, the first pre-stage can be used as a main biasing stage, and the second biasing stage can be used as an auxiliary biasing stage. The first pre-stage mainly plays a biasing role and mainly bears the problem of offsetting the threshold voltage deviation in the non-biasing stage. However, in order to prevent the biasing effect of the first biasing stage from being incomplete, other supplementary biasing stages can be set to fully supplement the biasing effect.

[0071] Optionally, in this embodiment, as Figure 1 shown, the latch module 16 includes a first capacitor C1. The first plate of the first capacitor C1 is connected to the gate of the driving transistor T0, and the second plate is connected to the first scan signal line. Because the capacitor has the functions of charging and discharging, it can be used as a latch module to regulate the potential of one node relative to another node. Moreover, the capacitor does not need to be separately provided with a control terminal for control, which simplifies the structure and process of the pixel circuit.

[0072] Optionally, the pixel circuit further includes a second capacitor C2; one plate of the second capacitor C2 is connected to the gate of the driving transistor T0 and is used to store the data signal transmitted to the gate of the driving transistor T0. As Figure 1As shown, one plate of the second capacitor C2 is connected to the gate of the driving transistor T0, and the other plate is connected to the first power signal terminal for storing the data signal Vdata. As Figure 2 As shown, one plate of the second capacitor C2 is connected to the gate of the driving transistor T0, and the other plate is connected to the light-emitting element 20 for storing the data signal.

[0073] In this embodiment, optionally, the capacitance value of the first capacitor C1 is less than that of the second capacitor C2. Since the function of the second capacitor C2 is to store the data signal Vdata written to the gate of the driving transistor T0, and the data signal Vdata written to the gate of the driving transistor T0 is one of the determining factors for determining the driving current generated in the driving transistor T0 during the light-emitting stage, therefore, a capacitor with a stronger storage capacity is required to fully store the signal of the driving transistor T0 during the data writing stage; during the biasing stage, currently it is to adjust the potential difference between the gate potential and the drain potential of the driving transistor T0. Therefore, from the perspective of accurately storing data, the requirement for the storage capacity of the second capacitor is greater than that of the first capacitor. Therefore, in this embodiment, the capacitance value of the first capacitor C1 is set to be less than that of the second capacitor C2.

[0074] Furthermore, optionally, the capacitance values of the first capacitor C1 and the second capacitor C2 satisfy: C2×1 / 8 ≤ C1 ≤ C2×1 / 4. The inventors of the present application have found that when C2×1 / 8 ≤ C1 ≤ C2×1 / 4, the capacitance value of the first capacitor C1 can meet the requirements of the biasing stage, and can avoid the problem that the load of the pixel circuit increases due to the too large capacitance value of the first capacitor C1, affecting the signal transmission of the first scanning signal line.

[0075] Refer to Figure 6 , Figure 6It is a schematic diagram of a pixel circuit of a display panel provided by another embodiment of the present invention. Among them, the display panel includes a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a driving module 11, a data writing module 12, a light-emitting control module 13, a compensation module 14, and a reset module 15; the driving module 11 is used to provide a driving current for the light-emitting element 20, and the driving module 11 includes a driving transistor T0; the data writing module 12 is used to selectively provide a data signal Vdata for the driving transistor T0; the light-emitting control module 13 is used to selectively allow the light-emitting element 20 to enter the light-emitting stage, and one end of the light-emitting control module 13 is connected to the first power signal terminal for receiving the first power signal PVDD; the compensation module 14 is connected between the gate and the drain of the driving transistor T0 for compensating the threshold voltage of the driving transistor T0; the reset module 15 is connected between the drain of the driving transistor T0 and the reset signal terminal for providing a reset signal for the gate of the driving transistor; among them, the reset module 15 is multiplexed as a bias module; the working process of the pixel circuit includes a reset stage and a bias stage. In the reset stage, the compensation module 14 and the reset module 15 are turned on, and the reset signal terminal provides a reset signal Vref for the gate of the driving transistor T0; in the bias stage, the compensation module 14 is turned off, the reset module 15 is turned on, and the reset signal terminal provides a bias signal Vobs for the drain of the driving transistor T0; the pixel circuit further includes a latching module 16 and a reset signal line, and the reset signal line is used to provide a reset signal Vref or a bias signal Vobs for the reset signal terminal. The latching module 16 is connected between the gate of the driving transistor T0 and the reset signal line.

[0076] Optionally, in this embodiment, the input end of the driving module 11 is connected to the source of the driving transistor T0, and the output end of the driving module 11 is connected to the drain of the driving transistor T0. Optionally, as Figure 1 shown in the pixel circuit, the driving transistor T0 is a PMOS transistor; further, the driving transistor T0 can be a low-temperature polysilicon transistor.

[0077] Optionally, in this embodiment, the control end of the data writing module 12 is connected to the second scanning signal line for receiving the second scanning signal S2, and the second scanning signal S2 controls the turning on and off of the data writing module 12; the first end of the data writing module 12 is connected to the data signal input end for receiving the data signal Vdata, and the second end of the data writing module 12 is connected to the input end of the driving module 11; optionally, the data writing module 12 includes a fifth transistor T5, the source of the fifth transistor T5 is connected to the first end of the data writing module 12, and the drain of the fifth transistor T5 is connected to the second end of the data writing module 12.

[0078] Optionally, in this embodiment, the light emission control module 13 includes a first light emission control module 13a and a second light emission control module 13b. The first end of the first light emission control module 13a is connected to the first power signal terminal for receiving the first power signal PVDD, and the second end of the first light emission control module 13a is connected to the input end of the driving module 11; the first end of the second light emission control module 13b is connected to the output end of the driving module 11, and the second end is connected to the light emitting element 20. The control ends of the first light emission control module 13a and the second light emission control module 13b may be connected to the same light emission control signal line for receiving the light emission control signal EM, as Figure 1 shown; in other alternative embodiments, the control ends of the first light emission control module 13a and the second light emission control module 13b may also be connected to different light emission control signal lines for receiving different light emission control signals. Optionally, the first light emission control module 13a includes a second transistor T2. The source of the second transistor T2 is connected to the first end of the first light emission control module 13a, and the drain is connected to the second end of the first light emission control module 13a; the second light emission control module 13a includes a third transistor T3. The source of the third transistor T3 is connected to the first end of the second light emission control module 13b, and the drain is connected to the second end of the second light emission control module 13b;

[0079] Optionally, in this embodiment, the pixel circuit 10 further includes a reset module 15 and a compensation module 14. The reset module 15 is connected between the reset signal terminal and the drain of the driving transistor T0 for providing a reset signal to the gate of the driving transistor T0. The reset signal includes a first transistor T1; the compensation module 14 is connected between the gate and the drain of the driving transistor T0 for compensating the threshold voltage of the driving transistor T0; an initialization module 17, which is connected between the initialization signal terminal and the light emitting element 20 for selectively providing an initialization signal Vini to the light emitting element 20.

[0080] Optionally, the source of the first transistor T1 is connected to the reset signal terminal, and the drain is connected to the drain of the driving transistor T0.

[0081] Optionally, the control terminal of the compensation module 14 is connected to the third scan signal line for receiving the third scan signal S3, and the third scan signal S3 controls the turning on and off of the compensation module 14. The compensation module 14 includes a fourth transistor T4. The source of the fourth transistor T4 is connected to the drain of the driving transistor T0, and the drain is connected to the gate of the driving transistor T0. Optionally, the fourth transistor T4 can be a PMOS transistor or an NMOS transistor. When the fourth transistor T4 is a PMOS transistor, the fourth transistor T4 is turned on when the third scan signal S3 is a low-level signal, and the fourth transistor T4 can be a low-temperature polysilicon transistor. When the fourth transistor T4 is an NMOS transistor, the fourth transistor T4 is turned on when the third scan signal S3 is a high-level signal, and the fourth transistor T4 can be an oxide semiconductor transistor. In the following, the fourth transistor T4 being an NMOS-type oxide semiconductor transistor is taken as an example for description.

[0082] Optionally, the initialization module Vini includes a sixth transistor T6. The source of the sixth transistor T6 is connected to the initialization signal terminal, and the drain is connected to the light-emitting element 20.

[0083] In this embodiment, the gate of the driving transistor is connected to the reset signal line through the latch module. Since the reset signal line is responsible for providing a reset signal or a bias signal to the reset signal terminal, and due to the difference in function and role, the voltages of the reset signal and the bias signal are different, resulting in a voltage jump when the signal at the reset signal terminal is switched between the reset signal and the bias signal. In this embodiment, this voltage jump is utilized to maintain the gate potential of the driving transistor when the gate voltage of the driving transistor changes.

[0084] Optionally, in this embodiment, the driving transistor T0 is a PMOS transistor, and the voltage of the bias signal Vobs is higher than the voltage of the reset signal Vref; or, the driving transistor T0 is an NMOS transistor, and the voltage of the bias signal Vobs is lower than the voltage of the reset signal Vref. Since the display panel is in a non-bias stage such as the light-emitting stage, the source of the driving transistor T0 receives the first power signal PVDD, and the gate of the driving transistor T0 is the signal written during the data writing stage. Therefore, for the case where the driving transistor is a PMOS transistor, in the light-emitting stage, there may be a situation where the gate potential of the driving transistor T0 is higher than the drain potential, and at this time, the driving transistor is in an on state. If this situation persists for a long time, it will cause the Id-Vg curve of the driving transistor T0 to shift, resulting in a shift in the threshold voltage of the driving transistor T0. Therefore, in order to improve this situation, a bias stage needs to be added. In the bias stage, the potential difference between the gate potential and the drain potential of the driving transistor T0 is adjusted to weaken the problem of the threshold voltage shift of the driving transistor T0 caused by the above-mentioned problem in the non-bias stage and ensure display uniformity. To weaken the above problem, for a PMOS transistor, it is necessary to appropriately increase the drain potential of the driving transistor T0 in the bias stage. Therefore, the bias signal Vobs is at a relatively high level, and the reset signal Vref is set to reset the gate of the driving transistor T0. Generally speaking, for a PMOS transistor, the reset signal Vref is at a relatively low level. For an NMOS transistor, it is necessary to appropriately reduce the drain potential of the driving transistor T0 in the bias stage. Therefore, the bias signal Vobs is at a relatively low level, and the reset signal Vref is set to reset the gate of the driving transistor T0. Generally speaking, for an NMOS transistor, the reset signal Vref is at a relatively high level.

[0085] Reference Figure 7 and Figure 8 , Figure 7 is Figure 6 One of the schematic diagrams of the working timing of the pixel circuit shown in FIG. 8 is Figure 6 Another schematic diagram of the working timing of the pixel circuit shown in FIG. 8. Optionally, as Figure 7 shown, the working process of the pixel circuit 10 includes a data writing stage. In the data writing stage, the data writing module 12, the driving module 11, and the compensation module 14 are all turned on, and the data signal Vdata is written to the gate of the driving transistor T0; among them, at the end of the data writing stage, while the compensation module 14 is turned off, the signal V0 at the reset signal terminal changes from the reset signal Vref to the bias signal Vobs; or, as Figure 8As shown, at the end of the data writing stage, the compensation module 14 is turned off. After the first interval stage, the signal V0 at the reset signal terminal changes from the reset signal Vref to the bias signal Vobs.

[0086] During the data writing stage, the data signal Vdata is written to the gate of the driving transistor T0. At the end of the data writing stage, the compensation module 14 is turned off, that is, the third scan signal S3 has a falling edge. This process may cause the gate potential of the driving transistor T0 to which the data signal has just been written to be unstable, and there may be a problem that the potential is pulled down. Then, in this embodiment, a latch module 16 is provided between the gate of the driving transistor T0 and the reset signal line. By making the signal V0 at the reset signal terminal have a rising edge at the same time when the falling edge of the third scan signal S3 arrives or after an interval of a first interval stage, the gate potential of the driving transistor T0 is raised to offset the problem caused by the falling edge of the third scan signal S3, so as to maintain the gate potential of the driving transistor T0 after the data signal Vdata is written, and ensure the stability of the driving current in the subsequent light emitting stage.

[0087] Optionally, the time length of the first interval stage is shorter than the time length of the data writing stage. As described above, since the jump of the signal V0 at the reset signal terminal is to offset the problem of the unstable gate potential of the driving transistor T0 caused by the falling edge of the third scan signal S3, therefore, if the time length of the first interval stage is too long, the jump of V0 cannot achieve this purpose well. And during the data writing stage, it is necessary to continuously write the data signal Vdata to the gate of the driving transistor T0, which requires a certain time length. Therefore, this embodiment is designed as above.

[0088] Optionally, in this embodiment, as Figure 8 shown, when the signal V0 at the reset signal terminal changes from the reset signal Vref to the bias signal Vobs, the first scan signal S1 has a falling edge, and the reset module 15 is turned on, and the pixel circuit 10 enters the bias stage; or, as Figure 7 shown, after the signal V0 at the reset signal terminal changes from the reset signal Vref to the bias signal Vobs, after a second interval stage, the first scan signal S1 has a falling edge, and the reset module 15 is turned on. The signals changing simultaneously can shorten the time of the pre-stage of the pixel circuit working process, which is beneficial to realizing high-frequency display. And the interval of the second interval stage between the signal jumps can provide a certain buffer time for the driving transistor, which helps to improve the stability of the driving transistor. How to set it specifically can be determined according to the specific situation. Optionally, the time length of the second interval stage is less than the time length of the bias stage, because the second interval stage is only used for transition, so it does not require a long time, while the bias stage requires a certain time to achieve the bias effect.

[0089] As Figure 7 and Figure 8 shown, within one frame time of the display panel, the working process of the pixel circuit includes a pre-stage and a light-emitting stage; wherein, within at least one frame time, the pre-stage of the pixel circuit includes a bias stage.

[0090] At least one bias stage of the pre-stage is carried out after the data writing stage. As described above, since the jump of the signal V0 at the reset signal terminal is mainly to offset the change of the falling edge of the third scan signal S3 after data writing, and after the signal V0 at the reset signal terminal jumps from the low-level reset signal Vref to the high-level bias signal Vobs, the first scan signal S1 controls the reset module 15 to be turned on, then the pixel circuit enters a bias stage.

[0091] Referring Figure 9 , Figure 9 is Figure 6 the third schematic diagram of the working timing of the pixel circuit in , where the pre-stage may include N bias stages, where N≥1; Figure 9 Two bias stages are shown in , but it may also be one or three, or more than three cases. Figure 9 In , the pre-stage includes a first bias stage and a second bias stage; the first bias stage is carried out before the data writing stage, and the second bias stage is carried out after the data writing stage; wherein, the time length of the first bias stage is longer than that of the second bias stage. Among them, the first pre-stage can be used as a main bias stage, and the second bias stage can be used as an auxiliary bias stage. The first pre-stage mainly plays a biasing role and mainly bears the problem of offsetting the threshold voltage deviation in the non-bias stage. However, in order to prevent the biasing effect of the first bias stage from being incomplete, other supplementary bias stages can be set to fully supplement the biasing effect.

[0092] Optionally, in this embodiment, the latch module 16 includes a first capacitor C1. The first plate of the first capacitor C1 is connected to the gate of the driving transistor T0, and the second plate is connected to the reset signal line. Since the capacitor has the functions of charging and discharging, it can be used as a latch module to regulate the potential of one node with respect to another node, and the capacitor does not need to be separately provided with a control terminal for control, which simplifies the structure and process of the pixel circuit.

[0093] Optionally, the pixel circuit further includes a second capacitor C2; one plate of the second capacitor C2 is connected to the gate of the driving transistor T0 for storing the data signal transmitted to the gate of the driving transistor T0. As shown in FIG. 6, one plate of the second capacitor C2 is connected to the gate of the driving transistor T0, and the other plate is connected to the first power signal terminal for storing the data signal.

[0094] In this embodiment, optionally, the capacitance value of the first capacitor C1 is less than that of the second capacitor C2. Since the function of the second capacitor C2 is to store the data signal Vdata written to the gate of the driving transistor T0, and the data signal Vdata written to the gate of the driving transistor T0 is one of the determining factors for determining the driving current generated in the driving transistor T0 during the light-emitting stage, therefore, a capacitor with a strong storage capacity is required to fully store the signal of the driving transistor T0 during the data writing stage; while the first capacitor C1 is mainly used to stabilize the gate potential of the driving transistor T0. Therefore, from the perspective of accurately storing data, the requirement for the storage capacity of the second capacitor C2 is greater than that of the first capacitor C1. Therefore, in this embodiment, the capacitance value of the first capacitor C1 is set to be less than that of the second capacitor C2.

[0095] Further, optionally, the capacitance values of the first capacitor C1 and the second capacitor C2 satisfy: C2×1 / 8≤C1≤C2×1 / 4. The inventors of the present application found that when C2×1 / 8≤C1≤C2×1 / 4, the capacitance value of the first capacitor C1 can meet the requirements of the bias stage, and can avoid the problem that the load of the pixel circuit increases due to the too large capacitance value of the first capacitor C1, affecting the signal transmission of the reset signal line.

[0096] In the foregoing embodiment of the present application, mainly a latch module is added to the pixel circuit, which has the effect of improving the bias stage or stabilizing the gate potential of the driving transistor. The working process related to the bias stage and the pixel circuit will be described in detail in the following part.

[0097] Reference Figures 1 - 9 , in this embodiment, optionally, the working process of the pixel circuit 10 further includes at least one non-bias stage; in the bias stage, the gate voltage of the driving transistor T0 is Vg1, the source voltage is Vs1, and the drain voltage is Vd1; in the non-bias stage, the gate voltage of the driving transistor is Vg2, the source voltage is Vs2, and the drain voltage is Vd2.

[0098] In some embodiments, |Vg1 - Vd1| < |Vg2 - Vd2|. Here, by setting |Vg1 - Vd1| < |Vg2 - Vd2|, the difference between the gate voltage and the drain voltage of the driving transistor T0 in the bias phase is made smaller than the difference between the gate voltage and the drain voltage of the driving transistor T0 in the non - bias phase, thereby facilitating the alleviation of the threshold voltage shift phenomenon of the driving transistor T0.

[0099] In other embodiments, (Vg1 - Vd1)×(Vg2 - Vd2) < 0. Here, by setting (Vg1 - Vd1)×(Vg2 - Vd2) < 0, the potential difference between the gate potential and the drain potential of the driving transistor T0 in the non - bias phase is reversed in the bias phase, thereby effectively balancing the problem of the threshold voltage shift of the driving transistor T0 caused by the non - bias phase.

[0100] Further optionally, Vd1 - Vg1 > Vg2 - Vd2 > 0. Here, by setting Vd1 - Vg1 > Vg2 - Vd2 > 0, and by setting a larger difference value of (Vd1 - Vg1), the potential difference between the gate potential and the drain potential of the driving transistor T0 in the non - bias phase can be balanced by another larger reversed potential difference in the bias phase, thereby facilitating the shortening of the time of the bias phase.

[0101] In addition, optionally, if the time length of the bias phase is t1 and the time length of the non - bias phase is t2, then (|Vg1 - Vd1| - |Vg2 - Vd2|)×(t1 - t2) < 0. Here, when |Vg1 - Vd1| is greater than |Vg2 - Vd2|, that is, the reversed potential difference used for biasing is larger, so the time of the bias phase can be set shorter than that of the non - bias phase; conversely, if |Vg1 - Vd1| is less than |Vg2 - Vd2|, that is, the reversed potential difference used for biasing is smaller, then the time of the bias phase can be set longer than that of the non - bias phase. The purpose of the above design is to fully offset the problem of the threshold voltage shift of the driving transistor generated in the non - bias phase during the bias phase, and at the same time, to avoid other problems caused by excessive progress of the bias phase.

[0102] In the foregoing embodiments, optionally, the non - bias phase is the light - emitting phase of the display panel, because during the light - emitting phase, the driving transistor T0 provides a driving current for the light - emitting element 20, such as Figures 2 to 5In the pixel circuit shown, before the light-emitting element 20 enters the light-emitting stage, a data signal Vdata is first written to the gate of the driving transistor T0 until the gate potential of the driving transistor T0 reaches (Vdata - Vth). Thereafter, the light-emitting stage begins. Therefore, during the light-emitting stage, the gate potential of the driving transistor T0 is at a relatively high potential. In some cases, during the light-emitting stage, for example, the source potential of the driving transistor T0 is 4.6V, the gate potential is 3V, and the drain potential is 1V. Therefore, during the light-emitting stage, the driving transistor T0 is turned on, but since the gate potential is higher than the drain potential, it causes the Id-Vg curve to shift, resulting in a shift in the threshold voltage Vth of the driving transistor T0. Therefore, in this embodiment, the light-emitting stage is set as a non-biased stage to solve the above-mentioned technical problems brought about by the light-emitting stage.

[0103] Reference Figures 3 - 5 , where, optionally, as Figure 3 shown, within one frame time, it includes a pre-stage and a light-emitting stage. The pre-stage sequentially includes a reset stage and a bias stage. During the reset stage, the first scan signal S1 controls the reset module 15 to turn on. Here, the first transistor T1 in the reset module 15 can be a PMOS transistor or an NMOS transistor. The NMOS transistor can be an oxide semiconductor transistor. In the figure, a PMOS transistor is taken as an example; the third scan signal S3 controls the compensation module 14 to turn on. Here, the fourth transistor T4 in the compensation module 14 can be a PMOS transistor or an NMOS transistor. The NMOS transistor can be an oxide semiconductor transistor. In the figure, an NMOS transistor is taken as an example; at this time, the reset signal terminal provides a reset signal Vref for the gate of the driving transistor T0 through the turned-on reset module 15 and compensation module 14. At this time, V0 is Vref, which is a relatively low-level signal.

[0104] When the reset stage ends, the compensation module 14 is turned off. Here, optionally, at the same time when the compensation module 14 is turned off, that is, at the falling edge of the third scan signal S3, at the same time, the V0 signal at the reset signal terminal rises from the low-level Vref to a relatively high-level signal Vobs. At this time, the reset module 15 remains turned on, and the pixel circuit enters the bias stage. The reset signal terminal provides a bias signal Vobs for the drain of the driving transistor T0. Here, by setting the bias stage to start simultaneously when the reset stage ends, the time length of the pre-stage can be shortened.

[0105] In addition, optionally, as Figure 3As shown, at the end of the reset stage, the compensation module 14 is first turned off. After a time interval, the V0 signal at the reset signal terminal rises from the low-level Vref to a relatively high high-level signal Vobs. The reset module 15 remains on, and the pixel circuit 10 enters the bias stage. Here, a time interval is set between the reset stage and the bias stage to avoid multiple signals being converted simultaneously, which may cause instability of the driving transistor. By stabilizing the driving transistor through the time interval and then performing the next operation, the stability of the pixel circuit can be improved. Optionally, the time length of this time interval is shorter than the time length of the reset stage, or the time length of this time interval is shorter than the time length of the bias stage. Because this time interval is only set to stabilize the driving transistor, there is no need for too long a time.

[0106] Optionally, as Figure 4 shown, after the reset stage ends, the reset module 15 is turned off, and the compensation module 14 remains on for a time interval. After a time interval, the compensation module 14 is turned off. At the same time, or thereafter, the reset module 15 is turned on again. And at the same time, or before this, the V0 signal at the reset signal terminal rises from the low-level Vref to a relatively high high-level signal Vobs, and the pixel circuit enters the bias stage. During this process, if all signals change simultaneously, it will be beneficial to shorten the time of the pre-stage, while if there is a time interval between the change times of all signals, it is beneficial to the stability of the driving transistor. How to design specifically can be flexibly set according to the specific situation.

[0107] Optionally, as Figure 4 shown, after the reset stage ends, during the time period between the turn-off of the reset module 15 and the turn-off of the compensation module 14, there is also a data writing stage. After the reset stage ends, the second scan signal S2 controls the data writing module 12 to turn on, and the data signal Vdata is written into the gate of the driving transistor T0 through the turned-on data writing module 12, the driving module 11, and the compensation module 14. After the data writing stage ends, the compensation module 14 is turned off, and the reset module 15 is turned on again to enter the bias stage.

[0108] Optionally, in this embodiment, the time length of the aforementioned reset stage is shorter than the time length of the bias stage. Because the purpose of the reset stage is to write the reset signal into the gate of the driving transistor, there is no need for too long a time. The bias stage is used to offset the threshold voltage offset in the non-bias stage. Therefore, a certain time length is required to achieve the effect, so there is this setting. In addition, as Figure 4In the shown scenario, the time length of the data writing stage is also shorter than that of the bias stage. Since the purpose of the data writing stage is to write the data signal to the gate of the driving transistor and does not require a long time, while the bias stage is used to offset the threshold voltage shift in the non-bias stage, a certain time length is required to achieve the effect, hence this setting.

[0109] In the foregoing embodiment, a reset stage is set before the bias stage. First, the gate potential of the driving transistor T0 is reset to a lower low-level signal by the reset signal Vref, and then the drain potential of the driving transistor T0 is raised to a higher high-level signal by the bias signal Vobs, achieving the purpose of, on the one hand, pulling down the gate potential of the driving transistor T0 and, on the other hand, raising the drain potential of the driving transistor T0 during the bias stage. Adjustments are made separately from two aspects, which is more conducive to improving the potential difference between the gate and the drain of the driving transistor T0 and enhancing the effect of the bias stage, fully offsetting the threshold voltage shift of the driving transistor T0 in the non-bias stage.

[0110] Reference Figure 5 , optionally, the pre-stage of this embodiment includes N bias stages, N≥1; an intermediate stage is included between any two adjacent bias stages among the N bias stages. The reset stage in the foregoing embodiment can be located before the first bias stage at the start of the bias stage, that is, the gate of the driving transistor T0 is reset first, and then the bias stage starts. Additionally, optionally, the reset stage can also be located in the intermediate stage between any two adjacent bias stages, such as the intermediate stage between the first bias stage and the second bias stage, or the intermediate stage between the second bias stage and the third bias stage, etc.; that is, at the start of the pre-stage, at least one bias stage is performed first, and then the reset stage is performed. Additionally, optionally, the reset stage can also be located after the last bias stage of the pre-stage, that is, before the light-emitting stage. In this case, it should be noted that the data writing stage must be performed after the reset stage, and then the light-emitting stage is entered. In the foregoing other embodiments, the data writing stage can be performed after the reset stage, or the data writing stage can be skipped and the bias stage can be directly entered, depending on the specific situation.

[0111] Exemplarily, Figure 5 shows two bias stages, but the actual situation is not limited to two. As Figure 5As shown, optionally, in the pre-stage, the time lengths of any two bias stages may not be equal. For example, the time length of the first bias stage is greater than that of other bias stages. It can be understood in this way that the first bias stage is the main bias stage, which mainly undertakes the problem of offsetting the threshold voltage deviation of the non-bias stage. However, in order to prevent the bias effect of the first bias stage from being incomplete, other supplementary bias stages can be set to fully supplement the bias effect. On this basis, it can be set that in the pre-stage, the time lengths of the bias stages decrease in sequence, so that the bias effect of the previous bias stage that is not sufficient can be supplemented by the subsequent bias stage. Based on the same concept, it can also be set conversely. For example, the time length of the last bias stage is greater than that of other bias stages. Specifically, in the pre-stage, the time lengths of the bias stages increase in sequence, and the bias effect can be gradually realized through the bias stages with gradually increasing time lengths one by one. In addition, combining the foregoing concepts, it can also be set that the time length of a certain intermediate bias stage is greater than that of the first bias stage and also greater than that of the second bias stage, that is, using the last bias stage as a supplement, and the intermediate bias stage as the main bias stage.

[0112] Optionally, in this embodiment, one data writing cycle of the display panel includes a total of S frame refresh screens, including a data writing frame and a holding frame, where S > 0; the data writing frame includes a data writing stage, and in the data writing stage, the data writing module writes a data signal to the gate of the driving transistor; the holding frame does not include a data writing stage.

[0113] In an implementation manner of this embodiment, the pre-stage of at least one data writing frame includes a bias stage. In this case, reference can be made to Figure 4 As shown, the data writing stage can be carried out before the bias stage, after the bias stage, or between two adjacent bias stages. When the data writing stage is carried out before the bias stage, as long as it is ensured that the compensation module 14 is turned off during the bias stage, the data signal Vdata can be locked at the gate of the driving transistor T0.

[0114] Optionally, in this implementation manner, if the time length of the pre-stage is T11 and the total time of all bias stages in the pre-stage is T22, after verification by the inventor, it is found that when T22 ≤ 2 / 3 × T11, it is possible to avoid the bias stage occupying too long a time in the pre-stage, resulting in an increase in the time of the pre-stage and a decrease in the refresh frequency of the display panel, which affects the display effect.

[0115] In another implementation manner of this embodiment, the pre-stage of at least one holding frame includes a biasing stage. In this case, the pre-stage may include a biasing stage and does not include a data writing stage. Optionally, the pre-stage may further include a reset stage. As Figure 3 shown, it may also not include a reset stage and directly enter the biasing stage. In this case, if the time length of the pre-stage is T11 and the total time of all biasing stages in the pre-stage is T22, through the verification of the inventor, T22 can be made equal to T11, that is, the entire pre-stage is a biasing stage, or T22 ≥ 2 / 3 × T11, so as to make full use of the time of the pre-stage for the biasing stage, thereby avoiding too long a pre-stage and being able to achieve a better biasing effect.

[0116] It should be noted that in this embodiment, only the pre-stage of the data writing frame may include a biasing stage, while the pre-stage of the holding frame does not include a biasing stage. At this time, if the biasing problem can be solved only by using the data writing frame, there is no need to set a biasing stage in the holding frame. It is also possible that only the pre-stage of the holding frame includes a biasing stage, while the pre-stage of the data writing frame does not include a biasing stage. Since the data writing frame also undertakes the work of the reset stage and the data writing stage, etc., if the holding frame can completely undertake the work of the biasing stage, there is no need to set a biasing stage in the data writing frame to simplify the timing of the data writing frame.

[0117] In still another implementation manner of this embodiment, it is also possible to select that the pre-stages of at least one holding frame and at least one data writing frame both include a biasing stage. With such a setting, the work of the biasing stage can be jointly undertaken by the holding frame and the data writing frame to ensure the effect of the biasing stage. Optionally, the time length of the biasing stage in the holding frame may be longer than the time length of at least one biasing stage in the data writing frame. As described above, the pre-stage of the holding frame does not include a data writing stage, so its timing is relatively simple. It is possible to make the biasing stage in the holding frame longer and at least one biasing stage in the data writing frame shorter, thereby avoiding too long a pre-stage of the data writing frame. On this basis, it can also be set that the total time length of the biasing stages in the holding frame is greater than or equal to the total time length of the biasing stages in the data writing frame. Further, optionally, the time length of the biasing stage in the holding frame is longer than the time length of any one biasing stage in the data writing frame to fully avoid too long a pre-stage of the data writing frame.

[0118] In addition, in this embodiment, as Figure 3As shown in the foregoing description, the turn-on time of the initialization module 17, i.e., the initialization stage of the pixel circuit, may not overlap with the bias stage, or may partially overlap with the bias stage. The initialization stage may end at the same time as the bias stage, or the initialization stage may end before or after the bias stage, depending on the specific situation.

[0119] In addition, in this embodiment, the display panel may further include an integrated chip, which is used to provide the required driving signals for the pixel circuit, such as a data signal Vdata, a reset signal Vref, a bias signal Vobs, and so on. Based on the same inventive concept, the integrated chip provided in this embodiment provides a reset signal Vref to the reset signal terminal during the reset stage of the pixel circuit, and provides a bias signal Vobs to the reset signal terminal during the bias stage of the pixel circuit, thereby ensuring the working process of the pixel circuit in this embodiment. For specific information about the reset signal Vref and the bias signal Vobs, reference may be made to the description in the foregoing embodiment.

[0120] In this application, some of T0, T1, T2, T3, T4, T5, and T6 may be PMOSs using polysilicon as the active layer, and some may be NMOSs using an oxide semiconductor as the active layer. For example, T4 is an NMOS transistor, and the other transistors are PMOS transistors; or, T0 and T1 are one type of transistor, such as a PMOS transistor or an NMOS transistor, and at least one of the remaining transistors is another type of transistor, such as an NMOS transistor or a PMOS transistor. It can be understood that the effective pulse of the scan signal of the NMOS transistor is a high level, and the effective pulse of the scan signal of the PMOS transistor is a low level. It should be noted that Figures 1 to 9 The pixel circuit shown is only an example, and the structure of the pixel circuit in the embodiment of the present invention is not limited thereto.

[0121] Optionally, the width-to-length ratio of the channel region of the NMOS transistor is greater than that of the PMOS transistor. In this application, if the NMOS transistor mainly functions as a switching transistor, a rapid response ability is required. For a transistor with a large width-to-length ratio, the length of its channel region is shorter, which is beneficial to improving the response ability of the transistor.

[0122] In addition, in the present application, the four scanning signals S1, S2, S3, and S4 can be different signals. In certain specific cases, such as when the timing meets certain conditions, at least two of the four signals S1, S2, S3, and S4 can also be the same signal. For example, when T5 and T6 are transistors of the same type, such as both being PMOS or both being NMOS, then S1 and S4 can be the same signal. Another example is that when T4 and T6 are transistors of the same type, such as both being PMOS or both being NMOS, then S3 and S4 can be the same signal. The specific situation depends on the specific circuit structure and timing, and this embodiment does not make special limitations on this.

[0123] Reference Figure 10 , Figure 10 is a partial cross-sectional schematic diagram of a pixel circuit. Among them, the pixel circuit includes two types of transistors: transistor Tm and transistor Tn. The gate of transistor Tm is located in the first metal layer M1, and the source and drain are both located in the fourth metal layer M4. Transistor Tm includes a first active layer w1, which is located between the first metal layer M1 and the substrate; transistor Tn includes a first gate and a second gate. The first gate is located in the second metal layer M2, and the second gate is located in the third metal layer M3. Transistor Tn includes a second active layer w2, which is located between the second metal layer M2 and the third metal layer M3. The source and drain of transistor Tn are located in the fourth metal layer M4. Among them, transistor Tm can be a low-temperature polysilicon transistor, and transistor Tn can be an oxide semiconductor transistor.

[0124] The pixel circuit includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 includes a first electrode plate C11 and a second electrode plate C12, and the second capacitor C2 includes a third electrode plate C23 and a fourth electrode plate C24. The first electrode plate and the second electrode plate are located on any two of the six film layers including the first active layer w1, the first metal layer M1, the second metal layer M2, the second active layer w2, the third metal layer M3, and the fourth metal layer; the third electrode plate and the fourth electrode plate are located on any two of the six film layers including the first active layer w1, the first metal layer M1, the second metal layer M2, the second active layer w2, the third metal layer M3, and the fourth metal layer M4.

[0125] In some cases, the first electrode plate and the third electrode plate are located on the same layer, and the second electrode plate and the fourth electrode plate are located on the same layer. In this case, the area of the first electrode plate is smaller than that of the third electrode plate, and the area of the second electrode plate is smaller than that of the fourth electrode plate, so as to achieve the purpose that the capacitance value of the first capacitor C1 is smaller than that of the second capacitor C2.

[0126] In some cases, the first electrode plate and the third electrode plate are located in the same layer, and the second electrode plate and the fourth electrode plate are located in different layers. Optionally, the distance between the first electrode plate and the second electrode plate is greater than the distance between the third electrode plate and the fourth electrode plate, so that the capacitance value of the first capacitor C1 can be less than the capacitance value of the second capacitor C2. In this case, optionally, the first electrode plate and the third electrode plate are located in the first metal layer M1, the fourth electrode plate is located in the second metal layer M2, and the second metal layer is located in the second active layer, or the third metal layer M3, or the fourth metal layer M4.

[0127] In some cases, the first electrode plate, the second electrode plate, the third electrode plate, and the fourth electrode plate are all located in different film layers, and their specific positions can be located in any one of the six film layers of the first active layer w1, the first metal layer M1, the second metal layer M2, the second active layer w2, the third metal layer M3, and the fourth metal layer M4, and all are within the protection scope of this case.

[0128] Optionally, a first insulating layer is included between the first electrode plate and the second electrode plate, and a second insulating layer is included between the third electrode plate and the fourth electrode plate, wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, so that the capacitance value of the first capacitor C1 is less than the capacitance value of the second capacitor C2. Additionally, optionally, when the driving transistor is a PMOS transistor, the transistor Tm can be the driving transistor. At this time, the hydrogen content of the second insulating layer is greater than the hydrogen content in the first insulating layer because, in this embodiment, the second capacitor C2 is the storage capacitor in the pixel circuit, and in the direction perpendicular to the surface of the display panel, the second capacitor C2 generally overlaps with the driving transistor, and the driving transistor is a top-gate structure. Therefore, the second capacitor C2 is generally located on the side of the first active layer w1 away from the substrate. In particular, the third electrode plate C23 of the second capacitor C2 can be multiplexed with the gate of the transistor Tm, and the fourth electrode plate can be located on the second metal layer M2 and overlap with the gate of the transistor Tm. At this time, the driving transistor is a PMOS transistor, optionally a low-temperature polysilicon transistor, and the active layer of the low-temperature polysilicon transistor needs to be hydrogenated, resulting in a relatively high hydrogen content in the surrounding film layers. Therefore, in this embodiment, the hydrogen content of the second insulating layer is greater than the hydrogen content in the first insulating layer.

[0129] Optionally, the oxygen content in the first insulating layer is greater than that in the second insulating layer. Since the first capacitor C1 is smaller than the second capacitor C2, in some cases, the thickness of the first insulating layer is greater than that of the second insulating layer. Therefore, in the first capacitor C2, at least one of the first electrode plate and the second electrode plate is closer to the active layer of the transistor Tn, that is, the active layer of the oxide semiconductor transistor, compared with the third electrode plate and the fourth electrode plate. In order to ensure the normal function of the oxide semiconductor transistor, in the film layer around the oxide semiconductor active layer, the hydrogen content is small and the oxygen content is relatively high. Therefore, in this case, the oxygen content in the first insulating layer is greater than that in the second insulating layer.

[0130] Based on the same inventive concept, an embodiment of the present invention further provides a driving method for a display panel. The display panel includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes a data writing module 12, a driving module 11, a compensation module 14, and a reset module 15. The data writing module 12 is connected between a data signal input terminal and the source electrode of a driving transistor T0, and is configured to provide a data signal Vdata for the driving module 11. The driving module is configured to provide a driving current for the light-emitting element 20. The driving module 11 includes a driving transistor T0. The compensation module 14 is connected between the gate electrode and the drain electrode of the driving transistor T0, and is configured to compensate for the threshold voltage of the driving transistor T0. The reset module 15 is connected between a reset signal terminal and the drain electrode of the driving transistor T0, and is configured to provide a reset signal Vref for the gate electrode of the driving transistor T0. Among them, the reset module 15 is also multiplexed as a bias module.

[0131] The driving method of the display panel includes:

[0132] Reset stage: In the reset stage, the reset module 15 and the compensation module 14 are turned on. The reset signal terminal provides a reset signal for the gate electrode of the driving transistor T0 to reset the gate electrode of the driving transistor T0.

[0133] Bias stage: In the bias stage, the reset module 15 is turned on and the compensation module 14 is turned off. The reset signal terminal provides a bias signal Vobs for the drain electrode of the driving transistor T0 to adjust the bias state of the driving transistor T0.

[0134] In other embodiments of this embodiment, the driving method may include the driving method adopted in the working process of the pixel circuit in any of the foregoing embodiments. The same content will not be repeated in this embodiment, but it should be considered that all are within the protection scope of the driving method provided in this embodiment.

[0135] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel described in any of the above embodiments. Optionally, the display panel is an organic light-emitting display panel or a micro LED display panel.

[0136] Reference Figure 11 , Figure 11 is a schematic diagram of a display device provided by an embodiment of the present invention. As Figure 11 shown, it is optional that the display device is applied to an electronic device 100 such as a smart phone or a tablet computer. It can be understood that the above embodiments only provide some examples of the pixel circuit structure and the driving method of the pixel circuit. The display panel further includes other structures, which will not be elaborated here one by one.

[0137] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the inventive concept of the present invention, several simple deductions or substitutions can still be made, which should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A display panel, characterized in that, including a pixel circuit and a light-emitting element; the pixel circuit includes a driving module, a data writing module, and a light-emitting control module; the driving module is configured to provide a driving current for the light-emitting element, the driving module includes a driving transistor, an input end of the driving module is connected to a source electrode of the driving transistor, and an output end of the driving module is connected to a drain electrode of the driving transistor; the data writing module is configured to selectively provide a data signal for the driving transistor; the light-emitting control module is configured to selectively allow the light-emitting element to enter a light-emitting stage, one end of the light-emitting control module is connected to a first power signal terminal for receiving a first power signal; wherein, the pixel circuit further includes a latching module and a first scan signal line for receiving a first scan signal; the latching module is connected between a gate electrode of the driving transistor and the first scan signal line; wherein, the pixel circuit includes a reset module connected between a reset signal terminal and the drain electrode of the driving transistor, and a control end of the reset module is connected to the first scan signal line; and / or, the pixel circuit includes an initialization module connected between an initialization signal terminal and the light-emitting element, and a control end of the initialization module is connected to the first scan signal line.

2. The display panel according to claim 1, wherein when the pixel circuit includes a reset module connected between a reset signal terminal and the drain electrode of the driving transistor, it is configured to provide a reset signal for the gate electrode of the driving transistor, and the reset module includes a first transistor; the pixel circuit includes a compensation module; the compensation module is connected between the gate electrode and the drain electrode of the driving transistor for compensating a threshold voltage of the driving transistor.

3. The display panel according to claim 2, wherein when the pixel circuit includes an initialization module connected between an initialization signal terminal and the light-emitting element, it is configured to selectively provide an initialization signal for the light-emitting element.

4. The display panel according to claim 2, wherein an operation process of the pixel circuit includes a reset stage and a bias stage; in the reset stage, the reset module and the compensation module are turned on, and the reset signal terminal provides a reset signal for the gate electrode of the driving transistor; in the bias stage, the reset module is turned on, the compensation module is turned off, and the reset signal terminal provides a bias signal for the drain electrode of the driving transistor.

5. The display panel according to claim 4, wherein both the driving transistor and the first transistor are PMOS transistors, and in the bias stage, a voltage of the first scan signal is lower than a voltage of the bias signal; or, both the driving transistor and the first transistor are NMOS transistors, and in the bias stage, a voltage of the first scan signal is higher than a voltage of the bias signal.

6. The display panel according to claim 4, wherein Both the driving transistor and the first transistor are PMOS transistors. During the biasing stage, the first scan signal pulls down the gate potential of the driving transistor through the latching module; Or, Both the driving transistor and the first transistor are NMOS transistors. During the biasing stage, the first scan signal raises the gate potential of the driving transistor through the latching module.

7. The display panel according to claim 4, wherein The driving transistor is a PMOS transistor. During the biasing stage, the drain voltage of the driving transistor is greater than the gate voltage of the driving transistor; or, The driving transistor is an NMOS transistor. During the biasing stage, the drain voltage of the driving transistor is less than the gate voltage of the driving transistor.

8. The display panel according to claim 4, wherein During one frame time of the display panel, the operation process of the pixel circuit includes a pre-stage and a light-emitting stage; wherein, During at least one frame time, the pre-stage of the pixel circuit includes the biasing stage.

9. The display panel according to claim 8, wherein The pre-stage further includes a reset stage; After the reset stage ends, the pixel circuit enters the biasing stage. At the start of the biasing stage, the gate potential of the driving transistor is the reset signal.

10. The display panel according to claim 8, wherein Before the start of the biasing stage, the gate potential of the driving transistor is not equal to the reset signal.

11. The display panel according to claim 10, wherein After the light-emitting stage of the pixel circuit ends and it enters the pre-stage, the reset module is turned on, the compensation module remains off, and it enters the biasing stage.

12. The display panel according to claim 11, wherein The pre-stage further includes a data writing stage. During the data writing stage, the data writing module, the driving module, and the compensation module are all turned on, and the data signal is written to the gate of the driving transistor; At least one of the biasing stages of the pre-stage is performed after the data writing stage.

13. The display panel according to claim 12, wherein The pre-stage includes a first biasing stage and a second biasing stage; The first biasing stage is performed before the data writing stage, and the second biasing stage is performed after the data writing stage; wherein, In the first biasing stage and the second biasing stage, the time length of at least one of them is greater than that of the other.

14. The display panel according to claim 1, wherein The latching module includes a first capacitor. The first electrode plate of the first capacitor is connected to the gate of the driving transistor, and the second electrode plate is connected to the first scan signal line.

15. The display panel according to claim 14, wherein The pixel circuit further includes a second capacitor; One electrode plate of the second capacitor is connected to the gate of the driving transistor and is used for storing the data signal transmitted to the gate of the driving transistor; The capacitance value of the first capacitor is smaller than that of the second capacitor.

16. The display panel according to claim 15, wherein The capacitance value of the first capacitor is C1, and the capacitance value of the second capacitor is C2, where 5 ≤ C1 / C2 ≤ 20.

17. A display device, characterized in that, It includes the display panel according to any one of claims 1-16.

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