Semiconductor device comprising an active region and a gate structure

Abstract

A semiconductor device includes: an active region extending in a vertical direction from a semiconductor substrate; source / drain regions spaced apart from each other on the active region; a fin structure between the source / drain regions on the active region; an isolation layer covering side surfaces of the active region; a gate structure overlapping the fin structure and covering an upper surface and side surfaces of the fin structure; and a contact plug electrically connected to the source / drain regions, the fin structure including: a lower semiconductor region on the active region; a stack structure having alternating first semiconductor layers and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being concave toward a corresponding center; and a semiconductor cap layer on the stack structure, the semiconductor cap layer being between the gate structure and each of the lower semiconductor region and the stack structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more specifically, to semiconductor devices having an active region and a gate structure. Background Technology

[0002] As the demand for high performance, high speed, and / or multifunctionality in semiconductor devices increases, the integration density of semiconductor devices is constantly increasing. To address the limitations in operating characteristics caused by the reduction in the size of planar MOSFETs, various efforts are underway to develop MOSFETs, including those with three-dimensional channel structures. Summary of the Invention

[0003] According to one example embodiment, a semiconductor device includes: a first active region extending vertically from a semiconductor substrate, the first active region extending in a first direction parallel to an upper surface of the semiconductor substrate; first source / drain regions spaced apart from each other in the first direction on the first active region; a fin structure on the first active region between the first source / drain regions; a first isolation layer covering a side surface of the first active region on the semiconductor substrate; a first gate structure overlapping the fin structure and extending in a second direction to cover an upper surface of the fin structure and a side surface of the fin structure in the second direction; a semiconductor capping layer between the first gate structure and a stacked structure and between the first gate structure and a first lower semiconductor region; and a first contact plug electrically connected to the first source / drain regions, the fin structure having: a first lower semiconductor region extending from the first active region; a stacked structure on the first lower semiconductor region, the stacked structure including alternating first and second semiconductor layers stacked in a vertical direction, and at least one of the alternating first and second semiconductor layers having a side surface of the first semiconductor layer recessed toward a corresponding center in a second direction perpendicular to the first direction; and a semiconductor capping layer on the stacked structure.

[0004] According to one example embodiment, a semiconductor device includes: an isolation layer defining an active region on a semiconductor substrate; source / drain regions on the active region; a fin structure extending from the active region in a vertical direction perpendicular to an upper surface of the semiconductor substrate and disposed between the source / drain regions; and a gate structure overlapping the fin structure and extending upward from the isolation layer. The active region extends in a first direction parallel to the upper surface of the semiconductor substrate. The source / drain regions contact side surfaces of the fin structure in the first direction. The gate structure covers side surfaces of the fin structure in a second direction and the upper surface of the fin structure. The second direction is perpendicular to the first direction. The fin structure includes: a lower semiconductor region extending from the active region in a vertical direction; a stacked structure on the lower semiconductor region; and a semiconductor capping layer including at least a portion between the gate structure and the stacked structure. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a vertical direction. At least one side surface of the fin structure overlaps a portion of the isolation layer.

[0005] According to one example embodiment, a semiconductor device includes: a shallow isolation layer defining a plurality of active regions on a semiconductor substrate; source / drain regions on the plurality of active regions; and a fin structure extending from the plurality of active regions in a vertical direction perpendicular to an upper surface of the semiconductor substrate and configured to contact the source / drain regions; and a gate structure overlapping the fin structure and extending upward from the shallow isolation layer. Each of the plurality of active regions extends in a first direction parallel to the upper surface of the semiconductor substrate. The source / drain regions contact a side surface of the fin structure in the first direction. The gate structure covers the side surface of the fin structure in a second direction and the upper surface of the fin structure. The second direction is perpendicular to the first direction. Each fin structure includes: a lower semiconductor region extending from the active region in a vertical direction; a stacked structure on the lower semiconductor region; and a semiconductor capping layer covering the side surface of the stacked structure in the second direction. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a vertical direction. The plurality of second semiconductor layers include a material different from the material of the plurality of first semiconductor layers. The side surfaces of the plurality of first semiconductor layers in the second direction are further recessed toward their respective centers than the side surfaces of the plurality of second semiconductor layers in the second direction. In at least one of the plurality of first semiconductor layers, the width of the central portion in the second direction is smaller than the width of each of its upper and lower portions in the second direction. Attached Figure Description

[0006] Features will become apparent to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0007] Figure 1 A top view of a semiconductor device according to an example embodiment is shown;

[0008] Figure 2A and Figure 2B A cross-sectional view of a semiconductor device according to an example embodiment is shown;

[0009] Figure 3 A cross-sectional view of a modified example of a semiconductor device according to an exemplary embodiment is shown;

[0010] Figure 4A and Figure 4B A cross-sectional view of a modified example of a semiconductor device according to an exemplary embodiment is shown;

[0011] Figure 5A and Figure 5B A cross-sectional view of a modified example of a semiconductor device according to an exemplary embodiment is shown;

[0012] Figure 6 A cross-sectional view of a modified example of a semiconductor device according to an exemplary embodiment is shown;

[0013] Figure 7 A cross-sectional view of a modified example of a semiconductor device according to an exemplary embodiment is shown;

[0014] Figure 8 A top view of a modified example of a semiconductor device according to an exemplary embodiment is shown;

[0015] Figure 9 A cross-sectional view of a modified example of a semiconductor device according to an exemplary embodiment is shown;

[0016] Figure 10 A cross-sectional view of a modified example of a semiconductor device according to an exemplary embodiment is shown;

[0017] Figure 11 A process flow diagram of a method for forming a semiconductor device according to an exemplary embodiment is shown;

[0018] Figures 12A to 14B Cross-sectional views of stages in a method for forming a semiconductor device according to an exemplary embodiment are shown; and

[0019] Figure 15A and Figure 15B A cross-sectional view of a stage in another example of a method for forming a semiconductor device according to an exemplary embodiment is shown. Detailed Implementation

[0020] In the following description, exemplary embodiments will be described with reference to the accompanying drawings.

[0021] Reference Figure 1 , Figure 2A and Figure 2BAn example of a semiconductor device according to an exemplary implementation. Figure 1 This is a top view of a semiconductor device according to an example embodiment. Figure 2A It is along Figure 1 The cross-sectional views taken along lines I-I' and II-II' show an example of a semiconductor device according to an exemplary embodiment. Figure 2B It is along Figure 1 The cross-sectional views taken along lines III-III' and IV-IV' show an example of a semiconductor device according to an exemplary embodiment.

[0022] Reference Figure 1 and Figure 2A A first active region 6a protruding from the semiconductor substrate 3 in the vertical direction Z and extending in the first direction D1, a fin structure 33 on the first active region 6a, a first gate structure 45a overlapping the fin structure 33, and a first source / drain region 40a on the first active region 6a may be disposed in the first transistor region TR1. The fin structure 33 may include a first lower semiconductor region 6b, stacked structures 10a, 10b, 10c, 12a1, 12b1 and 12c1, and a semiconductor capping layer 27.

[0023] The semiconductor substrate 3 can be, for example, a silicon substrate. The vertical direction Z can be a direction perpendicular to the upper surface 3S of the semiconductor substrate 3. The first active region 6a can extend in a first direction D1 parallel to the upper surface 3S of the semiconductor substrate 3.

[0024] The first isolation layer 16a may be disposed on the semiconductor substrate 3 to cover the side surface of the first active region 6a. The first isolation layer 16a may include a first buffer insulating layer 18a covering the upper surface 3S of the semiconductor substrate 3 and the side surface of the first active region 6a, a first insulating liner 19a covering the first buffer insulating layer 18a, and a first gap-filling insulating layer 20a covering the first insulating liner 19a.

[0025] The fin structure 33 may have a first side surface 33S1 in a first direction D1 and a second side surface 33S2 in a second direction D2 perpendicular to the first direction D1. The second direction D2 may be parallel to the upper surface 3S of the semiconductor substrate 3.

[0026] Throughout this specification, "side surface in the first direction D1" can refer to a side surface arranged in the first direction D1, and "side surface in the second direction D2" can refer to a side surface arranged in the second direction D2. For example, as Figure 1 and Figure 2AAs shown, the "side surface in the first direction D1" may have a longitudinal direction extending in the second direction D2 perpendicular to the first direction D1, and the "side surface in the second direction D2" may have a longitudinal direction extending in the first direction D1 perpendicular to the second direction D2.

[0027] The fin structure 33 may include a portion extending from the first active region 6a in the vertical direction Z. For example, the first lower semiconductor region 6b of the fin structure 33 may extend from the first active region 6a, for example, continuously and integrally, in the vertical direction Z. Therefore, the first lower semiconductor region 6b may be formed of the same material as the first active region 6a, such as silicon.

[0028] The stacked structures 10a, 10b, 10c, 12a1, 12b1 and 12c1 of the fin structure 33 may include a plurality of first semiconductor layers 10a, 10b and 10c and a plurality of second semiconductor layers 12a1, 12b1 and 12c1 alternately stacked on the first lower semiconductor region 6b.

[0029] The plurality of first semiconductor layers 10a, 10b and 10c may include a first silicon-germanium layer 10a, a second silicon-germanium layer 10b and a third silicon-germanium layer 10c spaced apart from each other in the vertical direction Z. The first silicon-germanium layer 10a may be in contact (e.g., in direct contact) with the first lower semiconductor region 6b.

[0030] The plurality of second semiconductor layers 12a1, 12b1, and 12c1 may include a first silicon layer 12a1, a second silicon layer 12b1, and a third silicon layer 12c1 spaced apart from each other in the vertical direction Z. The first silicon layer 12a1 may be interposed between the first silicon-germanium layer 10a and the second silicon-germanium layer 10b, the second silicon layer 12b1 may be interposed between the second silicon-germanium layer 10b and the third silicon-germanium layer 10c, and the third silicon layer 12c1 may be disposed on the upper surface of the third silicon-germanium layer 10c.

[0031] In one example, the first silicon-germanium layer 10a, the second silicon-germanium layer 10b, and the third silicon-germanium layer 10c may, for example, have the same first thickness along the vertical direction Z. In one example, for example, along the vertical direction Z, the first lower semiconductor region 6b may have a thickness greater than the thickness of each of the plurality of first semiconductor layers 10a, 10b, and 10c, as measured from the upper end of the first insulating layer 16a. In one example, for example, along the vertical direction Z, the first lower semiconductor region 6b may have a thickness greater than the thickness of the lowest second semiconductor layer 12a1 among the plurality of second semiconductor layers 12a1, 12b1, and 12c1. In one example, for example, along the vertical direction Z, at least one of the plurality of second semiconductor layers 12a1, 12b1, and 12c1 may have a thickness smaller than the thickness of each of the plurality of first semiconductor layers 10a, 10b, and 10c.

[0032] The semiconductor capping layer 27 of the fin structure 33 can be interposed between the first gate structure 45a and the stacked structures 10a, 10b, 10c, 12a1, 12b1, and 12c1, and can extend between the first gate structure 45a and the first lower semiconductor region 6b. The semiconductor capping layer 27 can cover (e.g., continuously cover) the side surface 6S2 of the first lower semiconductor region 6b in the second direction D2, the side surfaces of the stacked structures 10a, 10b, 10c, 12a1, 12b1, and 12c1 in the second direction D2, and the upper surfaces of the stacked structures 10a, 10b, 10c, 12a1, 12b1, and 12c1. For example, as... Figure 2A As shown, the semiconductor capping layer 27 can be continuous and conformal on the surfaces of the first lower semiconductor region 6b and the stacked structures 10a, 10b, 10c, 12a1, 12b1, 12c1. For example, the semiconductor capping layer 27 can completely separate the first gate structure 45a from the first lower semiconductor region 6b and the stacked structures 10a, 10b, 10c, 12a1, 12b1, 12c1 in the fin structure 33.

[0033] In one example, among the plurality of first semiconductor layers 10a, 10b, and 10c and the plurality of second semiconductor layers 12a1, 12b1, and 12c1, the lowest layer may be the lowest first semiconductor layer 10a. In the semiconductor capping layer 27, the portion 27L covering the side surface of the first lower semiconductor region 6b may have a maximum thickness, for example, along the second direction D2, which is different from the minimum thickness, for example, along the second direction D2, of the portion 27S1 covering the side surface of the lowest first semiconductor layer 10a. For example, in the semiconductor capping layer 27, the portion 27L covering the side surface of the first lower semiconductor region 6b may have a maximum thickness greater than the minimum thickness of the portion 27S1 covering the side surface of the lowest first semiconductor layer 10a.

[0034] In one example, in the semiconductor capping layer 27, the portion 27L covering the first lower semiconductor region 6b can have a maximum thickness greater than the minimum thickness of each of the portions 27S1 covering the plurality of first semiconductor layers 10a, 10b and 10c.

[0035] In one example, in the semiconductor capping layer 27, each of the portions 27S1 covering the plurality of first semiconductor layers 10a, 10b and 10c may have a different thickness than each of the portions 27S2 covering the plurality of second semiconductor layers 12a1, 12b1 and 12c1.

[0036] In one example, in the semiconductor capping layer 27, the thickness of the semiconductor capping layer 27 disposed on the uppermost second semiconductor layer 12c1 among the plurality of second semiconductor layers 12a1, 12b1, and 12c1 in the vertical direction Z can be approximately 4 nm or greater, and the thickness of each portion 27S1 of the semiconductor capping layer 27 covering the plurality of first semiconductor layers 10a, 10b, and 10c, for example along the second direction D2, can be approximately 2 nm or less. Therefore, in the semiconductor capping layer 27, the thickness of the semiconductor capping layer 27 disposed on the uppermost second semiconductor layer 12c among the plurality of second semiconductor layers 12a1, 12b1, and 12c1 in the vertical direction Z can be greater than or equal to twice the thickness of each portion 27S1 of the semiconductor capping layer 27 covering the plurality of first semiconductor layers 10a, 10b, and 10c, for example along the second direction D2. For example, the semiconductor capping layer 27 may include a first portion 27U on the upper surface of the uppermost second semiconductor layer 12c1 of alternating first semiconductor layers 10a, 10b, and 10c and second semiconductor layers 12a1, 12b1, and 12c1, and a second portion 27S1 contacting the first semiconductor layers 10a, 10b, and 10c. The thickness of the first portion 27U in the vertical direction Z may be greater than or equal to twice the thickness of at least one of the second portions 27S1 in the second direction D2. In one example, the first portion 27U has a rounded structure. In another example, the thickness of the first portion 27U in the vertical direction Z may be greater than its width in the second direction D2.

[0037] Each of the plurality of first semiconductor layers 10a, 10b, and 10c may have a thickness, for example, along the vertical direction Z, greater than, for example, the thickness of the semiconductor capping layer 27 in the region on the uppermost second semiconductor layer 12c. Each of the plurality of second semiconductor layers 12a1, 12b1, and 12c1 may have a thickness, for example, along the vertical direction Z, greater than, for example, the thickness of the semiconductor capping layer 27 in the region on the uppermost second semiconductor layer 12c1.

[0038] In the semiconductor capping layer 27, the thickness of the semiconductor capping layer 27 on the uppermost second semiconductor layer 12c1 among the plurality of second semiconductor layers 12a1, 12b1 and 12c1 in the vertical direction Z may be greater than or equal to twice the thickness of each of the portions 27S1 of the semiconductor capping layer 27 covering the side surfaces of the first silicon layer 12a1 and the second silicon layer 12b1 among the plurality of second semiconductor layers 12a1, 12b1 and 12c, for example, along the second direction D2.

[0039] At least one of the plurality of first semiconductor layers 10a, 10b, and 10c may have a recessed side surface such that the width of the central portion in the second direction D2 is narrower than the widths of the upper and lower portions in the second direction D2. For example, each of the plurality of first semiconductor layers 10a, 10b, and 10c may have a recessed side surface, such as a side surface that is curved toward the respective center of the plurality of first semiconductor layers 10a, 10b, and 10c.

[0040] At least one of the side surfaces 33S2 of the fin structure 33 in the second direction D2 may protrude further in the second direction D2 than one of the side surfaces of the first active region 6a in the second direction D2, so as to overlap with a portion of the first isolation layer 16a. For example, the side surface 33S2 of the fin structure 33 in the second direction D2 may protrude further in the second direction D2 than the side surface 33S2 of the first active region 6a adjacent to the side surface 33S2 of the fin structure 33, so as to overlap with a portion of the first isolation layer 16a.

[0041] For example, refer to Figure 2A A portion of the semiconductor capping layer 27 is a portion of the fin structure 33 that protrudes beyond the surface of the first active region 6a in the second direction D2. For example, a portion 27L of the semiconductor capping layer 27 covering the side surface of the first lower semiconductor region 6b may overlap with a portion of the first isolation layer 16a.

[0042] In one example, at least one of the side surfaces 33S2 of the fin structure 33 in the second direction D2 may overlap with the upper end of the first buffer insulating layer 18a. In one example, the side surfaces 33S2 of the fin structure 33 in the second direction D2 may overlap with the upper end of the first buffer insulating layer 18a but may not overlap with the first gap-filling insulating layer 20a. In one example, the semiconductor capping layer 27 of the fin structure 33 may overlap with the upper end of the first buffer insulating layer 18a but may not overlap with the first gap-filling insulating layer 20a.

[0043] In one example, the fin structure 33 may include a region whose width gradually increases and then decreases in the second direction D2 as the distance from the semiconductor substrate 3 in the vertical direction Z increases. For example, the upper region 27U of the fin structure 33 may have a width in the second direction D2 that gradually increases and then decreases as the distance from the semiconductor substrate 3 in the vertical direction Z increases.

[0044] In one example, the plurality of first semiconductor layers 10a, 10b, and 10c may not overlap with the first isolation layer 16a. In another example, the plurality of second semiconductor layers 12a1, 12b1, and 12c1 may not overlap with the first isolation layer 16a.

[0045] The first gate structure 45a may extend upward from the isolation layer 16a (e.g., over the isolation layer 16a) while covering the upper surface of the fin structure 33 and the side surface 33S2 of the fin structure 33 in the second direction D2. The first gate structure 45a may include a first gate dielectric layer 47a and a first gate electrode 49a on the first gate dielectric layer 47a.

[0046] The first gate dielectric layer 47a can contact the upper surface of the first isolation layer 16a, the side surface of the fin structure 33 in the second direction D2, and the upper surface of the fin structure 33. For example, in the second direction D2, the first gate dielectric layer 47a can have a thickness greater than that of the semiconductor capping layer 27.

[0047] In one example, the first gate dielectric layer 47a may include a first material layer 47a_1 and a second material layer 47a_2 on the first material layer 47a_1. The second material layer 47a_2 may extend along the side surface of the first gate electrode 49a. The first material layer 47a_1 may be formed of, for example, silicon oxide, and the second material layer 47a_2 may be formed of, for example, a high-k dielectric.

[0048] The first material layer 47a_1 of the first gate dielectric layer 47a of the first gate structure 45a may be formed of oxide oxide and deposited oxide. For example, the first material layer 47a_1 forming the first gate dielectric layer 47a of the first gate structure 45a may include oxidizing the surface of the semiconductor capping layer 27 to form oxide oxide and performing a deposition process on the oxide oxide to form deposited oxide. In one example, the first material layer 47a_1 may have a thickness greater than that of the second material layer 47a_2.

[0049] The first gate capping layer 53a may be disposed on the first gate structure 45a. The first gate capping layer 53a may be formed of an insulating material such as silicon nitride.

[0050] The first gate spacer 56a may be disposed on the side surface of the first gate structure 45a and the first gate capping layer 53a. The first gate spacer 56a may be disposed on the semiconductor capping layer 27 of the fin structure 33.

[0051] The first source / drain region 40a may contact the side surface 33S1 of the fin structure 33 in the first direction D1 (including the side surface 6S1 of the first lower semiconductor region 6b in the first direction). A first contact plug 62a may be disposed on the opposite side adjacent to the first gate structure 45a for electrical connection to the first source / drain region 40a. In one example, a first insulating layer 59a may be disposed between the first contact plug 62a and the first gate spacer 56a.

[0052] Reference Figure 2B as well as Figure 1 and Figure 2A A second active region 8a protruding from the semiconductor substrate 3 in the vertical direction Z, a second lower semiconductor region 8b extending from the second active region 8a in the vertical direction Z, a plurality of semiconductor channel layers 12a2, 12b2 and 12c2 spaced apart from each other in the vertical direction Z on the lower semiconductor region 8b, a second gate structure 45b overlapping the plurality of semiconductor channel layers 12a2, 12b2 and 12c2, and a second source / drain region 40b on the second active region 8a may be disposed in the second transistor region TR2.

[0053] The second active region 8a may be spaced apart from the first active region 6a. The second active region 8a may extend in the first direction D1.

[0054] The second isolation layer 16b can be configured to cover the upper surface 3S of the semiconductor substrate 3 and the side surface of the second active region 8a. The second isolation layer 16b includes a second buffer insulating layer 18b covering the side surface of the second active region 8a, a second insulating liner 19b covering the second buffer insulating layer 18b, and a second gap-filling insulating layer 20b covering the second insulating liner 19b.

[0055] The first buffer insulating layer 18a and the second buffer insulating layer 18b can be formed of the same material, such as silicon oxide. The first insulating liner 19a and the second insulating liner 19b can be formed of the same material, such as silicon nitride. The first gap-filling insulating layer 20a and the second gap-filling insulating layer 20b can be formed of the same material, such as silicon oxide.

[0056] The plurality of semiconductor channel layers 12a2, 12b2 and 12c2 may include a first semiconductor channel layer 12a2 on the second lower semiconductor region 8b, a second semiconductor channel layer 12b2 on the first semiconductor channel layer 12a2 and a third semiconductor channel layer 12c2 on the second semiconductor channel layer 122b.

[0057] Each of the plurality of semiconductor channel layers 12a2, 12b2, and 12c2 may have a thickness, for example, substantially the same along the vertical direction Z as the thickness of each of the plurality of second semiconductor layers 12a1, 12b1, and 12c1. The plurality of semiconductor channel layers 12a2, 12b2, and 12c2, as well as the plurality of second semiconductor layers 12a1, 12b1, and 12c1, may be formed of the same material (e.g., epitaxially grown silicon).

[0058] The second gate structure 45b may overlap with the plurality of semiconductor channel layers 12a2, 12b2, and 12c2, and may extend in the second direction D2 to be disposed on the second isolation layer 16b. The second gate structure 45b may cover the upper surface and the side surface of the second lower semiconductor region 8b in the second direction D2 while extending along the second direction D2, and may surround each of the plurality of semiconductor channel layers 12a2, 12b2, and 12c2. The second gate structure 45b may cover the upper surface, lower surface, and side surface of each of the plurality of semiconductor channel layers 12a2, 12b2, and 12c2 in the second direction while extending along the second direction D2.

[0059] The second gate structure 45b may include a second gate dielectric layer 47b and a second gate electrode 49b. In one example, the first gate dielectric layer 47a may have a thickness greater than that of the second gate dielectric layer 47b.

[0060] The second gate dielectric layer 47b may include a third material layer 47b_1 and a fourth material layer 47b_2. The fourth material layer 47b_2 of the second gate dielectric layer 47b may be disposed between the second gate electrode 49b and the second lower semiconductor region 8b, between the second gate electrode 49b and the first semiconductor channel layer 12a2, between the second gate electrode 49b and the second semiconductor channel layer 12b2, between the second gate electrode 49b and the third semiconductor channel layer 12c2, and between the second gate electrode 49b and the second source / drain region 40b, and may cover the side surface of the second gate electrode 49b. In one example, the third material layer 47b_1 of the second gate dielectric layer 47b can be disposed between the fourth material layer 47b_2 and the second lower semiconductor region 8b, between the fourth material layer 47b_2 and the first semiconductor channel layer 12a2, between the fourth material layer 47b_2 and the second semiconductor channel layer 12b2, and between the fourth material layer 47b_2 and the third semiconductor channel layer 12c2.

[0061] The second source / drain region 40b may extend in the vertical direction Z on the second active region 8a to contact the side surfaces of the plurality of semiconductor channel layers 12a2, 12b2, and 12c2 in the first direction D1. For example, as Figure 2B As shown, the second source / drain region 40b may at least partially overlap with the lower part of the side surface of the second gate structure 45b.

[0062] According to an example implementation, a first transistor may be provided in a first transistor region TR1. The first transistor may include a first gate structure 45a, a first source / drain region 40a, and a fin structure 33 between the first source / drain regions 40a. The fin structure 33 may be provided as a channel region of the first transistor.

[0063] The first gate dielectric layer 47a of the first gate structure 45a may not be in direct contact with the plurality of first semiconductor layers 10a, 10b, and 10c that may be formed from silicon and germanium, but may be in direct contact with the semiconductor capping layer 27 that may be formed from silicon. As described above, the first gate dielectric layer 47a of the first gate structure 45a may be spaced apart from the plurality of first semiconductor layers 10a, 10b, and 10c, and may be in direct contact with the semiconductor capping layer 27 to improve the reliability of the first gate dielectric layer 47a, thereby preventing the threshold voltage of the first transistor from abnormally decreasing or becoming unstable, and improving the electrical characteristics of the first transistor.

[0064] According to an example embodiment, a second transistor may be provided in a second transistor region TR2. The second transistor may include a second gate structure 45b, a second source / drain region 40b, and semiconductor channel layers 12a2, 12b2, and 12c2 between the second source / drain regions 40b. The second transistor may be a gate-all-around (GAA) MOSFET.

[0065] In one example, the second gate structure 45b may be in direct contact with the second source / drain region 40b, but the example implementation is not limited to this. For example, the second gate structure 45b may be spaced apart from the second source / drain region 40b. (See also...) Figure 3 An example of such a modification is described, wherein the second gate structure 45b and the second source / drain region 40b are spaced apart from each other. Figure 3 It is along Figure 1 The cross-sectional views taken from lines III-III' and IV-IV' show a modified example in which the second gate structure 45b and the second source / drain region 40b are spaced apart from each other.

[0066] Reference Figure 3 An insulating spacer 38 may be disposed between the second gate structure 45b and the second source / drain region 40b. The second gate structure 45b and the second source / drain region 40b may be spaced apart from each other by the insulating spacer 38.

[0067] Reference Figure 2A and Figure 2BThe plurality of second semiconductor layers 12a1, 12b1, and 12c1 may have the same thickness, and the plurality of semiconductor channel layers 12a2, 12b2, and 12c2 may have the same thickness, but the exemplary embodiment is not limited thereto. For example, in a modified example, one of the plurality of second semiconductor layers 12a1, 12b1, and 12c1 may have a thickness different from that of each of the other second semiconductor layers, and one of the plurality of semiconductor channel layers 12a2, 12b2, and 12c2 may have a thickness different from that of each of the other semiconductor channel layers. (Refer to...) Figure 4A and Figure 4B as well as Figure 5A and Figure 5B Describe an example of such a modification.

[0068] In a modified example, refer to Figure 4A and Figure 4B Among the plurality of second semiconductor layers 12a1, 12b1, and 12c1a spaced apart in the vertical direction Z, the uppermost second semiconductor layer 12c1a may have a thickness greater than that of each of the other second semiconductor layers 12a1 and 12b1. Among the plurality of semiconductor channel layers 12a2, 12b2, and 12c2a spaced apart in the vertical direction Z, the uppermost semiconductor channel layer 12c2a may have a thickness greater than that of each of the other semiconductor channel layers 12a2 and 12b2.

[0069] In another modified example, refer to Figure 5A and Figure 5B Among the plurality of second semiconductor layers 12a1, 12b1, and 12c1b spaced apart in the vertical direction Z, the uppermost second semiconductor layer 12c1b may have a thickness smaller than that of each of the other second semiconductor layers 12a1 and 12b1. Among the plurality of semiconductor channel layers 12a2, 12b2, and 12c2b spaced apart in the vertical direction Z, the uppermost semiconductor channel layer 12c2b may have a thickness smaller than that of each of the other semiconductor channel layers 12a2 and 12b2.

[0070] Next, refer to Figure 6 Describe the semiconductor capping layer ( Figure 2A Example of modification for 27) in the text.

[0071] In the modified example, refer to Figure 6 A semiconductor capping layer 27a with increased thickness can be provided. The semiconductor capping layer 27a can overlap with the upper end of the first buffer insulating layer 18a and the upper end of the first insulating liner 19a in the vertical direction Z.

[0072] Next, refer to Figure 7 Describe the fin structure ( Figure 2A Example of modification of 33).

[0073] Reference Figure 7 The fin structure 33a may include a plurality of first semiconductor layers 10a, 10b, 10c, and 10d, and a plurality of second semiconductor layers, alternately stacked on the first lower semiconductor region 6b. Among the alternately stacked plurality of first semiconductor layers 10a, 10b, 10c, and 10d and the plurality of second semiconductor layers, the bottommost layer may be the bottommost first semiconductor layer 10a, and the topmost layer may be the topmost first semiconductor layer 10d.

[0074] Next, the first active region ( Figure 1 and Figure 2A 6a) of the first gate electrode Figure 1 and 2A 45a), source / drain region ( Figure 1 and 2A 40a) and the first isolation layer ( Figure 1 and Figure 2A The example of the modification in 16a) will be referred to Figures 8 to 9 Described. Figure 8 This is a top view illustrating a modified example of a semiconductor device according to an exemplary embodiment. Figure 9 It is along Figure 8 The sectional view taken by lines V-V' and VI-VI' in the figure.

[0075] Reference Figure 8 and Figure 9 A base active region 104 protruding from the semiconductor substrate 103, a plurality of first active regions 106a extending from the base active region 104 in the vertical direction Z, and fin structures 133 extending from the first active regions 106a in the vertical direction Z can be provided. The first active regions 106a can extend in the first direction D1.

[0076] A shallow isolation layer 116a may be disposed on the base active region 104 to define the plurality of first active regions 106a. A deep isolation layer 122 may be disposed to define the base active region 104 and surround the outer side of the shallow isolation layer 116a.

[0077] The shallow isolation layer 116a may include a first shallow isolation portion 116a1 and a second shallow isolation portion 116a2. The first shallow isolation portion 116a1 may contact the deep isolation layer 122 in the second direction D2. The second shallow isolation portion 116a2 may be interposed between the first active regions 106a.

[0078] Each shallow isolation layer 116a may include: a buffer insulation layer 118a that covers the surface of the base active region 104 and extends along the side surface of each first active region 106a; an insulating liner 119a that covers the buffer insulation layer 118a; and a gap-filling insulation layer 120a that covers the insulating liner 119a.

[0079] Fin structures 133 may be disposed on the first active region 106a. Each fin structure 133 may extend from each first active region 106a in the vertical direction Z.

[0080] Each fin structure 133 can be composed of the aforementioned fin structures ( Figure 2A The material is essentially the same as that in 33) and can be formed to have the same fin structure as described above. Figure 2A The structure is essentially the same as that in fin structure 133. Therefore, each fin structure 133 may include the structure described above. Figure 2A The first lower semiconductor region 6b, a plurality of first semiconductor layers 10a, 10b and 10c, a plurality of second semiconductor layers 12a1, 12b1 and 12c1 and a semiconductor capping layer 27 are described.

[0081] Multiple gate structures 145 may be arranged parallel to each other and may overlap with fin structure 133 and extend in the second direction D2. Each of the multiple gate structures 145 may be formed by the first gate structure described above ( Figure 2A The material is substantially the same as that in 45a), and can be formed to have the same structure as the first gate structure described above. Figure 2A The structure is basically the same as that of 45a in the first gate structure. Therefore, since the structure and material of the plurality of gate structures 145 can be obtained from the first gate structure ( Figure 2A 45a) is understood, therefore its detailed description will be omitted.

[0082] The source / drain region 140a can be formed to contact the side surface 33S1 of each fin structure 133 in the first direction D1 on the first active region 106a.

[0083] Similar to the above Figure 2A As described above, the gate cap 43a may be disposed on each of the plurality of gate structures 145, the gate spacer 56a may be disposed on the side surface of each of the plurality of gate structures 145 and on the side surface of the gate cap 43a, the contact plug 62a may be disposed on the source / drain region 140a, and the insulating layer 59a may be disposed between the contact plug 62a and the gate spacer 56a.

[0084] The first shallow isolation portion 116a1 and the second shallow isolation portion 116a2 may have upper surfaces disposed at substantially the same level, but the exemplary embodiment is not limited thereto. For example, the upper surface of the second shallow isolation portion 116a2 may be modified to be disposed at a different level than the upper surface of the first shallow isolation portion 116a1. Examples of such modifications will be referred to Figure 10 Described. Figure 10 It is along Figure 8 A sectional view of lines V-V' and VI-VI' in the diagram.

[0085] In the modified example, refer to Figure 10 The above is in Figure 9 The shallow isolation layer 116a described herein may include a first shallow isolation portion 116a1 and a second shallow isolation portion 116a2', the second shallow isolation portion 116a2' having an upper surface that is positioned at a level lower than the upper surface of the first shallow isolation portion 116a1. Because the upper surface of the second shallow isolation portion 116a2' is positioned lower than the upper surface of the first shallow isolation portion 116a1, the lower end of the fin structure 133 that contacts the second shallow isolation portion 116a2' may be lower than the lower end of the fin structure 133 that contacts the first shallow isolation portion 116a1.

[0086] Next, refer to Figure 1 , Figure 11 and Figures 12A to 14B An example describing a method for forming a semiconductor device according to an exemplary implementation. Figure 11 This is a process flow diagram illustrating a method for forming a semiconductor device according to an exemplary embodiment. Figures 12A to 14B This is a cross-sectional view illustrating stages in a method for forming a semiconductor device according to an exemplary embodiment. Figures 12A to 14B middle, Figure 12A , Figure 13A and Figure 14A Corresponding to along Figure 1 The sectional view taken by lines I-I' and III-III' in the figure. Figure 12B , 13B And 14B corresponds to along Figure 1 The sectional view taken from lines II-II' and IV-IV'.

[0087] Reference Figure 1 , Figure 11 , Figure 12A and Figure 12BA first fin structure and a second fin structure can be formed that protrude from the isolation layers 16a and 16b (S10). Forming the first fin structure and the second fin structure that protrude from the isolation layers 16a and 16b may include: performing an epitaxial growth process on the semiconductor substrate 3 to form a plurality of alternately stacked silicon-germanium layers 10 and a plurality of silicon layers 12; etching the plurality of silicon-germanium layers 10, the plurality of silicon layers 12 and the semiconductor substrate 3 to form the first fin structure and the second fin structure; and forming isolation layers 16a and 16b on the semiconductor substrate 3 to cover the lower side surfaces of the portions of the first fin structure and the second fin structure disposed below the plurality of silicon-germanium layers 10 and the plurality of silicon layers 12.

[0088] Forming isolation layers 16a and 16b may include: after etching the plurality of silicon-germanium layers 10, the plurality of silicon layers 12 and the semiconductor substrate 3 to form the first fin structure and the second fin structure, oxidizing the surface of the semiconductor substrate 3 and the surface of the first fin structure and the second fin structure to form buffer insulating layers 18a and 18b; forming insulating liner layers 19a and 19b to conformally cover the buffer insulating layers 18a and 18b; forming gap-filling insulating layers 20a and 20b on the insulating liner layers 19a and 19b; and etching the gap-filling insulating layers 20a and 20b, the insulating liner layers 19a and 19b and the buffer insulating layers 18a and 18b to expose the upper regions of the first fin structure and the second fin structure.

[0089] The side surfaces of the plurality of silicon-germanium layers 10 may be further recessed than the side surfaces of the plurality of silicon layers 12 while forming the insulating layers 16a and 16b. For example, the side surfaces of the plurality of silicon-germanium layers 10 may be further recessed than the side surfaces of the plurality of silicon layers 12 while thermally oxidizing the plurality of silicon-germanium layers 10 and the plurality of silicon layers 12 to form buffer insulating layers 18a and 18b.

[0090] The first fin structure can be formed in the first transistor region. Figure 1 In the TR1), the second fin structure can be formed in the second transistor region ( Figure 1 In TR2). Set in Figure 1 The isolation layer in the first transistor region TR1 can be defined as the first isolation layer 16a, and is disposed in the second transistor region ( Figure 1 The isolation layer in TR2 can be defined as the second isolation layer 16b.

[0091] Formed in the first transistor region ( Figure 1The first fin structure in the TR1) may include: a first active region 6a having a side surface surrounded by a first isolation layer 16a; a first lower semiconductor region 6b disposed at a level higher than that of the isolation layer 16a; and the plurality of silicon-germanium layers 10 and the plurality of silicon layers 12 formed on the first lower semiconductor region 6b. The first active region 6a and the first lower semiconductor region 6b may be formed simultaneously with etching the semiconductor substrate 3.

[0092] Formed in the second transistor region ( Figure 1 The second fin structure in TR2 may include: a second active region 8a having a side surface surrounded by a second isolation layer 16b; a second lower semiconductor region 8b disposed at a level higher than that of the second isolation layer 16b; and the plurality of silicon-germanium layers 10 and the plurality of silicon layers 12 formed on the second lower semiconductor region 8b. The second active region 8a and the second lower semiconductor region 8b may be formed simultaneously with etching the semiconductor substrate 3.

[0093] In the first fin structure, the portion protruding from the first isolation layer 16a in the vertical direction Z can be defined as the first fin protrusion region 6P. In the second fin structure, the portion protruding from the second isolation layer 16b in the vertical direction Z can be defined as the second fin protrusion region 8P.

[0094] A sacrificial protective layer can be formed to cover the first fin protrusion region 6P of the first fin structure and the second fin protrusion region 8P of the second fin structure. For example, a first sacrificial protective layer 24a, a second sacrificial protective layer 24b, and a third sacrificial protective layer 24c can be formed sequentially to cover the surfaces of the first fin protrusion region 6P and the second fin protrusion region 8P, as well as the surfaces of the first isolation layer 16a and the second isolation layer 16b. The first sacrificial protective layer 24a and the second sacrificial protective layer 24b can be formed, for example, of silicon oxide, and the third sacrificial protective layer 24c can be formed, for example, of silicon nitride.

[0095] Reference Figure 11 , Figure 13A and Figure 13BA sacrificial protective layer can be formed to cover the second fin protrusion region 8P of the second fin structure (S20). For example, the first sacrificial protective layer 24a, the second sacrificial protective layer 24b, and the third sacrificial protective layer 24c on the first isolation layer 16a and the first fin protrusion region 6P can be removed. Then, among the first sacrificial protective layers 24a, 24b, and 24c remaining on the second isolation layer 16b and the second fin protrusion region 8P, the third sacrificial protective layer 24c can be removed. Therefore, the first sacrificial protective layer 24a and the second sacrificial protective layer 24b can be formed to cover the second fin protrusion region 8P of the second fin structure. A semiconductor capping layer 27 can be formed epitaxially grown from the first fin protrusion region 6P of the first fin structure (S30).

[0096] Reference Figure 11 , Figure 14A and Figure 14B The sacrificial protective layer can be removed (S40). Removing the sacrificial protective layer may include removing the first sacrificial protective layer 24a and the second sacrificial protective layer 24b retained on the second isolation layer 16b and the second fin protrusion region 8P.

[0097] Therefore, the first fin protrusion region 6P and the semiconductor capping layer 27 can be formed in the first transistor region TR1, and the second fin protrusion region 8P, which is not covered by the semiconductor capping layer 27, can be formed in the second transistor region TR2. The first fin protrusion region 6P and the semiconductor capping layer 27 can be used to form a reference. Figure 2A The described fin structure ( Figure 2A 33 in the middle).

[0098] In the following text, reference will be made to Figure 15A and Figure 15B This describes a modified example of the method for forming a semiconductor device according to an exemplary implementation.

[0099] In a modified example, refer to Figure 15A and Figure 15B It can form with Figure 12A and Figure 12B The same first and second fin structures are shown in the image. Similarly, as... Figure 12A and Figure 12B As shown, the first fin structure may have a first fin protrusion region 6P protruding from the first isolation layer 16a in the vertical direction Z, and the second fin structure may have a second fin protrusion region 8P protruding from the second isolation layer 16b in the vertical direction Z.

[0100] The sacrificial protective layer 24 can be formed to cover the second fin protrusion region 8P of the second fin structure. A semiconductor capping layer 27, epitaxially grown from the surface of the first fin protrusion region 6P, can be formed while simultaneously protecting the second fin protrusion region 8P of the second fin structure from the epitaxial growth process using the second sacrificial protective layer 24b. The sacrificial protective layer 24 can then be selectively removed. Therefore, a structure can be formed that... Figure 14A The same structure shown in the image.

[0101] Reference Figure 1 , Figure 2A , Figure 2B and Figure 11 The gate and source / drain formation process (S50) can be performed. This process can be executed to form a first gate structure 45a and a second gate structure 45b, as well as a first source / drain region 40a and a second source / drain region 40b, such as... Figure 2A and Figure 2B As shown in the image.

[0102] Forming the first gate structure 45a and the first source / drain region 40a may include: forming a region spanning the first fin protrusion ( Figure 14A and Figure 14B 6P in the middle) and semiconductor capping layer ( Figure 14A and Figure 14B (27) A first material layer 47a_1 and a first sacrificial gate structure are sequentially stacked; a first gate spacer 56a is formed on the side surface of the first sacrificial gate structure; a first fin protrusion region is etched on the opposite side adjacent to the first sacrificial gate structure. Figure 14A and Figure 14B 6P in the middle) and semiconductor capping layer ( Figure 14A and Figure 14B (27) in the middle, to form as Figure 2A The fin structure 33 shown; a first source / drain region 40a is formed on the opposite side adjacent to the fin structure 33; a first insulating layer 59a is formed; the first sacrificial gate structure is removed to form a first gate trench; and a second material layer 47a2 and a first gate electrode 49a are sequentially formed in the first gate trench, as shown. Figure 2A As shown; and a gate capping layer 53a is formed on the first gate electrode 49a, as... Figure 2A As shown. Then, the first contact plug 62a can be formed to penetrate the first insulating layer 59a.

[0103] Forming the second gate structure 45b and the second source / drain region 40b may include: forming a region spanning the second fin protrusion ( Figure 14A and Figure 14BThe first material layer and the second sacrificial gate structure are stacked sequentially in 8P; a second gate spacer 56b is formed on the side surface of the second sacrificial gate structure; a second fin protrusion region is etched on the opposite side adjacent to the second sacrificial gate structure. Figure 14A and Figure 14B (8P in the middle), thus forming a depression to expose the protruding area of ​​the second fin ( Figure 14A and Figure 14B The plurality of silicon-germanium layers (8P) in the middle Figure 14A and Figure 14B 10) and the plurality of silicon layers ( Figure 14A and Figure 14B 12); Form a second source / drain region 40b to fill the depression; Form a second source / drain region 40b; Form a second insulating layer 59b on the second source / drain region 40b; Remove the first material layer and the second sacrificial gate structure to form a second gate trench to expose the second fin protrusion region ( Figure 14A and Figure 14B The plurality of silicon-germanium layers (8P) in the middle Figure 14A and Figure 14B The side surface of 10) in the middle; selectively remove the protruding area of ​​the second fin ( Figure 14A and Figure 14B The plurality of silicon-germanium layers (8P) exposed by the second gate trench ( Figure 14A and Figure 14B 10); in the gate trench and the plurality of silicon-germanium layers ( Figure 14A and Figure 14B In the space where 10) is removed, a third material layer 41b_1, a fourth material layer 47b_2, and a second gate electrode 49b are sequentially formed, as shown in Figure 10. Figure 2B As shown; and a gate capping layer 53b is formed on the second gate electrode 49b, as... Figure 2B As shown. Then, the second contact plug 62b can be formed to penetrate the second insulating layer 59b.

[0104] By summarizing and reviewing, the exemplary embodiments provide semiconductor devices capable of improving electrical characteristics. That is, as described above, according to the exemplary embodiments, semiconductor devices with channel structures having improved electrical characteristics can be provided.

[0105] In other words, according to the example embodiment, the semiconductor device may include an epitaxially grown semiconductor capping layer, such as silicon, on the surface of a fin structure comprising alternating semiconductor layers, such as Si / SiGe, such that the semiconductor capping layer separates the alternating semiconductor layers from their gate electrodes. Thus, the alternating semiconductor layers provide the channel for the high-voltage transistor, while the semiconductor capping layer lies between the alternating semiconductor layers and the gate dielectric material of the high-voltage transistor. Therefore, the semiconductor capping layer prevents direct contact between the gate dielectric material of the high-voltage transistor and the alternating semiconductor layers.

[0106] Exemplary embodiments have been disclosed herein. Although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art at the time of filing of this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

[0107] Korean Patent Application No. 10-2019-0094901, entitled "Semiconductor Device Including Active Region and Gate Structure," filed on August 5, 2019, with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device comprising: a first active region extending from a semiconductor substrate in a vertical direction, the first active region extending in a first direction parallel to an upper surface of the semiconductor substrate; first source / drain regions spaced apart from each other on the first active region in the first direction; a fin structure on the first active region between the first source / drain regions, the fin structure including: a first lower semiconductor region extending from the first active region, a stack structure on the first lower semiconductor region, the stack structure including alternating first semiconductor layers and second semiconductor layers stacked in the vertical direction, a side surface of at least one first semiconductor layer of the alternating first semiconductor layers and second semiconductor layers being recessed toward a respective center in a second direction perpendicular to the first direction, the first semiconductor layers including a material different from a material of the second semiconductor layers, and the first semiconductor layers and the second semiconductor layers adjacent to each other along the vertical direction contacting each other, and a semiconductor cap layer on the stack structure; a first isolation layer covering side surfaces of the first active region on the semiconductor substrate; a first gate structure overlapping the fin structure and extending in the second direction to cover an upper surface of the fin structure and side surfaces of the fin structure in the second direction, the semiconductor cap layer being between the first gate structure and the stack structure and between the first gate structure and the first lower semiconductor region; and first contact plugs electrically connected to the first source / drain regions.

2. The semiconductor device of claim 1, wherein, Among the side surfaces of the fin structure in the second direction, at least one side surface of the fin structure protrudes in the second direction to overlap a portion of the first isolation layer.

3. The semiconductor device according to claim 2, wherein the alternating first semiconductor layers and second semiconductor layers do not overlap the first isolation layer.

4. The semiconductor device according to claim 2, wherein a portion of the semiconductor cap layer covering the first lower semiconductor region overlaps a portion of the first isolation layer.

5. The semiconductor device according to claim 1, wherein the semiconductor cap layer includes: a first portion on an upper surface of an uppermost second semiconductor layer of the alternating first semiconductor layers and second semiconductor layers; and a second portion contacting the first semiconductor layers, a thickness of the first portion in the vertical direction being greater than or equal to twice a thickness of at least one of the second portions in the second direction.

6. The semiconductor device according to claim 1, wherein: the first gate structure includes: a gate dielectric layer contacting an upper surface of the first isolation layer, side surfaces of the fin structure in the second direction, and the upper surface of the fin structure; and a gate electrode on the gate dielectric layer, and the gate dielectric layer has a thickness greater than a thickness of the semiconductor cap layer.

7. The semiconductor device according to claim 1, wherein: The first isolation layer includes: a buffer insulating layer covering side surfaces of the first active region; an insulating liner layer covering the buffer insulating layer; and a gap filling insulating layer covering the insulating liner layer; and Among side surfaces of the fin structure in the second direction, at least one side surface protrudes in the second direction to overlap with an upper end of the buffer insulating layer but not to overlap with an upper surface of the gap filling insulating layer.

8. The semiconductor device according to claim 1, wherein: each of the first semiconductor layers in the alternating first semiconductor layers and second semiconductor layers is formed of silicon germanium, each of the second semiconductor layers in the alternating first semiconductor layers and second semiconductor layers is formed of silicon, among the alternating first semiconductor layers and second semiconductor layers, a lowermost layer is a lowermost first semiconductor layer, an uppermost layer is an uppermost first semiconductor layer, and each of the first semiconductor layers in the alternating first semiconductor layers and second semiconductor layers has a thickness greater than a thickness of the semiconductor cap layer.

9. The semiconductor device according to claim 1, wherein: among the alternating first semiconductor layers and second semiconductor layers, a lowermost layer is a lowermost first semiconductor layer, the first lower semiconductor region is at a level higher than a level of the first isolation layer, the first lower semiconductor region has a thickness greater than a thickness of the lowermost first semiconductor layer, and the first lower semiconductor region has a thickness greater than a thickness of a lowermost second semiconductor layer among the second semiconductor layers in the alternating first semiconductor layers and second semiconductor layers.

10. The semiconductor device according to claim 1, wherein: among the alternating first semiconductor layers and second semiconductor layers, a lowermost layer is a lowermost first semiconductor layer, and among the alternating first semiconductor layers and second semiconductor layers, a maximum thickness of a portion of the semiconductor cap layer covering a side surface of the first lower semiconductor region is different from a minimum thickness of a portion of the semiconductor cap layer covering a side surface of the lowermost first semiconductor layer.

11. The semiconductor device according to claim 1, wherein: among the alternating first semiconductor layers and second semiconductor layers, an uppermost layer is an uppermost second semiconductor layer, among the first semiconductor layers in the alternating first semiconductor layers and second semiconductor layers, an uppermost first semiconductor layer is in contact with and below the uppermost second semiconductor layer, and a portion of the fin structure disposed at a level higher than a level of the uppermost first semiconductor layer has a rounded structure.

12. The semiconductor device according to claim 1, wherein: among the alternating first semiconductor layers and second semiconductor layers, an uppermost layer is an uppermost second semiconductor layer, and among the second semiconductor layers in the alternating first semiconductor layers and second semiconductor layers, the uppermost second semiconductor layer has a thickness different from a thickness of each of other second semiconductor layers.

13. The semiconductor device according to claim 1, wherein: among the first and second semiconductor layers, the uppermost layer is an uppermost first semiconductor layer, and the lowermost layer is a lowermost first semiconductor layer, each of the first semiconductor layers among the first and second semiconductor layers is a silicon layer, and each of the second semiconductor layers among the first and second semiconductor layers is a silicon germanium layer.

14. The semiconductor device according to claim 1, further comprising: a second active region protruding from the semiconductor substrate in the vertical direction and extending in the first direction; a second lower semiconductor region extending from the second active region in the vertical direction; semiconductor channel layers spaced apart from each other in the vertical direction on the second lower semiconductor region; a second isolation layer covering side surfaces of the second active region; a second gate structure extending on the second isolation layer in the second direction to surround the semiconductor channel layers; a second source / drain region extending on the second active region in the vertical direction to contact side surfaces of the semiconductor channel layers in the first direction; and a second contact plug electrically connected to the second source / drain region, wherein the first gate structure includes a first gate dielectric layer and a first gate electrode on the first gate dielectric layer, the second gate structure includes a second gate dielectric layer and a second gate electrode on the second gate dielectric layer, and the first gate dielectric layer has a thickness greater than a thickness of the second gate dielectric layer.

15. A semiconductor device, comprising: an isolation layer defining an active region on a semiconductor substrate, the active region extending in a first direction parallel to an upper surface of the semiconductor substrate; source / drain regions on the active region; fin structures extending from the active region in a vertical direction between the source / drain regions, the vertical direction being perpendicular to the upper surface of the semiconductor substrate, and the source / drain regions contacting side surfaces of the fin structures in the first direction; and a gate structure overlapping the fin structures and extending upward from the isolation layer, the gate structure covering side surfaces of the fin structures in a second direction perpendicular to the first direction and an upper surface of the fin structures; wherein the fin structures include: a lower semiconductor region extending from the active region in the vertical direction, a stack structure on the lower semiconductor region, the stack structure including alternating first and second semiconductor layers stacked in the vertical direction, the first semiconductor layers including a material different from a material of the second semiconductor layers, and the first and second semiconductor layers adjacent to each other in the vertical direction contacting each other, and a semiconductor cap layer including a portion between at least the gate structure and the stack structure, and among side surfaces of the fin structures, at least one side surface overlaps a portion of the isolation layer.

16. The semiconductor device according to claim 15, wherein: ​ among the first semiconductor layers and the second semiconductor layers that are alternately stacked, an uppermost layer is an uppermost second semiconductor layer, among the first semiconductor layers and the second semiconductor layers that are alternately stacked, an uppermost first semiconductor layer is in contact with the uppermost second semiconductor layer and is below the uppermost second semiconductor layer; and a portion of the fin structure that is disposed at a level higher than that of the uppermost first semiconductor layer has a thickness greater than a width in the second direction in the vertical direction.

17. A semiconductor device comprising: shallow isolation layers that define active regions on a semiconductor substrate, each of the active regions extending in a first direction parallel to an upper surface of the semiconductor substrate; source / drain regions on the active regions; fin structures that extend from the active regions in a vertical direction perpendicular to the upper surface of the semiconductor substrate, the source / drain regions being in contact with side surfaces of the fin structures in the first direction; and gate structures that overlap the fin structures and extend upward from the shallow isolation layers, the gate structures covering side surfaces of the fin structures in a second direction and upper surfaces of the fin structures, the second direction being perpendicular to the first direction; wherein each of the fin structures includes: lower semiconductor regions that extend from respective ones of the active regions in the vertical direction, a stacked structure of first semiconductor layers and second semiconductor layers that are alternately stacked in the vertical direction, the first semiconductor layers including a material different from that of the second semiconductor layers, the first semiconductor layers and the second semiconductor layers that are adjacent to each other in the vertical direction being in contact with each other, and surfaces of the first semiconductor layers in the second direction being further recessed toward respective centers than side surfaces of the second semiconductor layers in the second direction, and a central portion of at least one of the first semiconductor layers having a width in the second direction that is smaller than that of each of an upper portion and a lower portion thereof, and a semiconductor cap layer that covers side surfaces of the stacked structure in the second direction.

18. The semiconductor device according to claim 17, further comprising: base active regions that extend from the semiconductor substrate in the vertical direction; and deep isolation layers that define the base active regions on the semiconductor substrate, the active regions extending from the base active regions in the vertical direction, and the shallow isolation layers defining the active regions on the base active regions.

19. The semiconductor device according to claim 18, wherein: the shallow isolation layers include: gap-fill insulating layers; buffer insulating layers that cover side surfaces and a lower surface of the gap-fill insulating layers; and insulating liner layers interposed between the gap-fill insulating layers and the buffer insulating layers; and the insulating liner layers are formed of a material different from that of the gap-fill insulating layers and that of the buffer insulating layers.

20. The semiconductor device according to claim 19, wherein: the shallow isolation layer includes first shallow isolation portions and second shallow isolation portions between the first shallow isolation portions, the first shallow isolation portions are adjacent to or in contact with the deep isolation layer in the second direction, the second shallow isolation portions are between the active regions, and upper surfaces of the second shallow isolation portions adjacent to the active regions are lower than upper surfaces of the first shallow isolation portions adjacent to the deep isolation layer.

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