Method for Si gap filling by PECVD

Abstract

Embodiments of the present disclosure relate to a process for filling a trench. The process includes depositing a first amorphous silicon layer on a surface of a layer and depositing a second amorphous silicon layer in a portion of a trench formed in the layer, and a portion of a sidewall of the trench is exposed. The first amorphous silicon layer is removed. The process further includes depositing a third amorphous silicon layer on the surface of the layer and depositing a fourth amorphous silicon layer on the second amorphous silicon layer. The third amorphous silicon layer is removed. The deposition / removal cycle process may be repeated until the trench is filled with the amorphous silicon layer. Since the amorphous silicon layer is formed from the bottom up, the amorphous silicon layer forms a seamless amorphous silicon gap fill in the trench.

Description

Background Art

[0001] field

[0002] Embodiments of the present disclosure relate to methods of forming a gap-fill material on a substrate.

[0003] Related technical notes

[0004] In semiconductor processing, devices are being manufactured with ever-decreasing feature sizes. Typically, features used to manufacture devices at these advanced technology nodes include high aspect ratio structures, and gaps between high aspect ratio structures often need to be filled with gap fill materials, such as insulating materials. Examples of using insulating materials for gap fill applications include shallow trench isolation (STI), intermetallic dielectric layers (ILD), premetal dielectrics (PMD), passivation layers, patterning applications, etc. As device geometries shrink and thermal budgets decrease, void-free filling of high aspect ratio spaces becomes increasingly difficult due to limitations of existing deposition processes.

[0005] The gap fill material can be deposited by various deposition processes, such as flowable chemical vapor deposition (FCVD). The gap fill material deposited by FCVD is generally of poor quality, characterized by a high wet etch rate ratio (WERR) and high stress, and requires subsequent processes, such as curing and / or annealing, to improve the quality of the gap fill material.

[0006] Therefore, there is a need for improved processes for forming gap fill materials. Summary of the invention

[0007] Embodiments of the present disclosure relate to methods of forming a gap fill material on a substrate. In one embodiment, the method includes: heating a substrate disposed in a process chamber to a temperature in a range of about 150 degrees Celsius to about 650 degrees Celsius; flowing a silane-containing precursor into the process chamber; and depositing a first amorphous silicon layer on a bottom of a feature formed in the substrate and a second amorphous silicon layer on a surface of the substrate. A first portion of each sidewall of the feature is in contact with the first amorphous silicon layer, and a second portion of each sidewall is exposed. The method further includes removing the second amorphous silicon layer.

[0008] In another embodiment, a method includes: heating a substrate disposed in a process chamber to a temperature in a range of about 200 degrees Celsius to about 550 degrees Celsius; flowing silane or disilane into the process chamber; forming a plasma in the process chamber; and depositing a first amorphous silicon layer on a bottom of a feature formed in the substrate and a second amorphous silicon layer on a surface of the substrate. A first portion of each sidewall of the feature is in contact with the first amorphous silicon layer, and a second portion of each sidewall is exposed.

[0009] In another embodiment, a method includes depositing a first amorphous silicon layer on a bottom of a feature formed in a substrate and depositing a second amorphous silicon layer on a surface of the substrate. A first portion of each sidewall of the feature is in contact with the first amorphous silicon layer, and a second portion of each sidewall is exposed. Depositing the first amorphous silicon layer and the second amorphous silicon layer includes heating the substrate disposed in a process chamber to a temperature in a range of about 150 degrees Celsius to about 650 degrees Celsius; and flowing a silane-containing precursor into the process chamber. The method further includes removing the second amorphous silicon layer; and repeating the depositing of the first amorphous silicon layer and the second amorphous silicon layer and removing the second amorphous silicon layer until the feature is filled with amorphous silicon. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description of the present disclosure briefly summarized above may be given by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the present disclosure and are therefore not to be considered as limiting its scope, as the present disclosure may allow for other equally effective embodiments.

[0011] Figures 1A to 1F A process for forming a gap-fill material on a substrate according to one embodiment described herein is schematically illustrated.

[0012] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation thereto. DETAILED DESCRIPTION

[0013] Embodiments of the present disclosure relate to a process for filling a trench. The process includes depositing a first amorphous silicon layer on a surface of a layer and depositing a second amorphous silicon layer in a portion of a trench formed in the layer, and a portion of a sidewall of the trench is exposed. The first amorphous silicon layer is removed. The process further includes depositing a third amorphous silicon layer on the surface of the layer and depositing a fourth amorphous silicon layer on the second amorphous silicon layer. The third amorphous silicon layer is removed. The deposition / removal cycle process may be repeated until the trench is filled with the amorphous silicon layer. Since the amorphous silicon layer is formed from the bottom up, the amorphous silicon layer forms a seamless amorphous silicon gap fill in the trench.

[0014] As used herein, "substrate" refers to any substrate or a material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, depending on the application, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire and any other material (such as metal, metal nitride, metal alloy and other conductive materials). Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal and / or bake the substrate surface. In addition to the film processing performed directly on the surface of the substrate, any of the disclosed film processing steps may also be performed on an under-layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such an under-layer as indicated by the context. Thus, for example, when a film / layer or a portion of a film / layer has been deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015] Figures 1A to 1F Schematically illustrates a process for forming a gap filling material on a substrate according to one embodiment described herein. Figure 1A As shown, substrate 100 includes feature 102. For illustrative purposes, the figures show a substrate with a single feature; however, those skilled in the art will appreciate that there may be more than one feature. The shape of feature 102 may be any suitable shape, including but not limited to grooves and cylindrical vias. As used in this regard, the term "feature" means any intentional surface irregularity. Suitable examples of features include but are not limited to grooves and vias having a bottom and two sidewalls. The feature may have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to approximately 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1.

[0016] Substrate 100 includes surface 101, and feature 102 is an opening formed in surface 101. In one embodiment, substrate 100 includes an STI region made of a dielectric material such as silicon oxide or silicon nitride, and feature 102 is formed in the STI region. Feature 102 includes a bottom 104 and sidewalls 106. Next, as shown in FIG. Figure 1B As shown, a first amorphous silicon layer 108 is deposited on the bottom 104 of the feature 102, and a second amorphous silicon layer 110 is deposited on the surface 101 of the substrate 100. The first amorphous silicon layer 108 and the second amorphous silicon layer 110 are deposited by a plasma enhanced chemical vapor deposition (PECVD) process.

[0017] In one embodiment, the PECVD process for depositing the first amorphous silicon layer 108 and the second amorphous silicon layer 110 includes flowing a silicon-containing precursor into a process chamber and forming a plasma in the process chamber. In one embodiment, the process chamber is a PECVD process available from Applied Materials Inc., Santa Clara, California. XP Precision TM The plasma may be formed in situ or at a remote location and then flowed into the process chamber. The silicon-containing precursor may be a silane-containing precursor, such as silane, disilane, trisilane, or butasilane. In one embodiment, the silicon-containing precursor is a low-order silane-containing precursor, such as silane or disilane. The plasma power density is about 0.14 W / cm 2 to about 2.83W / cm 2 The process temperature (i.e., the substrate temperature during the process) is in the range of about 150 degrees Celsius to about 650 degrees Celsius, for example, 200 degrees Celsius to about 550 degrees Celsius. It has been found that when a silane-containing precursor (such as a low-order silane-containing precursor) is used under the process conditions mentioned above, the deposited first amorphous silicon layer 108 and the second amorphous silicon layer 110 are non-flowable. Since the first amorphous silicon layer 108 and the second amorphous silicon layer 110 are non-flowable, the material is not disposed on the sidewall 106 during the deposition process, reducing the possibility of bridging of the sidewall material (and corresponding void formation). Compared with a flowable amorphous silicon layer, the deposited first amorphous silicon layer 108 and the second amorphous silicon layer 110 have improved quality. In addition, no subsequent curing and / or annealing process is required.

[0018] Unlike a conformal layer formed by an atomic layer deposition (ALD) process, which mostly or completely covers the sidewalls 106 during deposition, a first amorphous silicon layer 108 is formed on the bottom 104 of the feature 102 and in contact with a first portion 112 of each sidewall 106. A second portion 114 of each sidewall 106 is exposed and not covered by the first amorphous silicon layer 108. Similarly, a second amorphous silicon layer 110 formed simultaneously with the first amorphous silicon layer 108 is formed on the surface 101, but not on the second portion 114 of each sidewall 106 of the feature 102. The first amorphous silicon layer 108 and the second amorphous silicon layer 110 are formed on the bottom 104 and the surface 101, respectively, and the bottom 104 is substantially parallel to the surface 101. Therefore, the first amorphous silicon layer 108 and the second amorphous silicon layer 110 are formed on substantially parallel surfaces and have approximately the same thickness or approximately the same thickness. In other words, the first amorphous silicon layer 108 and the second amorphous silicon layer 110 are formed on horizontal surfaces but not on vertical surfaces. The only covered portion of the sidewall 106 (vertical surface) is the portion corresponding to the thickness of the first amorphous silicon layer 108 disposed on the bottom 104.

[0019] Next, if Figure 1C As shown, the second amorphous silicon layer 110 is removed from the surface 101. The removal process may be a plasma etching process performed in the same process chamber as the process chamber in which the first amorphous silicon layer 108 and the second amorphous silicon layer 110 are formed. The chamber pressure of the plasma etching process may be the same as the chamber pressure during the PECVD process or different from the chamber pressure during the PECVD process. The process temperature may be the same process temperature as the PECVD process for depositing the first amorphous silicon layer 108 and the second amorphous silicon layer 110. Utilizing the same process temperature in the deposition and etching processes facilitates rapid transitions between the deposition process and the etching process, which increases substrate throughput. The plasma power density is approximately 0.14 W / cm 2 to about 2.83W / cm 2In the range of . Under the process conditions mentioned above, the second amorphous silicon layer 110 is removed without substantially affecting the first amorphous silicon layer 108, because the plasma ions lose energy due to collisions with the sidewalls 106, the free radicals are quenched / lost before reaching the bottom 104, and / or the plasma power density is controlled to minimize the ion bombardment of the bottom 104. The etchant used for the removal process may be any suitable etchant. In one embodiment, the removal process is a physical plasma etching process, and the etchant used is helium. In another embodiment, the removal process is a chemical plasma etching process using a halogen-containing etchant (such as a fluorine- or chlorine-containing etchant or hydrogen as an etchant), and the plasma is formed remotely. The halogen-containing etchant and hydrogen have a high selectivity for etching amorphous silicon over the material (e.g., silicon oxide) of the substrate 100. In yet another embodiment, the removal process is a physical and chemical plasma etching process using a halogen-containing etchant or hydrogen as an etchant, and the plasma is formed in situ, such as a capacitively coupled plasma.

[0020] After removing the second amorphous silicon layer 110, a second PECVD process is performed to form a third amorphous silicon layer 116 on the first amorphous silicon layer 108 and a fourth amorphous silicon layer 118 on the surface 101. Figure 1D As shown. The second PECVD process may be performed under the same process conditions as the PECVD process used to form the first amorphous silicon layer 108 and the second amorphous silicon layer 110. The third amorphous silicon layer 116 contacts the portion 120 of each sidewall 106, and the portion 122 of each sidewall 106 is exposed. The third amorphous silicon layer 116 and the fourth amorphous silicon layer 118 have the same properties as the first amorphous silicon layer 108 and the second amorphous silicon layer 110, respectively.

[0021] like Figure 1E As shown, the fourth amorphous silicon layer 118 is removed from the surface 101. The removal process may be the same as the removal process used to remove the second amorphous silicon layer 110. In one embodiment, the feature 102 is filled with the first amorphous silicon layer 108 and the third amorphous silicon layer 116. In other words, the entire bottom 104 is in contact with the first amorphous silicon layer 108, and the entire sidewall 106 is in contact with the first amorphous silicon layer 108 and the third amorphous silicon layer 116. In other embodiments, additional deposition / removal cycles may be performed to fill the feature 102. In one embodiment, as shown in FIG. Figure 1FAs shown, additional amorphous silicon layers 124, 126, 128 are deposited on the third amorphous silicon layer 116, and no amorphous silicon layer remains on the surface 101 because each deposition process is followed by a removal process. Because the power of the plasma used for the removal process is low, ion bombardment into the feature 102 is minimized. In addition, at the last deposition process of the deposition / removal cycle, the feature 102 is overfilled, and the last removal process removes the amorphous silicon layer on the surface 101 and above the feature 102. For each deposition / removal cycle (a cycle includes one deposition process and one removal process), the ratio of the deposition time to the etching time can be in the range of about 1 to 3 to about 1 to 15. In such examples, the etching time is substantially longer than the deposition time. The number of cycles depends on the depth of the feature 102 and / or the thickness of each amorphous silicon layer deposited in the feature 102. In one embodiment, the number of deposition / removal cycles is in the range of about 50 to about 200, and the thickness of each amorphous silicon layer formed during the corresponding deposition cycle is between about 250 angstroms and about 1000 angstroms. The plurality of amorphous silicon layers 108, 116, 124, 126, 128 formed in the feature 102 are formed from the bottom up. Therefore, no seams or gaps are formed in the amorphous silicon layers 108, 116, 124, 126, 128.

[0022] By using a deposition / removal cycle process, features (such as trenches) can be seamlessly filled from bottom to top. In addition, since the amorphous silicon layer formed in the features is non-flowable, the quality of the amorphous silicon layer is improved compared to conventional flowable amorphous silicon gap fill. In addition, subsequent curing and / or annealing processes that are typically performed after forming the flowable amorphous silicon gap fill are not necessary.

[0023] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments may be envisaged without departing from the basic scope of the present disclosure, and the scope of the embodiments is to be determined by the claims that follow.

Claims

1. A method comprising: heating a substrate disposed in a process chamber to a temperature in a range of 150 degrees Celsius to 650 degrees Celsius; flowing a silicon-containing precursor into the process chamber; depositing a first amorphous silicon layer on a bottom of a feature formed in the substrate and depositing a second amorphous silicon layer on a surface of the substrate, a first portion of each sidewall of the feature being in contact with the first amorphous silicon layer and a second portion of each sidewall being exposed; as well as removing the second amorphous silicon layer; The first amorphous silicon layer and the second amorphous silicon layer are deposited by a plasma enhanced chemical vapor deposition process, and the plasma power density of the plasma enhanced chemical vapor deposition process is 0.14 W / cm 2 Up to 2.83W / cm 2 within the range. 2 . The method of claim 1 , further comprising depositing a third amorphous silicon layer on the first amorphous silicon layer, and depositing a fourth amorphous silicon layer on the surface of the substrate. The method of claim 2 , further comprising removing the fourth amorphous silicon layer.

4. The method according to claim 1, characterized in that The silicon-containing precursor includes a silane precursor.

5. The method according to claim 4, characterized in that The silane precursor is silane or disilane.

6. The method according to claim 1, characterized in that The depositing and the removing are performed in a single process chamber.

7. The method according to claim 1, characterized in that The removing of the second amorphous silicon layer includes a plasma etching process.

8. The method according to claim 7, characterized in that The plasma etching process utilizes hydrogen as an etchant.

9. The method according to claim 7, characterized in that The plasma power density of the plasma etching process is 0.14W / cm 2 Up to 2.83W / cm 2 within the range.

10. A method comprising: heating a substrate disposed in a process chamber to a temperature in a range of 200 degrees Celsius to 550 degrees Celsius; flowing silane or disilane into the process chamber; forming a plasma in the process chamber; as well as depositing a first amorphous silicon layer on a bottom of a feature formed in the substrate, the feature having one or more sidewalls, the first amorphous silicon layer contacting a first portion of each sidewall of the feature, and a second portion of each sidewall being exposed; The plasma power density is 0.14W / cm 2 Up to 2.83W / cm 2 within the range.

11. The method according to claim 10, characterized in that The first amorphous silicon layer is deposited to a thickness of 250 angstroms to 1000 angstroms.

12. A method comprising: Depositing a first amorphous silicon layer on a bottom of a feature formed in a substrate and depositing a second amorphous silicon layer on a surface of the substrate, a first portion of each sidewall of the feature being in contact with the first amorphous silicon layer and a second portion of each sidewall being exposed, the depositing the first amorphous silicon layer and the second amorphous silicon layer comprising: heating the substrate disposed in a process chamber to a temperature in a range of 150 degrees Celsius to 650 degrees Celsius; and flowing a silane precursor into the process chamber; removing the second amorphous silicon layer; and Repeating the depositing of the first amorphous silicon layer and the second amorphous silicon layer, and removing the second amorphous silicon layer, until the feature is filled with amorphous silicon; The first amorphous silicon layer and the second amorphous silicon layer are deposited by a plasma enhanced chemical vapor deposition process, and the plasma power density of the plasma enhanced chemical vapor deposition process is 0.14 W / cm 2 Up to 2.83W / cm 2 within the range.

13. The method according to claim 12, characterized in that The first amorphous silicon layer and the second amorphous silicon layer are formed simultaneously.

14. The method according to claim 13, characterized in that The surface of the substrate is external to the feature.

15. The method according to claim 12, characterized in that The removing of the second amorphous silicon layer includes an etching process.

16. The method according to claim 15, characterized in that A ratio of a deposition time during the depositing of the first amorphous silicon layer and the second amorphous silicon layer to an etching time during the etching process is in a range of 1:3 to 1:15.

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