Semiconductor device including vias and wirings

Abstract

A semiconductor device is provided. The semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via hole between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposite to each other, the upper wiring has a third end surface and a fourth end surface opposite to each other, and the via hole has a first side surface adjacent to the second end surface of the lower wiring and a second side surface adjacent to the third end surface of the upper wiring. The distance between the lower end of the first side surface of the via hole and the upper end of the second end surface of the lower wiring is less than 1 / 3 of the width of the top surface of the via hole, and the distance between the upper end of the second side surface of the via hole and the upper end of the third end surface of the upper wiring is less than 1 / 3 of the width of the top surface of the via hole.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0096700, filed on Aug. 8, 2019, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including vias and wirings and a method of forming the semiconductor device. Background Art

[0003] As the demand for high performance, high speed, and / or multi-functionality of semiconductor devices increases, the integration degree of semiconductor devices also increases. According to the trend of higher integration of semiconductor devices, the size of transistors has generally been reduced. As a result, the size of wirings electrically connected to transistors having a reduced size can also be reduced. Summary of the Invention

[0004] One aspect of the present inventive concept is to provide a semiconductor device having an improved integration degree.

[0005] One aspect of the present inventive concept is to provide a semiconductor device having improved reliability.

[0006] According to some embodiments of the inventive concept, a semiconductor device includes a lower structure, a first structure on the lower structure, and a second structure on the first structure. The lower structure includes: source / drain regions and a gate electrode; on a semiconductor substrate; an insulating layer on the source / drain regions and the gate electrode; and a contact plug electrically connected to one of the source / drain regions and the gate electrode while penetrating the insulating layer. The first structure includes: a first via electrically connected to the contact plug; a first wiring electrically connected to the first via; and a first insulating structure defining a side surface of the first via and a side surface of the first wiring. The first insulating structure includes: a first lower etch stop layer; a first lower insulating layer on the first lower etch stop layer; a first upper etch stop layer on the first lower insulating layer; and a first upper insulating layer on the first upper etch stop layer. The first lower etch stop layer and the first lower insulating layer define the side surface of the first via. The first upper etch stop layer and the first upper insulating layer define the side surface of the first wiring. The first wiring has a first end surface and a second end surface opposite to each other. The first via has a first side surface adjacent to the first end surface of the first wiring and a second side surface opposite to the first side surface. The second structure includes: a second via; a second wiring; provided on the second via and electrically connected to the second via; and a second insulating structure defining a side surface of the second via and a side surface of the second wiring. The second insulating structure includes a second etch stop layer and a second insulating layer on the second etch stop layer. The second insulating layer defines the side surface of the second wiring and extends onto the side surface of the second via. The second wiring has a third end surface and a fourth end surface opposite to each other. The third end surface of the second wiring is closer to the second via than the fourth end surface of the second wiring. The second via has a third side surface adjacent to the second end surface of the first wiring and a fourth side surface adjacent to the third end surface of the second wiring. A distance between an upper end of the first side surface of the first via and a lower end of the first end surface of the first wiring is less than a distance between a lower end of the third end surface of the second wiring and an upper end of the fourth side surface of the second via.

[0007] According to some embodiments of the inventive concept, a semiconductor device includes: a first via hole on a semiconductor substrate; a first wiring disposed on the first via hole and electrically connected to the first via hole; a second via hole disposed on the first wiring and electrically connected to the first wiring; a second wiring disposed on the second via hole and electrically connected to the second via hole; a third via hole disposed on the second wiring and electrically connected to the second wiring; and a third wiring disposed on the third via hole and electrically connected to the third via hole. The first wiring has a first end surface and a second end surface opposite to each other. The second wiring has a third end surface and a fourth end surface opposite to each other. The third wiring has a fifth end surface and a sixth end surface opposite to each other. The first via hole has a first side surface adjacent to the first end surface and a second side surface opposite to the first side surface. The second via hole has a third side surface adjacent to the second end surface of the first wiring and a fourth side surface adjacent to the third end surface of the second wiring. The third via hole has a fifth side surface adjacent to the fourth end surface of the second wiring and a sixth side surface adjacent to the fifth end surface of the third wiring. A distance between an upper end of the first side surface of the first via hole and a lower end of the first end surface of the first wiring is less than a distance between an upper end of the fourth end surface of the second wiring and a lower end of the fifth side surface of the third via hole.

[0008] According to some embodiments of the inventive concept, a semiconductor device includes: a lower wiring on a semiconductor substrate; an upper wiring on the lower wiring; and a via hole between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposite to each other. The upper wiring has a third end surface and a fourth end surface opposite to each other. The via hole has a first side surface adjacent to the second end surface of the lower wiring and a second side surface adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side surface of the via hole and an upper end of the second end surface of the lower wiring is less than 1 / 3 of a width of a top surface of the via hole. A distance between an upper end of the second side surface of the via hole and an upper end of the third end surface of the upper wiring is less than 1 / 3 of a width of a top surface of the via hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features, and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a plan view showing a part of components of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0011] Figure 2 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0012] Figure 3A is a view showing Figure 2 an enlarged view of part “A”;

[0013] Figure 3B is an enlarged view showing part “B” Figure 2 ;

[0014] Figure 4A is a partially enlarged view showing a modified example of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0015] Figure 4B is a partially enlarged view showing a modified example of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0016] Figure 4C is a partially enlarged view showing a modified example of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0017] Figure 5 is a cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0018] Figure 6 is a partially enlarged view showing a modified example of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0019] Figure 7 is a cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment;

[0020] Figure 8 is a partially enlarged view showing a modified example of a semiconductor device according to an exemplary embodiment;

[0021] Figure 9 is a cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment;

[0022] Figure 10 is a partially enlarged view showing a modified example of a semiconductor device according to an exemplary embodiment; and

[0023] Figures 11 to 13 is a cross-sectional view showing an example of a method of forming a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION

[0024] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown. Throughout the specification, the same reference numerals or the same reference signs may denote the same elements or components.

[0025] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "on," "attached" to, "connected" to, "coupled" with, "contacting" another element, etc., the element can be directly on, directly attached to, coupled to, directly coupled with, or directly contacting the other element, or intervening elements may also be present. In contrast, when an element is referred to as being, for example, "directly on," "directly attached" to, "directly connected" to, "directly coupled" with, or "directly contacting" another element, no intervening elements are present. Note that aspects described with respect to one embodiment may be incorporated into different embodiments, even though not specifically described with respect thereto. That is, all embodiments and / or features of any embodiment can be combined in any way and / or combination.

[0026] Hereinafter, terms such as "first," "second," "third," etc. may be used to describe various components, but the components are not limited by the terms. The terms are only used to distinguish one component from another. For example, without departing from the scope of the inventive concept, a "first component" may be referred to as a "second component."

[0027] First, reference will be made to Figure 1 , Figure 2 , Figure 3A and Figure 3B to describe a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 1 is a plan view showing components of a semiconductor device according to an exemplary embodiment of the inventive concept, Figure 2 is a cross-sectional view taken along lines I-I' and II-II' of Figure 1 , Figure 3A is an enlarged view of a portion denoted by "A" of Figure 2 , Figure 3B is an enlarged view of a portion denoted by "B" of Figure 2 .

[0028] Referring to Figure 1 , Figure 2 , Figure 3A and Figure 3B , a semiconductor device 1 according to an exemplary embodiment of the inventive concept may include a lower structure 3, a first structure 40 on the lower structure 3, a second structure 62 on the first structure 40, and a third structure 103 on the second structure 62.

[0029] The lower structure 3 may include a semiconductor substrate 5 and isolation regions 9s that define active regions 9a on the semiconductor substrate 5. The isolation regions 9s may be shallow trench isolation regions. The lower structure 3 may further include: gate structures (12, 18, 20) that are stacked with the lower structure 3, the first structure 40, the second structure 62, and the third structure 103 in a direction parallel to the stacking direction thereof, and overlap with the active regions 9a and extend over the isolation regions 9s; and source / drain regions 23 that are disposed in the active regions 9a and are adjacent to the gate structures (12, 18, 20). The gate structures (12, 18, 20) may include a gate 12 and an insulating capping layer 18 that are sequentially stacked and insulating spacers 20 on the side surfaces of the gate 12 and the insulating capping layer 18. The gate 12 may include a gate electrode 16 and a gate dielectric 14, and the gate dielectric 14 is on the side surface and the bottom surface of the gate electrode 16 and at least partially covers the side surface and the bottom surface of the gate electrode 16. Accordingly, a transistor 10 including the source / drain regions 23 and the gate 12 can be provided. The transistor 10 may be a three-dimensional transistor, such as a FinFET, but embodiments of the transistor 10 are not limited thereto. For example, the transistor 10 may be a transistor including nanowires, or may be a transistor including nanosheets, for example, a multi-bridge channel FET

[0030] The lower structure 3 may further include interlayer insulating layers 26 and 29 on the gate structures (12, 18, 20) and at least partially covering the gate structures (12, 18, 20). The interlayer insulating layers (26 and 29) may include a first interlayer insulating layer 26 on the isolation regions 9s and the active regions 9a and a second interlayer insulating layer 29 on the first interlayer insulating layer 26. In an example, the second interlayer insulating layer 29 may be on the upper portion of the insulating capping layer 18 and at least partially cover the upper portion of the insulating capping layer 18.

[0031] The lower structure 3 may further include contact plugs 33. Each of the contact plugs 33 may include a plug pattern 37 and a barrier layer 35, and the barrier layer 35 is on the side surface and the bottom surface of the plug pattern 37 and at least partially covers the side surface and the bottom surface of the plug pattern 37.

[0032] Any one of the contact plugs 33 penetrates an insulating layer on the source / drain regions 23 and the gate electrode 16 and at least partially covers the source / drain regions 23 and the gate electrode 16, and may be electrically connected to one of the source / drain regions 23 and the gate electrode 16. For example, the contact plugs 33 may include: a gate contact plug 33a that penetrates the second interlayer insulating layer 29 and the insulating capping layer 18 and is electrically connected to the gate electrode 16; and a source / drain contact plug 33b that penetrates the first interlayer insulating layer 26 and the second interlayer insulating layer 29 and is electrically connected to the source / drain regions 23.

[0033] The first structure 40 may include a first via 47, a first wiring 57 electrically connected to the first via 47, and a first insulating structure 42 that defines or surrounds side surfaces of the first via 47 and the first wiring 57.

[0034] The first via 47 may include a first via gap-fill pattern 51 and a first via barrier layer 49. The first via barrier layer 49 is on side and bottom surfaces of the first via gap-fill pattern 51 and at least partially covers the side and bottom surfaces of the first via gap-fill pattern 51. The first wiring 57 may include a first wiring gap-fill pattern 61 and a first wiring barrier layer 59. The first wiring barrier layer 59 is on side and bottom surfaces of the first wiring gap-fill pattern 61 and at least partially covers the side and bottom surfaces of the first wiring gap-fill pattern 61. The first wiring barrier layer 59 may have a portion disposed between the first wiring gap-fill pattern 61 and the first via gap-fill pattern 51.

[0035] In an example, each of the first via barrier layer 49 and the first wiring barrier layer 59 may include one or more materials including but not limited to titanium (Ti), tantalum (Ta), cobalt (Co), TiN, and / or TaN. However, example embodiments are not limited to these types of materials, and these materials may be supplemented and / or replaced with other conductive materials. In an example, each of the first via gap-fill pattern 51 and the first wiring gap-fill pattern 61 may include one or more materials including but not limited to aluminum (Al), copper (Cu), and / or tungsten (W). However, example embodiments are not limited to these materials, and may be supplemented and / or replaced with other conductive materials.

[0036] The first insulating structure 42 may include a first lower etch stop layer 43, a first lower insulating layer 45 on the first lower etch stop layer 43, a first upper etch stop layer 53 on the first lower insulating layer 45, and a first upper insulating layer 55 on the first upper etch stop layer 53.

[0037] The first lower etch stop layer 43 and the first lower insulating layer 45 may define or surround side surfaces of the first via 47. The first upper etch stop layer 53 and the first upper insulating layer 55 may define or surround side surfaces of the first wiring 57.

[0038] In an example, the first lower etch stop layer 43 and the first upper etch stop layer 53 may be formed of a high-k dielectric material. The high-k dielectric material may include silicon nitride and / or aluminum oxide.

[0039] In an example, the first lower insulating layer 45 and the first upper insulating layer 55 may be formed of silicon oxide and / or a low-k dielectric material. The low-k dielectric material may include SiOC material.

[0040] The first wiring 57 may have a first end surface 57S1 and a second end surface 57S2 opposite to each other. The first via 47 may have a first side surface 47S1 adjacent to the first end surface 57S1 of the first wiring 57 and a second side surface 47S2 opposite to the first side surface 47S1.

[0041] In an example, the length of the first wiring 57 may be about 50 times or less the width of the first via 47. In an example, the length of the first wiring 57 may be about 40 times or less the width of the first via 47.

[0042] In an example, the length of the first wiring 57 may be the length measured along the distance between the first end surface 57S1 and the second end surface 57S2, and the width of the first via 47 may be the distance between the first side surface 47S1 and the second side surface 47S2.

[0043] In an example, in the case of the first via 47, the width W2 of the lower surface may be less than the width W1 of the top surface. Accordingly, the first side surface 47S1 and the second side surface 47S2 of the first via 47 may be inclined. In the case of the first wiring 57, the first end surface 57S1 and the second end surface 57S2 may be inclined. For example, in the first wiring 57, an acute angle may be formed between the top surface of the first wiring 57 and the first end surface 57S1, and an acute angle may be formed between the top surface of the first wiring 57 and the second end surface 57S2. Thus, in the first wiring 57, when viewed in a Figure 2 cross-sectional view, the width of the top surface in the horizontal direction may be greater than the width of the lower surface in the horizontal direction. The length of the top surface of the first wiring 57 may be about 50 times or less the width of the top surface of the first via 47.

[0044] In an example, the first side surface 47S1 of the first via 47 and the first end surface 57S1 of the first wiring 57 may be stacked in the vertical direction (i.e., in a direction parallel to the direction in which the lower structure 3, the first structure 40, the second structure 62, and the third structure 103 are stacked). The vertical direction may also be regarded as a direction perpendicular to the top surface of the first wiring 57.

[0045] The second structure 62 may include a second via 69, a second wiring 79 disposed on the second via 69 and electrically connected to the second via 69, and a second insulating structure 64 defining or surrounding the side surfaces of the second via 69 and the second wiring 79.

[0046] The lower surface of the second via 69 may physically contact and be electrically connected to a portion of the top surface of the first wiring 57. The second via 69 may include a second via gap-fill pattern 73 and a second via barrier layer 71, the second via barrier layer 71 being on the lower surface and side surfaces of the second via gap-fill pattern 73 and at least partially covering the lower surface and side surfaces of the second via gap-fill pattern 73.

[0047] The second wiring 79 may continuously extend from the second via 69 without an interface. The second wiring 79 may include: a second wiring gap-fill pattern 83 continuously extending from the second via gap-fill pattern 73 without an interface; and a second wiring barrier layer 81 continuously extending from the second via barrier layer 71 without an interface and extending on the lower surface and side surfaces of the second wiring gap-fill pattern 83.

[0048] The second via barrier layer 71 and the second wiring barrier layer 81 may be integrally formed. That is, the second via barrier layer 71 and the second wiring barrier layer 81 may include a single layer. The second via barrier layer 71 and the second wiring barrier layer 81 may include one or more materials including but not limited to Ti, Ta, Co, TiN, and / or TaN, but exemplary embodiments thereof are not limited to such material types and may be supplemented and / or replaced by other conductive materials.

[0049] The second via gap-fill pattern 73 and the second wiring gap-fill pattern 83 may be integrally formed. That is, the second via gap-fill pattern 73 and the second wiring gap-fill pattern 83 may include a single layer. The second via gap-fill pattern 73 and the second wiring gap-fill pattern 83 may include one or more materials including but not limited to Al, Cu, and / or W, but exemplary embodiments thereof are not limited to such material types and may be supplemented and / or replaced by other conductive materials.

[0050] The second insulating structure 64 may include a second lower etch stop layer 65 and a second lower insulating layer 67 on the second lower etch stop layer 65. The second lower etch stop layer 65 may be separated from the second wiring 79. The second lower etch stop layer 65 may be formed of a high-k dielectric material, and the second lower insulating layer 67 may include silicon oxide and / or a low-k dielectric.

[0051] The second wiring 79 may have a third end surface 79S1 and a fourth end surface 79S2 opposite to each other. The second via 69 may have a third side surface 69S1 adjacent to the fourth end surface 79S2 of the second wiring 79 and a fourth side surface 69S2 adjacent to the third end surface 79S1 of the second wiring 79. The third end surface 79S1 of the second wiring 79 may be closer to the second via 69 than the fourth end surface 79S2 of the second wiring 79.

[0052] The third structure 103 may include a third via 110, a third wiring 120 disposed on and electrically connected to the third via 110, and a third insulating structure 105 that defines or surrounds side surfaces of the third via 110 and the third wiring 120. The third insulating structure 105 may include a third etch stop layer 106 and a third insulating layer 108 on the third etch stop layer 106.

[0053] In an example, the third etch stop layer 106 may include a high-k dielectric, and the third insulating layer 108 may include silicon oxide and / or a low-k dielectric.

[0054] A bottom surface of the third via 110 may physically contact and electrically connect to a part of a top surface of the second wiring 79. The third via 110 may include a third via gap fill pattern 114 and a third via barrier layer 112, and the third via barrier layer 112 is on bottom and side surfaces of the third via gap fill pattern 114 and at least partially covers the bottom and side surfaces of the third via gap fill pattern 114.

[0055] The third wiring 120 may continuously extend from the third via 110 without an interface. The third wiring 120 may include: a third wiring gap fill pattern 123 that continuously extends from the third via gap fill pattern 114 without an interface; and a third wiring barrier layer 122 that continuously extends from the third via barrier layer 112 without an interface and extends onto bottom and side surfaces of the third wiring gap fill pattern 123.

[0056] The third via barrier layer 112 and the third wiring barrier layer 122 may be integrally formed. That is, the third via barrier layer 112 and the third wiring barrier layer 122 may include a single layer. The third via barrier layer 112 and the third wiring barrier layer 122 may include one or more materials including but not limited to Ti, Ta, Co, TiN, and / or TaN, but example embodiments thereof are not limited to such material types and may be supplemented and / or replaced by other conductive materials.

[0057] The third via gap fill pattern 114 and the third wiring gap fill pattern 123 may be integrally formed. That is, the third via gap fill pattern 114 and the third wiring gap fill pattern 123 may include a single layer. The third via gap fill pattern 114 and the third wiring gap fill pattern 123 may include one or more materials including but not limited to Al, Cu, and / or W, but example embodiments thereof are not limited to such material types and may also be supplemented and / or replaced by other conductive materials.

[0058] The third wiring 120 may have a fifth end surface 120S1 and a sixth end surface 120S2 opposite to each other. The third via 110 may include a fifth side surface 110S1 adjacent to the fourth end surface 79S2 of the second wiring 79 and a sixth side surface 110S2 adjacent to the fifth end surface 120S1 of the third wiring 120. The fifth end surface 120S1 of the third wiring 120 may be closer to the third via 110 than the sixth end surface 120S2 of the third wiring 120.

[0059] In an exemplary embodiment, the first via 47 may be formed as a single damascene structure, and the first wiring 57 may be formed as a single damascene structure. Therefore, the sizes of the first via 47 and the first wiring 57 can be significantly reduced. Accordingly, the integration degree of the semiconductor device can be improved.

[0060] In an exemplary embodiment, the distance between the upper end 47S1U of the first side surface 47S1 of the first via 47 and the lower end 57S1L of the first end surface 57S1 of the first wiring 57 may be less than or equal to 1 / 3 of the width W1 of the top surface of the first via 47, or may be "0". Since the distance between the upper end 47S1U of the first side surface 47S1 of the first via 47 and the lower end 57S1L of the first end surface 57S1 of the first wiring 57 can be significantly reduced, the integration degree of the semiconductor device can be improved.

[0061] Since the length of the first wiring 57 can be formed to be about 50 times or less the width W1 of the top surface of the first via 47, disconnection between the first wiring 57 and the first via 47 due to electromigration that may occur between the first wiring 57 and the first via 47 can be alleviated or prevented. Accordingly, the reliability of the semiconductor device 1 can be improved.

[0062] In an example, Figure 3A the distance between the upper end 47S1U of the first side surface 47S1 of the first via 47 and the lower end 57S1L of the first end surface 57S1 of the first wiring 57 in the cross-sectional view of may be less than the distance between the upper end 57S2U of the second end surface 57S2 of the first wiring 57 and the lower end 69S1L of the third side surface 69S1 of the second via 69.

[0063] In an example, the distance between the upper end 47S1U of the first side surface 47S1 of the first via 47 and the lower end 57S1L of the first end surface 57S1 of the first wiring 57 may be less than the distance between the upper end 79S2U of the fourth end surface 79S2 of the second wiring 79 and the lower end 110S1L of the fifth side surface 110S1 of the third via 110.

[0064] In an example, in Figure 3BIn the cross-sectional view, the distance between the upper end 57S2U of the second end surface 57S2 of the first wiring 57 and the lower end 69S1L of the third side surface 69S1 of the second via 69 may be less than the distance between the upper end 79S2U of the fourth end surface 79S2 of the second wiring 79 and the lower end 110S1L of the fifth side surface 110S1 of the third via 110.

[0065] The semiconductor device 1 according to the exemplary embodiment may further include a fourth structure 124 on the third structure 103 and a fifth structure 147 on the fourth structure 124.

[0066] The fourth structure 124 may include a fourth via 130, a fourth wiring 140 electrically connected to the fourth via 130 on the fourth via 130, and a fourth insulating structure 125 defining or surrounding the side surfaces of the fourth via 130 and the fourth wiring 140. The fourth insulating structure 125 may include a fourth etch stop layer 126 and a fourth insulating layer 138 on the fourth etch stop layer 126.

[0067] In the example, the fourth etch stop layer 126 may include a high-k dielectric, and the fourth insulating layer 138 may include silicon oxide and / or a low-k dielectric.

[0068] The lower surface of the fourth via 130 may physically contact a part of the top surface of the third wiring 120. The fourth via 130 may include a fourth via gap-fill pattern 134 and a fourth via barrier layer 132 on the lower surface and side surfaces of the fourth via gap-fill pattern 134 and at least partially covering the lower surface and side surfaces of the fourth via gap-fill pattern 134.

[0069] The fourth wiring 140 may continuously extend from the fourth via 130 without a boundary surface. The fourth wiring 140 may include: a fourth wiring gap-fill pattern 144 continuously extending from the fourth via gap-fill pattern 134 without a boundary surface; and a fourth wiring barrier layer 142 continuously extending from the fourth via barrier layer 132 without a boundary surface and extending onto the lower surface and side surfaces of the fourth wiring gap-fill pattern 144. The fourth via barrier layer 132 and the fourth wiring barrier layer 142 may be integrally formed. That is, the fourth via barrier layer 132 and the fourth wiring barrier layer 142 may include a single layer. The fourth via gap-fill pattern 134 and the fourth wiring gap-fill pattern 144 may be integrally formed. That is, the fourth via gap-fill pattern 134 and the fourth wiring gap-fill pattern 144 may include a single layer.

[0070] In the example, the fourth via stopper layer 132 and the fourth wiring stopper layer 142 may include one or more materials including but not limited to titanium (Ti), tantalum (Ta), cobalt (Co), TiN, and / or TaN, but the exemplary embodiments are not limited thereto. For example, the materials of the fourth via stopper layer 132 and the fourth wiring stopper layer 142 may also be supplemented or replaced with another conductive material. The fourth via gap-fill pattern 134 and the fourth wiring gap-fill pattern 144 may include one or more materials including but not limited to aluminum (Al), copper (Cu), and / or tungsten (W), but the exemplary embodiments are not limited to such material types and may be supplemented and / or replaced with other conductive materials.

[0071] The fifth structure 147 may include an upper conductive pattern 154 and a fifth insulating structure 149 that defines or surrounds a side surface of the upper conductive pattern 154. The fifth insulating structure 149 may include a fifth etch stop layer 150 and a fifth insulating layer 152 on the fifth etch stop layer 150. In the example, the fifth etch stop layer 150 may include a high-k dielectric material, and the fifth insulating layer 152 may include silicon oxide and / or a low-k dielectric material. The upper conductive pattern 154 may include an upper gap-fill pattern 158 and an upper stopper layer 156, and the upper stopper layer 156 is on a lower surface and a side surface of the upper gap-fill pattern 158 and at least partially covers the lower surface and the side surface of the upper gap-fill pattern 158. The upper stopper layer 156 may include one or more materials including but not limited to Ti, Ta, Co, TiN, and / or TaN, but the exemplary embodiments are not limited to these types of materials and may be supplemented and / or replaced with other conductive materials. The upper gap-fill pattern 158 may include one or more materials including but not limited to Al, Cu, and / or W, but the exemplary embodiments are not limited to these types of materials and may be supplemented and / or replaced with other conductive materials.

[0072] In the example, as Figure 3A shown, an upper end 57S1U of a first end surface 57S1 of the first wiring 57 may be aligned with an upper end 47S1U of a first side surface 47S1 of the first via 47, but the exemplary embodiments are not limited thereto. For example, a position of the upper end 57S1U of the first end surface 57S1 of the first wiring 57 may be modified based on process margins and the like. As described above, modification examples of the upper end 57S1U of the first end surface 57S1 of the first wiring 57 will be described with reference to Figure 4A and Figure 4B respectively. Figure 4A and Figure 4B show partial enlarged views of various modification examples of a portion indicated by “A” of Figure 2 . In this case, Figure 4A reference numeral “57S1a” of Figure 4BThe reference numeral "57S1b" can represent Figure 3A a modification of the first end surface 57S1.

[0073] In the modification example, referring to Figure 4A , the upper end 57S1U of the first end surface 57S1a of the first wiring 57 may not overlap with the top surface of the first via 47 in a direction parallel to the stacking direction of the lower structure 3, the first structure 40, the second structure 62, and the third structure 103. For example, the upper end 57S1U of the first end surface 57S1a of the first wiring 57 may protrude outward from the first side surface 47S1 of the first via 47. The first end surface 57S1a of the first wiring 57 and the first side surface 47S1 of the first via 47 may be aligned.

[0074] In the modification example, referring to Figure 4B , the upper end 57S1U of the first end surface 57S1b of the first wiring 57 may overlap with the top surface of the first via 47 in a direction parallel to the stacking direction of the lower structure 3, the first structure 40, the second structure 62, and the third structure 103. In the example, in the Figure 4B cross-sectional view, the distance between the lower end 57S1L of the first end surface 57S1b of the first wiring 57 and the upper end 47S1U of the first side surface 47S1 of the first via 47 may be equal to or less than 1 / 3 of the width W1 of the top surface of the first via 47.

[0075] Next, referring to Figure 4C , modifications of the side surfaces of the first wiring 57 and the first via 47 will be described. Figure 4C is an enlarged view showing a modification example of the portion indicated by "A" in Figure 2 .

[0076] Referring to Figure 4C , the first via 47 may have vertical side surfaces, and the first wiring 57 may have vertical side surfaces. In this case, "vertical" may mean that the top surface and the side surface of the first via 47 are perpendicular to each other, or the top surface and the side surface of the first wiring 57 are perpendicular to each other.

[0077] The first wiring 57 may have a first end surface 57S1c that may correspond to the first end surface ( Figure 3A 57S1 of Figure 3A ) described above with reference to Figure 3A , and the first via 47 may have a first side surface ( Figure 3A 47S1 of Figure 3AThe first side surface 47S1a and the second side surface 47S2a corresponding to 47S2). Thus, the first end surface 57S1c of the first wiring 57 and the first side surface 47S1a of the first via 47 can be vertically aligned.

[0078] Next, reference will be made to Figure 5 and Figure 6 to describe a modification of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 5 is a cross-sectional view showing a modification example of a semiconductor device according to an exemplary embodiment of the inventive concept, Figure 6 is Figure 5 an enlarged view of a portion “Ba”. Figure 5 and Figure 6 are views showing Figure 2 and Figure 3B modification examples of the second via 69 and the second wiring 79. Hereinafter, the second via 69 and the second wiring 79 will be described based on the portions to be modified thereof.

[0079] Referring to Figure 5 and Figure 6 in the modification example, second vias 169 and second wirings 179 having structures substantially the same as those of the above-described second via ( Figure 3B 69 of Figure 3B ) and second wiring (

[0080] The second wiring 179 may have a third end surface 179S1 and a fourth end surface 179S2 similar to those of the second wiring 79 in Figure 3B , and the second via 169 may have a third side surface 169S1b and a fourth side surface 169S2b similar to those of the second via 69 in Figure 3B .

[0081] The second wiring 179 may have a length greater than that of the first wiring 57, and in the cross-sectional views of Figure 5 and Figure 6 , the distance between the upper end 57S2U of the second end surface 57S2 of the first wiring 57 and the lower end 169S1L of the third side surface 169S1b of the second via 169 may be greater than 1 / 2 of the width of the lower surface of the second via 169.

[0082] Next, reference will be made to Figure 7 and Figure 8 to describe a modification example of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 7 is a cross-sectional view showing a modification example of a semiconductor device according to an exemplary embodiment of the inventive concept, Figure 8 is a view showing Figure 7 an enlarged view of a portion “Bb” in Figure 7 andFigure 8 shows a modification example of the second structure 62 described with reference to Figure 2 and Figure 3B In the modification example described with reference to

[0083] In the modification example with reference to Figure 7 and Figure 8 the second structure 62 includes a second via hole 269, a second wiring 279 electrically connected to the second via hole 269, and a second insulating structure 64' that defines or surrounds the side surfaces of the second via hole 269 and the second wiring 279.

[0084] The second via hole 269 may include a second via hole gap-fill pattern 73 and a second via hole barrier layer 71, and the second via hole barrier layer 71 is on the side surface and the bottom surface of the second via hole gap-fill pattern 73 and at least partially covers the side surface and the bottom surface of the second via hole gap-fill pattern 73.

[0085] The second wiring 279 may include a second wiring gap-fill pattern 83 and a second wiring barrier layer 81, and the second wiring barrier layer 81 is on the side surface and the bottom surface of the second wiring gap-fill pattern 83 and at least partially covers the side surface and the bottom surface of the second wiring gap-fill pattern 83.

[0086] The second insulating structure 64' may include a second lower etch stop layer 65, a second lower insulating layer 67 on the second lower etch stop layer 65, a second upper etch stop layer 75 on the second lower insulating layer 67, and a second upper insulating layer 77 on the second upper etch stop layer 75.

[0087] The second lower etch stop layer 65 and the second lower insulating layer 67 may define or surround the side surface of the second via hole 269. The second upper etch stop layer 75 and the second upper insulating layer 77 may define or surround the side surface of the second wiring 279.

[0088] The second wiring 279 may have a third end surface 279S1 and a fourth end surface 279S2 opposite to each other, and the second via hole 269 may have a third side surface 269S1 adjacent to the second end surface 57S2 of the first wiring 57 and a fourth side surface 269S2 adjacent to the third end surface 279S1 of the second wiring 279.

[0089] In the example, the second via hole 269 may have a square shape or may have a shape in which the corners of the square are rounded.

[0090] In the example, in Figure 7 and Figure 8In the cross-sectional view, the length of the second wiring 279 can be 50 times or less the width of the second via 269. The length of the second wiring 279 can be the length obtained by measuring the distance between the third end surface 279S1 and the fourth end surface 279S2. The length of the second wiring 279 can be the length measured based on a reference substantially the same as the reference for the length of the first wiring 57 described above. The width of the second via 269 can be the width measured based on a reference substantially the same as the reference for the width of the first via 47 described above.

[0091] In Figure 7 and Figure 8 's cross-sectional view, the length of the top surface of the second wiring 279 can be about 50 times or less the width of the top surface of the second via 269, and the length of the top surface of the first wiring 57 can be about 50 times or less the width of the top surface of the second via 269.

[0092] In the example, similar to the first side surface 47S1 and the second side surface 47S2 of the first via 47 (see Figure 3A ), the third side surface 269S1 and the fourth side surface 269S2 of the second via 269 can be inclined. Similar to the first end surface 57S1 and the second end surface 57S2 of the first wiring 57 (see Figure 3A ), the third end surface 279S1 and the fourth end surface 279S2 of the second wiring 279 can be inclined.

[0093] In the example, the third side surface 269S1 of the second via 269 and the second end surface 57S2 of the first wiring 57 can be stacked in the vertical direction (i.e., in the direction parallel to the direction in which the lower structure 3, the first structure 40, the second structure 62, and the third structure 103 are stacked).

[0094] In the example, the fourth side surface 269S2 of the second via 269 and the third end surface 279S1 of the second wiring 279 can be stacked in the vertical direction (i.e., in the direction parallel to the direction in which the lower structure 3, the first structure 40, the second structure 62, and the third structure 103 are stacked).

[0095] In the example, in Figure 7 and Figure 8 's cross-sectional view, the distance between the lower end 269S1L of the third side surface 269S1 of the second via 269 and the upper end 57S2U of the second end surface 57S2 of the first wiring 57 can be about 1 / 3 or less the width of the top surface of the second via 269, or can be "0".

[0096] In the example, in Figure 7 and Figure 8In a cross-sectional view, the distance between the upper end 269S2U of the fourth side surface 269S2 of the second via hole 269 and the lower end 279S1L of the third end surface 279S1 of the second wiring 279 may be about 1 / 3 or less of the width of the top surface of the second via hole 269, or may be "0".

[0097] In Figure 7 and Figure 8 's cross-sectional view, the distance between the lower end 269S1L of the third side surface 269S1 of the second via hole 269 and the upper end 57S2U of the second end surface 57S2 of the first wiring 57 may be less than the distance between the upper end 279S2U of the fourth end surface 279S2 of the second wiring 279 and the lower end 110S1L of the fifth side surface 110S1 of the third via hole 110.

[0098] In the example, in Figure 7 and Figure 8 's cross-sectional view, the distance between the upper end 269S2U of the fourth side surface 269S2 of the second via hole 269 and the lower end 279S1L of the third end surface 279S1 of the second wiring 279 may be less than the distance between the upper end 279S2U of the fourth end surface 279S2 of the second wiring 279 and the lower end 110S1L of the fifth side surface 110S1 of the third via hole 110.

[0099] Reference will be made to Figure 9 and Figure 10 to describe the modification of the semiconductor device according to an exemplary embodiment of the inventive concept. Figure 9 is a cross-sectional view showing a modification example of the semiconductor device according to an exemplary embodiment of the inventive concept, Figure 10 is showing Figure 9 a magnified view of a part "Bc" of Figure 9 and Figure 10 show the modification of the second structure 62 described with reference to Figure 2 and Figure 3B .

[0100] Referring to Figure 9 and Figure 10 in the modification example, the second structure 62 includes a second via hole 369, a second wiring 379 electrically connected to the second via hole 369, and a second insulating structure 64' defining or surrounding the side surfaces of the second via hole 369 and the second wiring 379.

[0101] The second via 369 may include a second via gap-fill pattern 73 and a second via barrier layer 71, and the second via barrier layer 71 is on the side surface and the bottom surface of the second via gap-fill pattern 73 or at least partially covers the side surface and the bottom surface of the second via gap-fill pattern 73. The second wiring 379 may include a second wiring gap-fill pattern 83 and a second wiring barrier layer 81, and the second wiring barrier layer 81 is on the side surface and the bottom surface of the second wiring gap-fill pattern 83 or at least partially covers the side surface and the bottom surface of the second wiring gap-fill pattern 83. The second insulating structure 64' may include a second lower etch stop layer 65, a second lower insulating layer 67 on the second lower etch stop layer 65, a second upper etch stop layer 75 on the second lower insulating layer 67, and a second upper insulating layer 77 on the second upper etch stop layer 75.

[0102] The second lower etch stop layer 65 and the second lower insulating layer 67 may define or surround the side surface of the second via 369. The second upper etch stop layer 75 and the second upper insulating layer 77 may define or surround the side surface of the second wiring 379.

[0103] The second wiring 379 may have a third end surface 379S1 and a fourth end surface 379S2 opposite to each other, and the second via 369 may have a third side surface 369S1 adjacent to the second end surface 57S2 of the first wiring 57 and a fourth side surface 369S2 adjacent to the third end surface 379S1 of the second wiring 379.

[0104] In an example, in Figure 9 and Figure 10 's cross-sectional view, the length of the second wiring 379 may be about 50 times or less than the width of the second via 369. The length of the second wiring 379 may be the length provided by measuring the distance between the third end surface 379S1 and the fourth end surface 379S2. The length of the second wiring 379 may be the length measured based on a reference substantially the same as the reference for the length of the first wiring 57 described above. The width of the second via 369 may be the width measured based on a reference substantially the same as the reference for the width of the first via 47 described above.

[0105] In an example, in Figure 9 and Figure 10 's cross-sectional view, the length of the second wiring 379 may be greater than the length of the first wiring 57.

[0106] In an example, similar to the first side surface 47S1 and the second side surface 47S2 of the first via 47 (see Figure 3A ), the third side surface 369S1 and the fourth side surface 369S2 of the second via 369 may be inclined. Similar to the first end surface 57S1 and the second end surface 57S2 of the first wiring 57 (see Figure 3A), the third end surface 379S1 and the fourth end surface 379S2 of the second wiring 379 may be inclined.

[0107] In Figure 9 and Figure 10 's cross-sectional view, the distance between the lower end 369S1L of the third side surface 369S1 of the second via 369 and the upper end 57S2U of the second end surface 57S2 of the first wiring 57 may be greater than about 1 / 2 of the width of the top surface of the second via 369. In Figure 9 and Figure 10 's cross-sectional view, the distance between the lower end 369S1L of the third side surface 369S1 of the second via 369 and the upper end 57S2U of the second end surface 57S2 of the first wiring 57 may be greater than about 1 / 3 of the width of the top surface of the second via 369.

[0108] In Figure 9 and Figure 10 's cross-sectional view, the distance between the upper end 369S2U of the fourth side surface 369S2 of the second via 369 and the lower end 379S1L of the third end surface 379S1 of the second wiring 379 may be greater than about 1 / 2 of the width of the top surface of the second via 369.

[0109] In Figure 9 and Figure 10 's cross-sectional view, the distance between the upper end 369S2U of the fourth side surface 369S2 of the second via 369 and the lower end 379S1L of the third end surface 379S1 of the second wiring 379 may be greater than about 1 / 3 of the width of the top surface of the second via 369.

[0110] In the exemplary embodiment, in Figure 9 and Figure 10 's cross-sectional view, the distance between the lower end 369S1L of the third side surface 369S1 of the second via 369 and the upper end 57S2U of the second end surface 57S2 of the first wiring 57 and the distance between the upper end 369S2U of the fourth side surface 369S2 of the second via 369 and the lower end 379S1L of the third end surface 379S1 of the second wiring 379 may both be greater than the distance between the upper end 47S1U of the first side surface 47S1 of the first via 47 and the lower end 57S1L of the first end surface 57S1 of the first wiring 57. Therefore, defects caused by electromigration can be reduced or prevented. For example, in Figure 9 and Figure 10In the cross-sectional view, the distance between the lower end 369S1L of the third side surface 369S1 of the second via hole 369 and the upper end 57S2U of the second end surface 57S2 of the first wiring 57, and the distance between the upper end 369S2U of the fourth side surface 369S2 of the second via hole 369 and the lower end 379S1L of the third end surface 379S1 of the second wiring 379 can be formed to be greater than about 1 / 3 of the width of the top surface of the second via hole 369. Accordingly, voids that may occur due to electromigration can be formed at the end portion of the second wiring 379 adjacent to the third end surface 379S1 and can be separated from the second via hole 369. Accordingly, defects such as disconnection between the second via hole 369 and the second wiring 379 may be less likely to occur or may not occur.

[0111] Next, an example of a method of forming a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to Figures 11 to 13 FIGS.

[0112] Referring to Figure 1 and Figure 11 FIGS. Figure 11 and

[0113] a first lower etch stop layer 43 and a first lower insulating layer 45 may be sequentially formed on the lower structure 3. The steps of forming the lower structure 3 may include: forming isolation regions 9s defining active regions 9a on a semiconductor substrate 5; forming transistors 10; forming interlayer insulating layers 26 and 29; and forming contact plugs 33 electrically connected to conductive regions 16 and 23 of the transistors 10. In this case, the conductive regions of the transistors 10 may be gate electrodes 16 and source / drain regions 23. The process of forming the transistors 10 may include: forming a gate structure (12, 18, 20) that overlaps the active region 9a in a vertical direction and extends onto the isolation region 9s in the cross-sectional view of Figure 11 ; and forming source / drain regions 23 disposed in the active region 9a and adjacent to the gate structure (12, 18, 20). The gate structure (12, 18, 20) may include a gate 12 and an insulating capping layer 18 sequentially stacked and insulating spacers 20 on side surfaces of the gate 12 and the insulating capping layer 18. The gate 12 may include a gate electrode 16 and a gate dielectric 14, and the gate dielectric 14 is on side surfaces and a bottom surface of the gate electrode 16 and at least partially covers the side surfaces and the bottom surface of the gate electrode 16.

[0113] The interlayer insulating layers (26 and 29) may include a first interlayer insulating layer 26 on the isolation regions 9s and the active regions 9a and a second interlayer insulating layer 29 on the first interlayer insulating layer 26. The second interlayer insulating layer 29 may be on an upper portion of the insulating capping layer 18 and at least partially cover the upper portion of the insulating capping layer 18. Each of the contact plugs 33 may include a plug pattern 37 and a barrier layer 35, and the barrier layer 35 is on side surfaces and a bottom surface of the plug pattern 37 and at least partially covers the side surfaces and the bottom surface of the plug pattern 37.

[0114] The first via 47 can be formed to penetrate the first lower etch stop layer 43 and the first lower insulating layer 45 and be electrically connected to the contact plug 33. The steps of forming the first via 47 can include: forming a hole that penetrates the first lower etch stop layer 43 and the first lower insulating layer 45; forming a first via barrier layer 49 on the sidewalls and bottom of the hole and at least partially covering the sidewalls and bottom of the hole, and on the first lower insulating layer 45 and at least partially covering the first lower insulating layer 45; forming a first via gap-fill pattern 51 on the first via barrier layer 49 and at least partially covering the first via barrier layer 49 and at least partially filling the remaining portion of the hole; and planarizing the first via gap-fill pattern 51 and the first via barrier layer 49 until the top surface of the first lower insulating layer 45 is exposed. Thus, the first via 47 having a single damascene structure can be formed.

[0115] Referring to Figure 1 and Figure 12 , a first upper etch stop layer 53 and a first upper insulating layer 55 can be sequentially formed on the first lower insulating layer 45. The first lower etch stop layer 43, the first lower insulating layer 45, the first upper etch stop layer 53, and the first upper insulating layer 55 can constitute a first insulating structure 42.

[0116] The first wiring 57 can be formed to penetrate the first upper etch stop layer 53 and the first upper insulating layer 55 and be electrically connected to the first via 47. The steps of forming the first wiring 57 can include: forming a trench that penetrates the first upper etch stop layer 53 and the first upper insulating layer 55; forming a first wiring barrier layer 59 on the sidewalls and bottom of the trench and at least partially covering the sidewalls and bottom of the trench, and on the first upper insulating layer 55 and at least partially covering the first upper insulating layer 55; forming a first wiring gap-fill pattern 61 on the first wiring barrier layer 59 and at least partially covering the first wiring barrier layer 59 and at least partially filling the remaining portion of the trench; and planarizing the first wiring gap-fill pattern 61 and the first wiring barrier layer 59 until the top surface of the first upper insulating layer 55 is exposed. Thus, the first wiring 57 having a single damascene structure can be formed. Thus, the first via 47 and the first wiring 57 identical to those described with reference to Figure 1 , Figure 2 , Figure 3A and Figure 3B can be formed. The first via 47, the first wiring 57, and the first insulating structure 42 can constitute the first via 47 and the first wiring 57 identical to those described with reference to Figure 1 , Figure 2 , Figure 3A and Figure 3BThe first structure 40 described is the same as the first structure 40 .

[0117] Reference Figure 1 and Figure 13 , a second insulating structure 64 may be formed on the first structure 40. The second insulating structure 64 may include a second lower etch stop layer 65 and a second lower insulating layer 67 sequentially stacked. The second insulating structure 64 may be patterned to form a dual damascene opening 78. The dual damascene opening 78 may include a through hole 78a exposing a portion of the first wiring 57 and a through hole 78a formed in the first wiring 57. Figure 13 In the cross-sectional view of FIG. 7 , the groove 78 b overlaps with the through hole 78 a in the vertical direction.

[0118] Refer again Figure 1 , Figure 2 , Figure 3A and Figure 3B , can be formed to at least partially fill the dual damascene opening 78 (see Figure 13 ) of the second via hole 69 and the second wiring 79. The steps of forming the second via hole 69 and the second wiring 79 may include: forming barrier layers 71 and 81, the barrier layers 71 and 81 are formed in the dual damascene opening 78 (see Figure 13 ) and at least partially covers the dual damascene opening 78 (see Figure 13 ), and on the second lower insulating layer 67 and at least partially covering the second lower insulating layer 67; gap filling patterns 73 and 83 are formed, the gap filling patterns 73 and 83 are on the barrier layers 71 and 81 and at least partially cover the barrier layers 71 and 81, and at least partially fill the dual damascene opening 78 (see Figure 13 and planarizing the gap filling patterns 73 and 83 and the barrier layers 71 and 81 until the top surface of the second lower insulating layer 67 is exposed. Thus, a dual damascene opening ( Figure 13 of 78) through holes ( Figure 13 78a) in the second via 69 and in the dual damascene opening ( Figure 13 Groove (78) Figure 13 Therefore, the second via 69 and the second wiring 79 can be formed by a dual damascene structure.

[0119] The second insulating structure 64, the second via 69, and the second wiring 79 may form the second structure 62. The third structure 103 and the fourth structure 124 may be formed using a similar method (e.g., a process for forming a dual damascene structure) as the second structure 62. The fifth structure 147 may be formed using a process for forming a single damascene structure.

[0120] As described above, according to an exemplary embodiment of the inventive concept, a semiconductor device having an increased degree of integration can be provided. According to an exemplary embodiment of the inventive concept, a semiconductor device having vias and wirings can be provided, in which reliability can be improved.

[0121] Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A lower structure; A first structure on the lower structure; And A second structure on the first structure, Wherein, the lower structure includes: a source / drain region and a gate electrode on a semiconductor substrate; an insulating layer on the source / drain region and the gate electrode; and a contact plug electrically connected to one of the source / drain region and the gate electrode while penetrating the insulating layer, Wherein, the first structure includes: a first via electrically connected to the contact plug; a first wiring electrically connected to the first via; and a first insulating structure defining the side surfaces of the first via and the first wiring, Wherein, the first insulating structure includes: a first lower etch stop layer; a first lower insulating layer on the first lower etch stop layer; a first upper etch stop layer on the first lower insulating layer; and a first upper insulating layer on the first upper etch stop layer, Wherein, the first lower etch stop layer and the first lower insulating layer define the side surfaces of the first via, Wherein, the first upper etch stop layer and the first upper insulating layer define the side surfaces of the first wiring, Wherein, the first wiring has a first end surface and a second end surface opposite to each other, Wherein, the side surfaces of the first via include a first side surface adjacent to the first end surface of the first wiring and a second side surface opposite to the first side surface, Wherein, the second structure includes: a second via; a second wiring disposed on the second via and electrically connected to the second via; and a second insulating structure defining the side surfaces of the second via and the second wiring, Wherein, the second insulating structure includes a second etch stop layer and a second insulating layer on the second etch stop layer, Wherein, the second insulating layer defines the side surfaces of the second wiring and extends onto the side surfaces of the second via, Wherein, the second wiring has a third end surface and a fourth end surface opposite to each other, Wherein, the third end surface of the second wiring is closer to the second via than the fourth end surface of the second wiring, Wherein, the side surfaces of the second via include a third side surface adjacent to the second end surface of the first wiring and a fourth side surface adjacent to the third end surface of the second wiring, and Wherein, the distance between the upper end of the first side surface of the first via and the lower end of the first end surface of the first wiring is less than the distance between the lower end of the third end surface of the second wiring and the upper end of the fourth side surface of the second via.

2. The semiconductor device according to claim 1, wherein, The distance between the upper end of the first side surface of the first via and the lower end of the first end surface of the first wiring is less than the distance between the upper end of the second end surface of the first wiring and the lower end of the third side surface of the second via.

3. The semiconductor device according to claim 1, wherein, The first via includes a first via gap fill pattern and a first via barrier layer on the side surface and the bottom surface of the first via gap fill pattern, Wherein, the first wiring includes a first wiring gap filling pattern and a first wiring barrier layer on side surfaces and a bottom surface of the first wiring gap filling pattern, and wherein, the first wiring barrier layer includes a portion disposed between the first wiring gap filling pattern and the first via hole gap filling pattern.

4. The semiconductor device according to claim 1, wherein, The second via hole includes a second via hole gap filling pattern and a second via hole barrier layer on side surfaces and a bottom surface of the second via hole gap filling pattern, wherein, the second wiring includes: a second wiring gap filling pattern extending from the second via hole gap filling pattern; and a second wiring barrier layer extending from the second via hole barrier layer and on side surfaces and a bottom surface of the second wiring gap filling pattern, wherein, the second via hole gap filling pattern and the second wiring gap filling pattern include a first single layer, and wherein, the second via hole barrier layer and the second wiring barrier layer include a second single layer.

5. The semiconductor device according to any one of claims 1 to 4, the semiconductor device further includes a third structure on the second structure, Among them, the third structure includes: a third via hole; a third wiring disposed on the third via hole and electrically connected to the third via hole; and a third insulating structure defining side surfaces of the third via hole and side surfaces of the third wiring, wherein, the third insulating structure includes a third etch stop layer and a third insulating layer on the third etch stop layer, wherein, the third insulating layer extends to one of the side surfaces of the third via hole while defining one of the side surfaces of the third wiring, wherein, the third wiring has a fifth end surface and a sixth end surface opposite to each other, wherein, the fifth end surface of the third wiring is closer to the third via hole than the sixth end surface of the third wiring, and wherein, the side surfaces of the third via hole include a fifth side surface adjacent to the fourth end surface of the second wiring and a sixth side surface adjacent to the fifth end surface of the third wiring.

6. The semiconductor device according to claim 5, wherein, A distance between an upper end of the fourth end surface of the second wiring and a lower end of the fifth side surface of the third via hole is greater than a distance between an upper end of the first side surface of the first via hole and a lower end of the first end surface of the first wiring.

7. A semiconductor device, the semiconductor device includes: a first via hole on a semiconductor substrate; a first wiring disposed on the first via hole and electrically connected to the first via hole; a second via hole disposed on the first wiring and electrically connected to the first wiring; a second wiring disposed on the second via hole and electrically connected to the second via hole; a third via hole disposed on the second wiring and electrically connected to the second wiring; and a third wiring disposed on the third via hole and electrically connected to the third via hole, wherein, the first wiring has a first end surface and a second end surface opposite to each other, wherein, the second wiring has a third end surface and a fourth end surface opposite to each other, wherein, the third wiring has a fifth end surface and a sixth end surface opposite to each other, Wherein, the first via has a first side adjacent to the first end surface and a second side opposite to the first side. Wherein, the second via has a third side adjacent to the second end surface of the first wiring and a fourth side adjacent to the third end surface of the second wiring. Wherein, the third via has a fifth side adjacent to the fourth end surface of the second wiring and a sixth side adjacent to the fifth end surface of the third wiring, and wherein, the distance between the upper end of the first side of the first via and the lower end of the first end surface of the first wiring is less than the distance between the upper end of the fourth end surface of the second wiring and the lower end of the fifth side of the third via.

8. The semiconductor device according to claim 7, wherein, The distance between the upper end of the first side of the first via and the lower end of the first end surface of the first wiring is not greater than 1 / 3 of the width of the top surface of the first via, or is "0".

9. The semiconductor device according to claim 7, wherein, The first end surface of the first wiring is aligned with the first side of the first via.

10. The semiconductor device according to claim 7, wherein, The distance between the upper end of the second end surface of the first wiring and the lower end of the third side of the second via is greater than 1 / 2 of the width of the bottom surface of the second via.

11. The semiconductor device according to any one of claims 7 to 10, the semiconductor device further comprising: A first insulating structure on the semiconductor substrate; A second insulating structure on the first insulating structure; And A third insulating structure on the second insulating structure, wherein, the first insulating structure includes a first lower etch stop layer, a first lower insulating layer on the first lower etch stop layer, a first upper etch stop layer on the first lower insulating layer, and a first upper insulating layer on the first upper etch stop layer, wherein, the first lower etch stop layer and the first lower insulating layer define the first side and the second side of the first via, wherein, the first upper etch stop layer and the first upper insulating layer define the first end surface and the second end surface of the first wiring, wherein, the second insulating structure includes a second etch stop layer and a second insulating layer on the second etch stop layer, wherein, the second insulating layer extends onto the third side and the fourth side of the second via while defining the third end surface and the fourth end surface of the second wiring, wherein, the third insulating structure includes a third etch stop layer and a third insulating layer on the third etch stop layer, and wherein, the third insulating layer extends onto the fifth side and the sixth side of the third via while defining the fifth end surface and the sixth end surface of the third wiring.

12. The semiconductor device according to any one of claims 7 to 10, the semiconductor device further comprising: A first insulating structure on the semiconductor substrate; A second insulating structure on the first insulating structure; And A third insulating structure on the second insulating structure, Wherein, the first insulating structure includes a first lower etch stop layer, a first lower insulating layer on the first lower etch stop layer, a first upper etch stop layer on the first lower insulating layer, and a first upper insulating layer on the first upper etch stop layer, Wherein, the first lower etch stop layer and the first lower insulating layer define the first side surface and the second side surface of the first via hole, Wherein, the first upper etch stop layer and the first upper insulating layer define the first end surface and the second end surface of the first wiring, Wherein, the second insulating structure includes a second lower etch stop layer, a second lower insulating layer on the second lower etch stop layer, a second upper etch stop layer on the second lower insulating layer, and a second upper insulating layer on the second upper etch stop layer, Wherein, the second lower etch stop layer and the second lower insulating layer define the third side surface and the fourth side surface of the second via hole, Wherein, the second upper etch stop layer and the second upper insulating layer define the third end surface and the fourth end surface of the second wiring, Wherein, the third insulating structure includes a third etch stop layer and a third insulating layer on the third etch stop layer, and Wherein, the third insulating layer extends on the fifth side surface and the sixth side surface of the third via hole, while defining the fifth end surface and the sixth end surface of the third wiring.

13. The semiconductor device according to claim 12, wherein, The distance between the upper end of the second end surface of the first wiring and the lower end of the third side surface of the second via hole is not greater than 1 / 3 of the width of the top surface of the second via hole, or is "0", and Wherein, the distance between the lower end of the third end surface of the second wiring and the upper end of the fourth side surface of the second via hole is equal to or less than 1 / 3 of the width of the top surface of the second via hole, or is "0".

14. The semiconductor device according to claim 13, wherein, The length of the top surface of the first wiring is not greater than 50 times the width of the top surface of the second via hole, and Wherein, the length of the top surface of the second wiring is not greater than 50 times the width of the top surface of the second via hole.

15. The semiconductor device according to claim 12, wherein The distance between the upper end of the second end surface of the first wiring and the lower end of the third side surface of the second via hole is greater than 1 / 3 of the width of the top surface of the second via hole, and Wherein, the distance between the lower end of the third end surface of the second wiring and the upper end of the fourth side surface of the second via hole is greater than 1 / 3 of the width of the top surface of the second via hole.

16. The semiconductor device according to claim 15, wherein, The length of the second wiring is greater than the length of the first wiring.

17. The semiconductor device according to claim 15, wherein, The length of the top surface of the second wiring is not greater than 50 times the width of the top surface of the second via hole.

18. A semiconductor device, the semiconductor device includes: A lower wiring on a semiconductor substrate; An upper wiring on the lower wiring; And A via hole between the lower wiring and the upper wiring, Wherein, the lower wiring has a first end surface and a second end surface opposite to each other, The upper wiring has a third end surface and a fourth end surface opposite to each other, The via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring, wherein, the distance between the lower end of the first side of the via and the upper end of the second end surface of the lower wiring is less than 1 / 3 of the width of the top surface of the via, and wherein, the distance between the upper end of the second side of the via and the lower end of the third end surface of the upper wiring is less than 1 / 3 of the width of the top surface of the via.

19. The semiconductor device according to claim 18, wherein, the length of the top surface of the lower wiring is not greater than 50 times the width of the top surface of the via, and wherein, the length of the top surface of the upper wiring is not greater than 50 times the width of the top surface of the via.

20. The semiconductor device according to claim 18 or 19, the semiconductor device further comprising: a lower etch stop layer; a lower insulating layer on the lower etch stop layer; an upper etch stop layer on the lower insulating layer; and an upper insulating layer on the upper etch stop layer, wherein, the lower insulating layer and the upper insulating layer include silicon oxide or a low-k dielectric material, wherein, the lower etch stop layer and the upper etch stop layer include a high-k dielectric material, wherein, the lower etch stop layer and the lower insulating layer define the side surface of the via, and wherein, the upper etch stop layer and the upper insulating layer define the side surface of the upper wiring.

Images