Memory device

Abstract

A memory device, the memory device comprising: a peripheral circuit region, comprising a first substrate and a circuit element located on the first substrate, the circuit element comprising a row decoder; a cell array region, comprising a word line and a channel structure, the word line being stacked on a second substrate on the peripheral circuit region, the channel structure extending in a direction perpendicular to an upper surface of the second substrate and penetrating the word line; and a cell contact region, comprising a cell contact, the cell contact being connected to the word line and being located on both sides of the cell array region in a first direction parallel to an upper surface of the second substrate, the cell contact region comprising a first cell contact region and a second cell contact region, the first cell contact region and the second cell contact region having different lengths from each other in the first direction.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0095526 filed on August 6, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to memory devices. Background Art

[0003] A memory device may provide a function of writing data and erasing data or reading written data. Memory devices may be classified into nonvolatile memory devices and volatile memory devices. Even when the power supply of a nonvolatile memory device is interrupted, the nonvolatile memory device retains its stored data. The data storage capacity required for the memory device tends to increase. Therefore, various methods have been proposed to increase the integration density of the memory device. Summary of the invention

[0004] Example embodiments provide a memory device whose integration density is increased by forming a cell region included in the memory device to be asymmetric in at least one direction among directions parallel to an upper surface of a substrate.

[0005] According to some example embodiments, a memory device includes: a peripheral circuit region including a first substrate and a circuit element located on the first substrate, the circuit element including a row decoder; a cell array region including a word line and a channel structure, the word line is stacked on a second substrate on the peripheral circuit region, the channel structure extends in a direction perpendicular to an upper surface of the second substrate and penetrates the word line; and a cell contact region including a cell contact, the cell contact is connected to the word line and is located on both sides of the cell array region in a first direction parallel to an upper surface of the second substrate, the cell contact includes a first cell contact region and a second cell contact region, the first cell contact region and the second cell contact region having different lengths from each other in the first direction. Each of the first cell contact region and the second cell contact region includes a first pad having different lengths from each other in the first direction and a second pad different from the first pad, and the cell contact is connected to the word line in the first pad. The number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region.

[0006] According to some example embodiments, a memory device includes: a peripheral circuit region including a transmission element located on a first substrate; and a plurality of cell regions located on a second substrate above the peripheral circuit region, each of the plurality of cell regions including at least one memory block. Each of the plurality of cell regions includes a cell array region and a cell connection region, in which a plurality of word lines are connected to the transmission element and a plurality of channel structures penetrate the word lines, and in which the word lines extending from the cell array region are connected to a plurality of cell contacts. At least one of the transmission elements is commonly connected to a pair of word lines in a pair of cell regions adjacent to each other included in the cell contacts, and the pair of word lines are located at the same level from an upper surface of the second substrate.

[0007] According to some example embodiments, a memory device includes: a peripheral circuit region including a transmission element; and a plurality of cell regions, each of the plurality of cell regions including a cell array region including a word line stacked on a substrate above the peripheral circuit region and a channel structure penetrating the word line. Each of the plurality of cell regions includes a first cell region and a second cell region adjacent to each other in a first direction parallel to an upper surface of the substrate, and a third cell region and a fourth cell region adjacent to each other in the first direction. The distance between the cell array region of the first cell region and the cell array region of the second cell region is different from the distance between the cell array region of the third cell region and the cell array region of the fourth cell region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 and Figure 2 is a schematic diagram of a memory device according to some example embodiments;

[0010] Figure 3 and Figure 4 shows a connection relationship between a memory cell array and a pass element in a memory device according to some example embodiments;

[0011] Figure 5 is a schematic plan view of a memory device according to some example embodiments;

[0012] Fig. 6A and Figure 6B Shows Figure 5 an area of ​​a memory device shown in;

[0013] Fig. 7A and Figure 7Bshows a portion of a memory device according to some example embodiments;

[0014] Fig. 8A and Figure 8B illustrates regions of a memory device according to some example embodiments;

[0015] Fig. 9 and Fig.10 shows a schematic construction of a memory device according to some example embodiments;

[0016] Figures 11 to 14 is a schematic plan view of a memory device according to some example embodiments;

[0017] Fig.15 is along Fig.11 A cross-sectional view taken along line II' in FIG.

[0018] Fig.16 is along Fig.11 A cross-sectional view taken along line II-II';

[0019] Fig.17 is along Fig.12 A cross-sectional view taken along line III-III';

[0020] Fig.18A and Fig.18B yes Fig.17 A schematic diagram of the transmission element shown in ;

[0021] Fig.19 and Fig. 20 is a cross-sectional view illustrating a cell contact region of a memory device according to some example embodiments;

[0022] Fig.21 is a cross-sectional view illustrating a cell array region of a memory device according to some example embodiments;

[0023] Fig. 22 , Fig.23A , Fig. 23B , Fig.24A and Fig. 24B yes Fig.21 Magnified view of the area in ;

[0024] Fig.25 is a cross-sectional view illustrating a cell array region of a memory device according to some example embodiments;

[0025] Fig.26A , Fig.26B , Fig.27A and Fig.27B yes Fig.25 A magnified image of the area in ; and

[0026] Fig.28 is a schematic block diagram of an electronic device including a memory device according to some example embodiments. DETAILED DESCRIPTION

[0027] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0028] Figure 1 and Figure 2 is a schematic block diagram of a memory device according to some example embodiments.

[0029] Reference Figure 1 , the memory device 10 may include a memory cell array 20 and a peripheral circuit 30. The peripheral circuit 30 may include a row decoder 31, a voltage generator 32, a page buffer 33, an input / output circuit 34, a control logic 35, etc. The memory cell array 20 may include a plurality of memory cells and may be divided into a plurality of memory blocks. The plurality of memory cells may be connected to the row decoder 31 through a string selection line SSL, a word line WL, and a ground selection line GSL, and connected to the page buffer 33 through a bit line BL. In an example embodiment, a plurality of memory cells arranged in the same row may be connected to the same word line WL, and a plurality of memory cells arranged in the same column may be connected to the same bit line BL.

[0030] The row decoder 31 may decode the address ADDR received from the control logic 35 or the like to generate and transmit a voltage for driving the word line WL. The row decoder 31 may input the word line voltage generated by the voltage generator 32 to the word line WL in response to the control of the control logic 35. As an example, the row decoder 31 may be connected to the word line WL through the transfer element of the transfer element unit 31A, and may input the word line voltage to the word line WL when the transfer element of the transfer element unit 31A is turned on.

[0031] The page buffer 33 is connected to the memory cell array 20 through the bit lines BL, and can read data stored in the memory cells or write data to the memory cells. The page buffer 33 may include a column decoder and a sense amplifier. The column decoder may select at least part of the bit lines BL of the memory cell array 20, and the sense amplifier may read data of the memory cells connected to the bit lines selected by the column decoder during a read operation.

[0032] The input / output circuit 34 may receive data DATA during a program operation and transfer the received data DATA to the page buffer 33, and may output data DATA read from the memory cell array 20 by the page buffer 33 to an external entity during a read operation. The input / output circuit 34 may transfer an address or instruction received from an external memory controller to the control logic 35.

[0033] The control logic 35 may control operations of the row decoder 31 , the voltage generator 32 , the page buffer 33 , etc. In some example embodiments, the control logic 35 may operate according to a control signal and an external voltage transmitted from an external memory controller, etc.

[0034] The voltage generator 32 may use an external input power supply voltage to generate a control voltage for the operation of the memory device 10, for example, a program voltage, a read voltage, an erase voltage, a pass voltage, etc. The voltage generated by the voltage generator 32 may be supplied to the peripheral circuit 30, or may be input to the memory cell array 20 through the row decoder 31 or the like.

[0035] As an example, during a programming operation, a program voltage may be input to a selected word line connected to a selected memory cell to which data is to be written. A transmission voltage lower than the program voltage may be input to a word line connected to an unselected memory cell included in a single memory cell string and sharing a channel region with the selected memory cell.

[0036] In some example embodiments, during a read operation, a read voltage may be input to a selected word line connected to a selected memory cell from which data is to be read, and a pass voltage may be input to an unselected word line connected to an unselected memory cell sharing a channel region with the selected memory cell. In some example embodiments in which each of the memory cells stores data having multiple bits, the row decoder 31 may input a plurality of read voltages having different magnitudes from each other into the selected word line.

[0037] Reference Figure 2 , the memory cell array 20 may include a plurality of memory blocks BLK1 to BLKn. Each of the memory blocks BLK1 to BLKn may include a word line stacked along a third direction (Z-axis direction) on a plane defined by a first direction (X-axis direction) and a second direction (Y-axis direction) and a channel structure extending along the third direction (Z-axis direction). The word line and the channel structure may provide a three-dimensionally arranged memory cell. Each of the memory blocks BLK1 to BLKn may include a bit line extending along a first direction (X-axis direction) or a second direction (Y-axis direction) and connected to the channel structure. As an example, in the memory cell array 20, the memory blocks BLK1 to BLKn may be arranged along a first direction (X-axis direction) and a second direction (Y-axis direction).

[0038] Figure 3 and Figure 4 A connection relationship between a memory cell array and a transmission element in a memory device according to some example embodiments is shown.

[0039] Reference Figure 3 , a single memory block BLK may include a plurality of memory cell strings CS, and at least part of the memory cell strings CS may share word lines WL1 to WLn and bit lines BL1 to BL3 .

[0040] Each of the memory cell strings CS may include a plurality of memory cells MC connected between the first string selection transistor SST1 and the second string selection transistor SST2 and the ground selection transistor GST. The first string selection transistor SST1 and the second string selection transistor SST2 may be connected in series with each other. The overlying second string selection transistor SST2 may be connected to one of the bit lines BL1 to BL2. The ground selection transistor GST may be connected to a common source line CSL.

[0041] A plurality of memory cells MC may be connected in series to each other between the first and second string selection transistors SST1 and SST2 and the ground selection transistor GST. In example embodiments, the number of string selection transistors SST1 and SST2 and the ground selection transistor GST may be variously changed. The memory cell string CS may further include at least one dummy memory cell.

[0042] The gate electrodes of the plurality of memory cells MC may be connected to the word lines WL1 to WLn. The gate electrodes of the ground selection transistors GST may be connected to the ground selection lines GSL, and the gate electrodes of the first string selection transistors SST1 and the second string selection transistors SST2 may be connected to the string selection lines SSL11 to SSL23 (i.e., string selection lines SSL11, SSL12, SSL13, SSL21, SSL22, and SSL23).

[0043] The word lines WL1 to WLn, the ground selection lines GSL, and the string selection lines SSL11 to SSL23 may be connected to a transfer element unit PTU including a transfer element PT. The transfer element PT may be turned on and off by a block selection signal BS. While the transfer element PT is turned on, a programming operation, a read operation, an erase operation, etc. may be performed on a plurality of memory cells MC by voltages S1 to Sn, GS, and SS11 to SS23 (i.e., voltages SS11, SS12, SS13, SS21, SS22, and SS23) input to the word lines WL1 to WLn, the ground selection lines GSL, and the string selection lines SSL11 to SSL23. Figure 3 In some example embodiments shown in , the pass elements PT connected to the word lines WL1 to WLn included in the memory block BLK may not be shared by word lines included in another memory block.

[0044] Reference Figure 4, the first memory block BLK1 and the second memory block BLK2 may share at least one of the transmission elements. Figure 4 In some example embodiments shown in , the transfer element unit PTU may include a first transfer element PT1 and at least one second transfer element PT2, and the second transfer element PT2 may be shared by at least one of the word lines WL1 to WLn of the first memory block BLK1 and the second memory block BLK2. Figure 4 , the second transfer element PT2 may be commonly connected to the first word line WL1 of the first memory block BLK1 and the first word line WL1 of the second memory block BLK2 .

[0045] The transmission elements of the word lines WL1 to WLn connected to the first memory block BLK1 can be turned on and off by the first block selection signal BS1, and the transmission elements of the word lines WL1 to WLn connected to the second memory block BLK2 can be turned on and off by the second block selection signal BS2. In an example embodiment, the first block selection signal BS1 and the second block selection signal BS2 may be the same as each other or different from each other. When the first block selection signal BS1 and the second block selection signal BS2 are the same as each other, the transmission elements included in the transmission element unit PTU may be turned on or off at the same time. Therefore, the first memory block BLK1 and the second memory block BLK2 may be driven at the same time.

[0046] Figure 5 is a schematic plan view of a memory device according to some example embodiments.

[0047] Reference Figure 5 , the memory device 40 according to some example embodiments may include a plurality of cell regions 50. The plurality of cell regions 50 may be arranged on a substrate 41. Each of the cell regions 50 may include a word line stacked in a direction perpendicular to an upper surface of the substrate 41, a channel structure extending in a direction perpendicular to the upper surface of the substrate 41, a cell contact connected to the word line, and the like.

[0048] Each of the cell regions 50 may include a cell array region in which a channel structure is disposed and a cell contact region extending from the cell array region, in which a word line and a cell contact are connected to each other. For example, the cell contact region may be disposed around the cell array region in a direction parallel to the upper surface of the substrate 41. Therefore, the cell contact regions may be disposed adjacent to each other on the boundary between the cell regions 50.

[0049] In accordance with Figure 5In the memory device 40 of the example embodiment shown in , the peripheral circuit region may be disposed under the substrate 41 on which the cell region 50 is disposed. The peripheral circuit region may include at least part of a circuit for driving the memory cells included in the cell region 50, for example, a row decoder, a voltage generator, a page buffer, an input / output circuit, and control logic.

[0050] The row decoder may include a transmission element connected to the word line of the cell region 50. In some example embodiments, among the word lines included in the cell regions 50 different from each other, at least one word line may share the transmission element. The cell contact region disposed around the cell array region may have an asymmetric structure so that at least one word line among the word lines included in the cell regions 50 adjacent to each other may share the transmission element. Hereinafter, reference will be made to Fig. 6A and Figure 6B This is described in further detail.

[0051] Fig. 6A and Figure 6B Shows Figure 5 As an example, Fig. 6A Can be Figure 5 An enlarged view of area A1 in FIG. Figure 6B Can be Figure 5 An enlarged view of area A2 in FIG. Fig. 6A and Figure 6B , the memory device 40 may include a cell region 50 and a peripheral circuit region 60 which are vertically stacked. As an example, the cell region 50 may be disposed above the peripheral circuit region 60.

[0052] Each of the cell regions 50 may include a first cell contact region 51, a second cell contact region 52, and a cell array region 53 disposed between the first cell contact region 51 and the second cell contact region 52. The cell array region 53 may include word lines stacked on each other, a channel structure penetrating the word lines, etc. Each of the first cell contact region 51 and the second cell contact region 52 may be a region in which a word line extending from the cell array region 53 and a cell contact are connected to each other, and may be disposed on both sides of the cell array region 53 in a first direction (X-axis direction).

[0053] In some example embodiments, the first cell contact region 51 and the second cell contact region 52 may have different lengths from each other in the first direction (X-axis direction). For example, in the first direction (X-axis direction), the length L1 of the first cell contact region 51 may be greater than the length L2 of the second cell contact region 52.

[0054] Refer to the following Figure 5 An enlarged view of area A1 in Fig. 6A , the first cell contact regions 51 may be adjacent to each other between the cell regions 50. Referring to FIG. Figure 5 An enlarged view of area A2 in Figure 6B , the second cell contact regions 52 may be adjacent to each other between the cell regions 50. Therefore, the distances between the cell array regions 53 included in the cell regions 50 adjacent to each other in the memory device 40 may be different from each other according to their positions. Fig. 6A In the example embodiment shown in FIG. 1 , the first distance DC1 between the cell array regions 53 may be greater than Figure 6B The second distance DC2 between the cell array regions 53 in the example embodiment shown in FIG. 5 is large.

[0055] In some example embodiments, a transfer element connected to a word line may be disposed in the peripheral circuit region 60 below each of the first cell contact region 51 and the second cell contact region 52. The word line and the transfer element may be connected to each other through cell contacts disposed in the first cell contact region 51 and the second cell contact region 52. In some example embodiments, at least a portion of the cell contacts connected to the word line in the second cell contact region 52 may be commonly connected to one of the transfer elements. Therefore, the number of transfer elements included in the peripheral circuit region 60 may be reduced, and the area of ​​the second cell contact region 52 may be reduced to increase the integration density of the memory device 40.

[0056] Fig. 7A and Figure 7B Portions of a memory device according to some example embodiments are shown.

[0057] Fig. 7A may be a cross-sectional view illustrating a region of a memory device according to some example embodiments, Figure 7B Can be with Fig. 7A As an example, in reference to Fig. 7A and Figure 7B In the described example embodiment, the first cell contact region may be connected to the Fig. 6A The areas described in correspond to those adjacent to each other.

[0058] First refer to Fig. 7A , the memory device may include a peripheral circuit region 200 and a cell region 100 disposed above the peripheral circuit region 200. The peripheral circuit region 200 may include a first substrate 210, a plurality of circuit elements 220 formed on the first substrate 210, lower interconnection lines 230 connected to the circuit elements 220, and a lower interlayer dielectric 240. The lower interlayer dielectric 240 may be disposed to cover the circuit elements 220 and the lower interconnection lines 230, and may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0059] The cell region 100 may include a first cell region 100A and a second cell region 100B, the first cell region 100A and the second cell region 100B having the same structure. Hereinafter, the structure of the cell region 100 will be described with reference to the first cell region 100A. As an example, each of the first cell region 100A and the second cell region 100B may provide at least one memory block.

[0060] The first cell region 100A may include a second substrate 110A disposed on a lower interlayer dielectric 240. A plurality of word lines 131A to 136A (130A) may be stacked on the second substrate 110A in a third direction (Z-axis direction) perpendicular to the upper surface of the second substrate 110A. String selection lines 141A to 142A (140A) and a ground selection line 120A may be disposed above and below the word line 130A, respectively. A channel structure 150A may extend in a third direction to penetrate the word line 130A, the string selection line 140A, and the ground selection line 120A. The channel structure 150A may include a data storage layer 151A, a channel layer 152A, a buried insulating layer 153A, etc., and the channel layer 152A may be electrically connected to the bit line BL through a bit line contact BLC. In some example embodiments, the bit line BL may extend in a second direction (Y-axis direction). A region in which the channel structure 150A and the bit lines BL are disposed may be defined as a cell array region CA.

[0061] The word line 130A may extend in a first direction (X-axis direction) and may be connected to a plurality of cell contacts 161A to 164A (160A) in a first cell contact region CT1 adjacent to the cell array region CA in the first direction. In some example embodiments, the word line 130A may extend in different lengths from each other in the first direction and the second direction to provide pads PAD1 and PAD2. The cell contact 160A and the word line 130A may be connected to each other on the pad PAD1.

[0062] Reference Fig. 7A , the first cell contact region CT1 may include a first pad PAD1 and a second pad PAD2 having an area different from that of the first pad PAD1. Each of the second pads PAD2 may have an area larger than that of each of the first pads PAD1. In some example embodiments, a length of each of the second pads PAD2 in the first direction may be larger than a length of each of the first pads PAD1 in the first direction.

[0063] The vertical vias 181A to 184A (180A) may be provided in at least a portion of the pad PAD2 to pass through a portion of the word line 130A and the second substrate 110A to connect to the lower interconnection line 230 of the peripheral circuit region 200. The pad PAD2 in which the vertical via 180A is provided may be provided in a position different from that of the pad PAD1 to which the cell contact 160A and the word line 130A are connected in the second direction.

[0064] The vertical via 180A may be connected to the cell contact 160A through the upper interconnection line 170A. The second pad PAD2, the word line 130A, and the vertical via 180A disposed below the second pad PAD2 may be electrically isolated from each other. As an example, the vertical via 180A may extend to the lower interconnection line 230 through a region where a sacrificial layer for forming the word line 130 is not removed but remains.

[0065] Figure 7B Can be Fig. 7A The equivalent circuit diagram of the memory device shown in FIG. Figure 7B Each of the first cell region 100A and the second cell region 100B may include a memory cell MC, a ground selection transistor GST, a first string selection transistor SST1, a second string selection transistor SST2, etc. The ground selection transistor GST may be connected to a common source line CSL, and the second string selection transistor SST2 may be connected to a bit line BL.

[0066] exist Fig. 7A and Figure 7B In the example embodiment shown in , the first unit region 100A and the second unit region 100B may not share the transmission element PT. Figure 7B , the transfer elements connected to the memory cells MC, the ground selection transistor GST, the first string selection transistor SST1, and the second string selection transistor SST2 in the first cell region 100A may be isolated from the second cell region 100B.

[0067] The transmission element PT connected to the first cell region 100A may be controlled by the first block selection signal BS1, and the transmission element PT connected to the second cell region 100B may be controlled by the second block selection signal BS2. According to the settings of the first block selection signal BS1 and the second block selection signal BS2, the first cell region 100A and the second cell region 100B may be driven simultaneously or independently.

[0068] Fig. 8A and Figure 8B Regions of a memory device according to some example embodiments are shown.

[0069] Fig. 8A may be a cross-sectional view illustrating a region of a memory device according to some example embodiments, Figure 8B Can be with Fig. 8A The corresponding equivalent circuit diagram. Fig. 8A and Figure 8B The memory device of the described example embodiment can be used with reference to Fig. 7A and Figure 7B The memory devices of the described example embodiments are the same. However, Fig. 8A The area shown in Fig. 7A As an example, in accordance with reference Fig. 8A and Figure 8B In the memory device of some example embodiments described above, the second cell contact region may be Figure 6B The regions described correspond to each other.

[0070] Reference Fig. 8A , the memory device may include a peripheral circuit region 200 and a cell region 100 disposed above the peripheral circuit region 200. The peripheral circuit region 200 may include a first substrate 210, a plurality of circuit elements 220 formed on the first substrate 210, lower interconnection lines 230 connected to the circuit elements 220, a lower interlayer dielectric 240, etc. The peripheral circuit region 200 may be formed from Fig. 7A The area of ​​the memory device shown in extends continuously.

[0071] The unit region 100 may include a second unit region 100B and a third unit region 100C. The second unit region 100B and the third unit region 100C may have the same Fig. 7A The structure of the first unit region 100A described above is the same as that of the first unit region 100A. Fig. 8A The second cell region 100B shown in FIG. 1 describes in detail the cell array region CA and the second cell contact region CT2 included in the cell region 100 .

[0072] The second cell region 100B may include a second substrate 110B disposed on the lower interlayer dielectric 240, and a plurality of word lines 131B to 136B (130B) may be stacked on the second substrate 110B in a third direction (Z-axis direction) perpendicular to the upper surface of the second substrate 110B. String selection lines 141B to 142B (140B) and a ground selection line 120B may be disposed above and below the word line 130B, respectively. A channel structure 150B may extend in a third direction and may penetrate the word line 130B, the string selection line 140B, and the ground selection line 120B. The channel structure 150B may include a data storage layer 151B, a channel layer 152B, a buried insulating layer 153B, etc., and the channel layer 152B may be electrically connected to the bit line BL through a bit line contact BLC. In some example embodiments, the bit line BL may extend in the second direction (Y-axis direction). A region in which the channel structure 150B, the bit line BL, etc. are disposed may be defined as a cell array region CA.

[0073] The word line 130B may extend in the first direction (X-axis direction) and may be connected to a plurality of cell contacts 161B to 164B (160B) in the second cell contact region CT2 adjacent to the cell array region CA in the first direction. In some example embodiments, the word line 130B may extend in different lengths from each other in the first direction and the second direction to provide pads PAD1 and PAD2. The cell contact 160B and the word line 130B may be connected to each other at a portion of the pad PAD1.

[0074] With reference Fig. 7A Similar to the first cell contact region CT1 described, the second cell contact region CT2 may include at least one second pad PAD2 different from the first pad PAD1. The second pad PAD2 may have an area larger than that of each of the first pads PAD1. In some example embodiments, the length of the second pad PAD2 in the first direction may be larger than the length of each of the first pads PAD1 in the first direction.

[0075] Reference Fig. 7A and Fig. 8A In both cases, the number of second pads PAD2 included in the first cell contact region CT1 in the second cell region 100B may be greater than the number of second pads PAD2 included in the second cell contact region CT2 in the second cell region 100B. Therefore, the second cell contact region CT2 may extend to be relatively shorter than the first cell contact region CT1 in the first direction, and the integration density of the cell regions 100A, 100B, and 100C may be increased.

[0076] As an example, the cell regions 100B and 100C adjacent to each other may share at least one of the transmission elements, and the second cell contact region CT2 is interposed between the cell regions 100B and 100C adjacent to each other. Fig. 8A , the circuit element 220 may include a first transmission element 221 and a second transmission element 222. At least a portion of the word line 130B among the word lines 130B included in the second cell region 100B may share the second transmission element 222 with the word line included in the third cell region 100C. The word lines sharing the second transmission element 222 may be disposed at the same height in the third direction.

[0077] Reference Fig. 8A , the second cell contact region CT2 may include common vertical vias 181B to 183B (180B), and the common vertical vias 181B to 183B (180B) connect the lower interconnection line connected to the second transmission element 222 to some of the cell contacts 161B to 163B among the cell contacts 160B. The common vertical vias 180B may be commonly connected to at least part of the word lines of the second cell region 100B and the third cell region 100C through the common upper interconnection lines 171B to 173B (170B). The common upper interconnection lines 171B to 173B may be arranged in different positions from each other in the second direction to be electrically isolated from each other. The common vertical vias 180B may extend to the peripheral circuit region 200 without penetrating the second substrate 110B.

[0078] Among the cell contacts 160B, some of the cell contacts 164B may be connected to the first transmission element 221 of the peripheral circuit region 200 through individual vertical vias 191B. Individual vertical vias 191B may be connected to the cell contacts 164B through individual upper interconnection lines 192B. As an example, individual vertical vias 191B may extend from at least one of the pads PAD2 to the peripheral circuit region 200.

[0079] like Fig. 8AAs shown in, in the second cell contact region CT2, portions of the word lines included in the adjacent cell regions 100B and 100C may be connected to the common vertical via 180B to share the second transfer element 222. Therefore, the number of second pads PAD2 for extending the individual vertical vias 191B to the peripheral circuit region 200 may be reduced, and the area of ​​the second cell contact region CT2 may be reduced to increase the integration density of the memory device 100. In addition, in some embodiments, the sum of the areas of the first pad PAD1 and the second pad PAD2 included in the first cell contact region CT1 is larger than the sum of the areas of the first pad PAD1 and the second pad PAD2 included in the second cell contact region CT2. In addition, in some embodiments, the sum of the number of the first pad PAD1 and the second pad PAD2 included in the first cell contact region CT1 is larger than the sum of the number of the first pad PAD1 and the second pad PAD2 included in the second cell contact region CT2.

[0080] Figure 8B Can be Fig. 8A The equivalent circuit diagram of the memory device shown in FIG. Figure 8B Each of the second and third cell regions 100B and 100C may include a memory cell MC, a ground selection transistor GST, a first string selection transistor SST1, a second string selection transistor SST2, etc. The ground selection transistor GST may be connected to a common source line CSL, and the second string selection transistor SST2 may be connected to a bit line BL.

[0081] The transmission elements PT1 and PT2 connected to the memory cells MC may be divided into the first transmission element PT1 and the second transmission element PT2 according to whether the transmission elements PT1 and PT2 connected to the memory cells MC are commonly connected to the second cell region 100B and the third cell region 100C. For example, the first transmission element PT1 may be connected to the memory cells MC of any one of the second cell region 100B and the third cell region 100C, and the second transmission element PT2 may be commonly connected to a portion of the memory cells MC included in the second cell region 100B and the third cell region 100C.

[0082] When the control operation is performed on the third cell region 100C, the second transfer element PT2 may be turned on using the first block selection signal BS1. However, the second cell region 100B and the third cell region 100C may be driven independently of each other by controlling a voltage input to the second cell region 100B through the first transfer element PT1 connected to the second cell region 100B. In example embodiments, the second cell region 100B and the third cell region 100C may be driven simultaneously.

[0083] Fig. 9 and Fig.10shows a schematic configuration of a memory device according to some example embodiments.

[0084] First refer to Fig. 9 , the memory device 300 may include a peripheral circuit region P and cell regions C1 and C2. The memory device 300 may have a cell-on-periphery (COP) structure in which the cell regions C1 and C2 are disposed above the peripheral circuit region P. For example, the cell regions C1 and C2 may be disposed above the peripheral circuit region P along a third direction (Z-axis direction). The peripheral circuit region P may include a plurality of circuit elements formed on the first substrate 301, and may be divided into a first peripheral circuit region P1 and a second peripheral circuit region P2.

[0085] The cell regions C1 and C2 may include a first cell region C1 and a second cell region C2 disposed in a first direction (X-axis direction). The first cell region C1 and the second cell region C2 may be formed in second substrates 302 and 303 that are different from each other, respectively. Each of the first cell region C1 and the second cell region C2 may include a cell array region CA, a first cell contact region CT1 disposed on both sides of the cell array region CA in the first direction, and a second cell contact region CT2. The first cell region C1 and the second cell region C2 may have the same structure and may be disposed to be horizontally symmetrical or substantially symmetrical with respect to a boundary between the first cell region C1 and the second cell region C2.

[0086] Referring to the first cell region C1, the cell array region CA may include first and second memory blocks BLK1 and BLK2 divided in the second direction (Y-axis direction). As an example, the first and second memory blocks BLK1 and BLK2 may be divided by a word line cutting region extending in the first direction.

[0087] The word lines of the first memory block BLK1 may extend in the first direction to provide a first connection region CR1 included in the first cell contact region CT1 and a second connection region CR2 included in the second cell contact region CT2. In addition, the word lines of the second memory block BLK2 may extend in the first direction to provide a first connection region CR1 included in the second cell contact region CT2 and a second connection region CR2 included in the first cell contact region CT1.

[0088] The first connection region CR1 and the second connection region CR2 may include a first pad and a second pad provided by a word line. In the first connection region CR1, the first pad and the second pad may form a step in the first direction and the second direction, that is, they may have different depths in the cross-sectional direction. In the second connection region CR2, the first pad and the second pad may form a step in the first direction. In some example embodiments, each of the first pads may be shorter than each of the second pads in the first direction.

[0089] In an example, the word lines of the first memory block BLK1 may be connected to a plurality of cell contacts in the first connection region CR1 of the first cell contact region CT1. At least a portion of the cell contacts connected to the word lines of the first memory block BLK1 in the first connection region CR1 of the first cell contact region CT1 may be connected to the transfer elements of the first peripheral circuit region P1 in the second connection region CR2 of the first cell contact region CT1.

[0090] A plurality of vertical vias connected to the transfer elements may be disposed in at least portions of the first pad and the second pad in the second connection region CR2 of the first cell contact region CT1. In some example embodiments, the vertical vias may be connected to at least portions of the cell contacts connected to the word lines of the first memory block BLK1 in the first connection region CR1 of the first cell contact region CT1 through upper interconnection lines extending in the second direction.

[0091] The cell contacts connected to the word lines of the first memory block BLK1 in the first connection region CR1 of the second cell contact region CT2 may be connected to the transmission elements of the first peripheral circuit region P1 in the second connection region CR2 of the second cell contact region CT2 or the transmission elements of the first peripheral circuit region P1 in the boundary region between the first cell region C1 and the second cell region C2. A plurality of vertical vias connected to the transmission elements may be provided in the second connection region CR2 of the second cell contact region CT2 and the boundary region BA.

[0092] Among the plurality of vertical vias, a vertical via disposed in the second connection region CR2 of the second cell contact region CT2 may be connected to at least a portion of a cell contact connected to a word line of the second memory block BLK2 in the first connection region CR1 of the second cell contact region CT2 through an upper interconnection line disposed above the first cell region C1. Among the vertical vias, a vertical via disposed in the boundary region BA may be connected to a cell contact connected to a word line of the second memory block BLK2 in the first connection region CR1 of the second cell contact region CT2 through an upper interconnection line disposed above the first cell region C1.

[0093] The vertical vias disposed in the boundary area BA may be commonly connected to a portion of the word line of the second memory block BLK2 and a portion of the word line of the fourth memory block BLK4. Portions of the word lines of the second memory block BLK2 and the fourth memory block BLK4 may share a transmission element through the vertical vias disposed in the boundary area BA. Therefore, the number of second pads PAD2 in the second cell contact area CT2 adjacent to the boundary area BA may be reduced, and the distance between the first cell area C1 and the second cell area C2 may be reduced to increase the integration density of the memory device 300.

[0094] exist Fig. 9 In the example embodiment shown in , part of the transmission elements disposed under the second cell contact region CT2 may be shared by word lines included in different memory blocks BLK1 to BLK4. Therefore, the number of transmission elements disposed under the first cell contact region CT1 may be greater than the number of transmission elements disposed under the second cell contact region CT2.

[0095] Reference Fig.10 , the memory device 300A may include a peripheral circuit region P and cell regions C1 and C2. The configuration of the peripheral circuit region P and the cell regions C1 and C2 may be similar to that of the reference Fig. 9 The configurations of the peripheral circuit region P and the cell regions C1 and C2 described are similar. However, the first cell region C1 and the second cell region C2 may be formed together on one second substrate 302. Therefore, the vertical via formed in the boundary region BA may be connected to the transmission element of the first peripheral circuit region P1 through the second substrate 302. In the boundary region BA, a substrate insulating layer may be provided to electrically isolate the vertical via and the second substrate 302 from each other.

[0096] Figures 11 to 14 is a schematic plan view of a memory device according to some example embodiments. Fig.15 is along Fig.11 A cross-sectional view taken along line II' in FIG. Fig.16 is along Fig.11 A cross-sectional view taken along line II-II'. Fig.17 is along Fig.12 A cross-sectional view taken along line III-III' in FIG. Fig.18A and Fig.18B yes Fig.17 Schematic diagram of the transmission element shown in .

[0097] Reference Fig.11 and Fig.12, the memory device 400 may include a first memory block 410 and a second memory block 420. Each of the first memory block 410 and the second memory block 420 may include a cell array region CA and first and second cell contact regions CT1 and CT2 disposed on both sides of the cell array region CA in a first direction (X-axis direction). The first memory block 410 and the second memory block 420 may be adjacent to each other in a second direction (Y-axis direction).

[0098] Each of the first cell contact region CT1 and the second cell contact region CT2 may include a first connection region CR1 and a second connection region CR2. Fig.11 and Fig.12 , the first cell contact region CT1 of the first memory block 410 may provide the first connection region CR1, and the second cell contact region CT2 of the first memory block 410 may provide the second connection region CR2. The first cell contact region CT1 of the second memory block 420 may provide the second connection region CR2, and the second cell contact region CT2 of the second memory block 420 may provide the first connection region CR1.

[0099] The first pad PAD1 and the second pad PAD2 may be formed in the first connection region CR1 and the second connection region CR2. In the first connection region CR1, the first pad PAD1 and the second pad PAD2 may form steps in the first direction and the second direction. In the second connection region CR2, the first pad PAD1 and the second pad PAD2 may form steps in the first direction.

[0100] Each of the second pads PAD2 may have an area greater than that of each of the first pads PAD 1. As an example, the second pads PAD2 may extend in the first direction to be longer than the first pads PAD 1. Fig.11 and Fig.12 The first pad PAD1 and the second pad PAD2 shown in the figure may be example embodiments, and the lengths of the first pad PAD1 and the second pad PAD2 may be changed differently. As an example, the length of each of the second pads PAD2 in the first direction may be at least 10 times the length of each of the first pads PAD1 in the first direction.

[0101] The first memory block 410 and the second memory block 420 may include a plurality of word lines WL stacked in a third direction (Z-axis direction). In the cell array region CA, a plurality of channel structures CH may be provided to extend in the third direction and penetrate the word lines WL. The plurality of word lines WL may be divided into the first memory block 410 and the second memory block 420 by a word line cutting portion WC.

[0102] The first cutting line CL1 and the second cutting line CL2 may be disposed between the word line cutting parts WC closest to each other in the second direction. The first cutting line CL1 may be formed in the cell array region CA and the cell contact regions CT1 and CT2, while the second cutting line CL2 may be formed only in the cell contact regions CT1 and CT2. Fig.11 and Fig.12 In the example embodiment shown in , the second cutting line CL2 may not be formed in the second connection region CR2.

[0103] In the first pad PAD1 and the second pad PAD2 formed in the first connection region CR1, the word line WL may be connected to the cell contact CC. At least a portion of the cell contact CC may be connected to at least a portion of a plurality of vertical vias VV formed in the second connection region CR2. In the cell array region CA, the vertical vias VV may be connected to the cell array region CA and circuit elements below the cell contact regions CT1 and CT2. As an example, the vertical vias VV may be connected to a transmission element disposed below the cell contact regions CT1 and CT2. The number and arrangement of the vertical vias VV are not limited to Fig.11 and Fig.12 The number and arrangement of the vertical vias VV may be variously disposed in the second connection region CR2 according to the number and arrangement shown in FIG. The number and arrangement of the vertical vias VV may be determined in consideration of the wiring of the word lines WL.

[0104] As described above, among the first cutting line CL1 and the second cutting line CL2, the second cutting line CL2 may not be formed in the second connection region CR2. Therefore, the process of introducing phosphoric acid through the grooves for forming the word line cutting part WC and the first cutting line CL1 and the second cutting line CL2 to replace the sacrificial layer with the word line WL may not be performed in the portion of the second connection region CR2. The vertical via VV may extend in the third direction in the region where the word line WL is not formed and the sacrificial layer is retained to be connected to the transmission element below.

[0105] Reference Fig.11 , the first cell contact region CT1 may include five second pads PAD2 arranged in the first direction. Fig.12 , the second cell contact region CT2 may include three second pads PAD2 arranged in the first direction. Therefore, the first memory block 410 and the second memory block 420 may have an asymmetric structure with respect to the cell array area CA in the first direction.

[0106] Reference Fig.11 and Fig.12, among the second pads PAD2 included in the first cell contact region CT1, a portion of the second pad PAD2 away from the cell array region CA may be omitted in the second connection region CR2 in consideration of the wiring of the cell contacts CC connected to the word lines WL and the vertical vias VV connected to the cell contacts CC. In some example embodiments, when the channel structure CH includes a lower channel structure and an upper channel structure connected to each other in the third direction, the second pad PAD2 included in the second cell contact region CT2 may be provided only by the upper word line through which the upper channel structure penetrates. For example, the lower word line through which the lower channel structure penetrates may provide only the first pad PAD1.

[0107] Since the number of second pads PAD2 included in the second cell contact region CT2 is smaller than the number of second pads PAD2 included in the first cell contact region CT1, an additional method of providing a vertical via VV to connect the cell contact CC and the transfer element to each other is required. In some example embodiments, the vertical via VV may be provided between the second cell contact regions CT2 adjacent to each other along the first direction to connect to the cell contact CC. The transfer element provided between the second cell contact regions CT2 adjacent to each other along the first direction may be commonly connected to at least a portion of the word lines of the memory blocks different from each other to solve the connection problem of the cell contact CC and the transfer element. Hereinafter, reference will be made to Fig.13 and Fig.14 Describe this.

[0108] Reference Fig.13 and Fig.14 , the memory device 400 may include first to fourth memory blocks 410 to 440. The first connection region CR1 of the first memory block 410 and the first connection region CR1 of the third memory block 430 may be adjacent to each other in the first direction, and the second connection region CR2 of the second memory block 420 and the second connection region CR2 of the fourth memory block 440 may be adjacent to each other in the first direction.

[0109] The transfer elements PT1 and PT2 may be disposed between the first cell region 400A having the first and second memory blocks 410 and 420 and the second cell region 400B having the third and fourth memory blocks 430 and 440. The transfer elements PT1 and PT2 may be formed in a peripheral circuit region disposed below the cell regions 400A and 400B, and may include the first transfer element PT1 and the second transfer element PT2.

[0110] At least part of the first transfer element PT1 may include at least part of the word line WL of the first memory block 410 and at least part of the word line WL of the third memory block 430. The second transfer element PT2 may be disposed between the second connection region CR2 of the first cell region 400A and the second connection region CR2 of the second cell region 400B to reduce complexity of interconnection lines connecting at least part of the word line WL and the second transfer element PT2 to each other.

[0111] exist Fig.13 In the example embodiment shown in , the first unit region 400A and the second unit region 400B may be disposed on different second substrates 401A and 401B. Fig.14 In the example embodiment shown in FIG. 4 , the first unit region 400A and the second unit region 400B may be disposed on one second substrate 401. Fig.14 In the example embodiment shown in , the vertical via VV connected to the second transmission element PT2 may penetrate the second substrate 401. In some example embodiments, a substrate insulating layer 403 may be formed on the second substrate 401 so that the vertical via VV and the second substrate 401 are isolated from each other. Fig.15 Can be along Fig.11 A cross-sectional view taken along line II' in FIG. Fig.11 , Fig.15 and Fig.16 , the memory device 400 may include a peripheral circuit region P and a cell region C above the peripheral circuit region P. The peripheral circuit region P may include a first substrate 405 and a circuit element formed on the first substrate 405. For example, the circuit element may be a transmission element 406 included in a row decoder and electrically connected to a word line WL, and the circuit element may be covered by a lower interlayer dielectric 408.

[0112] The cell region C may be formed in the second substrate 401 on the lower interlayer dielectric 408. Fig.15 In, along Fig.11 The cross section taken along the line II' in FIG. 4 may correspond to the second connection region CR2 of the memory device 400. The second cutting line CL2 may not be formed and the sacrificial layer SL may not be removed but may remain in the second connection region CR2. Fig.15 As shown in FIG. 4 , the sacrificial layers SL and the insulating layers IL may be alternately stacked on the second substrate 401. The sacrificial layers SL and the insulating layers IL may include insulating materials different from each other.

[0113] In the second connection region CR2, the sacrificial layer SL and the insulating layer IL may provide a first pad PAD1 and a second pad PAD2. In the first direction (X-axis direction), the length D1 of each of the first pads PAD1 may be smaller than the length of each of the second pads PAD2. A vertical via VV may be formed in the second pad PAD2 and may extend to the peripheral circuit region P to be connected to the transmission element 406. In the region through which the vertical via VV penetrates, the second substrate 401 may be formed of an insulating material.

[0114] Fig.16 Can be along Fig.11 A cross-sectional view taken along line II-II' in FIG. Fig.17 Can be along Fig.12 A cross-sectional view taken along line III-III' in FIG. Fig.11 and Fig.12 , Fig.16 may be a cross-sectional view showing a portion of the second connection region CR2 of the first cell contact region CT1, Fig.17 may be a cross-sectional view illustrating a portion of the second connection region CR2 of the second cell contact region CT2.

[0115] In some example embodiments, the second connection region CR2 of the first cell contact region CT1 and the second connection region CR2 of the second cell contact region CT2 may have different structures from each other. Fig.16 and Fig.17 , the second connection region CR2 of the first cell contact region CT1 and the second connection region CR2 of the second cell contact region CT2 may have structures different from each other at a certain height or less from the upper surface of the second substrate 401. Such a difference in structure may be caused by a difference between the number of second pads PAD2 included in the second connection region CR2 of the first cell contact region CT1 and the number of second pads PAD2 included in the second connection region CR2 of the second cell contact region CT2.

[0116] In some example embodiments, the number of second pads PAD2 included in the second connection region CR2 of the first cell contact region CT1 may be greater than the number of second pads PAD2 included in the second connection region CR2 of the second cell contact region CT2. Since the second connection region CR2 of the first cell contact region CT1 may include a greater number of second pads PAD2 than the second connection region CR2 of the second cell contact region CT2, the first cell contact region CT1 may extend in the first direction to be longer than the second cell contact region CT2. Therefore, the length in the first direction of at least one of the word lines WL extending to the first cell contact region CT1 (first side) of the cell array region CA may be different from the length in the first direction of at least one of the word lines WL extending to the second cell contact region CT2 (second side) of the cell array region CA. For example, the lowermost word line WL may extend in the first direction to be longer than the second cell contact region CT2 in the first cell contact region CT1.

[0117] As an example, the difference between the number of second pads PAD2 included in the second connection region CR2 of the first cell contact region CT1 and the number of second pads PAD2 included in the second connection region CR2 of the second cell contact region CT2 may be two or more. In some example embodiments, the length of the second cell contact region CT2 in the first direction may be greater than 0.6 times the length of the first cell contact region CT1 in the first direction and less than 0.9 times the length of the first cell contact region CT1 in the first direction. In some example embodiments, the length of each of the second pads PAD2 in the first direction may be greater than or equal to ten times the length of each of the first pads PAD1 in the first direction. Compared with the first cell contact region CT1, the number of second pads PAD2 included in the cell contact region CT2 may be reduced by two or more to obtain the above-mentioned length reduction effect.

[0118] Reference Fig.17 , the transmission elements 406 and 407 may include a first transmission element 406 and a second transmission element 407. The second transmission element 407 may be disposed outside the second connection region CR2 of the second cell contact region CT2 in the first direction, and may include at least two word lines WL passing through the vertical via hole VV. The second transmission element 407 may be connected to two or more word lines WL, and the number of second pads PAD2 included in the second connection region CR2 of the second cell contact region CT2 may be reduced. Therefore, the integration density of the memory device 400 may be increased.

[0119] Since the second transfer element 407 may be connected to two or more word lines WL to simultaneously drive the two or more word lines WL, the second transfer element 407 may have a shape or / and size different from that of the first transfer element 406. Fig.18A and Fig.18B , each of the first transfer element 406 and the second transfer element 407 may include a gate G and a source region S and a drain region D on opposite sides adjacent to the gate G. As an example, a gate length Lg2 of the second transfer element 407 may be greater than a gate length Lg1 of the first transfer element 406. In some example embodiments, a length H2 of the source region S and the drain region D of the second transfer element 407 in the second direction may be greater than a length H1 of the source region S and the drain region D of the first transfer element 406 in the second direction. In example embodiments, the second transfer element 407 has an area greater than or equal to that of the first transfer element 406.

[0120] Fig.19 and Fig. 20 is a cross-sectional view illustrating a cell contact region of a memory device according to some example embodiments.

[0121] Reference Fig.19 , the memory device 500 may include a peripheral circuit region P and a cell region C stacked in a third direction (Z-axis direction). The peripheral circuit region P may include a first substrate 505, circuit elements 506 and 507 formed on the first substrate 505, a lower interlayer dielectric 508 covering the circuit elements 506 and 507, etc. As an example, the circuit elements 506 and 507 may be transmission elements included in a row decoder.

[0122] The cell region C may include a first cell region 500A and a second cell region 500B. In addition, the cell region C may include a plurality of second substrates 501A and 501B and a plurality of sacrificial layers SL and a plurality of insulating layers IL stacked on the plurality of second substrates 501A and 501B. The sacrificial layers SL and the insulating layers IL may provide steps in the first direction (X-axis direction) and the second direction (Y-axis direction), and the first pads PAD1 and the second pads PAD2 may be formed by the steps. Each of the first pads PAD1 may have a length shorter than that of each of the second pads PAD2 in the first direction.

[0123] exist Fig.19 In the example embodiment shown in , the sacrificial layer SL may be a layer that is retained and not removed in the process of forming the word line. The sacrificial layer SL may be retained in the region in which the plurality of vertical vias VV are formed. In the region in which the vertical vias VV are not formed, the sacrificial layer SL may be replaced by the word line. The vertical vias VV may be connected to the transmission elements 506 and 507 through the sacrificial layer SL and the insulating layer IL.

[0124] As an example, at least one of the vertical vias VV may be connected to the first transmission element 506 through the sacrificial layer SL and the insulating layer IL in the second pad PAD2. At least one of the vertical vias VV may be connected to the second transmission element 507 in the boundary area BA between the second substrate 501A of the first unit region 500A and the second substrate 501B of the second unit region 500B.

[0125] The second transmission element 507 may be connected to a pair of word lines included in the first cell region 500A and the second cell region 500B through a vertical via VV, an upper interconnection line UW, and a cell contact CC. As an example, the pair of word lines may be arranged at the same height in the third direction. Fig.19 In the example embodiment shown in , a pair of word lines may be disposed behind the sacrificial layer SL in the second direction.

[0126] Reference Fig. 20 , the memory device 600 may include a peripheral circuit region P and a cell region C. The configuration of the peripheral circuit region P and the cell region C may be the same as that described above with reference to Fig.19 The configuration of the described memory device 500 is similar. For example, the cell region C may include a first cell region 600A and a second cell region 600B adjacent to each other in the first direction.

[0127] exist Fig. 20 In the example embodiment shown in , the first unit region 600A and the second unit region 600B may be disposed on one second substrate 601. For example, the second substrate 601 may extend from the first unit region 600A to the second unit region 600B. At least one of the vertical vias VV may penetrate the base insulating layer 603 formed in the boundary region BA between the first unit region 600A and the second unit region 600B to extend to the peripheral circuit region P.

[0128] Each word line in the memory devices 500 and 600 may have substantially the same thickness as each sacrificial layer SL. The gate length of each memory cell may be determined by the thickness of each word line, and the characteristics of each memory cell may vary according to the thickness of each word line. In example embodiments, the thickness of each word line may vary according to whether each word line is independently connected to the first transmission element 506 and 606 or shares the second transmission element 507 and 607 with at least one of the other word lines, etc., wherein the word lines are arranged in the cell region C in the third direction.

[0129] Fig.21 is a cross-sectional view illustrating a cell array region of a memory device according to some example embodiments.

[0130] Reference Fig.21 , the memory device 700 may include a peripheral circuit region P and a cell region C, and the cell region C may be disposed above the peripheral circuit region P. The peripheral circuit region P includes a first substrate 701, a circuit element 702 formed on the first substrate 701, a lower interconnection line 703 connected to the circuit element 702, a lower interlayer dielectric 704, etc. As an example, the circuit element 702 may provide a page buffer, etc.

[0131] The cell region C may include word lines WL stacked on the second substrate 710, a channel structure CH penetrating the word lines WL (see FIG. Fig. 22 ) and a word line cutting portion WC that divides the word line WL into a plurality of regions. The word line WL may be alternately stacked with the insulating layer IL, and may extend in a first direction (X-axis direction) and a second direction (Y-axis direction) to form a pad having a step. As described above in various embodiments, the pad may include a first pad and a second pad, and each of the first pads may have a length shorter than a length of each of the second pads in the first direction. As an example, Fig.21 The memory device 700 shown in FIG. 7 may include the memory device 700 shown in FIG. Fig.11 and Fig.12 The first cell contact region and the second cell contact region are described, and the first cell contact region and the second cell contact region may be disposed on both sides of the cell region C in the first direction.

[0132] The channel structure CH may be connected to the bit line BL through the bit line contact BLC. Fig.21 , the channel structures CH disposed in the same position in the first direction are shown to be connected to one bit line BL. However, the position of the channel structure CH is not limited thereto. The bit line contact BLC may penetrate the upper interlayer dielectric 705 to connect the channel structure CH and the bit line BL to each other.

[0133] The second substrate 710 may include a first layer 711 to a third layer 713. The channel structures CH disposed between the word line cut portions WC may be connected to each other through the first layer 711 to the third layer 713 to be connected to a single common source line. Fig. 22 , Fig.23A , Fig. 23B , Fig.24A and Fig. 24B Describe in further detail Fig.21 The memory device 700 shown in FIG.

[0134] Fig. 22 , Fig.23A , Fig. 23B , Fig.24A and Fig. 24B yes Fig.21 Magnified view of the area in .

[0135] Fig. 22 Can be Fig.21 Magnified view of area B in . Fig. 22 , the second substrate 710 may include first to third layers 711 to 713. The channel structure CH may include a data storage layer 720, a channel layer 730, a buried insulating layer 740, and the like.

[0136] Each of the first to third layers 711 to 713 of the second substrate 710 may include polysilicon doped with impurities having a first conductivity type. As an example, the first to third layers 711 to 713 may be doped with N-type impurities. Fig.21 Among the first to third layers 711 to 713 included in the second substrate 710, the third layer 713 and the second layer 712 may be isolated from each other by the word line cut portion WC in the second direction. Therefore, the channel structures CH disposed between a pair of word line cut portions WC adjacent to each other along the second direction may be connected to each other through the second substrate 710.

[0137] The data storage layer 720 may include a plurality of layers 721 to 723. As an example, the data storage layer 720 may include a blocking layer 721, a charge storage layer 722, and a tunneling layer 723. The number, arrangement order, and materials of the layers 721 to 723 included in the data storage layer 720 may be variously changed. The channel layer 730 may be formed of a semiconductor material (e.g., polysilicon, etc.), and an inner space of the channel layer 730 may be filled with a buried insulating layer 740 such as silicon oxide, etc.

[0138] Fig.23A and Fig. 23B Can be Fig.21 Magnified view of areas C1 and C2 in Figure 2. Fig.23A and Fig. 23B , the channel structure CH may penetrate the word line WL and the insulating layer IL, and the word line WL and the insulating layer IL may be divided into a plurality of regions by the word line cutting portion WC.

[0139] In accordance with Fig.21 In the memory device 700 of the example embodiment shown in , the channel structure CH and the word line cut portion WC may have a shape whose width decreases in the third direction (Z direction) toward the second substrate 710. For example, the side surfaces of the channel structure CH and the word line cut portion WC in the cross section may not be completely perpendicular to the upper surface of the second substrate 710, and may have a gently inclined shape. Fig.23A and Fig. 23B , the word line cutting portion WC has a first width Y1 in a region C1 disposed in a relatively high position, and has a second width Y2 smaller than the first width Y1 in a region C2 disposed in a relatively low position.

[0140] Therefore, if Fig.23A and Fig. 23B As shown in , the first width W1 of the word line WL disposed in the region C1 may be smaller than the second width W2 of the word line WL disposed in the region C2. Due to the difference in width, the resistance of the word line WL in the region C1 may be higher than the resistance of the word line WL in the region C2. In some example embodiments, the connection relationship between the word line WL and the transfer element may be determined in consideration of the resistance difference between the word lines WL.

[0141] The memory device 700 according to some example embodiments may include first and second pass elements disposed in the peripheral circuit region P, and each of the second pass elements may be connected to at least two word lines WL. As described above, each of the second pass elements may be shared by word lines WL disposed at the same height in cell regions different from each other. On the other hand, each of the first pass elements may be connected to a single word line WL.

[0142] In some example embodiments, the second transfer element may be connected to a word line WL having a relatively low resistance. Fig.23A and Fig. 23B In the example embodiment shown in , the word lines WL with relatively high resistance in region C1 may be connected to the first pass element, and the word lines WL with relatively low resistance in region C2 may be connected to the second pass element. In one cell region C of the memory device 700, the number of word lines WL connected to the first pass element may be greater than the number of word lines WL connected to the second pass element.

[0143] In some example embodiments, at least portions of the word lines WL may be formed to have different thicknesses from each other to reduce a deviation in resistance characteristics of the word lines WL. Fig.24A and Fig. 24B , the word line WL in the region C1 may be formed to have a first thickness T1, and the word line WL in the region C2 may be formed to have a second thickness T2. The first thickness T1 may be greater than the second thickness T2.

[0144] Therefore, in Fig.24A and Fig. 24B In the example embodiment shown in , the difference between the resistance of the word line WL in the region C1 and the resistance of the word line WL in the region C2 can be reduced. If necessary, the word line WL in the region C1 can also be connected to the second pass element. As an example, the word line WL in the region C1 can be connected to the second pass element, and the word line WL in the region C2 can be connected to the first pass element.

[0145] Optionally, with Fig.24A and Fig. 24BAs compared to the example embodiment shown in , each of the word lines WL in the region C2 may be formed to have a thickness higher than that of each of the word lines WL in the region C1, and the word lines WL in the region C2 may be connected to the second transfer element. Since the resistance of the word lines WL in the region C2 connected to the second transfer element is reduced, the load of the second transfer element may be reduced, and according to example embodiments, the second transfer element may be formed to have the same size as that of the first transfer element.

[0146] Fig.25 is a cross-sectional view illustrating a cell array region of a memory device according to some example embodiments.

[0147] Reference Fig.25 , the memory device 800 may include a peripheral circuit region P and a cell region C, and the cell region C may be disposed above the peripheral circuit region P. The configuration of the peripheral circuit region P may be similar to that of the reference Fig.21 The configuration of the peripheral circuit region P in the described memory device 700 is similar.

[0148] The cell region C may include word lines LWL, DWL, and UWL stacked on the second substrate 810, a channel structure CH penetrating the word lines LWL, DWL, and UWL, and a word line cutting portion WC dividing the word lines LWL, DWL, and UWL into a plurality of regions. The second substrate 810 may include a first layer 811 to a third layer 813, which may be formed according to the reference Fig. 22 The configuration of the second substrate 810 is understood through the description.

[0149] The word lines LWL, DWL, and UWL may include a lower word line LWL, at least one dummy word line DWL, and an upper word line UWL. The lower word line LWL may be stacked from the upper surface of the second substrate 810, and the lower channel structure CH2 extending from the upper surface of the second substrate 810 may penetrate the lower word line LWL. The upper word line UWL may be stacked on the lower word line LWL, and the upper channel structure CH1 extending from the lower channel structure CH2 may penetrate the upper word line UWL.

[0150] The dummy word line DWL may be disposed between the lower word line LWL and the upper word line UWL. As an example, a boundary region between the upper channel structure CH1 and the lower channel structure CH2 may be buried in the dummy word line DWL. According to example embodiments, another dummy word line DWL may be added in a different position.

[0151] In accordance with Fig.25In the memory device 800 of the example embodiment shown in , the channel structure CH can be formed by dividing the channel structure CH into an upper channel structure CH1 and a lower channel structure CH2. On the other hand, the word line cutting portion WC can be formed at one time. Therefore, in a plane parallel to the first direction (X-axis direction) and the second direction (Y-axis direction), each of the upper word lines UWL can have an area smaller than that of each of the lower word lines LWL, and the resistance of the upper word lines UWL can be increased. In the following, reference will be made to FIG. 26A to FIG. 27B This is described in further detail.

[0152] Fig.26A , Fig.26B , Fig.27A and Fig.27B yes Fig.25 Magnified view of the area in .

[0153] Fig.26A and Fig.26B Can be Fig.25 Magnified view of regions E1 and E2 in FIG. Fig.26A , the upper channel structure CH1 may penetrate the upper word line UWL and the insulating layer IL, and the upper word line UWL and the insulating layer IL may be divided into a plurality of regions by the word line cutting portion WC. Fig.26B , the lower channel structure CH2 may penetrate the lower word line LWL and the insulating layer IL, and the lower word line LWL and the insulating layer IL may be divided into a plurality of regions by the word line cutting portion WC.

[0154] Each of the upper and lower channel structures CH1 and CH2 may include a data storage layer 820 , a channel layer 830 , a buried insulating layer 840 , etc. The data storage layer 820 may include a blocking layer 821 , a charge storage layer 822 , a tunneling layer 823 , and the like.

[0155] As an example, the height from the lower surface of the upper channel structure CH1 to the region E1 may be the same as the height from the lower surface of the lower channel structure CH2 to the region E2. Therefore, the upper channel structure CH1 and the lower channel structure CH2 may have substantially the same size in each of the regions E1 and E2. However, the word line cut portion WC may be formed in the entire cell region C in one process, and the width of the word line cut portion WC may be gradually reduced in a direction toward the second substrate 810. Referring to Fig.26A and Fig.26B , a first width Y1 of the word line cutting portion WC in the region E1 may be greater than a second width Y2 of the word line cutting portion WC in the region E2.

[0156] Therefore, the first width W1 of the upper word line UWL in the region E1 may be smaller than the second width W2 of the lower word line LWL in the region E2, and the upper word line UWL may have a relatively higher resistance than the resistance of the lower word line LWL. In some example embodiments, considering the resistance characteristics, the upper word line UWL may be connected to the first transmission element, and at least a portion of the lower word line LWL may be connected to the second transmission element. Each of the first transmission elements may be an element connected to one of the upper word line UWL and the lower word line LWL, and each of the second transmission elements may be an element connected to two or more lower word lines LWL different from each other. The two or more lower word lines LWL connected to each of the second transmission elements may be included in cell regions C different from each other.

[0157] exist Fig.27A and Fig.27B In the example embodiment shown in , at least a portion of the upper word line UWL may have a thickness greater than that of the lower word line LWL. Fig.27A and Fig.27B , each upper word line UWL may have a first thickness T1, and each lower word line LWL may have a second thickness T2 that is smaller than the first thickness T1. Therefore, the resistance of the upper word line UWL may be reduced, and the upper word line UWL may be connected to the second transmission element as needed. The thickness of the upper word line UWL and the lower word line LWL may be changed differently. For example, the thickness of the lower word line LWL connected to the second transmission element may be increased to reduce the load of the second transmission element and improve the driving characteristics.

[0158] Fig.28 is a schematic block diagram of an electronic device including a memory device according to some example embodiments.

[0159] according to Fig.28 The electronic device 1000 of the exemplary embodiment shown in FIG. 1 may include a display 1010, a sensor unit 1020, a memory 1030, a communication unit 1040, a processor 1050, a port 1060, etc. The electronic device 1000 may also include a power supply, an input / output device, etc. Fig.28 Among the components shown in , a port 1060 may be provided to enable the electronic device 1000 to communicate with a graphics card, a sound card, a memory card, a USB device, etc. The electronic device 1000 may be a comprehensive concept including a typical desktop computer or a laptop computer as well as a smart phone, a tablet PC, a smart wearable device, etc.

[0160] The processor 1050 may perform specific arithmetic operations, commands, tasks, etc. The processor 1050 may be a central processing unit (CPU), a microprocessor unit (MCU), or a system on a chip (SoC), and may communicate with the display 1010, the sensor unit 1020, the memory 1030, the communication unit 1040, and other devices connected to the port 1060 via a bus 1070.

[0161] The memory 1030 may be a storage medium configured to store data for operation of the electronic device 1000, multimedia data, etc. The memory 1030 may include a volatile memory such as a random access memory (RAM) or a nonvolatile memory such as a flash memory, etc. The memory 1030 may include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical drive (ODD) as a storage device. Fig.28 In the example embodiment shown in FIG. 1 , the memory 1030 may include the memory 1031 according to the above reference Figures 1 to 27B Various embodiments of memory devices are described.

[0162] As described above, according to example embodiments, a memory device may include a peripheral circuit region and a cell region disposed above the peripheral circuit region. The cell region may have a cell array region in which a channel structure is disposed and a cell contact region in which a cell contact connected to a word line is disposed. The cell contact region may extend from the cell array region in a direction parallel to the upper surface of a substrate in which the cell region is formed, and may have different lengths from each other in at least one of the directions parallel to the upper surface of the substrate. In addition, at least a portion of the cell contacts may share a transmission element formed in the peripheral circuit region. Therefore, the integration density of the memory device may be increased.

[0163] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A memory device, comprising: The peripheral circuit area includes a row decoder and a page buffer; as well as a cell region, comprising a plurality of word lines stacked on each other, a plurality of channel structures penetrating the plurality of word lines, and a plurality of cell contacts connected to the plurality of word lines, the plurality of cell contacts being arranged in a first cell contact region and a second cell contact region, wherein the first cell contact region and the second cell contact region are arranged on both sides of the plurality of channel structures in a first direction, The cell region and the peripheral circuit region are stacked in a vertical direction along which the plurality of channel structures extend, Each of the first cell contact region and the second cell contact region has a plurality of first pads and a plurality of second pads, In the first direction, a length of each of the plurality of first pads is shorter than a length of each of the plurality of second pads, and A sum of areas of the plurality of first pads and the plurality of second pads included in the first cell contact region is greater than a sum of areas of the plurality of first pads and the plurality of second pads included in the second cell contact region.

2. The memory device according to claim 1, wherein: In the first direction, a length of the first cell contact region is longer than a length of the second cell contact region.

3. The memory device according to claim 1, wherein: The row decoder includes a plurality of first pass elements and a plurality of second pass elements connected to the plurality of word lines, A portion of the plurality of word lines is connected to the plurality of first pass elements, and a remaining portion of the plurality of word lines is connected to the plurality of second pass elements, and Each of the plurality of first pass elements is connected to one of the portions of the plurality of word lines, and each of the plurality of second pass elements is connected to one of the remaining portions of the plurality of word lines.

4. The memory device according to claim 3, wherein: The plurality of second transmission elements are disposed between the plurality of first transmission elements in the first direction.

5. The memory device according to claim 3, wherein: The number of the portion of the plurality of word lines is greater than the number of the remaining portion of the plurality of word lines.

6. The memory device according to claim 3, wherein: The unit region includes a first unit region and a second unit region adjacent to each other in the first direction, and At least one of the plurality of second transmission elements is disposed between the first unit region and the second unit region in the first direction.

7. The memory device according to claim 3, wherein: The unit region includes a first unit region and a second unit region adjacent to each other in the first direction, and At least one of the plurality of second transmission elements is disposed below a boundary region between the first unit region and the second unit region in the first direction.

8. The memory device according to claim 7, wherein: The plurality of word lines are not disposed above the at least one of the plurality of second transfer elements in the vertical direction.

9. The memory device according to claim 7, wherein: The at least one of the plurality of second transfer elements is connected to two or more of the remaining ones of the plurality of word lines through at least one vertical via extending in the vertical direction, and In the vertical direction, a length of the at least one vertical via is longer than a length of each of the plurality of cell contacts.

10. The memory device according to claim 9, wherein: In the vertical direction, a length of the at least one vertical via is longer than a length of each of the plurality of channel structures.

11. The memory device according to claim 1, wherein: The number of the plurality of second pads included in the first cell contact region is greater than the number of the plurality of second pads included in the second cell contact region.

12. A memory device, the memory device comprising: a plurality of cell regions, each of the plurality of cell regions including a plurality of word lines stacked in a vertical direction and extending in a first direction and a plurality of channel structures extending in the vertical direction and penetrating the plurality of word lines; and a peripheral circuit region including a plurality of transmission elements and arranged below the plurality of unit regions in the vertical direction, wherein each of the plurality of unit regions includes a first unit region and a second unit region arranged in the first direction, At least one of the plurality of transmission elements is disposed in a boundary region between the first cell region and the second cell region and is connected to at least one vertical via crossing a boundary between the peripheral circuit region and the plurality of cell regions, The at least one vertical via is commonly connected to at least one of the plurality of word lines included in the first cell region and at least one of the plurality of word lines included in the second cell region, Each of the first cell region and the second cell region includes a cell array region in which the plurality of channel structures are disposed and a first cell contact region and a second cell contact region disposed on both sides of the cell array region in the first direction, and In the first direction, a length of the second cell contact region is shorter than a length of the first cell contact region.

13. The memory device according to claim 12, wherein: The at least one of the plurality of word lines included in the first cell region and the at least one of the plurality of word lines included in the second cell region are disposed at the same height in the vertical direction.

14. The memory device according to claim 12, wherein: The first unit region and the second unit region have a symmetrical structure with respect to the boundary region.

15. The memory device according to claim 12, wherein: In the first direction, the boundary region is disposed between the second cell contact region of the first cell region and the second cell contact region of the second cell region.

16. The memory device of claim 15, wherein: Each of the at least one of the plurality of word lines included in the first cell region and the at least one of the plurality of word lines included in the second cell region is commonly connected to the at least one vertical via through a cell contact provided in the second cell contact region.

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