Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device is disclosed. The device can include a first source conductive pattern on a substrate, the first source conductive pattern including a polycrystalline material including first grains, the substrate can include a polycrystalline material including second grains, a granularity of the first grains being smaller than a granularity of the second grains; a stack including a plurality of gate electrodes, the plurality of gate electrodes being stacked on the first source conductive pattern; and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority from Korean Patent Application No. 10-2019-0097697, filed on August 9, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to a three-dimensional semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device having improved reliability. BACKGROUND

[0004] To meet the demand for excellent performance and low prices, there has been a continuing effort to develop a semiconductor device having a higher integration. Since the degree of integration of a semiconductor device is a major factor in determining the price of a product, increasing the degree of integration is particularly advantageous. In the case of a two-dimensional or planar semiconductor device, since the degree of integration is mainly determined by the area occupied by a unit memory cell, the degree of integration is greatly influenced by the level of fine pattern forming technology. However, extremely expensive process equipment required to increase the pattern fineness sets a practical limit in increasing the degree of integration of a two-dimensional or planar semiconductor device. Therefore, a three-dimensional semiconductor memory device including a memory cell arranged in three dimensions has recently been proposed. SUMMARY

[0005] Embodiments of the present inventive concept provide a three-dimensional semiconductor memory device having improved reliability.

[0006] According to embodiments of the present inventive concept, a three-dimensional semiconductor memory device can include a first source conductive pattern including a polycrystalline material including first grains, the first source conductive pattern being located on a substrate including a polycrystalline material including second grains, a granularity of the first grains being smaller than a granularity of the second grains; a stack including a plurality of gate electrodes stacked on the first source conductive pattern; and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

[0007] According to embodiments of the present inventive concept, a three-dimensional semiconductor memory device can include a first source conductive pattern and a second source conductive pattern located on a substrate, the first source conductive pattern including impurities not included in the second source conductive pattern; a stack including a plurality of gate electrodes stacked on the second source conductive pattern; and a vertical channel portion penetrating the stack and the first source conductive pattern and the second source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

[0008] According to an embodiment of the present inventive concept, a three-dimensional semiconductor memory device can include a peripheral circuit structure on a first substrate, the peripheral circuit structure including a peripheral circuit transistor; a second substrate on the peripheral circuit structure; a first source conductive pattern on the second substrate, the first source conductive pattern including a first impurity and a second impurity, the first impurity including an n-type impurity, the second impurity including a crystal growth inhibiting element for inhibiting crystal growth in the first source conductive pattern; a stack including a plurality of gate electrodes stacked on the first source conductive pattern; a vertical channel portion penetrating the stack and the first source conductive pattern and extending into the second substrate, the vertical channel portion in contact with a side surface of the first source conductive pattern; and a charge storage layer between the vertical channel portion and the stack. BRIEF DESCRIPTION OF DRAWINGS

[0009] Example embodiments will become more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which like elements are represented by like reference numerals, and in which:

[0010] Figure 1 FIG. 1 is a circuit diagram illustrating a unit array of a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept.

[0011] Figure 2 FIG. 2 is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept.

[0012] Figure 3 FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 2, illustrating a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Figure 2

[0013] Figure 4A Figure 3

[0014] Figure 4B Figure 3

[0015] Figure 4C Figure 3

[0016] Figure 5 Figure 2

[0017] Figure 6 FIG. 5 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept.

[0018] Figures 7A to 7K FIG. 6 is a cross-sectional view taken along line I-I' of FIG. 5, illustrating a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept.​​​​​​​​​Figure 2 FIG. 5 is a cross-sectional view taken along line I-I' of FIG. 4, illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept.

[0019] It should be noted that the drawings are intended to show general characteristics of the methods, structures, and / or materials used in particular example embodiments and to supplement the written description provided below. However, the drawings are not necessarily drawn to scale and can not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, relative thicknesses and positions of molecular, layer, regional, and / or structural elements can be reduced or exaggerated for clarity. When the term "about" or "substantially" is used in conjunction with a value, it is intended to encompass values that are within ±10% of the stated value. When a range is specified, it is intended to include all values within that range, such as in increments of 0.1% up to the stated range. The use of similar or identical reference numerals in various drawings is intended to indicate like or similar elements or features. DETAILED DESCRIPTION

[0020] Example embodiments of the inventive concept will now be more fully described with reference to the accompanying drawings, in which example embodiments of the inventive concept are shown.

[0021] Figure 1 FIG. 1 is a circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept.

[0022] Referring to FIG. 1, Figure 1 The cell array of the three-dimensional semiconductor memory device can include a common source line CSL, a plurality of bit lines BL0 to BL2, and a plurality of cell strings CSTR located between the common source line CSL and the bit lines BL0 to BL2.

[0023] The cell strings CSTR can be two-dimensionally arranged in a first direction X and a second direction Y, and can extend in a third direction Z. In an embodiment, the bit lines BL0 to BL2 can be spaced apart from each other in the first direction X, and can extend in the second direction Y.

[0024] A plurality of cell strings CSTR can be connected in parallel with each of the bit lines BL0 to BL2. The plurality of cell strings CSTR can be commonly connected to the common source line CSL. For example, the plurality of cell strings CSTR can be located between the plurality of bit lines BL0 to BL2 and one common source line CSL. A plurality of common source lines CSL can be two-dimensionally arranged. The common source lines CSL can be applied with the same voltage or can be independently controlled.

[0025] In an embodiment, each of the cell strings CSTR can include string select transistors SST1 and SST2 connected in series with each other, memory cell transistors MCT connected in series with each other, a ground select transistor GST, and an erase control transistor ECT. Each of the memory cell transistors MCT can include a data storage element.

[0026] As an example, each of the cell strings CSTR can include first and second string select transistors SST1 and SST2 connected in series, the second string select transistor SST2 can be tied to one of the bit lines BL0 to BL2. As another example, each of the cell strings CSTR can include one string select transistor. As other examples, in each of the cell strings CSTR, similar to the first and second string select transistors SST1 and SST2, the ground select transistor GST can be composed of a plurality of metal-oxide-semiconductor (MOS) transistors connected in series.

[0027] Each of the cell strings CSTR can include a plurality of memory cell transistors MCT located at a different height from a height of a common source line CSL. The memory cell transistors MCT can be connected in series between the first string select transistor SST1 and the ground select transistor GST. The erase control transistor ECT can be disposed between the ground select transistor GST and the common source line CSL and connected to the ground select transistor GST and the common source line CSL. In addition, each of the cell strings CSTR can include a dummy cell transistor DMC disposed between and connected to the first string select transistor SST1 and an uppermost one of the memory cell transistors MCT, and disposed between and connected to the ground select transistor GST and a lowermost one of the memory cell transistors MCT.

[0028] In an embodiment, the first string select transistor SST1 can be controlled by one of first string select lines SSL1_1, SSL1_2, and SSL1_3, the second string select transistor SST2 can be controlled by one of second string select lines SSL2_1, SSL2_2, and SSL2_3. The memory cell transistors MCT can be controlled by a plurality of word lines WL0 to WLn, respectively, the dummy cell transistor DMC can be controlled by a dummy word line DWL, respectively. The ground select transistor GST can be controlled by one of ground select lines GSL0, GSL1, and GSL2, the erase control transistor ECT can be controlled by an erase control line ECL. The common source line CSL can be commonly connected to a source of the erase control transistor ECT.

[0029] The gate electrodes of the memory cell transistors MCT located at substantially the same height from the common source line CSL can be commonly connected to one of the word lines WL0 to WLn and can be at an equipotential state. Alternatively, even if the gate electrodes of the memory cell transistors MCT are located at substantially the same height from the common source line CSL, the gate electrodes at different rows or different columns can be independently controlled.

[0030] The ground select lines GSL0 to GSL2 and the first string select lines SSL1_1, SSL1_2, SSL1_3 and the second string select lines SSL2_1, SSL2_2, SSL2_3 can extend in the first direction X and can be spaced apart from each other in the second direction Y. The ground select lines GSL0 to GSL2 and the first string select lines SSL1_1, SSL1_2, SSL1_3 and the second string select lines SSL2_1, SSL2_2, SSL2_3 located at substantially the same height from the common source line CSL can be electrically separated from each other. In addition, the erase control transistors ECT in different cell strings CSTR can be simultaneously controlled by the erase control line ECL. During an erase operation of the memory cell array, the erase control transistors ECT can cause gate-induced drain leakage (GIDL).

[0031] Figure 2 is a plan view showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Figure 3 is a cross-sectional view taken along line I-I' of Figure 2 showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Figure 4A is an enlarged cross-sectional view of portion 'A' of Figure 3 Figure 4B is an enlarged cross-sectional view of portion 'B' of Figure 3 Figure 4C is an enlarged cross-sectional view of portion 'C' of Figure 3

[0032] Referring to Figure 2 and Figure 3 ​​​The three-dimensional semiconductor memory device can include a lower substrate 100, a peripheral circuit structure PRS, a source structure SP, a stack ST, and a vertical channel portion VC. The lower substrate 100 can be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The lower substrate 100 can be formed of a single-crystal semiconductor material (e.g., single-crystal silicon). The peripheral circuit structure PRS can include peripheral circuit transistors TR, a peripheral circuit interlayer insulating layer 10, interconnection lines 13, and a via 15. A cell device isolation layer CSTI can be located in the lower substrate 100, and the peripheral circuit transistors TR can be located on an active region of the lower substrate 100 defined by the cell device isolation layer CSTI. Each of the peripheral circuit transistors TR can include a peripheral gate insulating layer 40, a peripheral gate electrode 43, and a source / drain region 45. The peripheral circuit interlayer insulating layer 10 can be located on the lower substrate 100. The peripheral circuit interlayer insulating layer 10 can cover the peripheral circuit transistors TR. The interconnection lines 13 and the via 15 can be located in the peripheral circuit interlayer insulating layer 10. The interconnection lines 13 located at different levels can be electrically connected to each other through the via 15 therebetween. In addition, the peripheral circuit transistors TR can be electrically connected to the interconnection lines 13 through the via 15.

[0033] A substrate 200 can be located on the peripheral circuit structure PRS. The substrate 200 can be formed of or include at least one of silicon, silicon germanium, and germanium. In an embodiment, the substrate 200 can be formed of a polycrystalline semiconductor material (e.g., polycrystalline silicon). The substrate 200 can be doped with an n-type impurity (e.g., phosphorus). A source structure SP can be located on the substrate 200. The source structure SP can include a first source conductive pattern SP1 and a second source conductive pattern SP2 sequentially stacked on the substrate 200. The first source conductive pattern SP1 can be in contact with a top surface of the substrate 200. The first source conductive pattern SP1 can have openings OP. The openings OP can be located between the stacks ST placed adjacent to each other in a second direction Y. The openings OP can be spaced apart from each other in a first direction X or in a direction crossing the second direction Y. Although not shown in the drawings, a portion of the top surface of the substrate 200 can be exposed through the openings OP.

[0034] The first source conductive pattern SP1 can be formed of a polycrystalline semiconductor material (e.g., polysilicon). In an embodiment, the first source conductive pattern SP1 can include one impurity. The impurity can be an n-type element (e.g., phosphorus). In another embodiment, the first source conductive pattern SP1 can include two or more impurities. For example, the first source conductive pattern SP1 can include a first impurity and a second impurity. The first impurity can be an element that does not form a compound with an element (e.g., silicon) in the first source conductive pattern SP1. The second impurity can be an element that can form a compound with the element (e.g., silicon) in the first source conductive pattern SP1. For example, the first impurity can include an n-type element (e.g., phosphorus). The second impurity can include, for example, at least one of carbon (C), nitrogen (N), oxygen (O), chlorine (Cl), bromine (Br), and any combination thereof. In an embodiment, as shown in FIG. 1A, the first source conductive pattern SP1 can include a first source conductive layer 210 and a second source conductive layer 220. The first source conductive layer 210 can include the first impurity. The second source conductive layer 220 can include the second impurity. The first source conductive layer 210 can be formed of a polycrystalline semiconductor material (e.g., polysilicon). The second source conductive layer 220 can be formed of a polycrystalline semiconductor material (e.g., polysilicon). The first source conductive layer 210 can be in contact with the second source conductive layer 220. The first source conductive layer 210 can be in contact with the top surface of the substrate 200. The second source conductive layer 220 can extend to cover the side surface of the opening OP of the first source conductive layer 210. The second source conductive layer 220 can not include the first impurity. The first source conductive layer 210 can include the first impurity. The second source conductive layer 220 can include the second impurity. The first source conductive layer 210 can include an n-type impurity. The concentration of the n-type impurity in the first source conductive layer 210 can be higher than the concentration of the n-type impurity in the second source conductive layer 220. In an embodiment, the first source conductive layer 210 can include a first source conductive layer 211 and a second source conductive layer 212. The first source conductive layer 211 can include the first impurity. The second source conductive layer 212 can include the second impurity. The first source conductive layer 211 can be in contact with the second source conductive layer 212. The first source conductive layer 211 can be in contact with the top surface of the substrate 200. The second source conductive layer 212 can extend to cover the side surface of the opening OP of the first source conductive layer 211. The second source conductive layer 212 can not include the first impurity. The first source conductive layer 211 can include the first impurity. The second source conductive layer 212 can include the second impurity. The first source conductive layer 211 can include an n-type impurity. The concentration of the n-type impurity in the first source conductive layer 211 can be higher than the concentration of the n-type impurity in the second source conductive layer 212. Figure 4A In an embodiment, as shown in FIG. 1A, the grain size of the grains GS1 of the first source conductive pattern SP1 can be smaller than the grain size of the grains GS2 of the substrate 200 (e.g., grain size (GS1) < grain size (GS2)). The grain size can be, for example, the average grain size of the grains measured in any portion of the material or the average of the measurement results from any number of portions, or can be the grain size of a representative grain found at any portion of the material. The ratio of the grain size of the grains GS1 of the first source conductive pattern SP1 to the grain size of the grains GS2 of the substrate 200 can be in the range of about 0.1 to about 0.01. In an embodiment, the grain size of the grains GS1 of the first source conductive pattern SP1 can be less than about 10 nm.

[0035] The second source conductive pattern SP2 can be located on the first source conductive pattern SP1. The second source conductive pattern SP2 can be formed of a polycrystalline semiconductor material (e.g., polysilicon). The second source conductive pattern SP2 can be in contact with the top surface of the first source conductive pattern SP1. The second source conductive pattern SP2 can extend to cover the side surface of the opening OP of the first source conductive pattern SP1. The second source conductive pattern SP2 can not include an impurity, or can include at least one impurity. In this case, the first source conductive pattern SP1 can include an impurity that is not included in the second source conductive pattern SP2. The second source conductive pattern SP2 can include an n-type impurity. The concentration of the n-type impurity in the first source conductive pattern SP1 can be higher than the concentration of the n-type impurity in the second source conductive pattern SP2. In an embodiment, the grain size of the grains GS3 of the second source conductive pattern SP2 can be greater than the grain size of the grains GS1 of the first source conductive pattern SP1 (e.g., grain size (GS1) < grain size (GS3)). The grain size of the grains GS3 of the second source conductive pattern SP2 can be smaller than the grain size of the grains GS2 of the substrate 200 (e.g., grain size (GS3) < grain size (GS2)).

[0036] The stack ST can be located on the source structure SP. The stack ST can extend in a first direction X and can be spaced apart from each other in a second direction Y. Each of the stack ST can include gate electrodes 210a, 210b, 210c, and 210d and an insulating pattern 220. The gate electrodes 210a, 210b, 210c, and 210d and the insulating pattern 220 can be alternately and repeatedly stacked on the source structure SP. The gate electrodes 210a, 210b, 210c, and 210d can include an erase gate electrode 210a, a ground select gate electrode 210b, a cell gate electrode 210c, and a string select gate electrode 210d.

[0037] The erase gate electrode 210a can be located on the source structure SP. The erase gate electrode 210a can be adjacent to the source structure SP. The erase gate electrode 210a can be a lowermost electrode among the gate electrodes 210a, 210b, 210c, and 210d. The erase gate electrode 210a can correspond to an erase control transistor ECT as illustrated in FIG. 1B and be used to cause gate induced drain leakage (GIDL) during an erase operation of the memory cell array. The ground select gate electrode 210b can be located on the erase gate electrode 210a. In another embodiment, the ground select gate electrode 210b can be adjacent to the erase gate electrode 210a. The ground select gate electrode 210b can correspond to ground select lines GSL0 to GSL2 as illustrated in FIG. 1B. Figure 1 Figure 1 The string select gate electrode 210d can be located on the ground select gate electrode 210b. The string select gate electrode 210d can be an uppermost electrode among the gate electrodes 210a, 210b, 210c, and 210d. The string select gate electrode 210d can correspond to first string select lines SSL1_1, SSL1_2, SSL1_3 and second string select lines SSL2_1, SSL2_2, SSL2_3 of FIG. 1B. The cell gate electrode 210c can be located between the ground select gate electrode 210b and the string select gate electrode 210d. The cell gate electrode 210c can correspond to word lines WL0 to WLn of FIG. 1B. Figure 1 Figure 1 The string select gate electrode 210d can be located on the ground select gate electrode 210b. The string select gate electrode 210d can be an uppermost electrode among the gate electrodes 210a, 210b, 210c, and 210d. The string select gate electrode 210d can correspond to first string select lines SSL1_1, SSL1_2, SSL1_3 and second string select lines SSL2_1, SSL2_2, SSL2_3 of FIG. 1B. The cell gate electrode 210c can be located between the ground select gate electrode 210b and the string select gate electrode 210d. The cell gate electrode 210c can correspond to word lines WL0 to WLn of FIG. 1B.

[0038] The insulating pattern 220 can be located between the gate electrodes 210a, 210b, 210c, and 210d adjacent to each other in a third direction Z perpendicular to a top surface of the substrate 200, between the erase gate electrode 210a and the source structure SP, and on the string select gate electrode 210d. Those of the insulating pattern 220 located between the ground select gate electrode 210b and a lowermost electrode among the cell gate electrodes 210c and on the string select gate electrode 210d can be thicker than the other insulating patterns 220.

[0039] ​​The vertical channel portions VC can penetrate the stack ST and the source structure SP. The vertical channel portions VC can extend into the substrate 200. For example, the vertical channel portions VC can be located in channel recessed portions CRR of the substrate 200. The channel recessed portions CRR can be regions recessed from a top surface of the substrate 200. The vertical channel portions VC can be physically spaced apart from the substrate 200. The vertical channel portions VC can be in contact with side surfaces of the first source conductive pattern SP1 and can be spatially spaced apart from side surfaces of the second source conductive pattern SP2. The vertical channel portions VC can be electrically connected to the substrate 200 through the source structure SP. The vertical channel portions VC can have a bottom-enclosed tubular or penne shape. The vertical channel portions VC can be formed of or include at least one of a semiconductor material (e.g., silicon (Si) and / or germanium (Ge)). In addition, the vertical channel portions VC can be formed of a doped semiconductor material or an undoped semiconductor material (i.e., an intrinsic semiconductor material). The vertical channel portions VC can be formed of or include a polycrystalline semiconductor material.

[0040] The first source conductive pattern SP1 can include a horizontal portion HP, a first protruding portion P1, and a second protruding portion P2. The horizontal portion HP can be located between the substrate 200 and the second source conductive pattern SP2. The first protruding portion P1 can be located between a portion of an outer side surface of each of the vertical channel portions VC and a portion of a side surface of the second source conductive pattern SP2, and the second protruding portion P2 can be located between a portion of the outer side surface of each of the vertical channel portions VC and a portion of a side surface of each of the channel recessed portions CRR of the substrate 200. The horizontal portion HP can be interposed between the substrate 200 and the first source conductive pattern SP1 and between the first protruding portion P1 and the second protruding portion P2. The first protruding portion P1 can be a portion of the first source conductive pattern SP1 that extends from the horizontal portion HP to a region between a portion of the outer side surface of the vertical channel portion VC and a portion of the side surface of the second source conductive pattern SP2, and the second protruding portion P2 can be a portion of the first source conductive pattern SP1 that extends from the horizontal portion HP to a region between a portion of the outer side surface of the vertical channel portion VC and a portion of the side surface of the channel recessed portion CRR.

[0041] The charge storage structure CTS can be located on a top surface of the first protruding portion P1 of the first source conductive pattern SP1 to enclose the outer lateral surface of the vertical channel portion VC. The charge storage structure CTS can be interposed between the gate electrodes 210a, 210b, 210c, and 210d and the vertical channel portion VC and can extend in the third direction Z to enclose the outer lateral surface of the vertical channel portion VC. The charge storage structure CTS can be located on a portion of a lateral surface of the second source conductive pattern SP2 that is not covered by the first source conductive pattern SP1. Referring to Figure 4B The charge storage structure CTS can include a tunneling insulating layer TL, a blocking insulating layer BLL, and a charge storage layer CTL. The tunneling insulating layer TL can be adjacent to the vertical channel portion VC and can enclose the outer lateral surface of the vertical channel portion VC. The blocking insulating layer BLL can be adjacent to the gate electrodes 210a, 210b, 210c, and 210d. The charge storage layer CTL can be located between the tunneling insulating layer TL and the blocking insulating layer BLL. The tunneling insulating layer TL can be formed of or include at least one of, for example, silicon oxide and / or a high-k dielectric material such as aluminum oxide (Al2O3) and hafnium oxide (HfO2). The blocking insulating layer BLL can be formed of or include at least one of, for example, silicon oxide and / or a high-k dielectric material such as aluminum oxide (Al2O3) and hafnium oxide (HfO2). The charge storage layer CTL can be formed of or include, for example, a silicon nitride layer.

[0042] The gap filling layer 230 can be located in an inner space defined in the vertical channel portion VC. The gap filling layer 230 can be formed of or include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. The pad 240 can be located on a top surface of the vertical channel portion VC and the gap filling layer 230. The pad 240 can be formed of or include a conductive material or a doped semiconductor material having a different conductivity type from the vertical channel portion VC.

[0043] The dummy pattern DP can be located in each of the channel recessed portions CRR. The dummy pattern DP can surround the lower side surface and the bottom surface of the vertical channel portion VC in the channel recessed portion CRR. The dummy pattern DP can be in contact with the bottom surface of the second protruding portion P2 of the first source conductive pattern SP1. The dummy pattern DP can be vertically spaced apart from the charge storage structure CTS. The dummy pattern DP can have substantially the same layer stack structure as the charge storage structure CTS. For example, the dummy pattern DP can include the same layers as the layers stacked in the charge storage structure CTS. In one embodiment, the dummy pattern DP can include: a first stack layer formed of or including at least one of silicon oxide and / or high-k dielectric material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)); a second stack layer formed of or including silicon nitride; and a third stack layer formed of or including at least one of silicon oxide and / or high-k dielectric material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)).

[0044] The first interlayer insulating layer ILD1 can cover the top surface of the stack ST. The first interlayer insulating layer ILD1 can cover the top surface of the pad 240 and the top surface of the uppermost insulating pattern in the insulating patterns 220. The first interlayer insulating layer ILD1 can be formed of or include, for example, silicon oxide.

[0045] The common source pattern CSP can penetrate the first interlayer insulating layer ILD1 and can be located between the stacks ST adjacent to each other in the second direction Y. The common source pattern CSP between the stacks ST can extend in the first direction X. The common source pattern CSP can extend into the opening OP (see, for example, FIG. 2) to be in contact with the portion of the substrate 200 located under the opening OP. The common source pattern CSP can penetrate the source structure SP, and a portion of the bottom surface of the common source pattern CSP can be in contact with the substrate 200. Referring to FIG. 2, the common source pattern CSP can be in contact with the substrate 200 through the opening OP. Figure 2 ) in the first interlayer insulating layer ILD1, and can be located between the stacks ST adjacent to each other in the second direction Y. The common source pattern CSP between the stacks ST can extend in the first direction X. The common source pattern CSP can extend into the opening OP (see, for example, FIG. 2) to be in contact with the portion of the substrate 200 located under the opening OP. The common source pattern CSP can penetrate the source structure SP, and a portion of the bottom surface of the common source pattern CSP can be in contact with the substrate 200. Referring to FIG. 2, the common source pattern CSP can be in contact with the substrate 200 through the opening OP. Figure 4CThe width W1 of the first portion PA1 of the common-source pattern CSP, which is located between the first source conductive patterns SP1 adjacent to each other in the second direction Y, can be greater than the width W2 of the second portion PA2 of the common-source pattern CSP, which is located between the second source conductive patterns SP2 adjacent to each other in the second direction Y. For example, the first portion PA1 can be a portion of the common-source pattern CSP whose sidewall extends laterally with respect to a side surface of the second portion PA2 of the common-source pattern CSP. The common-source pattern CSP can be formed of or include at least one of, for example, a conductive material (e.g., tungsten, copper, and / or aluminum) and / or a metal nitride (e.g., titanium nitride and / or tantalum nitride). The spacers SL can be located between the common-source pattern CSP and the stack ST and between the source structure SP and the common-source pattern CSP. The spacers SL can surround a side surface of the common-source pattern CSP. The spacers SL can be interposed between a portion of the top surface of the substrate 200 and a portion of the bottom surface of the common-source pattern CSP. For example, the spacers SL can be formed of or include at least one insulating material (e.g., silicon oxide and / or silicon nitride).

[0046] The common-source region CSR can be located in a region of the substrate 200 under the common-source pattern CSP. The common-source region CSR can be disposed in a region of the substrate 200 between the stacks ST adjacent to each other in the second direction Y. The common-source pattern CSP can have a different conductive type from a conductive type of the substrate 200.

[0047] The blocking pattern BP can be located between the source structure SP and the spacers SL. The blocking pattern BP can extend into a region between the substrate 200 and a portion of the spacers SL on the top surface of the substrate 200. The blocking pattern BP can be formed of or include, for example, silicon oxide. The horizontal insulating layer PL can be located between the gate electrodes 210a, 210b, 210c, and 210d and the charge storage structure CTS and can extend to cover the top and bottom surfaces of the gate electrodes 210a, 210b, 210c, and 210d. The horizontal insulating layer PL can extend to be interposed between the insulating pattern 220 and the spacers SL and between the blocking pattern BP and the spacers SL. The horizontal insulating layer PL can be formed of or include at least one of, for example, silicon oxide (e.g., SiO2) and / or a high-k dielectric material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)).

[0048] A second interlayer insulating layer ILD2 can be located on the first interlayer insulating layer ILD1 and the common source pattern CSP. The second interlayer insulating layer ILD2 can be formed of or include, for example, silicon oxide. A channel contact plug 310 can be located on the pad 240. The channel contact plug 310 can be disposed to penetrate the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, and can be electrically connected to the pad 240. Bit lines BL can be located on the second interlayer insulating layer ILD2. The bit lines BL can extend in the second direction Y, and can cross the stacks ST. The bit lines BL can be spaced apart from each other in the first direction X. The bit lines BL can be electrically connected to the channel contact plug 310.

[0049] Figure 5 is a cross-sectional view taken along a line I-I' of Figure 2 a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept.

[0050] Referring to Figure 5 , the three-dimensional semiconductor memory device can include a lower substrate 100, a peripheral circuit structure PRS, a substrate 200, a source structure SP, stacks ST, and vertical channel portions VC. Each of the stacks ST can include a lower stack LST and an upper stack UST. The source structure SP can be located between the lower stack LST and the substrate 200. The lower stack LST can include an erase gate electrode 210a, a ground select gate electrode 210b located on the erase gate electrode 210a, a cell gate electrode 210c located on the ground select gate electrode 210b, and an insulating pattern 220. The erase gate electrode 210a, the ground select gate electrode 210b, and the cell gate electrode 210c of the lower stack LST and the insulating pattern 220 can be alternately and repeatedly stacked in a third direction Z. The cell gate electrode 210c of the lower stack LST can be sequentially stacked on the ground select gate electrode 210b. The erase gate electrode 210a can correspond to a lowermost gate electrode in the lower stack LST, and an uppermost electrode among the cell gate electrodes 210c can correspond to an uppermost gate electrode in the lower stack LST. Charge storage structures CTS, pads 240, and the vertical channel portions VC in the lower stack LST can be substantially the same as those described with reference to Figure 2 , and thus a detailed description thereof will be omitted for the sake of brevity.

[0051] The upper stack UST can be located on the lower stack LST. The upper stack UST can include the cell gate electrodes 210c, the string selection gate electrodes 210d, and the insulating pattern 220. The cell gate electrodes 210c and the string selection gate electrodes 210d of the upper stack UST and the insulating pattern 220 can be alternately and repeatedly stacked in the third direction Z. The cell gate electrodes 210c of the upper stack UST can be sequentially stacked on the lower stack LST, and the string selection gate electrodes 210d can be located on the uppermost electrode among the cell gate electrodes 210c of the upper stack UST. The lowermost electrode among the cell gate electrodes 210c of the upper stack UST can correspond to the lowermost gate electrode in the upper stack UST, and the string selection gate electrodes 210d can correspond to the uppermost gate electrode in the upper stack UST.

[0052] The vertical channel portions VC can penetrate the lower stack LST and the upper stack UST. Each of the vertical channel portions VC can include a lower portion penetrating the lower stack LST and an upper portion penetrating the upper stack UST. A bottom width WD1 of the upper portion of the vertical channel portion VC can be smaller than a top width WD2 of the lower portion of the vertical channel portion VC. For example, a side surface of the upper portion of the vertical channel portion VC can be misaligned with a side surface of the lower portion of the vertical channel portion VC. Each of the charge storage structures CTS can conformally surround an outer side surface of each of the vertical channel portions VC. The gap fill layer 230 can be disposed to fill an inner space of the vertical channel portion VC, and the pad 240 can be located on a top surface of the vertical channel portion VC and the gap fill layer 230. The first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the bit line BL can be sequentially located on the upper stack UST.

[0053] The common source pattern CSP can extend to penetrate the upper stack UST, the lower stack LST, and the source structure SP. A top surface of the common source pattern CSP can be coplanar with a top surface of the first interlayer insulating layer ILD1. The spacers SL can be located on a side surface of the common source pattern CSP.

[0054] Figure 6 FIG. 1 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept.

[0055] Referring to Figure 6 In the three-dimensional semiconductor memory device according to an embodiment of the present inventive concept, the reference Figure 2The lower substrate 100 and the peripheral circuit structure PRS are described. The substrate 200 can be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The substrate 200 can be formed of a single-crystal semiconductor material (e.g., single-crystal silicon). The substrate 200 can include a cell array region CAR and a peripheral circuit region PER. The stack ST and the source structure SP can be located on the cell array region CAR of the substrate 200. The stack ST and the source structure SP can expose the peripheral circuit region PER of the substrate 200.

[0056] The peripheral device isolation layer PSTI can be located in the peripheral circuit region PER of the substrate 200 to define active regions of the substrate 200. The low-voltage transistor LTR and the high-voltage transistor HTR can be located in the peripheral circuit region PER of the substrate 200 as well as on the active regions. Each of the low-voltage transistor LTR and the high-voltage transistor HTR can include a source / drain region (not shown) formed in each of the active regions as well as a stack pattern STP. The source / drain region can be formed in portions of the active regions located on both sides of the stack pattern STP. The stack pattern STP can include a peripheral gate insulating layer 50, a doped peripheral polysilicon pattern 52, a gate metal pattern 54, and a mask pattern 56 sequentially stacked on the substrate 200. A peripheral spacer PSL can be disposed to cover side surfaces of the stack pattern STP. A dummy-sacrifice pattern DHP can be disposed to conformally cover side surfaces of the peripheral spacer PSL, a top surface of the stack pattern STP, and a top surface of the peripheral device isolation layer PSTI. The dummy-sacrifice pattern DHP can be formed of or include a silicon nitride layer.

[0057] In an embodiment, the insulating pattern 220 located on the cell array region CAR of the substrate 200 and between the lowermost electrode of the cell gate electrode 210c and the ground select gate electrode 210b can extend to the peripheral circuit region PER of the substrate 200 to cover the peripheral circuit region PER of the substrate 200 as well as the dummy-sacrifice pattern DHP. The interlayer insulating pattern 400 can be located on the insulating pattern 220 in the peripheral circuit region PER of the substrate 200.

[0058] Figures 7A to 7K are cross-sectional views taken along lines I-I' and II-II' of FIG. 1, respectively, illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 2

[0059] Referring to FIGS. 1 and 2, Figure 7A ​A unit device isolation layer CSTI can be provided in the lower substrate 100. The lower substrate 100 can be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The lower substrate 100 can be formed of a single-crystal semiconductor material (e.g., single-crystal silicon). The unit device isolation layer CSTI can define an active region of the lower substrate 100. A peripheral circuit structure PRS can be provided on the lower substrate 100. The peripheral circuit structure PRS can include peripheral circuit transistors TR, interconnection lines 13, vias 15, and peripheral circuit interlayer insulating layers 10. The peripheral circuit transistors TR can be formed on the active region of the lower substrate 100. Each of the peripheral circuit transistors TR can include a peripheral gate insulating layer 40, a peripheral gate electrode 43, and a source / drain region 45. The peripheral circuit interlayer insulating layers 10 can be formed on the lower substrate 100. The peripheral circuit interlayer insulating layers 10 can be formed to cover the peripheral circuit transistors TR. The interconnection lines 13 and the vias 15 can be formed in the peripheral circuit interlayer insulating layers 10.

[0060] The substrate 200 can be located on the peripheral circuit structure PRS. The substrate 200 can be formed of or include at least one of silicon, silicon germanium, and germanium. In an embodiment, the substrate 200 can be formed of a polycrystalline semiconductor material (e.g., polycrystalline silicon). The substrate 200 can be doped with an n-type impurity (e.g., phosphorus). A first buffer insulating layer 500, a first sacrificial layer 502, a second buffer insulating layer 504, and a source conductive layer 506 can be sequentially formed on the substrate 200. The first buffer insulating layer 500 can be located on the substrate 200. The first buffer insulating layer 500 can include a thermal oxide layer or a silicon oxide layer. The first sacrificial layer 502 can be located on the first buffer insulating layer 500. The first sacrificial layer 502 can be formed of a material having etching selectivity with respect to the first buffer insulating layer 500. For example, the first sacrificial layer 502 can be formed of or include at least one of silicon nitride, silicon oxynitride, silicon carbide, and / or silicon germanium. The second buffer insulating layer 504 can be formed on the first sacrificial layer 502. The second buffer insulating layer 504 can be formed of or include silicon oxide. The source conductive layer 506 can be formed on the second buffer insulating layer 504. As an example, the source conductive layer 506 can be a polycrystalline silicon layer doped with an n-type impurity and / or carbon (C) atoms. As another example, the source conductive layer 506 can be a polycrystalline silicon layer doped with only an n-type impurity. The source conductive layer 506 can be formed on the second buffer insulating layer 504 with a deposition process.

[0061] A mold structure MS can be formed on the source conductive layer 506. The mold structure MS can include insulating layers 510 and second sacrificial layers 512 that are alternately and repeatedly stacked on the source conductive layer 506. The insulating layers 510 and the second sacrificial layers 512 can include materials that are etch-selective with respect to each other. For example, the insulating layers 510 can be formed of or include silicon oxide, and the second sacrificial layers 512 can be formed of or include at least one of silicon oxynitride, silicon carbide, and / or silicon germanium.

[0062] Referring to Figure 7B The mold structure MS, the source conductive layer 506, the second buffer insulating layer 504, the first sacrificial layer 502, and the first buffer insulating layer 500 can be etched to form a channel hole CH that exposes the substrate 200. For example, a mask pattern (not shown) can be formed on the uppermost layer of the insulating layers 510, and then the mold structure MS, the source conductive layer 506, the second buffer insulating layer 504, the first sacrificial layer 502, and the first buffer insulating layer 500 can be anisotropically etched using the mask pattern as an etch mask. The etching process can be performed to recess a portion of the top surface of the substrate 200 to a certain depth. The channel hole CH can have a side surface that is inclined at an angle with respect to the top surface of the substrate 200. The channel hole CH can have a circular, elliptical, or polygonal shape when viewed in a planar view.

[0063] A primary structure PCS can be formed in the channel hole CH. The primary structure PCS can be formed to conformally cover the side surface and the bottom surface of the channel hole CH. In an embodiment, the primary structure PCS can include a blocking insulating layer BLL, a charge storage layer CTL, and a tunneling insulating layer TL that are sequentially stacked on the side surface and the bottom surface of the channel hole CH, similar to the charge storage structure CTS shown in FIG. 2. Figure 4B The primary structure PCS can include a blocking insulating layer BLL, a charge storage layer CTL, and a tunneling insulating layer TL that are sequentially stacked on the side surface and the bottom surface of the channel hole CH, similar to the charge storage structure CTS shown in FIG. 2. A vertical channel portion VC can be formed in the channel hole CH in which the primary structure PCS is formed. The vertical channel portion VC can be formed to conformally cover the side surface and the bottom surface of the primary structure PCS. A gap fill layer 230 can be formed in an inner space of the vertical channel portion VC. The gap fill layer 230 can be formed to completely fill the channel hole CH. A pad 240 can be formed in an upper region of the channel hole CH. The formation of the pad 240 can include the steps of etching an upper portion of the vertical channel portion VC and an upper portion of the gap fill layer 230 to form a recessed area, and filling the recessed area with a conductive material. Alternatively, the pad 240 can be formed by doping an upper portion of the vertical channel portion VC with an impurity of a conductive type different from that of the vertical channel portion VC.

[0064] A first interlayer insulating layer ILD1 can be formed on the mold structure MS. The first interlayer insulating layer ILD1 can cover a top surface of the mold structure MS, a top surface of the pad 240, and a top surface of the primary structure PCS.

[0065] Referring to Figure 7C An anisotropic etching process can be performed to etch the mold structure MS and a portion of the source conductive layer 506, where the first interlayer insulating layer ILD1 can serve as an etching mask in the anisotropic etching process. As a result of the anisotropic etching process, a trench TH can be formed to penetrate the mold structure MS. The trench TH can also be formed in a portion of the source conductive layer 506. A bottom surface of the trench TH can be located at a level between a top surface and a bottom surface of the source conductive layer 506. Due to the trench TH, the mold structure MS can be divided into a plurality of mold structures MSa spaced apart from each other in the second direction Y. Each of the mold structures MSa can include the insulating pattern 220 and the second sacrificial pattern 222 alternately stacked on the source conductive layer 506. The trench TH can be formed to expose a top surface of the source conductive layer 506, a side surface of the first interlayer insulating layer ILD1, a side surface of the insulating pattern 220, a side surface of the second sacrificial pattern 222, and a portion of the source conductive layer 506 recessed.

[0066] A protective layer SAL can be formed to conformingly cover the side and bottom surfaces of the trench TH and the top surface of the first interlayer insulating layer ILD1. The protective layer SAL can be formed of or include a material having etching selectivity with respect to the mold structures MSa and the first sacrificial layer 502. For example, the protective layer SAL can be formed of or include polysilicon. The protective layer SAL can be formed by a deposition process.

[0067] Referring to Figure 7D An anisotropic etching process can be performed on the protective layer SAL to form a protective spacer SA. The protective spacer SA can be formed to cover the side surfaces of the trench TH. The source conductive layer 506 and the second buffer insulating layer 504 located under the trench TH can be etched during the anisotropic etching process. Accordingly, a portion of the top surface of the first sacrificial layer 502 can be exposed through the trench TH. As a result of etching the source conductive layer 506 and the second buffer insulating layer 504, the source conductive layer 506 can be divided into a plurality of second source conductive patterns SP2 spaced apart from each other in the second direction Y, and the second buffer insulating layer 504 can be divided into a plurality of second buffer insulating patterns 504a spaced apart from each other in the second direction Y.

[0068] Referring to Figure 7EThe first sacrificial layer 502 exposed through the trench TH can be removed to form a first recessed area R1. The formation of the first recessed area R1 can include a step of selectively removing the first sacrificial layer 502 exposed through the trench TH to expose a top surface of the first buffer insulating layer 500, a bottom surface of the second buffer insulating pattern 504a, and a portion of the primary structure PCS. The first sacrificial layer 502 can be removed by an isotropic etching process using an etching solution selected to have an etching selectivity with respect to the protective spacer SA, the second source conductive pattern SP2, the second buffer insulating pattern 504a, and the first buffer insulating layer 500. The process of etching the first sacrificial layer 502 can be performed using an etching solution containing phosphoric acid.

[0069] Those portions of the primary structure PCS exposed through the first recessed area R1 can be etched to form the charge storage structure CTS and the dummy pattern DP. The portions of the primary structure PCS can be removed isotropically by supplying an etching solution to the primary structure PCS through the first recessed area R1. As a result, the outer side surface of the vertical channel portion VC can be exposed between the substrate 200 and the second source conductive pattern SP2. The first buffer insulating layer 500 and the second buffer insulating pattern 504a can also be removed during the etching of the portions of the primary structure PCS. In this case, the bottom surface of the second source conductive pattern SP2 can be exposed through the first recessed area R1. Due to the isotropic etching process, an undercut region UR can be formed between the outer side surface of the vertical channel portion VC and the side surface of the second source conductive pattern SP2 and between the side surface of the vertical channel portion VC and the side surface of the channel hole CH in the substrate 200. The first recessed area R1 can be an empty space extending horizontally from the trench TH into a region between the second source conductive pattern SP2 and the substrate 200. The undercut region UR can be an empty space extending in the third direction Z from the first recessed area R1.

[0070] The isotropic etching process on the primary structure PCS can include sequentially etching the blocking insulating layer BLL (as disclosed with reference to Figure 4B ), the charge storage layer CTL (as disclosed with reference to Figure 4B ), and the tunnel insulating layer TL (as disclosed with reference to Figure 4B ). For example, the isotropic etching process can include sequentially performing a first etching process for etching a portion of the blocking insulating layer BLL, a second etching process for etching a portion of the charge storage layer CTL, and a third etching process for etching a portion of the tunnel insulating layer TL. In this case, an etching solution containing hydrofluoric acid and / or sulfuric acid can be used in the first and third etching processes, and an etching solution containing phosphoric acid can be used in the second etching process.

[0071] The charge storage structure CTS and the dummy pattern DP can be patterns formed by dividing the primary structure PCS in the third direction Z via an isotropic etching process. The charge storage structure CTS can enclose the outer side surface of the vertical channel portion VC located above the bottom surface of the second source conductive pattern SP2, and the dummy pattern DP can enclose the side surface and the bottom surface of the vertical channel portion VC located below the top surface of the substrate 200.

[0072] Referring to Figure 7F The primary source conductive layer 410 can be formed in the first recessed region R1 and the undercut region UR. The primary source conductive layer 410 can be formed to cover the top surface of the first interlayer insulating layer ILD1 and the side surface of the protection spacer SA, and to completely fill the first recessed region R1 and the undercut region UR. The primary source conductive layer 410 can be formed by a deposition process. The primary source conductive layer 410 can be formed of or include an amorphous semiconductor material (e.g., amorphous silicon).

[0073] In an embodiment, the primary source conductive layer 410 can be doped with a first impurity while being deposited in an in-situ manner. The first impurity can be an n-type impurity (e.g., phosphorus). In certain embodiments, the primary source conductive layer 410 can be doped with a first impurity and a second impurity while being deposited in an in-situ manner. The first impurity can be an n-type impurity (e.g., phosphorus), and the second impurity can be an element that suppresses the growth of grains of the primary source conductive layer 410 in a subsequent annealing process for crystallization. The second impurity can include at least one of, for example, carbon (C), nitrogen (N), oxygen (O), chlorine (Cl), and / or bromine (Br). In an embodiment, the second impurity can be doped in the primary source conductive layer 410 such that the number of atoms per unit area is less than about 10%. The first impurity and / or the second impurity can be doped in the primary source conductive layer 410 by an additional implantation process performed after the deposition of the primary source conductive layer 410. In this case, the implantation process can be an ion implantation process or a gas-phase doping process.

[0074] Referring to Figure 7GA part of the primary source conductive layer 410 can be etched by an isotropic etching process to locally form the primary source conductive pattern PSP1 in the first recessed region R1. The isotropic etching process can include etching the primary source conductive layer 410 formed on the top surface of the substrate 200 under the side surface of the protection spacer SA, the top surface of the first interlayer insulating layer ILD1, and the trench TH. The protection spacer SA can also be etched during the isotropic etching process. Accordingly, the side surface of the mold structure MSa can be etched. Due to the isotropic etching process, the side surface of the primary source conductive pattern PSP1 can not be aligned with the side surface of the trench TH. For example, a width between the second source conductive patterns SP2 in the second direction Y that are adjacent to each other in the second direction Y in the trench TH can be smaller than a width between the primary source conductive patterns PSP1 in the second direction Y that are adjacent to each other in the second direction Y. The isotropic etching process can be performed using an etching recipe that has etching selectivity with respect to the mold structure MSa. The isotropic etching process can be performed by a wet etching process using a mixed solution (e.g., standard cleaning solution 1 (SC1)) including deionized water, ammonia water (NH4OH), peroxide, potassium hydroxide (KOH), and / or ethylenediamine o-phenanthroline (EDP).

[0075] Referring to Figure 7H A barrier layer BKL can be formed on the side surface of the second source conductive pattern SP2, the side surface of the primary source conductive pattern PSP1, and the portion of the top surface of the substrate 200 exposed by the trench TH. The barrier layer BKL can be formed by an oxidation process that oxidizes the side surface of the second source conductive pattern SP2, the side surface of the primary source conductive pattern PSP1, and the portion of the top surface of the substrate 200 exposed by the trench TH. The oxidation process can be performed at a temperature in a range of about 300 °C to about 600 °C. During the oxidation process, the primary source conductive pattern PSP1 can be maintained in an amorphous state. The oxidation process can be a thermal oxidation process, a wet oxidation process, or a dry oxidation process. The barrier layer BKL can be formed of or include, for example, silicon oxide. The barrier layer BKL can reduce or prevent damage to the substrate 200, the second source conductive pattern SP2, and the primary source conductive pattern PSP1 exposed by the trench TH during subsequent processes.

[0076] Referring to Figure 7IThe second sacrificial pattern 222 exposed through the trench TH can be selectively removed to form second recessed regions R2 between the insulating patterns 220 spaced apart from each other along the third direction Z. The second recessed regions R2 can be formed by a wet etching process and / or an isotropic dry etching process to remove the second sacrificial pattern 222. Since the insulating patterns 220 include a material having etching selectivity with respect to the second sacrificial pattern 222, the insulating patterns 220 can not be removed when the second sacrificial pattern 222 is removed. In addition, the barrier layer BKL can not be removed when the second sacrificial pattern 222 is removed. The selective removal of the second sacrificial pattern 222 can be performed by an etching process (e.g., by applying an etching solution including phosphoric acid). The second recessed regions R2 can horizontally extend into regions between the insulating patterns 220 from the trench TH. A portion of the top and bottom surfaces of the insulating patterns 220 and the outer side surface of the charge storage structure CTS can be exposed through the second recessed regions R2. After forming the second recessed regions R2, a curing process can be performed to repair damage to the surfaces of the insulating patterns 220.

[0077] Referring to Figure 7J A horizontal insulating layer PL can be formed to cover some surfaces of layers exposed by the second recessed regions R2 and the trench TH. For example, the horizontal insulating layer PL can be formed to conformally cover surfaces of the insulating patterns 220, the portion of the outer side surface of the charge storage structure CTS exposed by the second recessed regions R2, the side and bottom surfaces of the barrier layer BKL, and the top and side surfaces of the first interlayer insulating layer ILD1. The horizontal insulating layer PL can be formed by a deposition method having good step coverage properties. For example, the horizontal insulating layer PL can be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The horizontal insulating layer PL can be formed of or include at least one of silicon oxide (e.g., SiO2) and / or high-k dielectric materials (e.g., aluminum oxide (Al2O3) and / or hafnium oxide (HfO2)).

[0078] After forming the horizontal insulating layer PL, a heat treatment process can be performed to crystallize the primary source conductive pattern PSP1. The heat treatment process can crystallize an amorphous structure of the primary source conductive pattern PSP1 to form a polycrystalline structure in the first source conductive pattern SP1 in a short time. In an embodiment, the heat treatment process can be performed by a rapid thermal annealing (RTA) process. The RTA process can be performed at a temperature of about 600 °C or more for a process time of about 30 seconds to about 1 minute. The size of the grains can be proportional to the process time of the heat treatment process. For example, the shorter the process time of the heat treatment process, the smaller the size of the grains, and the longer the process time of the heat treatment process, the larger the size of the grains. In an embodiment, the first source conductive pattern SP1 can be formed to have a grain GS1 (e.g., see FIG. 2B) having a size of about 10 nm to about 100 nm. Figure 4A) has a small grain size. For example, the grain size of the grains GS1 of the first source conductive pattern SP1 can be formed to be smaller than the grain size of the grains GS2 (see, for example, Figure 4A ) of the substrate 200. In addition, the grain size of the grains GS1 of the first source conductive pattern SP1 can be formed to be smaller than the grain size of the grains GS3 (see, for example, Figure 4A ) of the second source conductive pattern SP2.

[0079] In an embodiment, the grain size of the grains of the first source conductive pattern SP1 including the second impurity (e.g., a non-conductive impurity) can be smaller than the grain size of the grains of the first source conductive pattern SP1 in an embodiment not including the second impurity. For example, the second impurity can be used to inhibit grain growth of the grains of the first source conductive pattern SP1.

[0080] If the grains GS1 of the first source conductive pattern SP1 are formed to have a small grain size, the number of grain boundaries of the first source conductive pattern SP1 can increase. According to embodiments of inventive concepts, by reducing the grain size of the grains GS1 of the first source conductive pattern SP1, the amount of the first impurity (e.g., phosphorus) in the first source conductive pattern SP1 and the amount of the impurity doped in the substrate 200 can increase. For example, by isolating the impurity at the grain boundaries of the first source conductive pattern SP1 can prevent diffusion of the impurity from the first source conductive pattern SP1 and the substrate 200 to the vertical channel portion VC. Thus, diffusion of the impurity into the vertical channel portion VC can be prevented or inhibited.

[0081] Referring to Figure 7K The gate electrodes 210a, 210b, 210c, and 210d can be formed by filling the second recessed regions R2 with a conductive material. The formation of the gate electrodes 210a, 210b, 210c, and 210d can include forming a conductive layer (not shown) to fill the second recessed regions R2 and performing an etching process to remove the conductive layer in the trenches TH and locally leave the conductive layer in the second recessed regions R2. After the gate electrodes 210a, 210b, 210c, and 210d are formed, spacers SL can be conformally formed on side surfaces of the horizontal insulating layer PL, on side surfaces of the first interlayer insulating layer ILD1, and on side surfaces of the gate electrodes 210a, 210b, 210c, and 210d on the side of the trenches TH, on the horizontal insulating layer PL at a bottom surface of the trenches TH, and on a top surface of the first interlayer insulating layer ILD1. The spacers SL can be formed of or include at least one of insulating materials (e.g., silicon oxide and / or silicon nitride).

[0082] Referring back to Figure 3 and Figure 4CAn anisotropic etching process can be performed to etch a portion of the barrier layer BKL, a portion of the horizontal insulating layer PL, and a portion of the spacer SL to expose a top surface of the substrate 200 under the trench TH. A barrier pattern BP can be formed by etching a portion of the barrier layer BKL, and the barrier pattern BP can be formed to cover side surfaces of the first source conductive pattern SP1 and the second source conductive pattern SP2 and to expose a portion of the top surface of the substrate 200 under the trench TH. A portion of the horizontal insulating layer PL on the top surface of the first interlayer insulating layer ILD1 and a portion of the spacer SL can also be etched during the anisotropic etching process to expose the top surface of the first interlayer insulating layer ILD1.

[0083] A common source region CSR can be formed in the substrate 200 under the trench TH. The common source region CSR can be formed by an ion implantation process. The common source region CSR can be formed to have a different conductivity type from the substrate 200. A common source pattern CSP can be formed in the trench TH. The common source pattern CSP can be electrically connected to the common source region CSR. The common source pattern CSP can be formed of or include at least one of a conductive material (e.g., tungsten, copper, and / or aluminum) and a metal nitride (e.g., titanium nitride and / or tantalum nitride).

[0084] A second interlayer insulating layer ILD2 can be formed on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 can be formed to cover a top surface of the first interlayer insulating layer ILD1 and a top surface of the common source pattern CSP. A channel contact plug 310 can be located on the pad 240. The channel contact plug 310 can penetrate the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 and can be electrically connected to the pad 240. A bit line BL can be formed on the second interlayer insulating layer ILD2. The bit line BL can be formed to extend in the second direction Y. The bit line BL can be electrically connected to the channel contact plug 310.

[0085] According to embodiments of the inventive concept, a grain size of a first source conductive pattern in contact with a vertical channel portion can be reduced. In this case, more grain boundaries can be formed in the first source conductive pattern, and impurities doped in the first source conductive pattern and the substrate can be isolated in the grain boundaries. Accordingly, impurities can be prevented or inhibited from diffusing into the vertical channel portion, thereby improving electrical characteristics and reliability characteristics of a three-dimensional semiconductor memory device.

[0086] While example embodiments of the inventive concept have been particularly shown and described, those of ordinary skill in the art will understand that changes can be made in form and details without departing from the spirit and scope of the appended claims.

Claims

1. A three-dimensional semiconductor memory device comprising: a first source conductive pattern including a polycrystalline material including first grains, the first source conductive pattern being located on a substrate including a polycrystalline material including second grains, each of the substrate and the first source conductive pattern including an n-type impurity, and a granularity of the first grains being smaller than a granularity of the second grains; a stack including a plurality of gate electrodes, the plurality of gate electrodes being stacked on the first source conductive pattern; and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern. the first source conductive pattern is in contact with a top surface of the substrate.

2. The three-dimensional semiconductor memory device of claim 1, wherein, a ratio of the granularity of the first grains to the granularity of the second grains is in a range of 0.1 to 0.

01.

3. The three-dimensional semiconductor memory device of claim 1, wherein, 4. The three-dimensional semiconductor memory device according to claim 1, wherein the first source conductive pattern further includes a crystal growth suppression element for suppressing crystal growth of the first grains of the first source conductive pattern. the crystal growth suppression element includes at least one of carbon, nitrogen, oxygen, chlorine, and bromine.

5. The three-dimensional semiconductor memory device of claim 4, wherein, 6. The three-dimensional semiconductor memory device according to claim 1, further comprising: a charge storage layer interposed between the vertical channel portion and the stack, wherein the charge storage layer is in contact with a portion of a top surface of the first source conductive pattern.

7. The three-dimensional semiconductor memory device according to claim 1, further comprising: a second source conductive pattern located between the first source conductive pattern and the stack; and the first source conductive pattern includes: a horizontal portion interposed between the substrate and the second source conductive pattern; a first protruding portion extending from the horizontal portion and interposed between a portion of a side surface of the second source conductive pattern and a portion of an outer side surface of the vertical channel portion; and a second protruding portion extending from the horizontal portion and interposed between a portion of the outer side surface of the vertical channel portion and a portion of a side surface of the substrate, wherein the vertical channel portion extends into the substrate.

8. The three-dimensional semiconductor memory device according to claim 1, further comprising: a channel recessed portion recessed from a top surface of the substrate; a charge storage layer located on the first source conductive pattern and surrounding a portion of an outer side surface of the vertical channel portion; and a dummy pattern located in the channel recessed portion and surrounding a lower side surface and a bottom surface of the vertical channel portion, the dummy pattern being spaced apart from the charge storage layer, wherein the vertical channel portion extends into the channel recessed portion.

9. The three-dimensional semiconductor memory device according to claim 1, further comprising: a second source conductive pattern located between the first source conductive pattern and the stack, the second source conductive pattern including third grains, wherein a granularity of the third grains is smaller than a granularity of the second grains, and the granularity of the third grains is larger than the granularity of the first grains. each of the substrate and the first source conductive pattern is formed of a semiconductor material. ​ ​ 10. The three-dimensional semiconductor memory device of claim 1, wherein, ​ 11. The three-dimensional semiconductor memory device according to claim 1, further comprising: a lower substrate located below the substrate; and a peripheral circuit structure located between the lower substrate and the substrate, wherein the peripheral circuit structure includes a peripheral circuit transistor.

12. The three-dimensional semiconductor memory device according to claim 1, further comprising: an upper stack including a plurality of upper gate electrodes stacked on the stack, wherein the vertical channel portion extends in a vertical direction from a top surface of the substrate to penetrate the upper stack, and a top width of a lower portion of the vertical channel portion penetrating the stack is larger than a bottom width of an upper portion of the vertical channel portion penetrating the upper stack.

13. The three-dimensional semiconductor memory device according to claim 1, further comprising: a common source pattern located on the substrate at one side of the stack and extending in a first direction.

14. A three-dimensional semiconductor memory device comprising: a first source conductive pattern and a second source conductive pattern located on a substrate, the first source conductive pattern including impurities not contained in the second source conductive pattern; a stack including a plurality of gate electrodes stacked on the second source conductive pattern; and a vertical channel portion penetrating the stack and the first source conductive pattern and the second source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

15. The three-dimensional semiconductor memory device according to claim 14, wherein the first source conductive pattern includes a first impurity and a second impurity, the first impurity includes an n-type impurity, and the second impurity includes at least one of carbon, nitrogen, oxygen, chlorine, and bromine.

16. The three-dimensional semiconductor memory device according to claim 14, wherein the first source conductive pattern has a first grain, the substrate has a second grain, and a ratio of a size of the first grain to a size of the second grain is in a range of 0.1 to 0.

01.

17. The three-dimensional semiconductor memory device according to claim 14, wherein the substrate is formed of a single crystal silicon, and the first source conductive pattern is formed of a polycrystal silicon.

18. A three-dimensional semiconductor memory device comprising: a peripheral circuit structure located on a first substrate, the peripheral circuit structure including a peripheral circuit transistor; a second substrate located on the peripheral circuit structure; a first source conductive pattern located on the second substrate, the first source conductive pattern including a first impurity and a second impurity, the first impurity including an n-type impurity, the second impurity including a crystal growth inhibiting element for inhibiting crystal growth in the first source conductive pattern; a stack including a plurality of gate electrodes stacked on the first source conductive pattern; a vertical channel portion penetrating the stack and the first source conductive pattern and extending into the second substrate, the vertical channel portion being in contact with a side surface of the first source conductive pattern; and a charge storage layer interposed between the vertical channel portion and the stack.

19. The three-dimensional semiconductor memory device according to claim 18, further comprising: a dummy pattern located in the second substrate and surrounding the lower side surface and the bottom surface of the vertical channel portion, wherein the dummy pattern includes a material identical to that of the charge storage layer.

20. The three-dimensional semiconductor memory device of claim 18, wherein, the n-type impurity includes phosphorus, and the second impurity includes at least one of carbon, nitrogen, oxygen, chlorine, and bromine.

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