Semiconductor device structure and manufacturing method thereof

Abstract

A semiconductor device structure including a bonding pad isolation structure. A semiconductor substrate has a backside surface and a frontside surface opposite to the backside surface. A bonding pad extends through the semiconductor substrate. The bonding pad isolation structure is disposed in the semiconductor substrate. The bonding pad isolation structure extends from the frontside surface of the semiconductor substrate to the backside surface and extends continuously around the bonding pad.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor device structure and a manufacturing method thereof, and more particularly to an isolation structure for a bonding pad structure and a manufacturing method thereof. Background Art

[0002] Integrated circuits (ICs) with image sensors are widely used in modern electronic devices such as cameras and mobile phones. Complementary metal-oxide semiconductor (CMOS) devices have become a commonly used IC image sensor. Compared with charge-coupled devices (CCDs), CMOS image sensors are increasingly popular due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. CMOS image sensors include some types such as front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors. Summary of the invention

[0003] According to some embodiments, a semiconductor device structure includes a semiconductor substrate, a bonding pad, and a bonding pad isolation structure. The semiconductor substrate has a backside surface and a frontside surface opposite to the backside surface, the bonding pad extends through the semiconductor substrate, and the bonding pad isolation structure is disposed in the semiconductor substrate, wherein the bonding pad isolation structure extends from the frontside surface to the backside surface of the semiconductor substrate, and the bonding pad isolation structure continuously extends around the bonding pad.

[0004] According to some embodiments, a semiconductor device structure includes a semiconductor substrate, an interconnect structure, a bonding pad, and a bonding pad isolation structure. The semiconductor substrate overlies a carrier substrate, a photodetector is disposed in the semiconductor substrate, the interconnect structure is disposed between the semiconductor substrate and the carrier substrate, wherein an upper conductive line layer is disposed in the interconnect structure, the bonding pad extends through the semiconductor substrate to the interconnect structure, wherein the bonding pad contacts the upper conductive line layer and has a top surface disposed above the semiconductor substrate, wherein the bonding pad is laterally offset from the photodetector, and the bonding pad isolation structure is disposed in the semiconductor substrate, wherein the bonding pad isolation structure continuously surrounds an outer sidewall of the bonding pad.

[0005] According to some embodiments, a method for forming a semiconductor device structure includes forming a bonding pad isolation structure in a semiconductor substrate, extending the bonding pad isolation structure from the front side surface of the semiconductor substrate to the back side surface, forming an internal wiring structure on the front side surface of the semiconductor substrate, wherein the internal wiring structure includes a conductive wire layer, patterning the front side surface of the semiconductor substrate to define a bonding pad opening and expose the upper surface of the conductive wire layer, wherein the bonding pad opening is laterally arranged between the inner side walls of the bonding pad isolation structure, and forming a bonding pad in the bonding pad opening, extending the bonding pad from the semiconductor substrate to the conductive wire layer and continuously surrounded by the bonding pad isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated chip including bond pads extending through a semiconductor substrate are shown.

[0008] Figure 2 As shown by Figure 1 and Figure 2 The cutting lines in the Figure 1 Top views of some alternative embodiments of an IC.

[0009] Figure 3 Cross-sectional views of some embodiments of image sensors including bond pads laterally offset from multiple photodetectors are shown.

[0010] Figure 4 As shown by Figure 3 and Figure 4 The cutting lines in the Figure 3 Top views of some alternative embodiments of image sensors.

[0011] Figure 5 , Fig. 6A , Figure 6B , Figure 7 as well as Figure 8 Cross-sectional views of some alternative embodiments of bond pad isolation structures surrounding bond pads are shown.

[0012] Figures 9 to 21 A series of cross-sectional views illustrating some embodiments of a first method for forming a bond pad isolation structure surrounding a bond pad.

[0013] Fig. 22 Show Figures 9 to 21 A block diagram of some embodiments of the first method.

[0014] Figures 23 to 30 A series of cross-sectional views illustrating some embodiments of a second method for forming a bond pad isolation structure surrounding a bond pad.

[0015] Fig.31 Show Figures 23 to 30 A block diagram of some embodiments of the second method.

[0016] Figure 32 to Figure 38 A series of cross-sectional views illustrating some embodiments of a third method for forming a bond pad isolation structure surrounding a bond pad.

[0017] Fig.39 Show Figure 32 to Figure 38 A block diagram of some embodiments of the third method.

[0018] Description of Figure Numbers

[0019] 100, 500, 600, 700, 800: integrated chip;

[0020] 101a: device area;

[0021] 101b: bonding pad area;

[0022] 102: carrier substrate;

[0023] 103: Inner connection dielectric structure;

[0024] 104: Internal connection structure;

[0025] 106: via hole;

[0026] 108: conductive wire;

[0027] 108a: upper conductive line layer;

[0028] 110: semiconductor substrate;

[0029] 110bs: dorsal;

[0030] 110fs: front side;

[0031] 110is: internal sidewall;

[0032] 110us: upper surface;

[0033] 112: Shallow trench isolation structure;

[0034] 114: bonding pad isolation structure;

[0035] 114a: a first bonding pad isolation layer;

[0036] 114b: a second bonding pad isolation layer;

[0037] 116: bonding pad;

[0038] 116a: upper conductive body;

[0039] 116b: conductive protrusion;

[0040] 116o: pad opening;

[0041] 116ts: top surface;

[0042] 118: Dielectric structure;

[0043] 120: semiconductor devices;

[0044] 200: top view;

[0045] 300: image sensor;

[0046] 302: Photodetector;

[0047] 304a: a first dielectric layer;

[0048] 304b: a second dielectric layer;

[0049] 304c: a third dielectric layer;

[0050] 304d: fourth dielectric layer;

[0051] 306: etching stop layer;

[0052] 308: first grid layer;

[0053] 310: second grid layer;

[0054] 312: grid structure;

[0055] 314: Color filter;

[0056] 400: top view;

[0057] 502: generally straight line;

[0058] 702: device STI structure;

[0059] 802: first insulating layer;

[0060] 804: second insulating layer;

[0061] 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2300, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3200, 3300, 3400, 3500, 3600, 3700, 3800: cross-sectional view;

[0062] 902: masking layer;

[0063] 1002: deep trench isolation layer;

[0064] 1202: dielectric protection layer;

[0065] 1302: plunger opening;

[0066] 1702: plunger structure;

[0067] 1802, 2402: bonding pad opening;

[0068] 2002: Bonding pad layer;

[0069] 2200: First method;

[0070] 2202, 2204, 2206, 2208, 2210, 2212, 2214, 2216, 2218, 3102, 3104, 3106, 3108, 3110, 3112, 3114, 3116, 3118, 3120, 3902, 3904, 3906, 3908, 3910: action;

[0071] 3100: Second method;

[0072] 3402: Bonding pad isolation opening;

[0073] 3502: first DTI layer;

[0074] 3504: second DTI layer;

[0075] 3900: Third method;

[0076] d1, d2, d v :distance;

[0077] Fig.1: Figure 1 ;

[0078] Fig.2: Figure 2 ;

[0079] Fig.3: Figure 3 ;

[0080] Fig.4: Figure 4 ;

[0081] h1, h2, h bp 、h dl :high;

[0082] T i , T s :thickness;

[0083] W1: Width. DETAILED DESCRIPTION

[0084] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature may not be in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0085] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted similarly accordingly.

[0086] The integrated chip generally includes a plurality of metal interconnect layers arranged along the front side of the substrate. The plurality of metal interconnect layers are configured to electrically connect the devices (e.g., transistors, photodetectors, etc.) arranged in the substrate. A back-side illuminated CMOS image sensor (BSI-CIS) includes a photodetector arranged in the substrate close to the back side of the substrate, so that the photodetector can receive light along the back side of the substrate. By receiving light along the back side of the substrate, the incident light does not pass through the plurality of metal interconnect layers, thereby increasing the optical efficiency of the photodetector.

[0087] With the BSI-CIS receiving light along the back side of the substrate, the substrate with the BSI-CIS is usually placed in a packaging structure in the form of a front side downward configuration that exposes the back side of the substrate. Because the back side of the substrate is exposed, the bonding pad is usually arranged along the back side of the substrate and connected to the metal inner wiring layer. The bonding pad may have several different configurations. For example, the bonding pad may be arranged in a bonding pad opening that extends through the front side of the substrate to the back side of the substrate. In order to electrically isolate the bonding pad from the substrate, a dielectric structure is arranged along the sidewall of the substrate that defines the bonding pad opening. However, the dielectric structure is arranged along the bonding pad opening to increase the complexity, time and cost associated with manufacturing the BSI-CIS. In addition, the top surface of the bonding pad may be arranged below the back side of the substrate. This can increase the light received by the photodetector, however, this will reduce the reliability of the bonding between the bonding pad and another bonding structure. In addition, the bonding pad may include an upper conductive section extending above the back side of the substrate, thereby increasing the reliability of the bonding between the bonding pad and another bonding structure. However, in such embodiments, the upper conductive segment may reflect light away from the photodetector, thereby reducing the reliability and / or quality of the image reproduced from the photodetector.

[0088] Therefore, in some embodiments, the present disclosure relates to an integrated chip including a bonding pad isolation structure surrounding a bonding pad. The integrated chip includes a plurality of photodetectors arranged in a substrate. The bonding pad region extends through the substrate to a metal interconnect wire at a position laterally offset from the photodetector, and the metal interconnect wire is arranged in an interconnect dielectric structure arranged along the front side of the substrate. The bonding pad is arranged in the bonding pad region and extends from the front side of the substrate to the back side of the substrate and is electrically coupled to the metal interconnect wire. In some embodiments, the bonding pad directly contacts the upper surface of the substrate and contacts the sidewall of the substrate. The bonding pad isolation structure has an annular shape and laterally surrounds the bonding pad. In addition, the bonding pad isolation structure extends from the back side of the substrate to the front side, thereby electrically isolating the bonding pad from a device (e.g., a photodetector and / or a transistor) disposed on and / or in the substrate. The bonding pad contacts the substrate to reduce the complexity, time, and cost associated with forming the bonding pad. In addition, the bonding pad isolation structure prevents "leakage" (i.e., current flow) from the bonding pad to a device disposed on and / or in the substrate.

[0089] Figure 1 A cross-sectional view of some embodiments of an integrated chip 100 having bonding pads 116 disposed within a bonding pad region 101 b is shown.

[0090] The integrated chip 100 includes an interconnect structure 104 disposed along a front side 110fs of a semiconductor substrate 110 (e.g., a silicon substrate). The interconnect structure 104 overlies a carrier substrate 102 (e.g., a silicon substrate), wherein the interconnect structure 104 is disposed between the semiconductor substrate 110 and the carrier substrate 102. The interconnect structure 104 includes a plurality of interconnect layers disposed within an interconnect dielectric structure 103. The plurality of interconnect layers alternate between conductive lines 108 and vias 106. The conductive lines 108 are configured to provide lateral connections (i.e., connections parallel to the upper surface of the carrier substrate 102), while the vias 106 are configured to provide vertical connections between adjacent conductive lines 108. The conductive lines 108 include an upper conductive line layer 108a. A dielectric structure 118 overlies a back side 110bs of the semiconductor substrate 110. A shallow trench isolation (STI) structure 112 is disposed in the semiconductor substrate 110 and extends along the upper surface of the interconnect dielectric structure 103 .

[0091] The bonding pad region 101b extends through the semiconductor substrate 110 to the upper conductive line layer 108a at a position laterally offset from the device region 101a. In some embodiments, the device region 101a includes one or more semiconductor devices 120 (e.g., transistors, resistors, varactors, etc.) and / or photodetectors (not shown) disposed in and / or on the semiconductor substrate 110. The bonding pad 116 and the bonding pad isolation structure 114 are disposed in the bonding pad region 101b. The bonding pad 116 includes an upper conductive body 116a and a conductive protrusion 116b located below the upper conductive body 116a. The upper conductive body 116a includes the same material as the conductive protrusion 116b (e.g., aluminum, copper). In some embodiments, the upper conductive body 116a directly overlies the upper surface 110us of the semiconductor substrate 110 and directly contacts the upper surface 110us. In such embodiments, the conductive protrusion 116b directly contacts the sidewall of the semiconductor substrate 110 and extends from the upper conductive body 116a to the upper conductive line layer 108a. In addition, the upper conductive body 116a has a sidewall that defines a pad opening 116o overlying the conductive protrusion 116b. The bonding pad 116 can be configured to electrically couple one or more semiconductor devices 120 to another integrated chip (not shown). In some embodiments, the upper conductive body 116a is laterally offset from the inner sidewall 110is of the semiconductor substrate 110 by a non-zero distance.

[0092] The bonding pad isolation structure 114 is laterally offset from and surrounds the outer sidewalls of the bonding pad 116. In some embodiments, the bonding pad isolation structure 114 includes a material different from the semiconductor substrate 110 (e.g., silicon dioxide). The bonding pad isolation structure 114 may extend from the front side 110fs of the semiconductor substrate 110 to the back side 110bs. In some embodiments, the bonding pad isolation structure 114 has a height h1, which is greater than or equal to the height h2 of the semiconductor substrate 110. The bonding pad isolation structure 114 is configured to electrically isolate the bonding pad 116 from other devices (e.g., semiconductor device 120) and / or doped regions (not shown) disposed in and / or on the semiconductor substrate 110. This can reduce and / or prevent "leakage" (i.e., current flow) between the bonding pad 116 and other devices and / or doped regions disposed in and / or on the semiconductor substrate 110, thereby increasing the reliability and tolerance of the integrated chip 100. Additionally, in some embodiments, when the bonding pads 116 directly contact the semiconductor substrate 110 , the complexity, cost, and time associated with forming the integrated chip 100 may be reduced.

[0093] Figure 2 As shown by Figure 1 and Figure 2 The cutting lines in the Figure 1 200 of some alternative embodiments of the integrated chip 100. For ease of illustration, Figure 2 The top view 200 is omitted Figure 1 The dielectric structure 118 is provided.

[0094] like Figure 2As shown in , the bonding pad isolation structure 114 has an annular shape, wherein the inner sidewall of the bonding pad isolation structure 114 completely surrounds the outer sidewall of the bonding pad 116. The inner sidewall of the bonding pad isolation structure 114 is laterally offset from the outer sidewall of the bonding pad isolation structure 114 by a distance d1. In some embodiments, the distance d1 is non-zero. When viewed from above, the bonding pad isolation structure 114 has a rectangular / square shape with rounded edges, however, the bonding pad isolation structure 114 may have other shapes, such as a circular / elliptical shape. When viewed from above, the bonding pad 116 has a rectangular / square shape with rounded edges, however, the bonding pad 116 may have other shapes, such as a circular / elliptical shape. In some embodiments, the shape of the bonding pad isolation structure 114 corresponds to the shape of the bonding pad 116. In addition, the sidewalls of the bonding pad 116 that define the pad opening 116o are laterally offset from each other by a non-zero distance. In some embodiments, a solder bump (not shown) may be laterally disposed between the pad openings 116o. When viewed from above, the pad opening 116o may have, for example, a square / rectangular shape. The bonding pad isolation structure 114 continuously surrounds the outer sidewall of the bonding pad 116 and extends from the front side ( Figure 1 The front side 110fs) extends to the back side ( Figure 1 Thus, the bonding pad isolation structure 114 electrically isolates the bonding pad 116 from other semiconductor devices and / or doped regions disposed within and / or on the semiconductor substrate 110. The STI structure 112 is directly below the bonding pad 116. In some embodiments, the outer sidewalls of the bonding pad 116 are laterally spaced apart between the outer sidewalls of the STI structure 112.

[0095] Figure 3 A cross-sectional view of some embodiments of an image sensor 300 including a bond pad 116 laterally offset from a plurality of photodetectors 302 is shown.

[0096] The semiconductor substrate 110 overlies the carrier substrate 102. In some embodiments, the semiconductor substrate 110 and / or the carrier substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. A plurality of photodetectors 302 are disposed in the semiconductor substrate 110. In some embodiments, the photodetectors 302 extend from the back side 110bs of the semiconductor substrate 110 to a point below the back side 110bs. In other embodiments, the point is located at the front side 110fs of the semiconductor substrate 110, the front side 110fs being opposite to the back side 110bs of the semiconductor substrate 110. An interconnect structure 104 is disposed along the front side 110fs of the semiconductor substrate 110. The interconnect structure 104 includes an interconnect dielectric structure 103, a plurality of conductive lines 108, and a plurality of vias 106. The semiconductor substrate 110 is bonded to the carrier substrate 102 by means of the interconnect structure 104. In some embodiments, the conductive line 108 and / or the via 106 may be or include aluminum, copper, aluminum-copper, tungsten, etc. In some embodiments, the interconnect dielectric structure 103 may include one or more dielectric layers (eg, silicon dioxide).

[0097] The dielectric structure 118 overlies the back side 110bs of the semiconductor substrate 110. In some embodiments, the dielectric structure 118 includes one or more dielectric layers, such as a first dielectric layer 304a, a second dielectric layer 304b, a third dielectric layer 304c, and a fourth dielectric layer 304d. In some embodiments, the first dielectric layer 304a may be, for example, or include a metal oxide, such as aluminum oxide or another suitable oxide. The second dielectric layer 304b may be, for example, or include a metal oxide, such as hafnium oxide or another suitable oxide. The third dielectric layer 304c may be, for example, or include a metal oxide, such as tantalum oxide or another suitable oxide. The fourth dielectric layer 304d may be, for example, or include an oxide (e.g., silicon dioxide, another suitable oxide), undoped silicon glass (USG), polysilicon, another suitable dielectric, and / or may have a thickness in the range of about 500 angstroms to 3,000 angstroms. The dielectric structure 118 may be configured to protect the back side 110 bs of the semiconductor substrate 110 .

[0098] The etch stop layer 306 overlies the dielectric structure 118. The first grid layer 308 overlies the etch stop layer 306, and the second grid layer 310 overlies the first grid layer 308. A grid structure 312 includes segments of the first grid layer 308 and the second grid layer 310 vertically located above the photodetectors 302. The grid structure 312 is laterally located around and between the photodetectors 302 to define a plurality of color filter openings. A plurality of color filters 314 are arranged within the plurality of color filter openings and overlying the plurality of photodetectors 302. The grid structure 312 includes a dielectric material having a refractive index less than the refractive index of the color filters 314. Due to the lower refractive index, the grid structure 312 acts as a radiation guide for guiding incident electromagnetic radiation (i.e., light) to the corresponding photodetector 302. Additionally, the color filters 314 are each configured to block a first frequency range of incident electromagnetic radiation while passing a second frequency range of incident electromagnetic radiation (different from the first frequency range) to the underlying photodetector 302 .

[0099] In some embodiments, the etch stop layer 306 may be, for example, or include silicon carbide, silicon nitride, etc. and / or may have a thickness of about 1,500 angstroms. In some embodiments, the first grid layer 308 may be, for example, or include an oxide (e.g., silicon dioxide or another suitable oxide) and / or may have a thickness of about 5,600 angstroms. In other embodiments, the second grid layer 310 may be, for example, or include an oxide (e.g., silicon oxynitride or another suitable oxide) and / or may have a thickness of about 1,500 angstroms. In still other embodiments, the first grid layer 308 may be or include a metal, such as tungsten, another suitable metal, etc. In such embodiments, the grid structure 312 may be configured as a combined grid structure including one or more metal layers and one or more dielectric layers. In other embodiments, the grid structure 312 may be configured as a dielectric grid structure including one or more dielectric layers.

[0100] One or more semiconductor devices 120 (e.g., transistors, resistors, etc.) may be disposed within and / or on the front side 110fs of the semiconductor substrate. In such embodiments, the one or more semiconductor devices 120 may be, for example, pixel devices, such as transfer transistors, source follower transistors, reset transistors, etc. The one or more semiconductor devices 120, the photodetector 302, and the grid structure 312 are laterally arranged within the device region 101a of the image sensor 300. The device region 101a is laterally offset from the bonding pad region 101b of the image sensor 300. The bonding pad 116 and the bonding pad isolation structure 114 are laterally arranged within the bonding pad region 101b of the image sensor 300. Therefore, in some embodiments, the bonding pad 116 and the bonding pad isolation structure 114 are laterally offset from the photodetector 302 and / or the one or more semiconductor devices 120 by a non-zero distance.

[0101] The bonding pad 116 is configured to electrically couple one or more semiconductor devices 120 and / or the photodetector 302 to another integrated chip (not shown) by means of the interconnect structure 104. In some embodiments, the bonding pad 116 directly contacts the upper surface 110us of the semiconductor substrate 110 and has a protrusion extending through the semiconductor substrate 110 to the upper conductive line layer 108a. In such embodiments, the protrusion directly contacts the sidewall of the semiconductor substrate 110 disposed below the upper surface 110us of the semiconductor substrate 110. The protrusion extends through the shallow trench isolation (STI) structure 112 and the interconnect dielectric structure 103. In addition, the bonding pad 116 has a sidewall defining a pad opening 116o of the protrusion overlying the bonding pad 116. In other embodiments, the bonding pad 116 is laterally offset from the upper sidewall of the semiconductor substrate 110 and the sidewall of the dielectric structure 118 by a distance d2. In some embodiments, distance d2 is non-zero, so that bonding pad 116 can be electrically isolated from dielectric structure 118. In addition, in such embodiments, with non-zero distance d2, the upper sidewalls of semiconductor substrate 110 and / or the sidewalls of dielectric structure 118 can be protected from the bonding process performed on bonding pad 116 (i.e., from the downward force applied to bonding pad 116). This can increase the structural integrity of image sensor 300. In some embodiments, the top surface of bonding pad 116 is aligned with the top surface (not shown) of dielectric structure 118 (e.g., see FIG. 1 ). Figure 5 The bonding pad 116 has a bonding pad height h defined as from the upper surface 110 us of the semiconductor substrate 110 to the top surface of the bonding pad 116. bpIn some embodiments, the bonding pad height h bp It is about 12,000 angstroms.

[0102] The bonding pad isolation structure 114 laterally surrounds the bonding pad 116, wherein the bonding pad isolation structure 114 extends from the back side 110bs of the semiconductor to a point below the front side 110fs. Therefore, the bonding pad isolation structure 114 electrically isolates the bonding pad 116 from one or more semiconductor devices 120 and / or the photodetector 302, thereby preventing "leakage" (i.e., current flow) between the bonding pad 116 and adjacent devices. This improves the performance, stability, and reliability of the image sensor 300. The bonding pad isolation structure 114 has a height h1 that is greater than the height h2 of the semiconductor substrate 110. The bottom surface of the bonding pad isolation structure 114 is vertically located below the front side 110fs of the semiconductor substrate 110, separated by a distance d v In some embodiments, the distance d v is non-zero, where the bonding pad isolation structure 114 extends into the interconnect dielectric structure 103. In some embodiments, if the bottom surface of the bonding pad isolation structure 114 is above the front side 110fs (ie, the distance d v is negative and / or height h1 is less than height h2), then “leakage” may occur between bonding pad 116 and one or more semiconductor devices 120 and / or photodetector 302, thereby degrading the performance of image sensor 300. Bond pad isolation structure 114 may, for example, be or include an oxide, such as silicon dioxide or silicon nitride, silicon oxynitride, etc.

[0103] Figure 4 As shown by Figure 3 and Figure 4 The cutting lines in the Figure 3 A top view 400 of some alternative embodiments of image sensor 300 is shown.

[0104] like Figure 4 As shown in , the bonding pad isolation structure 114 has a ring shape, wherein the inner sidewall of the bonding pad isolation structure 114 completely surrounds the outer sidewall of the bonding pad 116. The outer sidewall of the bonding pad 116 is laterally offset from the inner sidewall 110is of the semiconductor substrate 110 by a distance d2. In some embodiments, the distance d2 is non-zero. The color filters 314 are arranged in an array including rows and columns and are respectively overlaid on the photodetectors ( Figure 3 In some embodiments, the color filters 314 have a rectangular / square shape and / or a circular / elliptical shape when viewed from above (not shown).

[0105] Figure 5Cross-sectional views of some alternative embodiments of an integrated chip 500 having a bond pad 116 surrounded by a bond pad isolation structure 114 are shown.

[0106] The top surface 116ts of the bonding pad 116 and the top surface of the dielectric structure 118 are aligned along substantially straight lines 502, respectively. In some embodiments, the substantially straight lines 502 are parallel to the back side 110bs of the semiconductor substrate 110. In other embodiments, the top surface 116ts of the bonding pad 116 is located above the top surface of the dielectric structure 118 (not shown). In addition, the bonding pad isolation structure 114 has an inclined sidewall, wherein the width W1 of the bonding pad isolation structure 114 increases continuously from the back side 110bs of the semiconductor substrate 110 to the front side 110fs of the semiconductor substrate 110. In such embodiments, during the formation of the integrated chip 500, the bonding pad isolation structure 114 may, for example, have been formed simultaneously with the STI structure 112 or after the STI structure 112 is formed and before the interconnect structure 104 is formed. In some embodiments, for example, the substantially straight lines 502 are configured as flat horizontal lines. In further embodiments, the substantially straight line 502 may vary from a range of -25 angstroms to 25 angstroms or from a range of -5 angstroms to 5 angstroms from a flat horizontal line disposed along the top surface 116ts of the bond pad 116. In still other embodiments, an angle is defined between a first point disposed along the substantially straight line 502 and a second point disposed along the substantially straight line 502, wherein the first point is laterally offset from the second point and the angle is approximately 180 degrees.

[0107] Fig. 6A Cross-sectional views of some alternative embodiments of an integrated chip 600 having a bond pad 116 surrounded by a bond pad isolation structure 114 are shown.

[0108] The bonding pad isolation structure 114 extends from the back side 110bs of the semiconductor substrate 110 to a point below the front side 110fs of the semiconductor substrate 110. In some embodiments, the bottom surface of the bonding pad isolation structure 114 may be aligned with the front side 110fs of the semiconductor substrate 110 (not shown). The bonding pad isolation structure 114 has an inclined sidewall, wherein the width W1 of the bonding pad isolation structure 114 decreases continuously from the back side 110bs of the semiconductor substrate 110 to the front side 110fs of the semiconductor substrate 110. In such embodiments, during the formation of the integrated chip 600, the bonding pad isolation structure 114 may, for example, have been formed after forming the interconnect structure 104.

[0109] Figure 6B Show Fig. 6AFIG. 6 is a cross-sectional view of some alternative embodiments of an integrated chip 600 in which the bond pad isolation structures 114 are laterally spaced between the outer sidewalls of the STI structures 112 .

[0110] Figure 7 Cross-sectional views of some alternative embodiments of an integrated chip 700 are shown having a device region 101 a laterally offset from a bond pad region 101 b .

[0111] The device STI structure 702 is disposed in the device region 101a, wherein the device STI structure 702 includes the same material as the STI structure 112. In some embodiments, the device STI structure 702 has a bottom surface and a top surface that are aligned with the bottom surface and the top surface of the STI structure 112, respectively. In other embodiments, the device STI structure 702 has a ring shape and surrounds at least one semiconductor device 120 disposed in and / or on the semiconductor substrate 110. The device STI structure 702 can further increase the electrical isolation between the semiconductor device 120 and the bonding pad 116. In addition, the bottom surface of the bonding pad isolation structure 114 is aligned with the bottom surface of the STI structure 112 and / or the bottom surface of the device STI structure 702. In some embodiments, the STI structure 112 extends continuously between the outer sidewalls of the bonding pad isolation structure 114, wherein the STI structure 112 further increases the electrical isolation between the bonding pad 116 and other devices disposed on and / or within the semiconductor substrate 110 (e.g., the semiconductor device 120, a photodetector (not shown), etc.). In other embodiments, the STI structure 112 and the bonding pad isolation structure 114 include the same material, wherein the bonding pad isolation structure 114 is a protrusion of the STI structure 112.

[0112] Figure 8 Cross-sectional views of some alternative embodiments of an integrated chip 800 having a bond pad isolation structure 114 disposed around a bond pad 116 are shown.

[0113] The first insulating layer 802 is disposed along the sidewalls of the dielectric structure 118 and the sidewalls of the semiconductor substrate 110. The first insulating layer 802 is disposed between the bonding pad 116 and the upper surface 110us of the semiconductor substrate 110. The bonding pad 116 includes a conductive body disposed above the upper surface 110us of the semiconductor substrate 110 and a conductive protrusion extending from the conductive body to the upper conductive line layer 108a. The second insulating layer 804 is disposed along the sidewalls of the first insulating layer 802 and along the sidewalls of the protrusion of the bonding pad 116. The second insulating layer 804 is disposed between the sidewalls of the semiconductor substrate 110 and the protrusion of the bonding pad 116, wherein the second insulating layer 804 extends continuously around the corresponding protrusion. The first insulating layer 802 and the second insulating layer 804 are respectively configured to electrically isolate the bonding pad 116 from the semiconductor substrate 110. This further improves the performance and reliability of the integrated chip 800. In some embodiments, the first insulating layer 802 may be or include an oxide, such as silicon dioxide, undoped silicon glass silicon dioxide (USGOX), another suitable oxide, etc. In some embodiments, the second insulating layer 804 may be or include an oxide, such as silicon dioxide, USGOX, another suitable oxide, etc.

[0114] Figures 9 to 21 Cross-sectional views 900 to 2100 illustrate some embodiments of a first method of forming an integrated chip including a bonding pad isolation structure that surrounds a bonding pad according to various aspects of the present disclosure. Figures 9 to 21 900 to 2100, but it should be understood that Figures 9 to 21 The structure shown in is not limited to the method described but can actually be independent of the method described. Figures 9 to 21 Described as a series of actions, it should be understood that these actions are not limited to the order of the actions and can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be completely or partially omitted.

[0115] like Fig. 9As shown in the cross-sectional view 900 of FIG. 1 , a semiconductor substrate 110 is provided and a masking layer 902 is formed on the front side 110 fs of the semiconductor substrate 110. In some embodiments, the semiconductor substrate 110 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. A shallow trench isolation (STI) structure 112 is formed on the front side 110 fs of the semiconductor substrate 110. In some embodiments, a process for forming the STI structure 112 may include: selectively etching the semiconductor substrate 110 to form a trench extending into the front side 110 fs of the semiconductor substrate 110; and filling the trench with a dielectric material (e.g., silicon dioxide, silicon carbide, etc.) (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, etc.). In further embodiments, the semiconductor substrate 110 is selectively etched by exposing the unmasked portions of the semiconductor substrate 110 to one or more etchants configured to selectively remove the unmasked portions of the semiconductor substrate 110. The masking layer 902 may be or include silicon-oxy-nitride, for example.

[0116] like Fig.10As shown in the cross-sectional view 1000 of FIG. 1 , a deep trench isolation (DTI) layer 1002 is formed over and in the semiconductor substrate 110. In some embodiments, the process for forming the DTI layer 1002 includes: forming a second masking layer over the masking layer 902 and the STI structure 112; patterning the semiconductor substrate 110 and the masking layer 902 according to the second masking layer, thereby forming a DTI opening in the semiconductor substrate 110; forming a DTI material (e.g., silicon oxide, silicon nitride, silicon oxynitride, plasma-enhanced oxide (PEOX), another suitable dielectric material, etc.) over the semiconductor substrate 110 (e.g., by a plasma-enhanced CVD (PECVD) process, a high aspect ratio process (HARP), PVD, or another suitable deposition process), wherein the DTI material fills the DTI opening. In some embodiments, forming the DTI material includes forming a first dielectric layer (e.g., comprising silicon oxide) over a second dielectric layer (e.g., comprising silicon nitride), the second dielectric layer lining the DTI opening, and the first dielectric layer filling the remainder of the DTI opening. In some embodiments, the bottom surface of the DTI layer 1002 is disposed over the back side 110bs of the semiconductor substrate 110. In some embodiments, the DTI layer 1002 is formed by, for example, CVD, PVD, ALD, or another suitable deposition process. In some embodiments, the DTI layer 1002 has a height h in a range of about 12,000 angstroms to 15,000 angstroms or greater than 20,000 angstroms. dl .

[0117] like Fig.11 As shown in the cross-sectional view 1100, the DTI layer ( Fig.10 The DTI layer 1002 of FIG. 1004 is planarized to define the bonding pad isolation structure 114. In some embodiments, the planarization process includes: Fig.10 The DTI layer 1002 of the semiconductor substrate 110 and / or the STI structure 112 are subjected to chemical-mechanical planarization (CMP) until the front side 110fs of the semiconductor substrate 110 is reached. In other embodiments, the planarization process can remove the masking layer 902. In some embodiments, after the planarization process is performed, the bond pad isolation structure 114 has a height h1 greater than 2 microns. In other embodiments, the width W1 of the bond pad isolation structure 114 decreases continuously from the front side 110fs to a point above the back side 110bs of the semiconductor substrate 110.

[0118] In some embodiments, the planarization process includes: Fig.10 CMP is performed on the DTI layer 1002 until the top surface of the STI structure 112 is exposed, thereby defining a bonding pad isolation structure 114 (not shown). In such an embodiment, Figure 7 As shown in the cross-sectional view of FIG. 1 , the upper surface of the STI structure 112 and the upper surface of the bonding pad isolation structure 114 are respectively vertically offset from the front side 110fs of the semiconductor substrate 110. In addition, in such embodiments, after the planarization is performed, a removal process is performed to remove the masking layer 902 (not shown).

[0119] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 12 , an interconnect structure 104 is formed on the front side 110 fs of the semiconductor substrate 110. The interconnect structure 104 includes an interconnect dielectric structure 103, a plurality of conductive lines 108, and a plurality of vias 106. In some embodiments, the interconnect dielectric structure 103 may be or include one or more inter-level dielectric (ILD) layers. The one or more ILD layers may be, for example, or include an oxide, such as silicon dioxide or another suitable oxide. In some embodiments, a process for forming the interconnect structure 104 includes forming the vias 106 and the conductive lines 108 by a single damascene process or a dual damascene process. For example, the first layer of the vias 106 and the first layer of the conductive lines 108 may be formed by a single damascene process, respectively. In addition, in such embodiments, the process includes forming the remaining layers of the conductive lines 108 and the vias 106 by repeatedly performing a dual damascene process. In some embodiments, the conductive line 108 and / or the via 106 may be or include, for example, aluminum, copper, aluminum-copper, tungsten, etc.

[0120] like Fig.13 As shown in the cross-sectional view 1300, Fig.12 The structure of is rotated 180 degrees, and the interconnect structure 104 is bonded to the carrier substrate 102. In some embodiments, the bonding process may include a fusion bonding process. In some embodiments, the carrier substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, after performing the bonding process, a thinning process is performed on the semiconductor substrate 110 until the bonding pad isolation structure 114 is exposed. In such embodiments, the thinning process reduces the initial thickness T of the semiconductor substrate 110 to 100%. i Reduce to thickness T s In some embodiments, the thickness T sis equal to the height h1 of the bonding pad isolation structure 114. In other embodiments, the thinning process is performed by a mechanical grinding process, CMP, some other thinning process, or any combination of the foregoing. For example, the thinning process may be performed entirely by a mechanical grinding process.

[0121] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 14 , a dielectric structure 118 is formed over the back side 110bs of the semiconductor substrate 110. In some embodiments, the dielectric structure 118 includes one or more dielectric layers, such as a first dielectric layer 304a, a second dielectric layer 304b, a third dielectric layer 304c, and a fourth dielectric layer 304d. In some embodiments, the first dielectric layer 304a, the second dielectric layer 304b, the third dielectric layer 304c, and / or the fourth dielectric layer 304d may be formed by CVD, PVD, ALD, or another suitable deposition process, respectively. In other embodiments, the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer 304a-d may include dielectric materials that are different from each other. For example, the first dielectric layer 304a may include aluminum oxide, the second dielectric layer 304b may include hafnium oxide, the third dielectric layer 304c may include tantalum oxide, and the fourth dielectric layer 304d may include silicon dioxide. The fourth dielectric layer 304d may, for example, have a thickness of about 1,300 angstroms. In addition, a dielectric cap layer 1202 is formed over the dielectric structure 118. The dielectric cap layer 1202 may include an oxide (e.g., silicon dioxide) and / or may serve as a hard mask protective layer for the dielectric structure 118 during subsequent processing steps. In some embodiments, the dielectric cap layer 1202 may, for example, have a thickness of about 4,500 angstroms. In such embodiments, the thickness of the dielectric cap layer 1202 is large enough (e.g., about 4,500 angstroms) so that the thickness of the fourth dielectric layer is not increased during subsequent processing steps (e.g., Fig.15 A first etching process and / or Fig.16 In some embodiments, the dielectric structure 118 has a thickness t1 of about 2,000 angstroms.

[0122] like Fig.15 As shown in the cross-sectional view 1500 of , a first etching process is performed on the dielectric protection layer 1202, the dielectric structure 118, and the semiconductor substrate 110, thereby forming a plug opening 1302. In some embodiments, the first etching process may include: performing a wet etching process, a dry etching process, or another suitable etching process. In some embodiments, the first etching process includes: forming a masking layer (not shown) above the dielectric protection layer 1202; exposing the unmasked area and the bottom layer of the dielectric protection layer 1202 to one or more etchants, thereby defining the plug opening 1302; and performing a removal process to remove the masking layer.

[0123] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1601 , a second etching process is performed on the STI structure 112, the interconnect dielectric structure 103, and the dielectric protection layer (dielectric protection layer 1202). This enlarges the plug opening 1302 and exposes the upper surface of the upper conductive line layer 108a. In some embodiments, the second etching process may include: performing a wet etching process, a dry etching process, or another suitable etching process. In some embodiments, the second etching process may include: performing a wet etching process, a dry etching process, or another suitable etching process. Fig.15 In such embodiments, the dielectric protection layer (dielectric protection layer 1202) may be removed by the blanket dry etching process and / or after performing the second etching process, the thickness of the fourth dielectric layer 304d may be, for example, about 1,300 angstroms.

[0124] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17 , a plug structure 1702 is formed in at least a portion of the plug opening 1302. In some embodiments, an upper surface of the plug structure 1702 is disposed below the back side 110bs of the semiconductor substrate 110. In some embodiments, a process for forming the plug structure 1702 includes: forming a plug material in the plug opening 1302; and performing an etch back process (e.g., a dry etching process, a wet etching process, etc.) to remove at least a portion of the plug material, thereby defining the plug structure 1702.

[0125] like Fig.18 As shown in the cross-sectional view 1800 of , a third etching process is performed on the dielectric structure 118 and the semiconductor substrate 110, thereby defining the bonding pad opening 1802. The third etching process defines an upper surface 110us of the semiconductor substrate 110, wherein the upper surface 110us of the semiconductor substrate 110 is located below the upper surface of the plug structure 1702. In some embodiments, the third etching process may include: performing a wet etching process, a dry etching process, or another suitable etching process. In some embodiments, the third etching process includes: forming a masking layer (not shown) above the dielectric structure 118; exposing the unmasked area of ​​the dielectric structure 118 and the semiconductor substrate 110 to one or more etchants, thereby defining the bonding pad opening 1802; and performing a removal process to remove the masking layer.

[0126] like Fig.19 As shown in the cross-sectional view 1900 of , a plug removal process is performed to remove the plug structure 1702, thereby expanding the bonding pad opening 1802 and exposing the upper surface of the upper conductive line layer 108a. In some embodiments, the plug removal process includes: performing a wet ash process and / or a dry ash process, followed by a wet etching process.

[0127] like Fig. 20 As shown in the cross-sectional view 2000, Fig.19 The bonding pad layer 2002 is formed over the structure of . In some embodiments, the bonding pad layer 2002 may be deposited and / or grown, for example, by electroless plating, electroplating, sputtering, or another suitable deposition process. In other embodiments, the bonding pad layer 2002 may be, for example, or include aluminum, copper, aluminum copper, etc. In some embodiments, the bonding pad layer 2002 may include the same material as the via 106 and / or the conductive line 108.

[0128] like Fig.21 As shown in the cross-sectional view 2100, the bonding pad layer ( Fig. 20 The bonding pad layer (2002) is subjected to a fourth etching process to define the bonding pad 116. The bonding pad 116 is laterally offset from the sidewalls of the semiconductor substrate 110 and the dielectric structure 118 by a distance d2. In some embodiments, the distance d2 is non-zero. In other embodiments, the fourth etching process includes: Fig. 20 A masking layer (not shown) is formed on the bonding pad layer 2002); the bonding pad layer ( Fig. 20 The unmasked area of ​​the bonding pad layer 2002 is exposed to one or more etchants, thereby defining the bonding pad 116; and a removal process is performed to remove the masking layer.

[0129] Although Figures 9 to 13 The bonding pad isolation structure 114 is described as being formed before forming the interconnect structure 104 on the front side 110fs of the semiconductor substrate 110, but it should be understood that the formation of the bonding pad isolation structure 114 is not limited to such a manufacturing method. For example, in some embodiments, the bonding pad isolation structure 114 may be formed after forming the interconnect structure 104, wherein the bonding pad isolation structure 114 extends into the upper surface of the interconnect dielectric structure 103 (e.g., see Fig. 6A In such embodiments, the bonding pad isolation structure 114 may be, for example, Fig.13 The bonding pad isolation structure 114 is formed after the thinning process of the semiconductor substrate 110 but before the formation of the dielectric structure 118. In still other embodiments, the bonding pad isolation structure 114 may be formed, for example, after the formation of the bonding pad 116. In such embodiments, the bonding pad isolation structure 114 extends through the dielectric structure 118 to the front side 110fs (not shown) of the semiconductor substrate 110.

[0130] Fig. 22A first method 2200 of forming an integrated circuit according to the present disclosure is shown. Although the first method 2200 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions can be performed in a different order than shown and / or can be performed simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown can be omitted, and other actions or events not shown can be included.

[0131] At act 2202, a shallow trench isolation (STI) structure is formed on a front side of a semiconductor substrate. Fig. 9 A cross-sectional view 900 corresponding to some embodiments of act 2202 is shown.

[0132] At act 2204, a bond pad isolation structure is formed in the semiconductor substrate. The bond pad isolation structure extends from a front side of the semiconductor substrate to a back side of the semiconductor substrate. Fig.10 and Fig.11 Cross-sectional view 1000 and cross-sectional view 1100 are shown corresponding to some embodiments of act 2204 .

[0133] At act 2206, an interconnect structure is formed on the front side of the semiconductor substrate. The interconnect structure includes an upper conductive line layer. Fig.12 A cross-sectional view 1200 is shown corresponding to some embodiments of act 2206 .

[0134] At act 2208, a dielectric structure is formed over the backside of the semiconductor substrate. Fig.14 A cross-sectional view 1400 is shown corresponding to some embodiments of act 2208 .

[0135] At act 2210, an etching process is performed to define a plug opening in the semiconductor substrate, thereby exposing an upper surface of the upper conductive line layer. Fig.15 and Fig.16 Cross-sectional view 1500 and cross-sectional view 1600 are shown corresponding to some embodiments of act 2210 .

[0136] At act 2212, a plug is formed in the plug opening. An upper surface of the plug is disposed between the front side and the back side of the semiconductor substrate. Fig.17 Cross-sectional view 1700 is shown corresponding to some embodiments of act 2212 .

[0137] At act 2214 , the dielectric structure and the semiconductor substrate are patterned, thereby defining a bond pad opening and an upper surface of the semiconductor substrate. Fig.18Cross-sectional view 1800 is shown corresponding to some embodiments of act 2214 .

[0138] At activity 2216, the plug is removed, thereby enlarging the bond pad opening and exposing the upper surface of the upper conductive line layer. Fig.19 Cross-sectional view 1900 is shown corresponding to some embodiments of act 2216 .

[0139] At act 2218, a bond pad is formed in the bond pad opening. The bond pad isolation structure extends continuously around the bond pad. Fig. 20 and Fig.21 Cross-sectional view 2000 and cross-sectional view 2100 are shown corresponding to some embodiments of act 2218 .

[0140] Figure 23 to Figure 30 Cross-sectional views 2300 to 3000 illustrate some embodiments of a second method of forming an integrated chip including a bonding pad isolation structure that surrounds a bonding pad according to various aspects of the present disclosure. Figures 23 to 30 2300 to 3000, but it should be understood that Figure 23 to Figure 30 The structure shown in is not limited to the method described but can actually be independent of the method described. Figure 23 to Figure 30 Described as a series of actions, it should be understood that these actions are not limited to the order of the actions and can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be completely or partially omitted.

[0141] like Fig.23 As shown in the cross-sectional view 2300 of FIG. 1 , a dielectric structure 118 is formed over the semiconductor substrate 110. In some embodiments, as shown in FIG. Figures 9 to 14 As shown and / or described in Fig.23 structure.

[0142] like Fig.24 As shown in the cross-sectional view 2400 of , a first etching process is performed on the dielectric structure 118 and the semiconductor substrate 110, thereby forming a bonding pad opening 2402. In some embodiments, the first etching process may be, for example, or include a dry etching process, a wet etching process, or another suitable etching process. In some embodiments, the first etching process includes: forming a masking layer (not shown) above the dielectric structure 118; exposing the unmasked area of ​​the dielectric structure 118 and the semiconductor substrate 110 to one or more etchants, thereby defining the bonding pad opening 2402; and performing a removal process to remove the masking layer. In some embodiments, the first etching process defines an upper surface 110us of the semiconductor substrate 110 disposed below the back side 110bs of the semiconductor substrate 110.

[0143] like Fig.25 As shown in cross-sectional view 2500 of FIG. 1 , a first insulating layer 802 is formed over dielectric structure 118 and semiconductor substrate 110, wherein first insulating layer 802 lines at least a portion of bonding pad opening 2402. In some embodiments, first insulating layer 802 may be, for example, or include an oxide (e.g., silicon oxide or another suitable oxide) and / or have a thickness of about 4,500 angstroms. In other embodiments, the thickness of first insulating layer 802 is large enough (e.g., about 4,500 angstroms) so that the thickness of fourth dielectric layer 304d is not increased during subsequent processing steps (e.g., Fig.28 during the third etching process).

[0144] like Fig.26 As shown in the cross-sectional view 2600 of , a second etching process is performed on the first insulating layer 802 and the semiconductor substrate 110, thereby enlarging the bonding pad opening 2402 and exposing the upper surface of the STI structure 112. In some embodiments, the second etching process includes: forming a masking layer (not shown) over the first insulating layer 802; exposing the unmasked area of ​​the first insulating layer 802 and the semiconductor substrate 110 to one or more etchants, thereby exposing the upper surface of the STI structure 112; and performing a removal process to remove the masking layer.

[0145] like Fig. 27 As shown in the cross-sectional view 2700 of , a second insulating layer 804 is formed over the first insulating layer 802 and the semiconductor substrate 110. The second insulating layer 804 lines the bonding pad opening 2402. In some embodiments, the second insulating layer 804 may be formed, for example, by PVD, CVD, or another suitable deposition process. In some embodiments, the second insulating layer 804 may be, for example, or include an oxide, such as silicon oxide or another suitable oxide.

[0146] like Fig.28 As shown in the cross-sectional view 2800 of FIG. 1 , a third etching process is performed on the first insulating layer 802 and the second insulating layer 804, the STI structure 112, and the interconnect dielectric structure 103, thereby exposing the upper surface of the upper conductive line layer 108a. In some embodiments, the third etching process may include performing a wet etching process, a dry etching process, or another suitable etching process. In another embodiment, the third etching process may include: Fig. 27 A blanket dry etching process is performed on the structure of , thereby removing the first insulating layer 802 from the upper surface of the fourth dielectric layer 304d. In such an embodiment, after the third etching process, the thickness of the fourth dielectric layer 304d may be about 1,300 angstroms.

[0147] like Fig.29As shown in the cross-sectional view 2900 of FIG. 29 , a bonding pad layer 2002 is formed in the bonding pad opening 2402. In some embodiments, the bonding pad layer 2002 may be deposited and / or grown, for example, by electroless plating, electroplating, sputtering, or another suitable deposition process. In other embodiments, the bonding pad layer 2002 may be, for example, or include aluminum, copper, aluminum copper, etc. In other embodiments, the bonding pad layer 2002 may include the same material as the via 106 and / or the conductive line 108.

[0148] like Fig.30 As shown in the cross-sectional view 3000, the bonding pad layer ( Fig.29 The bonding pad layer (2002) is subjected to a fourth etching process to define the bonding pad 116. The bonding pad 116 is laterally offset from the sidewalls of the first insulating layer 802 and the second insulating layer 804 by a distance d2. In some embodiments, the distance d2 is non-zero. In other embodiments, the fourth etching process includes: Fig.29 A masking layer (not shown) is formed on the bonding pad layer 2002); the bonding pad layer ( Fig.29 The unmasked area of ​​the bonding pad layer 2002 is exposed to one or more etchants, thereby defining the bonding pad 116; and a removal process is performed to remove the masking layer.

[0149] Fig.31 A second method 3100 of forming an integrated circuit according to the present disclosure is shown. Although the second method 3100 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions can be performed in a different order than shown and / or can be performed simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown can be omitted, and other actions or events not shown can be included.

[0150] At act 3102, a shallow trench isolation (STI) structure is formed on a front side of a semiconductor substrate. Fig. 9 A cross-sectional view 900 corresponding to some embodiments of act 3102 is shown.

[0151] At act 3104, a bond pad isolation structure is formed in the semiconductor substrate. The bond pad isolation structure extends from a front side of the semiconductor substrate to a back side of the semiconductor substrate. Fig.10 and Fig.11 Cross-sectional view 1000 and cross-sectional view 1100 are shown corresponding to some embodiments of act 3104 .

[0152] At act 3106, an interconnect structure is formed on the front side of the semiconductor substrate. The interconnect structure includes an upper conductive line layer. Fig.12 A cross-sectional view 1200 is shown corresponding to some embodiments of act 3106 .

[0153] At act 3108 , a dielectric structure is formed over the backside of the semiconductor substrate. Fig.14 A cross-sectional view 1400 corresponding to some embodiments of act 3108 is shown.

[0154] At act 3110 , the dielectric structure and the semiconductor substrate are patterned, thereby defining bond pad openings. Fig.24 A cross-sectional view 2400 corresponding to some embodiments of act 3110 is shown.

[0155] A first insulating layer is formed over the dielectric structure and the semiconductor substrate at act 3112. The first insulating layer lines the bond pad opening. Fig.25 Cross-sectional view 2500 is shown corresponding to some embodiments of act 3112 .

[0156] At act 3114, the first insulating layer and the semiconductor substrate are patterned, thereby enlarging the bond pad openings and exposing the upper surface of the STI structure. Fig.26 Cross-sectional view 2600 is shown corresponding to some embodiments of act 3114 .

[0157] At act 3116 , a second insulating layer is formed over the first insulating layer and the STI structure. Fig. 27 Cross-sectional view 2700 is shown corresponding to some embodiments of act 3116 .

[0158] At action 3118, the first and second insulating layers, the STI structure, and the interconnect structure are patterned, thereby exposing the upper surface of the upper conductive line layer and enlarging the bonding pad opening. Fig.28 Cross-sectional view 2800 is shown corresponding to some embodiments of act 3118 .

[0159] At act 3120, a bond pad is formed in the bond pad opening. A bond pad isolation structure extends continuously around the bond pad. Fig.29 and Fig.30 Cross-sectional view 2900 and cross-sectional view 3000 are shown corresponding to some embodiments of act 3120 .

[0160] Figure 32 to Figure 38 Cross-sectional views 3200 to 3800 illustrate some embodiments of a third method of forming an integrated chip including a bonding pad isolation structure that surrounds a bonding pad according to various aspects of the present disclosure. Figure 32 to Figure 383200 to 3800, but it should be understood that Figure 32 to Figure 38 The structure shown in is not limited to the method described but can actually be independent of the method described. Figure 32 to Figure 38 Described as a series of actions, it should be understood that these actions are not limited to the order of the actions and can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be completely or partially omitted.

[0161] like Fig.32 As shown in the cross-sectional view 3200 of FIG. 3 , a shallow trench isolation (STI) structure 112 is formed on the front side 110fs of the semiconductor substrate 110. In some embodiments, as Figures 9 to 11 As shown and / or described in Fig.32 The STI structure 112 .

[0162] like Fig.33 As shown in the cross-sectional view 3300 of FIG. 3 , an interconnect structure 104 is formed on the front side 110fs of the semiconductor substrate 110. The interconnect structure 104 is bonded to the carrier substrate 102, and a dielectric structure 118 is formed over the back side 110bs of the semiconductor substrate 110. In addition, a dielectric protection layer 1202 is formed over the dielectric structure 118. In some embodiments, as shown in FIG. Figure 12 to Figure 14 As shown and / or described in Fig.33 structure.

[0163] like Fig.34 As shown in the cross-sectional view 3400 of , an etching process is performed on the dielectric protection layer 1202, the dielectric structure 118, and the semiconductor substrate 110, thereby forming the bonding pad isolation opening 3402. In some embodiments, the etching process may remove at least a portion of the interconnect dielectric structure 103. In some embodiments, the etching process may include performing a wet etching process, a dry etching process, or another suitable etching process. In some embodiments, the etching process includes: forming a masking layer (not shown) above the dielectric protection layer 1202; exposing the unmasked area and the bottom layer of the dielectric protection layer 1202 to one or more etchants, thereby defining the bonding pad isolation opening 3402; and performing a removal process to remove the masking layer.

[0164] like Fig.35 As shown in the cross-sectional view 3500, above the dielectric protection layer 1202 and the bonding pad isolation opening ( Fig.34 The first DTI layer 3502 and the second DTI layer 3504 are formed in the bonding pad isolation opening 3402. In some embodiments, the first DTI layer 3502 is omitted and the second DTI layer 3504 completely fills the bonding pad isolation opening ( Fig.34In some embodiments, the first DTI layer 3502 may be, for example, or include an oxide (e.g., silicon dioxide, another suitable oxide, etc.) and / or may be formed to a thickness of about 15,000 angstroms. In other embodiments, the second DTI layer 3504 may be, for example, or include silicon oxynitride, another suitable dielectric material, etc. and / or may be formed to a thickness of about 700 angstroms.

[0165] like Fig.36 As shown in the cross-sectional view 3600, the first DTI layer and / or the second DTI layer ( Fig.35 The first DTI layer 3502 and the second DTI layer 3504 are planarized to define the bonding pad isolation structure 114. The bonding pad isolation structure 114 may include the first bonding pad isolation layer 114a and / or the second bonding pad isolation layer 114b. In some embodiments, the planarization process includes: Fig.35 Chemical mechanical planarization (CMP) is performed on the first DTI layer 3502, the second DTI layer 3504, and the dielectric protection layer 1202. In another embodiment, the planarization process can reduce the thickness of the dielectric protection layer 1202.

[0166] like Fig.37 As shown in the cross-sectional view 3700 of FIG. 37 , the bonding pad 116 is formed in the semiconductor substrate 110 and is continuously surrounded by the bonding pad isolation structure 114. In some embodiments, as shown in FIG. Figure 15 to Figure 21 As shown and / or described in Fig.37 In another embodiment, Figure 24 to Figure 30 The bonding pad 116 is formed as shown and / or described in FIG. Fig.35 The first DTI layer 3502 is formed Fig.37 In the structure, the bonding pad isolation structure 114 includes a first bonding pad isolation layer 114a. In some embodiments, the first bonding pad isolation layer 114a may be or include, for example, silicon dioxide, another suitable oxide, etc.

[0167] like Fig.38 As shown in the cross-sectional view 3800 of FIG. 1 , the bonding pad 116 is formed in the semiconductor substrate 110 and is continuously surrounded by the bonding pad isolation structure 114. In some embodiments, as shown in FIG. Figure 15 to Figure 21 As shown and / or described in Fig.38 In another embodiment, Figure 24 to Figure 30The bonding pad 116 is formed as shown and / or described in the drawings. The bonding pad isolation structure 114 includes a first bonding pad isolation layer 114a and a second bonding pad isolation layer 114b. In some embodiments, the first bonding pad isolation layer 114a may be, for example, or include silicon dioxide, another suitable oxide, etc. In other embodiments, the second bonding pad isolation layer 114b may be, for example, or include silicon oxynitride, another suitable dielectric material, etc.

[0168] Fig.39 A third method 3900 of forming an integrated circuit according to the present disclosure is shown. Although the third method 3900 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions can be performed in a different order than shown and / or can be performed simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown can be omitted, and other actions or events not shown can be included.

[0169] At act 3902, a shallow trench isolation (STI) structure is formed on a front side of a semiconductor substrate. Fig.32 A cross-sectional view 3200 is shown corresponding to some embodiments of act 3902 .

[0170] At act 3904, an interconnect structure is formed on the front side of the semiconductor substrate. The interconnect structure includes an upper conductive line layer. Fig.33 A cross-sectional view 3300 is shown corresponding to some embodiments of act 3904 .

[0171] At act 3906 , a dielectric structure is formed over the backside of the semiconductor substrate. Fig.33 A cross-sectional view 3300 is shown corresponding to some embodiments of act 3906 .

[0172] At act 3908, a bond pad isolation structure is formed in the semiconductor substrate and the dielectric structure. The bond pad isolation structure extends from the front side of the semiconductor substrate to the back side of the semiconductor substrate. Fig.35 and Fig.36 Cross-sectional view 3500 and cross-sectional view 3600 are shown corresponding to some embodiments of act 3908 .

[0173] At act 3910, a bond pad is formed in a semiconductor substrate. A bond pad isolation structure extends continuously around the bond pad. Fig.37 and Fig.38 Cross-sectional view 3700 and cross-sectional view 3800 are shown corresponding to some embodiments of act 3910 .

[0174] Therefore, in some embodiments, the present disclosure relates to a bonding pad region laterally offset from a device region. The bonding pad region includes a bonding pad extending through a semiconductor substrate to an internal wiring structure. A bonding pad isolation structure is disposed in the semiconductor substrate and continuously surrounds an outer sidewall of the bonding pad.

[0175] In some embodiments, the present disclosure provides a semiconductor device structure, which includes: a semiconductor substrate having a backside surface and a frontside surface opposite to the backside surface; a bonding pad extending through the semiconductor substrate; and a bonding pad isolation structure disposed within the semiconductor substrate, wherein the bonding pad isolation structure extends from the frontside surface of the semiconductor substrate to the backside surface, and wherein the bonding pad isolation structure extends continuously around the bonding pad.

[0176] In some embodiments, the bonding pad directly contacts the upper surface and sidewalls of the semiconductor substrate. In some embodiments, the bonding pad includes a conductive body and a conductive protrusion, the conductive body directly contacts the upper surface of the semiconductor substrate, wherein the top surface of the conductive body is vertically located above the backside surface of the semiconductor substrate, the conductive protrusion extends from the conductive body to a point below the frontside surface of the semiconductor substrate, wherein the conductive protrusion directly contacts the sidewalls of the semiconductor substrate, and the top surface of the conductive protrusion is aligned with the upper surface of the semiconductor substrate. In some embodiments, the semiconductor device structure further includes a plurality of photodetectors and a dielectric structure, the plurality of photodetectors are disposed in the semiconductor substrate, wherein the photodetectors are laterally offset from the bonding pad isolation structure by a non-zero distance, and the dielectric structure is disposed above the backside surface of the semiconductor substrate, wherein the top surface of the dielectric structure is aligned with the top surface of the bonding pad. In some embodiments, the semiconductor device structure further includes a transistor, which is laterally disposed on the frontside surface of the semiconductor substrate between the photodetector and the bonding pad isolation structure. In some embodiments, the semiconductor device structure further includes an interconnect structure disposed along the front surface of the semiconductor substrate, wherein the interconnect structure includes a conductive wire layer disposed within an interconnect dielectric structure, and the bonding pad extends through the interconnect dielectric structure and contacts the conductive wire layer. In some embodiments, the bottom surface of the bonding pad isolation structure is disposed below the front surface of the semiconductor substrate, and the bonding pad isolation structure extends into the interconnect dielectric structure. In some embodiments, the bonding pad isolation structure has a height greater than the height of the semiconductor substrate. In some embodiments, the semiconductor device structure further includes a first insulating layer and a second insulating layer, the first insulating layer being disposed along a first opposing sidewall of the semiconductor substrate and an upper surface of the semiconductor substrate, wherein the lower surface of the bonding pad directly contacts the upper surface of the first insulating layer, the first opposing sidewall continuously extending from the back surface to the upper surface of the semiconductor substrate, and the second insulating layer extending from the upper surface of the semiconductor substrate to a point above the front surface of the semiconductor substrate, wherein the second insulating layer separates the bonding pad from the semiconductor substrate. In some embodiments, an upper sidewall of the bond pad is laterally offset from a sidewall of the first insulating layer, wherein the second insulating layer extends along a lower sidewall of the bond pad from the lower surface of the bond pad to the point above the frontside surface.

[0177] In some embodiments, the present disclosure provides a semiconductor device structure, which includes: a semiconductor substrate overlying a carrier substrate, wherein a photodetector is disposed in the semiconductor substrate; an internal wiring structure disposed between the semiconductor substrate and the carrier substrate, wherein an upper conductive line layer is disposed in the internal wiring structure; a bonding pad extending through the semiconductor substrate to the internal wiring structure, wherein the bonding pad contacts the upper conductive line layer and has a top surface disposed above the semiconductor substrate, wherein the bonding pad is laterally offset from the photodetector; and a bonding pad isolation structure disposed in the semiconductor substrate, wherein the bonding pad isolation structure continuously surrounds the outer side wall of the bonding pad.

[0178] In some embodiments, the bonding pad isolation structure extends from the top surface of the semiconductor substrate to the interconnect structure. In some embodiments, the inner sidewall of the bonding pad isolation structure is laterally offset from the outer sidewall of the bonding pad by a non-zero distance. In some embodiments, the semiconductor device structure further includes a dielectric structure and a grid structure, the dielectric structure overlying the top surface of the semiconductor substrate, wherein the top surface of the dielectric structure is arranged along a substantially straight line, the grid structure overlying the photodetector, the dielectric structure is arranged between the grid structure and the semiconductor substrate, and the top surface of the bonding pad is arranged along the substantially straight line. In some embodiments, the semiconductor device structure further includes a shallow trench isolation structure, the shallow trench isolation structure is arranged in the semiconductor substrate and along the upper surface of the interconnect structure, the bonding pad includes a conductive protrusion, and the conductive protrusion extends through the shallow trench isolation structure to the upper conductive line layer. In some embodiments, the bonding pad isolation structure includes the same material as the shallow trench isolation structure. In some embodiments, the shallow trench isolation structure is laterally disposed between inner sidewalls of the bonding pad isolation structure, and the shallow trench isolation structure is laterally offset from the inner sidewalls of the bonding pad isolation structure by a non-zero distance.

[0179] In some embodiments, the present disclosure provides a method for forming a semiconductor device structure, the method comprising: forming a bonding pad isolation structure in a semiconductor substrate, wherein the bonding pad isolation structure extends from a front side surface of the semiconductor substrate to a back side surface; forming an internal wiring structure on the front side surface of the semiconductor substrate, wherein the internal wiring structure comprises a conductive wire layer; patterning the front side surface of the semiconductor substrate to define a bonding pad opening and expose an upper surface of the conductive wire layer, wherein the bonding pad opening is laterally disposed between inner side walls of the bonding pad isolation structure; and forming a bonding pad in the bonding pad opening, wherein the bonding pad extends from the semiconductor substrate to the conductive wire layer, and wherein the bonding pad isolation structure continuously surrounds the bonding pad.

[0180] In some embodiments, forming the bonding pad includes forming a bonding pad layer above the semiconductor substrate and the interconnect structure, so that the bonding pad layer fills the bonding pad opening and directly contacts the semiconductor substrate, and patterning the bonding pad layer to define the bonding pad, wherein the semiconductor substrate includes an upper sidewall and a lower sidewall below the upper sidewall, the upper sidewall and the lower sidewall define the bonding pad opening, and the bonding pad is laterally offset from the upper sidewall by a non-zero distance and directly contacts the lower sidewall. In some embodiments, the method for forming a semiconductor device structure further includes forming a shallow trench isolation structure on the front side surface of the semiconductor substrate, so that the outer sidewall of the shallow trench isolation structure is laterally located between the inner sidewalls of the bonding pad isolation structure, wherein the shallow trench isolation structure includes the same material as the bonding pad isolation structure.

[0181] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, comprising: A semiconductor substrate having a backside surface and a frontside surface opposite to the backside surface; a bonding pad extending through the semiconductor substrate; A shallow trench isolation structure is disposed along the front surface of the semiconductor substrate; as well as A bonding pad isolation structure is arranged in the semiconductor substrate, wherein the bonding pad isolation structure extends from the front side surface of the semiconductor substrate to the back side surface, and the bonding pad isolation structure extends continuously around the bonding pad, wherein at least a portion of the shallow trench isolation structure is laterally spaced between opposite side walls of the bonding pad isolation structure. 2 . The semiconductor device structure according to claim 1 , wherein the bonding pad directly contacts an upper surface and a sidewall of the semiconductor substrate, wherein the upper surface of the semiconductor substrate overlies the front side surface of the semiconductor substrate.

3. The semiconductor device structure according to claim 1, wherein the bonding pad comprises: a conductive body directly contacting an upper surface of the semiconductor substrate, wherein a top surface of the conductive body is vertically located above the backside surface of the semiconductor substrate, and the upper surface of the semiconductor substrate overlies the frontside surface of the semiconductor substrate; as well as A conductive protrusion extends from the conductive body to a point below the front side surface of the semiconductor substrate, wherein the conductive protrusion directly contacts the sidewall of the semiconductor substrate and a top surface of the conductive protrusion is aligned with the upper surface of the semiconductor substrate.

4. The semiconductor device structure according to claim 1, further comprising: a plurality of photodetectors disposed within the semiconductor substrate, wherein the photodetectors are laterally offset from the bond pad isolation structure by a non-zero distance; as well as A dielectric structure is disposed over the backside surface of the semiconductor substrate, wherein a top surface of the dielectric structure is aligned with a top surface of the bonding pad.

5. The semiconductor device structure according to claim 4, further comprising: A transistor is laterally disposed on the frontside surface of the semiconductor substrate between the photodetector and the bond pad isolation structure.

6. The semiconductor device structure according to claim 4, further comprising: The interconnect structure is disposed along the front surface of the semiconductor substrate, wherein the interconnect structure comprises a conductive line layer disposed in an interconnect dielectric structure, and the bonding pad extends through the interconnect dielectric structure and contacts the conductive line layer. 7 . The semiconductor device structure according to claim 6 , wherein a bottom surface of the bonding pad isolation structure is disposed below the front side surface of the semiconductor substrate, and the bonding pad isolation structure extends into the interconnect dielectric structure. 8 . The semiconductor device structure according to claim 1 , wherein the bonding pad isolation structure has a height greater than a height of the semiconductor substrate.

9. The semiconductor device structure according to claim 1, further comprising: a first insulating layer disposed along first opposing side walls of the semiconductor substrate and an upper surface of the semiconductor substrate, wherein the upper surface of the semiconductor substrate overlies the front surface of the semiconductor substrate, the lower surface of the bonding pad directly contacts the upper surface of the first insulating layer, and the first opposing side walls continuously extend from the back surface to the upper surface of the semiconductor substrate; as well as A second insulating layer extends from the upper surface of the semiconductor substrate to a point above the frontside surface of the semiconductor substrate, wherein the second insulating layer separates the bonding pad from the semiconductor substrate.

10. The semiconductor device structure of claim 9, wherein an upper sidewall of the bonding pad is laterally offset from a sidewall of the first insulating layer, and wherein the second insulating layer extends along a lower sidewall of the bonding pad from the lower surface of the bonding pad to the point above the front side surface. 11 . The semiconductor device structure according to claim 1 , wherein the shallow trench isolation structure continuously extends from a first sidewall of the bonding pad to a second sidewall of the bonding pad.

12. A semiconductor device structure, comprising: a semiconductor substrate overlying the carrier substrate, wherein the photodetector is disposed in the semiconductor substrate; an inner connection structure disposed between the semiconductor substrate and the carrier substrate, wherein an upper conductive line layer is disposed in the inner connection structure; A shallow trench isolation structure is disposed on the semiconductor substrate and continuously extends along the inner connection structure; a bonding pad extending through the semiconductor substrate to the interconnect structure, wherein the bonding pad contacts the upper conductive line layer and has a top surface disposed above the semiconductor substrate, the bonding pad being laterally offset from the photodetector; as well as A bonding pad isolation structure is arranged in the semiconductor substrate, wherein the bonding pad isolation structure continuously surrounds the outer side wall of the bonding pad, wherein the shallow trench isolation structure is laterally arranged between the inner side walls of the bonding pad isolation structure, and the shallow trench isolation structure is laterally offset from the inner side wall of the bonding pad isolation structure by a non-zero distance. 13 . The semiconductor device structure of claim 12 , wherein the bond pad isolation structure extends from the top surface of the semiconductor substrate to the interconnect structure. 14 . The semiconductor device structure of claim 12 , wherein an inner sidewall of the bond pad isolation structure is laterally offset from the outer sidewall of the bond pad by a non-zero distance.

15. The semiconductor device structure according to claim 12, further comprising: a dielectric structure overlying a top surface of the semiconductor substrate, wherein the top surface of the dielectric structure is disposed along a substantially straight line; as well as A grid structure overlies the photodetector, wherein the dielectric structure is disposed between the grid structure and the semiconductor substrate, and a top surface of the bond pad is disposed along the substantially straight line. 16 . The semiconductor device structure of claim 12 , wherein the bonding pad comprises a conductive protrusion extending through the shallow trench isolation structure to the upper conductive line layer. 17 . The semiconductor device structure of claim 16 , wherein the bonding pad isolation structure comprises a same material as the shallow trench isolation structure.

18. A method for forming a semiconductor device structure, comprising: forming a shallow trench isolation structure on the front side surface of the semiconductor substrate; forming a bonding pad isolation structure in the semiconductor substrate so that the bonding pad isolation structure extends from the front side surface to the back side surface of the semiconductor substrate, wherein the outer sidewall of the shallow trench isolation structure is laterally located between the inner sidewalls of the bonding pad isolation structure; forming an interconnect structure on the front surface of the semiconductor substrate, wherein the interconnect structure comprises a conductive line layer; Patterning the front side surface of the semiconductor substrate to define a bonding pad opening and expose an upper surface of the conductive line layer, wherein the upper surface of the conductive line layer underlies the front side surface of the semiconductor substrate, and the bonding pad opening is laterally disposed between inner sidewalls of the bonding pad isolation structure; as well as A bonding pad is formed in the bonding pad opening such that the bonding pad extends from the semiconductor substrate to the conductive line layer and is continuously surrounded by the bonding pad isolation structure.

19. The method for forming a semiconductor device structure according to claim 18, wherein forming the bonding pad comprises: forming a bonding pad layer over the semiconductor substrate and the interconnect structure, such that the bonding pad layer fills the bonding pad opening and directly contacts the semiconductor substrate; as well as The bonding pad layer is patterned to define the bonding pad, wherein the semiconductor substrate includes an upper sidewall and a lower sidewall below the upper sidewall, the upper sidewall and the lower sidewall define the bonding pad opening, and the bonding pad is laterally offset from the upper sidewall by a non-zero distance and directly contacts the lower sidewall. 20 . The method for forming a semiconductor device structure according to claim 18 , wherein the shallow trench isolation structure comprises a same material as the bond pad isolation structure.

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