Semiconductor device

Abstract

A semiconductor device is provided. A characteristic change of the semiconductor device due to a temperature change is suppressed. The semiconductor device includes a semiconductor substrate provided with a drift region of a first conductivity type; a transistor portion having a collector region of a second conductivity type in contact with a lower surface of the semiconductor substrate; and a diode portion having a cathode region of the first conductivity type in contact with the lower surface of the semiconductor substrate and arranged alternately with the transistor portion along an arrangement direction on an upper surface of the semiconductor substrate. Two or more transistor portions selected in order from a transistor portion near a center of the semiconductor substrate in the arrangement direction in the transistor portion have a width in the arrangement direction larger than a width in the arrangement direction of any other transistor portion.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Previously, it was known that reverse-conduction type semiconductor devices had transistor portions such as IGBTs (Insulated Gate Bipolar Transistors) and diode portions such as FWDs (Freewheeling Diodes) formed on a semiconductor substrate (see, for example, Patent Documents 1-3).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2018-46187

[0004] Patent Document 2: Japanese Patent Application Publication No. 2013-138069

[0005] Patent Document 3: Japanese Patent Application Publication No. 2018-78153 Summary of the Invention

[0006] Technical issues

[0007] In semiconductor devices, the temperature in the central part of the substrate tends to rise.

[0008] Technical solution

[0009] To address the aforementioned issues, in one aspect of the present invention, a semiconductor device is provided comprising a semiconductor substrate having a drift region of a first conductivity type. The semiconductor device may include a transistor portion having a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate. The semiconductor device may also include diode portions having a cathode region of the first conductivity type in contact with the lower surface of the semiconductor substrate, and arranged alternately with the transistor portions along an arrangement direction on the upper surface of the semiconductor substrate. The width in the arrangement direction of two or more transistor portions selected sequentially from the transistor portion closest to the center of the semiconductor substrate in the arrangement direction may be larger than the width in the arrangement direction of any other transistor portion.

[0010] Two or more first transistor sections, selected sequentially from the transistor section closest to the center of the semiconductor substrate in the arrangement direction, may each have a first width in the arrangement direction. Two or more second transistor sections, arranged further away from the center than the first transistor sections, may each have a second width smaller than the first width in the arrangement direction.

[0011] The value obtained by dividing the second width by the first width can be greater than 0.5. The value obtained by dividing the first width by the second width can be less than 1.

[0012] The first width can be greater than 700 μm. The first width can be less than 1100 μm.

[0013] The width of each diode section in the arrangement direction can be greater than 300μm.

[0014] The width of each diode section in the arrangement direction can be greater than 2.5 times the thickness of the semiconductor substrate.

[0015] Each diode section can have the same width in the arrangement direction.

[0016] The width of the first transistor section, which is closest to the center of the semiconductor substrate in the arrangement direction, can be greater in the arrangement direction than the width of the second transistor section, which is farther from the center than the first transistor section. The width of the second transistor section in the arrangement direction can be greater than the width of the third transistor section, which is farther from the center than the second transistor section.

[0017] The semiconductor device may also include an outer peripheral diode portion disposed on the upper surface of the semiconductor substrate in such a way that regions surrounding transistor portions and diode portions are alternately arranged along the arrangement direction.

[0018] The semiconductor device may also include a gate pad that is electrically connected to the transistor section. The distance between the diode section closest to the gate pad and the gate pad in the arrangement direction may be greater than the width of the diode section in the arrangement direction.

[0019] The oxygen concentration in the semiconductor substrate can be 1.0 × 10⁻⁶. 17 / cm 3 above.

[0020] The semiconductor device may include a buffer of a first conductivity type disposed between the drift region and the lower surface of the semiconductor substrate, containing hydrogen, and having multiple concentration peaks in the depth direction of the semiconductor substrate with a doping concentration higher than that of the drift region.

[0021] The crystal defect density distribution of a semiconductor substrate in the depth direction can have defect density peaks between concentration peaks configured in a buffer.

[0022] It should be noted that the above summary of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0023] Figure 1 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention.

[0024] Figure 2 This is a top view showing another structural example of the semiconductor device 100.

[0025] Figure 3This is a diagram showing an example of the configuration of the diode section 80 and the transistor section 70 near the gate pad 112 which is electrically connected to the transistor section 70.

[0026] Figure 4 yes Figure 1 and Figure 2 An enlarged view of region A in the image.

[0027] Figure 5 It means Figure 4 A diagram of an example of the bb section.

[0028] Figure 6 It means Figure 5 A figure showing an example of the doping concentration distribution, crystal defect density distribution, and helium concentration distribution at the CC line.

[0029] Figure 7 This is a top view showing another structural example of the semiconductor device 100.

[0030] Figure 8 This is a diagram showing another configuration example of the diode section 80 and the transistor section 70 in the active section 120.

[0031] Figure 9 This is a diagram showing another configuration example of the diode section 80 and the transistor section 70 in the active section 120.

[0032] Figure 10 This is a diagram showing another structural example of the active part 120.

[0033] Symbol Explanation

[0034] 10…Semiconductor substrate, 11…Well region, 12…Emitter region, 14…Base region, 15…Contact region, 16…Accumulation region, 18…Drift region, 20…Buffer zone, 21…Upper surface, 22…Collector region, 23…Lower surface, 24…Collector, 25…Concentration peak, 29…Linear portion, 30…Dummy trench, 31…Front end, 32…Dummy insulating film, 34…Dummy conductive portion, 38…Interlayer insulating film, 39…Linear portion, 40…Gate trench, 41…Front end, 42…Gate insulating film, 44…Gate conductive portion, 52…Emitter, 56… Contact holes, 60, 61…mesh surface, 70…transistor section, 75…connecting transistor section, 80…diode section, 81…extension region, 82…cathode region, 85…peripheral diode section, 90…edge termination structure section, 92…upper surface-side lifetime control region, 93…defect density peak, 94…lower surface-side lifetime control region, 95…defect density peak, 96, 97…concentration peak, 100…semiconductor device, 102…edge, 104…central position, 112…gate pad, 120…active section, 130…peripheral gate wiring, 131…active side gate wiring Detailed Implementation

[0035] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as described in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the technical solution of the invention.

[0036] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0037] In this specification, orthogonal coordinate axes (X-axis, Y-axis, and Z-axis) are used to explain technical matters. Orthogonal coordinate axes merely determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis is not limited to the direction of height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to the +Z-axis and -Z-axis. Furthermore, in this specification, the view from the +Z-axis direction is sometimes referred to as a top view.

[0038] In the context of this specification, the terms "identical" or "equal" may also include cases with errors caused by manufacturing deviations, etc. Such errors may be, for example, within 10%.

[0039] In this specification, the conductivity type of doped regions containing impurities is described as P-type or N-type. However, the conductivity types of each doped region can be of opposite polarities. Furthermore, when described as P+ or N+ type, it indicates a higher doping concentration than P-type or N-type; conversely, when described as P- or N- type, it indicates a lower doping concentration than P-type or N-type. Similarly, when described as P++ or N++ type, it indicates a higher doping concentration than P+ or N+ type.

[0040] In this specification, doping concentration refers to the concentration of impurities activated as donors or acceptors. Sometimes, the concentration difference between donors and acceptors is defined as the doping concentration. This concentration difference can be measured using the voltage-capacitance method (CV method). Alternatively, the carrier concentration measured by the extended resistance method (SR) can be used as the doping concentration. Furthermore, when the doping concentration distribution has a peak, the peak value can be used as the doping concentration in that region. When the doping concentration is almost uniform in a region where donors or acceptors are present, the average doping concentration can be used as the doping concentration in that region. Additionally, in this specification, the dopant concentration refers to the individual concentrations of donors and acceptors.

[0041] Figure 1 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention. Figure 1 The image shows the positions of the components projected onto the upper surface of the semiconductor substrate 10. Figure 1 In this paper, only a portion of the components of the semiconductor device 100 are shown, and some components are omitted.

[0042] Semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has end edges 102 when viewed from above. In this specification, "viewed from above" refers to viewing from the upper surface of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two sets of end edges 102 that are opposite each other when viewed from above. Figure 1 In this configuration, the X and Y axes are parallel to one end edge 102. Additionally, the Z axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0043] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region located between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating, and where a main current flows in the depth direction. An emitter is provided above the active portion 120, but... Figure 1 Omitted in the text.

[0044] The active section 120 is provided with a transistor section 70 containing transistor elements such as IGBTs and a diode section 80 containing diode elements such as freewheeling diodes (FWDs). The transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10.

[0045] exist Figure 1 In this specification, the area where the transistor section 70 is arranged is marked with the symbol "I", and the area where the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction when viewed from above is sometimes referred to as the extension direction (in...). Figure 1 (The middle direction is the Y-axis). The transistor section 70 and the diode section 80 may each have a long side in the extending direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending directions of the transistor section 70 and the diode section 80 may be the same as the long side directions of the trench sections described later.

[0046] The diode portion 80 has an N+ type cathode region in the area contacting the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode portion 80. In other words, the diode portion 80 is the area that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in the area other than the cathode region. In this specification, the extension region 81 formed by extending the diode portion 80 along the Y-axis direction to the gate wiring described later is sometimes also included in the diode portion 80. A collector region is provided on the lower surface of the extension region 81.

[0047] The transistor section 70 has a P+ type collector region in the area that contacts the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure having a gate conductive portion and a gate insulating film periodically disposed on the upper surface side of the semiconductor substrate 10.

[0048] Semiconductor device 100 may have one or more pads above semiconductor substrate 10. In this example, semiconductor device 100 has a gate pad 112. Semiconductor device 100 may have pads such as anode pads, cathode pads, and current sensing pads. Each pad is located near the edge 102. "Near the edge 102" refers to the area between the edge 102 and the emitter when viewed from above. During the mounting of semiconductor device 100, each pad can be connected to external circuitry via wiring such as wires.

[0049] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench portion of the active portion 120. The semiconductor device 100 includes gate wiring connecting the gate pad 112 to the gate trench portion. Figure 1 In the image, the gate wiring is marked with a shading of the diagonal lines.

[0050] The gate wiring in this example includes a peripheral gate wiring 130 and an active-side gate wiring 131. In top view, the peripheral gate wiring 130 is disposed between the active portion 120 and the end edge 102 of the semiconductor substrate 10. In this example, the peripheral gate wiring 130 surrounds the active portion 120 in top view. The area surrounded by the peripheral gate wiring 130 in top view can be considered as the active portion 120. Furthermore, the peripheral gate wiring 130 is connected to the gate pad 112. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 can be a metal wiring containing aluminum or the like.

[0051] An active-side gate wiring 131 is provided in the active portion 120. By providing the active-side gate wiring 131 in the active portion 120, the deviation of the wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10.

[0052] The active-side gate wiring 131 is connected to the gate trench portion of the active portion 120. The active-side gate wiring 131 is disposed above the semiconductor substrate 10. The active-side gate wiring 131 can be a wiring formed from a semiconductor such as polysilicon doped with impurities.

[0053] The active-side gate wiring 131 can be connected to the outer peripheral gate wiring 130. In this example, the active-side gate wiring 131 extends from one outer peripheral gate wiring 130 to another in the X-axis direction approximately at the center of the Y-axis, cutting across the active portion 120. When the active portion 120 is divided by the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 can be alternately arranged in the X-axis direction in each divided region.

[0054] In addition, the semiconductor device 100 may include a temperature sensing unit (not shown) that is a PN junction diode formed of polysilicon or the like, and a current sensing unit (not shown) that simulates the operation of the transistor unit disposed in the active unit 120.

[0055] In this example, the semiconductor device 100 has an edge termination structure 90 between the outer peripheral gate wiring 130 and the edge 102. The edge termination structure 90 mitigates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 has, for example, a protective ring arranged in a ring around the active part 120, a field plate, a surface electric field reduction part, and a structure combining these components.

[0056] If the semiconductor device 100 is operated, heat is generated due to the current flowing through the semiconductor device 100. Near the central position 104 when viewed from above, the temperature tends to rise more easily than the area near the edge 102 because heat sources surround it.

[0057] The heat generated by the diode section 80 can be suppressed because it can diffuse to the transistor section 70. Therefore, the current density of the diode section 80 is sometimes made higher than that of the transistor section 70. For purposes such as improving the electron injection (IE) effect or adjusting the gate capacitance, a dummy gate structure is sometimes provided in the transistor section 70. Therefore, the current density of the transistor section 70 is more likely to be lower than that of the diode section 80. Consequently, the heat generated per unit area of ​​the diode section 80 is more likely to be greater than that of the transistor section 70.

[0058] In the semiconductor device 100, the density of diode sections 80 near the central position 104 is lower than the density of diode sections 80 at positions farther from the central position 104. This helps to suppress temperature rise near the central position 104.

[0059] Furthermore, if a current exceeding half of the rated current continuously flows through the diode section 80 and the self-heating temperature rises, the forward voltage of the diode section 80 may sometimes decrease. For example, in order to shorten the carrier lifetime in the diode section 80, crystal defects may sometimes form in the diode section 80. By shortening the carrier lifetime in the diode section 80, the reverse recovery time of the diode section 80 can be shortened, thereby reducing the reverse recovery loss.

[0060] As described above, if the temperature of the diode section 80 rises due to continuous current flow, crystal defects in the diode section 80 may sometimes recover. If the density of crystal defects changes due to recovery, the resistance of the semiconductor substrate 10 in the diode section 80 changes, thereby reducing the forward voltage of the diode section 80 and increasing the reverse recovery loss.

[0061] In the semiconductor device 100, the density of diode sections 80 near the central position 104 is lower than the density of diode sections 80 located further away from the central position 104. This suppresses characteristic changes in the diode sections 80 that occur as the temperature near the central position 104 rises.

[0062] In this example, two or more transistor sections 70 selected sequentially from the transistor section 70 located near the central position 104 of the semiconductor substrate 10 in the X-axis direction among the plurality of discretely arranged transistor sections 70 in the X-axis direction are referred to as the first transistor section 70-1. Figure 1 In this example, the three transistor sections 70 located near the central position 104 in the X-axis direction are designated as the first transistor section 70-1. The transistor sections 70 other than the first transistor section 70-1 are designated as the second transistor section 70-2. The second transistor section 70-2 is positioned further outward in the X-axis direction compared to the first transistor section 70-1. "Outward" refers to the side furthest from the central position 104.

[0063] Preferably, two or more second transistor sections 70-2 are arranged in the X-axis direction between the central position 104 and one end edge 102. In other words, it is preferable to arrange two or more second transistor sections 70-2 on both sides of the two or more first transistor sections 70-1. Figure 1 In the example, three second transistor sections 70-2 are respectively arranged on both sides of the three first transistor sections 70-1.

[0064] Three or more first transistor sections 70-1 can be arranged consecutively in the X-axis direction. "Consecutive arrangement of the first transistor sections 70-1" means that, excluding the second transistor section 70-2, the first transistor sections 70-1 and diode sections 80 are arranged alternately. Three or more second transistor sections 70-2 can be arranged consecutively in the X-axis direction. "Consecutive arrangement of the second transistor sections 70-2" means that, excluding the first transistor section 70-1, the second transistor sections 70-2 and diode sections 80 are arranged alternately.

[0065] The first width W1 of the first transistor section 70-1 in the X-axis direction is larger than the second width W2 of any second transistor section 70-2 in the X-axis direction. In this example, the first width W1 of the first transistor sections 70-1 is the same. In addition, the second width W2 of each second transistor section 70-2 is the same. In other words, a transistor section 70 with a larger width is arranged near the central position 104 compared with other areas.

[0066] In the X-axis direction, diode sections 80 are arranged between each transistor section 70. The width Wf of each diode section 80 may be the same or different. The width Wf of the diode section 80 may be smaller than the second width W2, the same as the second width W2, or larger than the second width W2.

[0067] In this example, a wide first transistor section 70-1 is disposed near the central position 104, and a narrow second transistor section 70-2 is disposed away from the central position 104. Therefore, the density of diode sections 80 is lower near the central position 104 compared to the location further away from the central position 104. This helps suppress temperature rise near the central position 104. Furthermore, the temperature difference between the transistor sections 70 and the diode sections 80 is smaller at the outer periphery than at the central position 104. This reduces the overall chip temperature, minimizes heat accumulation near the center, and helps suppress the decrease in forward voltage of the diode sections 80.

[0068] Furthermore, by arranging two or more first transistor sections 70-1 in the X-axis direction, the temperature distribution in the X-axis direction can be stabilized. For example, if transistor sections 70 with different widths are arranged alternately, peaks and valleys will occur in the temperature distribution in the X-axis direction with short periods because large and small heat sources are arranged in short intervals. In contrast, by arranging two or more transistor sections 70 with the same width consecutively, the number of peaks and valleys in the temperature distribution in the X-axis direction can be reduced.

[0069] It should be noted that the first transistor portion 70-1 is preferably disposed at the central position 104 in the X-axis direction of the semiconductor substrate 10. This prevents the diode portion 80 from being disposed at the central position 104 in the X-axis direction, and suppresses changes in the characteristics of the diode portion 80.

[0070] The value W2 / W1, obtained by dividing the second width W2 by the first width W1, can be greater than 0.5. This reduces the density of the diode section 80 near the central position 104. W2 / W1 can also be greater than 0.6, and even greater than 0.7.

[0071] W2 / W1 can be less than 1. This prevents excessive variations in characteristics such as channel density and temperature distribution at the boundary between the region where the first transistor section 70-1 is located and the region where the second transistor section 70-2 is located. W2 / W1 can also be less than 0.9, and even less than 0.8.

[0072] The first width W1 can be greater than 700 μm. This reduces the density of the diode portion 80 near the central position 104. The first width W1 can also be greater than 800 μm, and even greater than 900 μm.

[0073] The first width W1 can be less than 1100 μm. This prevents the first transistor section 70-1 from becoming too large, thus avoiding excessive changes in characteristics such as channel density and temperature distribution at the boundary between it and the region where the second transistor section 70-2 is located. The first width W1 can also be less than 1000 μm, or even less than 900 μm.

[0074] The first width W1 can be greater than the width of the gate pad 112 in the X-axis direction. The first width W1 can be greater than the width Wf of the diode section 80. Furthermore, the shortest distance in the X-axis direction between the central position 104 and the diode section 80 can be 10% or more of the width of the semiconductor substrate 10 in the X-axis direction. This shortest distance can also be 15% or more of the width of the semiconductor substrate 10, or even 20% or more of the width of the semiconductor substrate 10.

[0075] The second width W2 can be greater than 200 μm. The second width W2 can also be greater than 300 μm, or even greater than 400 μm. The second width W2 can be less than 700 μm. The second width W2 can also be less than 600 μm, or even less than 500 μm.

[0076] The width Wf of the diode section 80 can be greater than 200 μm. The total area of ​​the diode sections 80 on the upper surface of the semiconductor substrate 10 can be determined according to the performance requirements of the semiconductor device 100. If the width Wf of the diode section 80 is increased, the area of ​​each diode section 80 becomes larger, thus reducing the number of diode sections 80. If the number of diode sections 80 is large, the area of ​​the boundary between the diode section 80 and the transistor section 70 increases, and the peak current during reverse recovery of the diode section 80 will increase due to the flow of charge carriers from the transistor section 70 to the diode section 80. Therefore, the reverse recovery loss tends to increase. The fewer the number of diode sections 80, the smaller the boundary area with the transistor section 70 can be, but the temperature difference between the transistor section 70 and the diode section 80 will increase, and the chip heat generation will increase. There is a trade-off between the number of diode sections 80 and the diode loss or the chip heat generation.

[0077] The width Wf of the diode section 80 can be greater than 400 μm or greater than 500 μm. The width Wf of the diode section 80 can be more than 2.5 times the thickness of the semiconductor substrate 10 in the Z-axis direction, more than 3.5 times the thickness of the semiconductor substrate 10 in the Z-axis direction, or more than 4.5 times the thickness of the semiconductor substrate 10 in the Z-axis direction.

[0078] Figure 2 This is a top view showing another structural example of the semiconductor device 100. In this example, the width of two or more transistor sections 70 selected sequentially from near the central position 104 is larger than the width of the other transistor sections 70 in the arrangement direction. In the semiconductor device 100 of this example, the transistor sections 70 include one or more first transistor sections 70-1, one or more second transistor sections 70-2, and one or more third transistor sections 70-3.

[0079] The first transistor section 70-1 is positioned closest to the center position 104. The first width W1 of the first transistor section 70-1 can be... Figure 1 The first width W1 of the first transistor section 70-1 described herein is the same.

[0080] The second transistor section 70-2 is configured in the X-axis direction to be farther away from the central position 104 than the first transistor section 70-1. The third transistor section 70-3 is configured in the X-axis direction to be farther away from the central position 104 than the second transistor section 70-2.

[0081] The first width W1 of the first transistor section 70-1 in the X-axis direction is larger than the second width W2 of the second transistor section 70-2 in the X-axis direction. Furthermore, the second width W2 of the second transistor section is larger than the third width W3 of the third transistor section 70-3 in the X-axis direction. In other words, in this example of the semiconductor device 100, the width of the transistor section 70 decreases progressively with distance from the central position 104. In this example, one of the second transistor section 70-2 and the third transistor section 70-3 may have the same width as... Figure 1 The second transistor section 70-2 shown has the same width.

[0082] In this example of the semiconductor device 100, the width of the transistor section 70 decreases the further away from the central position 104. Figure 2 In this example, the width of the transistor section 70 is one of three types: W1, W2, and W3. However, in other examples, the width of the transistor section 70 can be four or more types. Furthermore, two or more transistor sections 70 with the same width can be arranged consecutively in the X-axis direction. In this example, the density of the diode sections 80 near the central position 104 can be lower than the density of the diode sections 80 further away from the central position 104. This suppresses temperature rise near the central position 104 and also suppresses changes in the characteristics of the diode sections 80.

[0083] Figure 3 This diagram shows an example of the configuration of the diode section 80 and the transistor section 70 near the gate pad 112, which are electrically connected to the transistor section 70. This example configuration can be applied to... Figure 1 and Figure 2 Any one of them.

[0084] In this example, the gate pad 112 is positioned opposite the first transistor section 70-1, which has a first width W1, in the Y-axis direction. The gate pad 112 may be positioned above the first transistor section 70-1.

[0085] In this example, the distance between the diode portion 80 closest to the gate pad 112 in the X-axis direction and the gate pad 112 in the X-axis direction is set as D. A P+ type well region is provided on the upper surface of the semiconductor substrate 10 below the gate pad 112. The doping concentration of the well region is higher than that of the drift region described later, and the well region is located at a deeper position than the base region described later.

[0086] An N+ type cathode region is provided on the lower surface of the diode section 80. Therefore, if the distance D between the gate pad 112 and the diode section 80 decreases, the distance between the high-concentration well region and the cathode region becomes closer, and the reverse recovery withstand capability decreases. In this example, the distance D is greater than the width Wf of the diode section 80. As a result, the decrease in reverse recovery withstand capability can be suppressed. The distance D can be more than 0.25 times the width Wf, or more than 1 times the width Wf.

[0087] Figure 4 yes Figure 1 and Figure 2 This is an enlarged view of region A. Region A includes the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 disposed inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. Furthermore, the semiconductor device 100 in this example includes an emitter 52 and an active-side gate wiring 131 disposed above the upper surface of the semiconductor substrate 10. The emitter 52 and the active-side gate wiring 131 are disposed separately from each other.

[0088] An interlayer insulating film is disposed between the emitter 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but in Figure 4 (Omitted). In this example, the interlayer insulating film has contact holes 56 provided through it. Figure 4 In the middle, the shading of the diagonal lines marks each contact hole 56.

[0089] An emitter 52 is disposed above the gate trench 40, the dummy trench 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 56. Additionally, the emitter 52 is connected to a dummy conductive portion within the dummy trench 30 through a contact hole disposed in the interlayer insulating film. The emitter 52 can be connected to the dummy conductive portion of the dummy trench 30 at its front end in the Y-axis direction.

[0090] The active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 can be connected to the gate conductive portion of the gate trench portion 40 at the front end 41 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion within the dummy trench portion 30.

[0091] The emitter 52 is formed of a material containing metal. Figure 4The area where the emitter 52 is provided is shown. For example, at least a portion of the emitter 52 is formed of aluminum or an aluminum-silicon alloy. The area of ​​the emitter 52 formed of aluminum or the like may have a barrier metal formed of titanium, titanium compounds, or the like. Furthermore, a plug formed by embedding tungsten or the like in contact with the barrier metal and the aluminum or the like may be provided within the contact hole.

[0092] Well region 11 is configured to overlap with active-side gate wiring 131. Well region 11 also extends by a predetermined width to a range that does not overlap with active-side gate wiring 131. In this example, well region 11 is configured to extend away from the contact hole 56 in the Y-axis direction towards the active-side gate wiring 131. Well region 11 is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, base region 14 is P-type, and well region 11 is P+ type.

[0093] The transistor section 70 and the diode section 80 each have a plurality of trench sections arranged along the arrangement direction. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately arranged along the arrangement direction. In this example, the diode section 80 has a plurality of dummy trench sections 30 arranged along the arrangement direction. In this example, the diode section 80 does not have a gate trench section 40.

[0094] In this example, the gate trench portion 40 may have two straight portions 39 (the trench portion that is straight along the extension direction) extending in an extension direction perpendicular to the arrangement direction and a front end portion 41 connecting the two straight portions 39. Figure 4 The extension direction in the middle is the Y-axis direction.

[0095] At least a portion of the front end portion 41 is preferably curved when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction through the front end portion 41, the electric field concentration at the ends of the straight portions 39 can be mitigated.

[0096] In the transistor section 70, dummy trench sections 30 are provided between each straight portion 39 of the gate trench section 40. One dummy trench section 30 may be provided between each straight portion 39, or multiple dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight shape extending in the extending direction, and may have the same straight portion 29 and front end portion 31 as the gate trench section 40. Figure 4 The semiconductor device 100 shown includes both a dummy trench portion 30 with a straight shape and a front end portion 31.

[0097] The diffusion depth of the well region 11 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located within the well region 11 when viewed from above. In other words, at the Y-axis ends of each trench portion, the bottom of each trench portion in the depth direction is covered by the well region 11. This mitigates the electric field concentration at the bottom of each trench portion.

[0098] Mesa-shaped portions are provided between the trench portions in the alignment direction. A mesa-shaped portion refers to the area within the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa-shaped portion is the upper surface of the semiconductor substrate 10. The lower end of the mesa-shaped portion has the same depth as the lower end of the trench portion. In this example, the mesa-shaped portion is configured to extend along the trench and in the extension direction (Y-axis direction) on the upper surface of the semiconductor substrate 10. In this example, a mesa-shaped portion 60 is provided in the transistor portion 70, and a mesa-shaped portion 61 is provided in the diode portion 80. In this specification, the term "mesa-shaped portion" refers only to each of mesa-shaped portion 60 and mesa-shaped portion 61.

[0099] A base region 14 is provided on each mesa. The region of the base region 14 exposed on the upper surface of the semiconductor substrate 10 within the mesa, closest to the active-side gate wiring 131, is denoted as base region 14-e. Figure 4 The diagram shows a base region 14-e disposed at one end of each stage in the extending direction, but a base region 14-e is also disposed at the other end of each stage. In each stage, the area sandwiched between the base regions 14-e when viewed from above can be provided with at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 can be disposed between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0100] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is configured to contact the gate trench portion 40. The mesa portion 60 that contacts the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0101] The contact area 15 and the emission area 12 in the platform 60 are respectively provided from one groove portion to another in the X-axis direction. As an example, the contact area 15 and the emission area 12 of the platform 60 are alternately arranged along the extension direction of the groove portion (Y-axis direction).

[0102] In another example, the contact area 15 and the emission area 12 of the platform surface 60 can be arranged in a stripe pattern along the extension direction (Y-axis direction) of the groove portion. For example, the emission area 12 is provided in the area that contacts the groove portion, and the contact area 15 is provided in the area sandwiched by the emission area 12.

[0103] The emitter region 12 is not provided on the mesa 61 of the diode section 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa 61. A contact region 15 may be provided on the upper surface of the mesa 61 in a manner that contacts each of the base regions 14-e, within the area enclosed by the base regions 14-e. A base region 14 may be provided on the upper surface of the mesa 61 within the area enclosed by the contact regions 15. The base region 14 may be disposed over the entire area enclosed by the contact regions 15.

[0104] A contact hole 56 is provided above each stage surface. The contact hole 56 is located in the area enclosed by the base region 14-e. In this example, the contact hole 56 is located above each of the contact region 15, the base region 14, and the emitter region 12. The contact hole 56 is not located in the region corresponding to the base region 14-e and the sink region 11. The contact hole 56 may be located at the center of the stage surface 60 in the arrangement direction (X-axis direction).

[0105] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 can be provided on the lower surface of the semiconductor substrate 10 in the region where the cathode region 82 is not provided. Figure 4 In the diagram, the boundary between the cathode region 82 and the collector region 22 is represented by a dashed line.

[0106] Figure 5 It means Figure 4 A diagram showing an example of a bb section. The bb section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter 52, and a collector 24 in this section. The interlayer insulating film 38 is disposed on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film containing at least one layer of an insulating film such as silicate glass with added impurities such as boron or phosphorus, a thermally oxidized film, or other insulating films. The interlayer insulating film 38 has... Figure 2 Contact hole 56 as described in the text.

[0107] The emitter 52 is disposed above the interlayer insulating film 38. The emitter 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 56 of the interlayer insulating film 38. The collector 24 is disposed on the lower surface 23 of the semiconductor substrate 10. The emitter 52 and the collector 24 are formed of a metal material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter 52 and the collector 24 is referred to as the depth direction.

[0108] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is disposed in the transistor section 70 and the diode section 80, respectively.

[0109] On the mesa 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are sequentially disposed from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is disposed below the base region 14. An N+ type accumulation region 16 may be disposed on the mesa 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0110] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is configured to contact the gate trench 40. The emitter region 12 may contact the trenches on both sides of the mesa 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0111] The base region 14 is located below the transmitter region 12. In this example, the base region 14 is positioned in contact with the transmitter region 12. The base region 14 may contact the groove portions on both sides of the stage surface 60.

[0112] An accumulation region 16 is disposed below the base region 14. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be improved, and the turn-on voltage can be reduced. The accumulation region 16 can be configured to cover the entire lower surface of the base region 14 in each mesa 60.

[0113] A P-type base region 14 is provided on the mesa 61 of the diode section 80, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided on the mesa 61, below the base region 14.

[0114] In each of the transistor section 70 and the diode section 80, an N+ type buffer 20 may be provided below the drift region 18. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 functions as a field cutoff layer to prevent the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82. The buffer 20 may have multiple peaks or a single peak in the doping concentration distribution along the depth direction.

[0115] In the transistor section 70, a P+ type collector region 22 is provided below the buffer zone 20. In the diode section 80, an N+ type cathode region 82 is provided below the buffer zone 20. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24.

[0116] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench portion extends from the upper surface 21 of the semiconductor substrate 10 through the base region 14 to reach the drift region 18. In regions where at least one of the emitter region 12, contact region 15, and accumulation region 16 is provided, each trench portion also extends through these doped regions to reach the drift region 18. The term "trench portion extending through the doped region" is not limited to products manufactured in a sequence where trench portions are formed after the formation of doped regions. Products in which doped regions are formed between trench portions after the formation of trench portions are also included in products where trench portions extend through the doped regions.

[0117] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0118] The gate trench portion 40 has a gate trench disposed on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is disposed to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is disposed inside the gate trench at a position closer to the inner side than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0119] The gate conductive portion 44 can be made longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel composed of an electron inversion layer is formed on the surface layer of the interface in the base region 14 that contacts the gate trench portion 40.

[0120] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 disposed on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter 52. The dummy insulating film 32 is disposed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is disposed inside the dummy trench and is located closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 can be formed of a conductive material such as polysilicon. The dummy conductive portion 34 can have the same length in the depth direction as the gate conductive portion 44.

[0121] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that the bottom of the dummy trench portion 30 and the gate trench portion 40 can be a downwardly convex curved surface (curved in cross-section).

[0122] The diode section 80 has an upper surface-side lifetime control region 92. The lifetime control region is a region in the semiconductor substrate 10 where the carrier lifetime distribution in the depth direction has valleys.

[0123] A top-surface lifetime control region 92 is disposed on the top surface 21 side of the semiconductor substrate 10. The top surface 21 side refers to the region between the center of the semiconductor substrate 10 in the depth direction and the top surface 21. For example, the top-surface lifetime control region 92 can be formed by injecting impurities such as helium or protons from the top surface 21 side of the semiconductor substrate 10 with a predetermined range. Crystallization defects are formed by injecting impurities, and the carrier lifetime is reduced by allowing the crystallization defects to combine with the carriers. A defect density peak 93 representing the crystallization defect density distribution in the depth direction can be formed in the top-surface lifetime control region 92. Figure 5 In the diagram, the defect density peak 93 is schematically represented by an × symbol. At the location of the defect density peak 93, the carrier lifetime distribution can reach a minimum.

[0124] The upper surface-side lifetime control region 92 can be provided throughout the entire diode section 80 in the X-axis direction. Alternatively, the upper surface-side lifetime control region 92 can also be provided in the region of the transistor section 70 that contacts the diode section 80. In other words, the upper surface-side lifetime control region 92 can be continuously provided from the diode section 80 to a portion of the transistor section 70 in the X-axis direction.

[0125] The diode section 80 and the transistor section 70 may have a lower surface-side lifetime control region 94. The lower surface-side lifetime control region 94 may be provided throughout the entire transistor section 70 and diode section 80 in the X-axis direction. The lower surface-side lifetime control region 94 is provided on the lower surface 23 side of the semiconductor substrate 10. The lower surface 23 side refers to the region between the center of the semiconductor substrate 10 in the depth direction and the lower surface 23. For example, the lower surface-side lifetime control region 94 can be formed by injecting impurities such as helium from the lower surface 23 side of the semiconductor substrate 10 with a predetermined range. A defect density peak 95 representing the crystal defect density distribution in the depth direction may be provided in the lower surface-side lifetime control region 94. At the location of the defect density peak 95, the carrier lifetime distribution may be at a minimum.

[0126] Figure 6 It means Figure 5The diagram shows an example of the doping concentration distribution, crystal defect density distribution, and helium concentration distribution at the CC line. The CC line is a line in the diode section 80 that runs from above the upper surface-side lifetime control region 92 to below the lower surface-side lifetime control region 94.

[0127] In this example, the doping concentration distribution in buffer 20 has more than one concentration peak 25. Multiple concentration peaks 25 can be set in the depth direction. The doping concentration in buffer 20 is higher than the doping concentration in drift region 18.

[0128] Each concentration peak 25 can be formed by implanting hydrogen ions such as protons. This is achieved by implanting hydrogen ions into the semiconductor substrate 10 and then annealing it, thereby making the hydrogen itself a donor, or by sealing crystal defects such as holes in the semiconductor substrate 10 with hydrogen and oxygen, thus making them donors. The buffer zone 20 can have hydrogen concentration peaks corresponding to each concentration peak 25. The positions of the concentration peaks 25 and the hydrogen concentration peaks can be the same.

[0129] The crystal defect density distribution in diode section 80 has more than one defect density peak. Figure 6 In the example, the crystallization defect density distribution has defect density peaks 93 and 95. Crystallization defects also form in regions where impurities such as helium pass through. Therefore, each defect density peak has a gentle slope on the side where impurities are injected and a steep slope on the side where no impurities are injected. Furthermore, the density at the defect density peaks can be controlled by the dosage of impurities such as helium.

[0130] The defect density peak 95 is positioned in buffer 20. The defect density peak 95 can be positioned between the concentration peaks 25 in buffer 20. In this specification, "predetermined peak positioned between two other peaks" means that the vertex of the predetermined peak is positioned between the vertices of the other two peaks, and the vertex of the predetermined peak is not contained in the half-value width of each of the other two peaks.

[0131] Furthermore, the helium concentration distribution exhibits more than one concentration peak. Figure 6 In the example, there is a concentration peak 96 corresponding to the defect density peak 93, and a concentration peak 97 corresponding to the defect density peak 95. The corresponding density peaks and concentration peaks can be set at the same depth position.

[0132] With this configuration, a predetermined density of defect peaks can be set at a predetermined depth, allowing for adjustment of carrier lifetime. However, as mentioned above, if the temperature rises during the operation of the semiconductor device 100, crystal defects formed by holes (V) created by helium irradiation may combine with hydrogen (H) and oxygen (O) in the semiconductor substrate 10, increasing VOH defects and decreasing the density of crystal defects formed by holes created by helium irradiation. In particular, in this example, since a large amount of hydrogen is present in the buffer zone 20, the density of crystal defects formed by holes created by helium irradiation in the buffer zone 20 is prone to decrease.

[0133] In this regard, in the semiconductor device 100, there are fewer diode sections 80 near the central position 104 of the semiconductor substrate 10 where the temperature is prone to rise. Therefore, it is possible to suppress the decrease in the density of crystal defects caused by holes formed by helium irradiation in the diode section 80.

[0134] If the oxygen concentration in the semiconductor substrate 10 is high, crystal defects formed by holes created by helium irradiation are more likely to form VOH defects along with hydrogen. Therefore, when the oxygen concentration in the semiconductor substrate 10 is high, the density of crystal defects formed by holes created by helium irradiation in the diode section 80 of the semiconductor device 100 decreases significantly. The oxygen concentration in the semiconductor substrate 10 can be 1.0 × 10⁻⁶. 17 / cm 3 The oxygen concentration of the semiconductor substrate 10 can also be 2.0 × 10⁻⁶. 17 / cm 3 The above can also be 5.0×10 17 / cm 3 The oxygen concentration of the semiconductor substrate 10 can be either an average value or a maximum value. Furthermore, the semiconductor substrate 10 can be an MCZ substrate. An MCZ substrate refers to a substrate formed using the MCZ (Magnetic Field Applied Czochralski) method. MCZ substrates have a higher oxygen concentration. It should be noted that by positioning the defect density peak 95 between the concentration peak 25, hydrogen capping of crystallization defects can be further suppressed.

[0135] In this example, although a configuration where the defect density peak 95 is positioned between the concentration peaks 25 is shown, the defect density peak 95 can also be positioned at a location further from the lower surface 23 than the concentration peak 25 that has the longest distance from the lower surface 23 among the plurality of concentration peaks 25. Furthermore, the concentration peaks 25 can also be formed by implanting phosphorus ions. Moreover, when there is only one concentration peak 25, the defect density peak 95 can be positioned at a location further from the lower surface than the concentration peak 25. Additionally, when there is only one concentration peak 25, the defect density peak 95 can also be positioned between the concentration peak 25 and the concentration peak of the cathode region 82.

[0136] Figure 7 This is a top view showing another structural example of the semiconductor device 100. In this example, the semiconductor device 100 is relative to... Figures 1-6 The method described herein also includes a peripheral diode section 85. The peripheral diode section 85 surrounds a region on the upper surface of the semiconductor substrate 10 where transistor sections 70 and diode sections 80 are alternately arranged along the X-axis. The arrangement of transistor sections 70 and diode sections 80 within the region surrounded by the peripheral diode section 85 is similar to... Figure 1 or Figure 2 The example shown is the same.

[0137] The structure of the peripheral diode section 85 is the same as that of the diode section 80. In other words, the peripheral diode section 85 has a cathode region 82 on the lower surface 23 of the semiconductor substrate 10, and a dummy trench section 30, a base region 14, etc. on the upper surface 21. With this configuration, the density of diode sections 80 near the central position 104 of the semiconductor substrate 10 can also be reduced.

[0138] Figure 8 This diagram shows another configuration example of the diode section 80 and the transistor section 70 in the active unit 120. In this example, the active unit 120 has a diode section 80-1 and a diode section 80-2. Diode section 80-1 is disposed in the region including the central position 104. The center of diode section 80-1 in the X-axis direction can be the central position 104. The width Wf of diode section 80-1 is... Figures 1 to 7 The diode section 80 described herein is the same.

[0139] Compared to diode 80-1, diode section 80-2 is positioned in the X-axis direction closer to the end edge 102 of semiconductor substrate 10. In other words, diode section 80-2 is positioned at the end of active section 120 in the X-axis direction. The width Wf of diode section 80-2 is the same as or larger than the first width W1 of transistor section 70. Two diode sections 80-2 can be arranged with a gap between diode sections 80-1 in the X-axis direction. Transistor section 70 is arranged with a gap between each diode section 80.

[0140] According to this example, by reducing the density of diode sections 80 near the central position 104, heat generation near the central position 104 can be suppressed. Furthermore, by increasing the width Wf of diode sections 80-2, the boundary area between transistor section 70 and diode section 80 can be reduced, thereby improving diode losses. It should be noted that diode section 80-1 may be omitted. Transistor section 70 may be used instead of diode section 80-1.

[0141] Figure 9 This diagram illustrates another configuration example of the diode section 80 and the transistor section 70 in the active section 120. In this example, the active section 120 has region A and region B. Region B is the region including the central position 104. Compared to region A, region B is positioned in the X-axis direction closer to the end edge 102 of the semiconductor substrate 10. A diode section 80-1 and a transistor section 70-1 are configured in region B. The configuration of the diode section 80-1 and the transistor section 70-1 in region B can be... Figures 1 to 7 The active part 120 described herein is the same.

[0142] In region A, diode sections 80 and transistor sections 70 are arranged alternately along the X-axis. In region A of this example, diode sections 80-3 to 80-8 are arranged from the central position 104 towards the end edge 102. The width Wf of diode sections 80-3 to 80-8 increases in the X-axis direction as they move away from the central position 104. Additionally, in region A of this example, transistor sections 70-2 to 70-7 are arranged from the central position 104 towards the end edge 102. The first width W1 of the plurality of transistor sections 70-2 to 70-6 provided in region A increases in the X-axis direction as they move away from the central position 104. However, the first width W1 of transistor section 70-7, located at the far end in the X-axis direction, may be smaller than the first width W1 of the adjacent transistor section 70-6.

[0143] In region A, the density of diode sections 80 is higher closer to the central position 104. In this example, because there are many boundaries between transistor sections 70 and diode sections 80 in region A, the temperature difference between transistor sections 70 and diode sections 80 is small, resulting in a lower chip heating temperature. Furthermore, while the temperature tends to rise in region B, the overall chip temperature rise is suppressed because heating is inhibited in region A.

[0144] Furthermore, the width of the diode section 80 in region A increases as it approaches the edge 102 of the semiconductor substrate 10. Therefore, heat generation in region C near the central position 104 in region A can be suppressed. In region C, the boundary region between the transistor section 70 and the diode section 80 is large, resulting in poor diode loss. However, by expanding the width of the diode section 80 in region D, which is farther from the central position 104 in region A, the boundary region can be reduced. Therefore, diode loss can be improved. Thus, since region D can cover the area with poor loss in region C, the trade-off between the number of diodes and diode loss or heat generation can be improved. It should be noted that the diode section 80-1 in region B may not be provided. It should be noted that in... Figure 8 and Figure 9 You can also set it in the middle. Figure 1 The active-side gate wiring 131 is shown in the figure.

[0145] Figure 10 This is a diagram showing another structural example of the active unit 120. In this example, the active unit 120, in addition to being equipped with... Figures 1-9 In addition to the structure described herein, a connecting transistor section 75 is also provided. The connecting transistor section 75 connects two adjacent transistor sections 70 in the X-axis direction. The connecting transistor section 75 can extend from one transistor section 70 to another transistor section 70 along the X-axis direction.

[0146] The diode section 80 is disconnected from the transistor section 75 in the Y-axis direction. In other words, at least one diode section 80 has an island shape when viewed from above, surrounded by the transistor section 70.

[0147] The island-shaped diode sections 80 can be arranged with a higher density the further away from the center position 104 of the semiconductor substrate 10. The density of the diode sections 80 refers to the area of ​​the diode sections 80 contained per unit area of ​​the upper surface of the semiconductor substrate 10. With this arrangement, the density of the diode sections 80 near the center position 104 can also be reduced.

[0148] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, such modifications or improvements may also be included within the technical scope of the present invention.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor substrate having a drift region of a first conductivity type; The transistor section has a collector region of a second conductivity type that is in contact with the lower surface of the semiconductor substrate; as well as The diode section has a cathode region of a first conductivity type that contacts the lower surface of the semiconductor substrate, and is alternately arranged with the transistor section along the arrangement direction on the upper surface of the semiconductor substrate. Of the transistor portions, two or more transistor portions selected sequentially from the transistor portion closest to the center of the semiconductor substrate in the arrangement direction have a width in the arrangement direction that is larger than the width of any other transistor portion in the arrangement direction. Two or more first transistor portions, selected sequentially from the transistor portion closest to the center of the semiconductor substrate in the arrangement direction, each have a first width in the arrangement direction. Two or more second transistor sections, which are arranged further away from the center than the first transistor section, each have a second width smaller than the first width in the arrangement direction. The first width is greater than 700 μ m and less than 1100 μ m.

2. The semiconductor device according to claim 1, characterized in that, The value obtained by dividing the second width by the first width is greater than 0.5 and less than 1.

3. The semiconductor device according to claim 1, characterized in that, The width of each of the diode portions in the arrangement direction is greater than 300. μ m.

4. The semiconductor device according to claim 1, characterized in that, The width of each of the diode portions in the arrangement direction is greater than 2.5 times the thickness of the semiconductor substrate.

5. The semiconductor device according to claim 1, characterized in that, Each of the diodes has the same width in the arrangement direction.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a peripheral diode portion disposed on the upper surface of the semiconductor substrate in such a way that it surrounds a region in which the transistor portion and the diode portion are alternately arranged along the arrangement direction.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The oxygen concentration in the semiconductor substrate is 1.0 × 10⁻⁶. 17 / cm 3 above.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a buffer of a first conductivity type, the buffer being disposed between the drift region and the lower surface of the semiconductor substrate, and containing hydrogen, and having a plurality of concentration peaks in the depth direction of the semiconductor substrate having a doping concentration higher than that of the drift region.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor substrate has a defect density peak in the depth direction of the crystal defect density distribution, and the defect density peak is disposed between the concentration peaks in the buffer.

10. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a buffer of a first conductivity type, the buffer being disposed between the drift region and the lower surface of the semiconductor substrate, and containing phosphorus, and having a concentration peak in the depth direction of the semiconductor substrate having a doping concentration higher than that of the drift region.

11. The semiconductor device according to claim 8, characterized in that, The semiconductor substrate has a defect density peak in the depth direction of the crystal defect density distribution. The defect density peak is located at a distance from the lower surface of the semiconductor substrate that is longer than the distance from the concentration peak in the buffer to the lower surface of the semiconductor substrate.

12. A semiconductor device, characterized in that, have: A semiconductor substrate having a drift region of a first conductivity type; The transistor section has a collector region of a second conductivity type that is in contact with the lower surface of the semiconductor substrate; as well as The diode section has a cathode region of a first conductivity type that contacts the lower surface of the semiconductor substrate, and is alternately arranged with the transistor section along the arrangement direction on the upper surface of the semiconductor substrate. Of the transistor portions, two or more transistor portions selected sequentially from the transistor portion closest to the center of the semiconductor substrate in the arrangement direction have a width in the arrangement direction that is larger than the width of any other transistor portion in the arrangement direction. The semiconductor device further includes a gate pad electrically connected to the transistor section. The distance between the diode portion closest to the gate pad and the gate pad in the arrangement direction is greater than the width of the diode portion in the arrangement direction.

13. The semiconductor device according to claim 12, characterized in that, Two or more first transistor portions, selected sequentially from the transistor portion closest to the center of the semiconductor substrate in the arrangement direction, each have a first width in the arrangement direction. Two or more second transistor sections, which are arranged further away from the center than the first transistor section, each have a second width smaller than the first width in the arrangement direction.

14. The semiconductor device according to claim 13, characterized in that, The value obtained by dividing the second width by the first width is greater than 0.5 and less than 1.

15. The semiconductor device according to claim 13, characterized in that, The first width is greater than 700 μ m and less than 1100 μ m.

16. The semiconductor device according to claim 12, characterized in that, The width of each of the diode portions in the arrangement direction is greater than 300. μ m.

17. The semiconductor device according to claim 12, characterized in that, The width of each of the diode portions in the arrangement direction is greater than 2.5 times the thickness of the semiconductor substrate.

18. The semiconductor device according to claim 12, characterized in that, Each of the diodes has the same width in the arrangement direction.

19. The semiconductor device according to claim 12, characterized in that, The width of the first transistor portion, which is closest to the center of the semiconductor substrate in the arrangement direction, is greater than the width of the second transistor portion, which is farther from the center than the first transistor portion, in the arrangement direction. The width of the second transistor portion in the arrangement direction is greater than the width of the third transistor portion, which is farther from the center than the second transistor portion, in the arrangement direction.

20. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes a peripheral diode portion disposed on the upper surface of the semiconductor substrate in such a way that it surrounds a region in which the transistor portion and the diode portion are alternately arranged along the arrangement direction.

21. The semiconductor device according to any one of claims 12 to 20, characterized in that, The oxygen concentration in the semiconductor substrate is 1.0 × 10⁻⁶. 17 / cm 3 above.

22. The semiconductor device according to claim 21, characterized in that, The semiconductor device further includes a buffer of a first conductivity type, the buffer being disposed between the drift region and the lower surface of the semiconductor substrate, and containing hydrogen, and having a plurality of concentration peaks in the depth direction of the semiconductor substrate having a doping concentration higher than that of the drift region.

23. The semiconductor device according to claim 22, characterized in that, The semiconductor substrate has a defect density peak in the depth direction of the crystal defect density distribution, and the defect density peak is disposed between the concentration peaks in the buffer.

24. The semiconductor device according to claim 21, characterized in that, The semiconductor device further includes a buffer of a first conductivity type, the buffer being disposed between the drift region and the lower surface of the semiconductor substrate, and containing phosphorus, and having a concentration peak in the depth direction of the semiconductor substrate having a doping concentration higher than that of the drift region.

25. The semiconductor device according to claim 22, characterized in that, The semiconductor substrate has a defect density peak in the depth direction of the crystal defect density distribution. The defect density peak is located at a distance from the lower surface of the semiconductor substrate that is longer than the distance from the concentration peak in the buffer to the lower surface of the semiconductor substrate.

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