Successive approximation register analog-to-digital converter and integrated circuit including the converter

Abstract

The present invention relates to a successive approximation register analog-to-digital converter and an integrated circuit including the successive approximation register analog-to-digital converter. The analog-to-digital converter includes a low voltage power supply rail (538), a high voltage power supply rail (540), a successive approximation circuit (506), a level shifter (534), and a capacitive digital-to-analog converter CDAC (502). The successive approximation circuit system (506) is coupled to the low voltage power supply rail (538). The level shifter (534) is coupled to the high voltage power supply rail (540) and includes an input (534A) coupled to a first output (506A) of the successive approximation circuit system (506). The CDAC (502) includes a first section (512) and a second section (522). The first section (512) includes a first plurality of capacitors (514) and a first plurality of switches (516) coupled to an output (534B) of the level shifter (534). The second section (522) includes a second plurality of capacitors (524) and a second plurality of switches (526) coupled to a second output (506B) of the successive approximation circuit system (506).

Description

Technical Field

[0001] This application relates to semiconductor technology, and more particularly, to analog / digital data converters. Background Art

[0002] Various analog / digital data converters and conversion techniques can be used to convert an electrical signal from the analog domain to the digital domain. Generally, the process of analog / digital conversion involves sampling an analog signal and comparing the sampled analog signal with a threshold. A binary result is recorded depending on the comparison result. The process of comparing the sample with the threshold can be repeated several times for each successive comparison using different thresholds and sample residuals. The number of iterations typically affects the noise level of any result and the resolution of the final digital signal.

[0003] A successive approximation register (SAR) converter is an example of an analog / digital converter (ADC). The SAR ADC performs a binary search for a digital value that best corresponds to the voltage of the analog signal. In the SAR ADC, the voltage input is compared with 1 / 2 of the voltage reference. If the voltage input is greater than 1 / 2 of the reference voltage, then a logic '1' is stored in the register. Alternatively, if the voltage input is less than 1 / 2 of the voltage reference, then a logic '0' is stored in the register. Next, if the previous comparison indicated that the voltage input was greater than 1 / 2 of the reference voltage, then the voltage input is compared with 3 / 4 of the reference voltage. Also, if the comparison indicates a greater condition, then a logic '1' is stored in the register. Conversely, if the comparison indicates a less condition, then a logic '0' is stored in the register. Alternatively, if the previous comparison indicated that the voltage input was less than 1 / 2 of the voltage reference, then the voltage input is compared with 1 / 4 of the voltage reference. Also, if the comparison indicates a greater condition, then a logic '1' is stored in the register. Conversely, if the comparison indicates a less condition, then a logic '0' is stored in the register. This process continues for lower order multiples of the voltage reference. As will be appreciated, the above process is capable of providing ADC results with high resolution in a relatively small amount of time. Specifically, only a single iteration can be used to generate each bit of resolution. For example, 10-bit resolution only requires 10 iterations, and 20-bit resolution only requires 20 iterations. Summary of the Invention

[0004] This disclosure reveals a successive approximation register analog-to-digital converter with an improved reference drive circuit system. In one example, an analog-to-digital converter includes a low voltage power rail, a high voltage power rail, a successive approximation circuit system, a level shifter, and a capacitive digital-to-analog converter (CDAC). The successive approximation circuit system is coupled to the low voltage power rail. The level shifter is coupled to the high voltage power rail and includes an input coupled to a first output of the successive approximation circuit system. The CDAC includes a first section and a second section. The first section includes a first plurality of capacitors and a first plurality of switches coupled to an output of the level shifter. The second section includes a second plurality of capacitors and a second plurality of switches coupled to a second output of the successive approximation circuit system.

[0005] In another example, an integrated circuit includes a reference voltage terminal, a first buffer circuit, a voltage divider, a second buffer circuit, a third buffer circuit, a first analog-to-digital converter, and a second analog-to-digital converter. The first buffer circuit includes an output coupled to the reference voltage terminal. The voltage divider is coupled to the output of the first buffer circuit. The second buffer circuit includes an input coupled to the output of the voltage divider. The first analog-to-digital converter includes a first CDAC coupled to the output of the first buffer circuit and the output of the second buffer circuit. The third buffer circuit includes an input coupled to the output of the voltage divider. The second analog-to-digital converter includes a second CDAC coupled to the output of the first buffer circuit and the output of the third buffer circuit.

[0006] In another example, an analog-to-digital converter includes a reference voltage terminal, a first buffer circuit, a voltage divider, a second buffer circuit, a successive approximation circuit system, a level shifter, and a CDAC. The first buffer circuit includes an output coupled to the reference voltage terminal. The voltage divider includes an input coupled to the output of the first buffer circuit. The second buffer circuit includes an input coupled to the output of the voltage divider. The level shifter is coupled to a first output of the successive approximation circuit system. The CDAC includes a first section and a second section. The first section includes a first plurality of capacitors and a first plurality of switches coupled to the output of the level shifter and the output of the first buffer circuit. The second section includes a second plurality of capacitors and a second plurality of switches coupled to a second output of the successive approximation circuit system and the output of the second buffer circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To describe the various examples in detail, reference will now be made to the accompanying drawings, in which:

[0008] Figure 1 A block diagram showing an example integrated circuit including a plurality of analog-to-digital converters is presented;

[0009] Figure 2 Block diagram showing an example analog-to-digital converter including a reference buffer;

[0010] Figure 3 Block diagram showing an example analog-to-digital converter including multiple reference buffers;

[0011] Figure 4 Block diagram showing an example analog-to-digital converter including a low-voltage successive approximation circuitry; and

[0012] Figure 5 Block diagram showing an example analog-to-digital converter that operates a portion of a capacitive digital-to-analog converter in a low-voltage domain. DETAILED DESCRIPTION

[0013] In the present invention, the term "coupled" means indirectly or directly wired or wirelessly connected. Thus, if a first device is coupled to a second device, the connection can be through a direct connection or through an indirect connection via other devices and connections. Further, in this specification, the recitation "based on" means "at least in part based on". Thus, if X is based on Y, then X can vary with Y and any number of other factors.

[0014] Some high-speed successive approximation register (SAR) analog-to-digital converters employ a capacitive digital-to-analog converter (CDAC) that operates with a large capacitor that is charged during the conversion process. A reference voltage provided to the ADC is applied to charge the capacitor during the conversion. To produce an accurate conversion result, the reference voltage must settle to a predetermined value within the time of the conversion cycle. The time required for the reference voltage to settle limits the conversion time. The impedance of the reference voltage source should be relatively low to provide fast settling.

[0015] To convert large-amplitude signals, the switches of the CDAC must be controlled with a corresponding high voltage. However, the control logic implemented at high voltages tends to be large and relatively slow. Some ADCs employ low-voltage logic to reduce size, delay, and power consumption, but must include a level shifter to drive the CDAC switches at a higher voltage. The level shifter adds delay, and the propagation through the level shifter within each conversion cycle increases the conversion time. For example, a level shifter having a propagation delay "N" for each bit of the CDAC increases the conversion time by N times the number of bits.

[0016] Some circuit implementations include multiple SAR ADCs, which further increases the capacitance to be charged. In such circuits, separate reference voltage pins are provided for each ADC so that noise on the reference voltage caused by the conversion timing of one ADC does not corrupt the reference voltage at another ADC. The multiple reference pins increase the package size and pin count.

[0017] The SAR ADC disclosed herein allows a single reference voltage pin to be used with multiple ADCs disposed on an integrated circuit, which reduces the package cost and size. The ADC includes a high-voltage buffer to buffer the reference voltage provided for converting the higher significant bits, and includes a low-voltage buffer to buffer the fractional reference voltage used for converting the lower significant bits. There is no need for a level shifter to control the CDAC switches to use the low-voltage buffer to convert bits, which allows for a reduced conversion time. Since most ADC circuit systems use a low-voltage semiconductor process and are powered by a low voltage, the power consumption and circuit area of the ADC are reduced relative to an ADC constructed using a higher-voltage process.

[0018] Figure 1 FIG. 4 shows a block diagram of an example integrated circuit 100 including a plurality of analog-to-digital converters in accordance with the present invention. The integrated circuit 100 includes a SAR ADC 102, a SAR ADC 104, a reference voltage terminal 106, a signal input terminal 108, and a signal input terminal 110. The reference voltage terminal 106 is coupled to the SAR ADC 102 and the SAR ADC 104 and provides a reference voltage for digitization. In some embodiments of the integrated circuit 100, the reference voltage terminal 106 is provided to connect a decoupling capacitor to a reference voltage external to the integrated circuit 100. The signal input terminal 108 is coupled to the SAR ADC 102 and provides a signal to be digitized by the SAR ADC 102. The signal input terminal 110 is coupled to the SAR ADC 104 and provides a signal to be digitized by the SAR ADC 104. In some embodiments of the integrated circuit 100, the signal input terminal 108 and / or the signal input terminal 110 are internal to the integrated circuit 100. In some embodiments of the integrated circuit 100, the SAR ADC 102 and the SAR ADC 104 are coupled in parallel to a first buffer that provides a reference voltage for use in a high-voltage domain and a second buffer that provides a fraction of the reference for use in a low-voltage domain. Thus, embodiments of the integrated circuit 100 include only one reference voltage terminal 106 for providing a reference voltage, which reduces the pin count and associated cost of the integrated circuit 100. Additionally, the circuit propagation delay is reduced by operating most of the circuit systems of the SAR ADC 102 and the SAR ADC 104 in a low-voltage domain, which allows for a faster conversion time or a longer settling time.

[0019] Figure 2A block diagram showing an example analog-to-digital converter 200 including a reference buffer. The analog-to-digital converter 200 includes a CDAC 202, a comparator 204, a successive approximation circuitry 206, and a buffer circuit 210. The comparator 204 is coupled to the CDAC 202 and compares the output of the CDAC 202 with a threshold voltage to determine whether the current setting of the CDAC 202 exceeds the threshold voltage. The successive approximation circuitry 206 is coupled to the comparator 204 and the CDAC 202 and controls the CDAC 202 based on the output of the comparator 204. For example, if the output of the comparator 204 indicates that the output of the CDAC 202 exceeds the threshold voltage, the successive approximation circuitry 206 changes the input to the CDAC 202 to identify the next highest significant bit that causes the output of the CDAC 202 not to exceed the threshold voltage.

[0020] The CDAC 202 is a split CDAC including a plurality of segments separated by capacitors. Each segment includes a plurality of capacitors and a plurality of switches coupled to each capacitor. The CDAC 202 includes segment 212 and segment 222. Embodiments of the CDAC 202 include two or more segments. Segment 212 includes capacitor 214 and switch 216. The switch 216 selectively connects one of a signal input terminal 220, a reference voltage 218, or ground to each of the capacitors 214. The switch 216 is coupled to the successive approximation circuitry 206 and is controlled by a switch control signal generated by the successive approximation circuitry 206. Embodiments of the analog-to-digital converter 200 include any number of capacitors 214, capacitors 224, switches 216, and switches 226 required to provide the desired number of output bits.

[0021] Segment 222 includes capacitor 224 and switch 226. The switch 226 selectively connects one of the reference voltage 218 or ground to each of the capacitors 224. The switch 226 is coupled to the successive approximation circuitry 206 and is controlled by a switch control signal 228 generated by the successive approximation circuitry 206.

[0022] The buffer circuit 210 buffers the reference voltage 208 to generate a reference voltage 218 provided to segment 212 and segment 222 of the CDAC 202. Decoupling capacitors 211 are provided external to the integrated circuit including the analog-to-digital converter 200.

[0023] All circuitry of the analog-to-digital converter 200 is powered by a high voltage supply (e.g., 5 volts) and includes semiconductor devices that are compatible with the high voltage supply, which increases circuit size and power consumption. Although the combination of the buffer circuit 210 and the decoupling capacitor 211 provides a low impedance, due to the bonding pad inductance that causes the bit decision in one SAR ADC to affect the reference voltage provided to another SAR ADC, the reference voltage 218 cannot be shared by multiple SAR ADCs (e.g., SAR ADC 102 and SAR ADC 104). Accordingly, each instance of the analog-to-digital converter 200 provided on the same integrated circuit must include an example of the package pin 213 and the decoupling capacitor 211, which increases package size and cost.

[0024] Figure 3 A block diagram showing an example analog-to-digital converter 300 that includes multiple reference buffers. The analog-to-digital converter 300 includes a CDAC 302, a comparator 304, a successive approximation circuitry 306, a buffer circuit 310, and a buffer circuit 330. The comparator 304 is coupled to the CDAC 302 and compares the output of the CDAC 302 with a threshold voltage to determine whether the current setting of the CDAC 302 exceeds the threshold voltage. The successive approximation circuitry 306 is coupled to the comparator 304 and the CDAC 302 and controls the CDAC 302 based on the output of the comparator 304. For example, if the output of the comparator 304 indicates that the output of the CDAC 302 exceeds the threshold voltage, then the successive approximation circuitry 306 changes the input to the CDAC 302 to identify the next highest value bit that causes the output of the CDAC 302 to not exceed the threshold voltage.

[0025] The CDAC 302 is a split CDAC that includes multiple segments separated by capacitors. Each segment includes multiple capacitors and multiple switches coupled to each capacitor. The CDAC 302 includes a segment 312 and a segment 322. Embodiments of the CDAC 302 include two or more segments. The segment 312 includes a capacitor 314 and a switch 316. The switch 316 selectively connects one of a signal input terminal 320, a reference voltage 318, or ground to each of the capacitors 314. The switch 316 is coupled to the successive approximation circuitry 306 and is controlled by a switch control signal 328 generated by the successive approximation circuitry 306. Embodiments of the analog-to-digital converter 300 include any number of capacitors 314, capacitors 324, switches 316, and switches 326 required to provide the desired number of output bits.

[0026] Section 322 includes capacitors 324 and switches 326. The switches 326 selectively connect either a reference voltage 332 or ground to each of the capacitors 324. The switches 326 are coupled to a successive approximation circuitry 306 and are controlled by a switch control signal 328 generated by the successive approximation circuitry 306.

[0027] A buffer circuit 310 buffers the reference voltage 308 to generate a reference voltage 318 provided to the switches 316. Decoupling capacitors 311 are provided external to the integrated circuit including the analog-to-digital converter 300. A buffer circuit 330 is coupled to the buffer circuit 310 and buffers the reference voltage 318 to generate a reference voltage 332 provided to the switches 326.

[0028] All circuitry of the analog-to-digital converter 300 is powered by a high voltage power supply (e.g., 5 volts) and includes semiconductor devices compatible with the high voltage power supply, which increases circuit size and power consumption. Implementing the buffer circuit 330 in the high voltage domain is challenging, and the relatively slow speed of the successive approximation circuitry 306 implemented in the high voltage process increases the conversion time.

[0029] Figure 4 A block diagram of an example analog-to-digital converter 400 including a low voltage successive approximation circuitry is shown. The analog-to-digital converter 400 includes a CDAC 402, a comparator 404, a successive approximation circuitry 406, a level shifter 434, a buffer circuit 410, and a buffer circuit 430. The comparator 404 is coupled to the CDAC 402 and compares the output of the CDAC 402 with a threshold voltage to determine whether the current setting of the CDAC 402 exceeds the threshold voltage. The successive approximation circuitry 406 is coupled to the comparator 404 and the CDAC 402 and controls the CDAC 402 based on the output of the comparator 404. For example, if the output of the comparator 404 indicates that the output of the CDAC 402 exceeds the threshold voltage, then the successive approximation circuitry 406 changes the input to the CDAC 402 to identify the next highest value bit that causes the output of the CDAC 402 not to exceed the threshold voltage.

[0030] The CDAC 402 is a split CDAC that includes multiple segments separated by capacitors. Each segment includes multiple capacitors and multiple switches coupled to each capacitor. The CDAC 402 includes segment 412 and segment 422. Embodiments of the CDAC 402 include two or more segments. Segment 412 includes capacitor 414 and switches 416. The switches 416 selectively connect one of a signal input terminal 420, a reference voltage 418, or ground to each of the capacitors 414. The switches 416 are coupled to a successive approximation circuitry 406 and are controlled by a switch control signal 428 generated by the successive approximation circuitry 406. Embodiments of the analog-to-digital converter 400 include any number of capacitors 414, capacitors 424, switches 416, and switches 426 required to provide a desired number of output bits.

[0031] Segment 422 includes capacitor 424 and switches 426. The switches 426 selectively connect one of a reference voltage 432 or ground to each of the capacitors 424. The switches 426 are coupled to the successive approximation circuitry 406 and are controlled by the switch control signal 428 generated by the successive approximation circuitry 406.

[0032] The buffer circuit 410 buffers the reference voltage 408 to generate a reference voltage 418 provided to the switches 416. A decoupling capacitor 411 is provided outside the integrated circuit including the analog-to-digital converter 400. The buffer circuit 430 is coupled to the buffer circuit 410 and buffers the reference voltage 418 to generate a reference voltage 432 provided to the switches 426.

[0033] In the analog-to-digital converter 400, the comparator 404 and the successive approximation circuitry 406 are powered by a low voltage supply (e.g., 1.5 volts), and other circuitry of the analog-to-digital converter 400 is powered by a high voltage supply (e.g., 5 volts). Providing the comparator 404 and the successive approximation circuitry 406 in a low voltage process reduces the size, power consumption, and latency of the comparator 404 and the successive approximation circuitry 406. However, due to the low voltage of the switch control signal 428, a level shifter 434 is coupled to the successive approximation circuitry 406 to level shift the switch control signal 428 upward to a higher voltage required to drive the switches 416 and 426. The propagation through the level shifter 434 introduces a latency at each bit decision, which increases the conversion time (or reduces the settling time) of the analog-to-digital converter 400 (e.g., increases the latency multiplied by the number of output bits of the analog-to-digital converter 400).

[0034] Figure 5Block diagram showing an example analog-to-digital converter 500 that operates a portion of a CDAC in a low voltage domain. The analog-to-digital converter 500 is an implementation of SAR ADC 102 or SAR ADC 104. The analog-to-digital converter 500 includes a CDAC 502, a comparator 504, a successive approximation circuitry 506, a level shifter 534, a buffer circuit 510, a buffer circuit 530, and a voltage divider 536. The comparator 504 is coupled to the CDAC 502 and compares the output of the CDAC 502 with a threshold voltage to determine whether the current setting of the CDAC 502 exceeds the threshold voltage. The successive approximation circuitry 506 is coupled to the comparator 504 and the CDAC 502 and controls the CDAC 502 based on the output of the comparator 504. For example, if the output of the comparator 504 indicates that the output of the CDAC 502 exceeds the threshold voltage, the successive approximation circuitry 506 changes the input to the CDAC 502 to identify the next highest value bit that causes the output of the CDAC 502 not to exceed the threshold voltage.

[0035] The CDAC 502 is a split CDAC that includes a plurality of segments separated by capacitors. Each segment includes a plurality of capacitors and a plurality of switches coupled to each capacitor. The CDAC 502 includes a segment 512 and a segment 522. Implementations of the CDAC 502 include two or more segments. The segment 512 is configured to convert the MSB output by the analog-to-digital converter 500, while the segment 522 and any other segments are configured to convert the lower significant bits. The segment 512 includes a capacitor 514 and a switch 516. The switch 516 selectively connects one of a signal input terminal 520, a reference voltage 518, or ground to each of the switches 516. The switch 516 is coupled to the successive approximation circuitry 506 via the level shifter 534 and is controlled by a switch control signal 528 generated by the successive approximation circuitry 506. Implementations of the analog-to-digital converter 500 include any number of capacitors 514, capacitors 524, switches 516, and switches 526 required to provide the desired number of output bits.

[0036] The segment 522 includes a capacitor 524 and a switch 526. The switch 526 selectively connects one of a reference voltage 532 or ground to each of the capacitors 524. The switch 526 is coupled to the successive approximation circuitry 506 and is controlled by a switch control signal 528 generated by the successive approximation circuitry 506.

[0037] The output 510A of buffer circuit 510 is coupled to switch 516 and reference voltage terminal 513. Buffer circuit 510 buffers reference voltage 508 to generate reference voltage 518 provided to switch 516. Decoupling capacitor 511 is coupled to reference voltage terminal 513 and is provided external to the integrated circuit containing analog-to-digital converter 500. Voltage divider 536 includes an input 536B coupled to the output 510A of buffer circuit 510. Voltage divider 536 divides reference voltage 518 by a value to generate reference voltage 532. Some embodiments of voltage divider 536 include a resistive voltage divider network. For example, voltage divider 536 includes a resistive voltage divider network that divides reference voltage 518 by 4 in some embodiments of analog-to-digital converter 500. The input 530A of buffer circuit 530 is coupled to the output 536A of voltage divider 536, and the output 530B of buffer circuit 530 is coupled to switch 526. Buffer circuit 530 buffers the divided reference voltage 519 to generate reference voltage 532 provided to switch 526.

[0038] In analog-to-digital converter 500, most of the circuitry is coupled to low voltage power rail 538 and is powered by a low voltage power supply (e.g., 1.5 volts) to reduce circuit size, power consumption, and latency. For example, comparator 504, successive approximation circuitry 506, buffer circuit 530, and section 522 are implemented in a low voltage semiconductor process and are coupled to low voltage power rail 538, while level shifter 534 and buffer circuit 510 are implemented in a high voltage semiconductor process and are coupled to high voltage power rail 540. Implementing buffer circuit 530 in a low voltage process with fast transistors reduces the settling time of reference voltage 532, which allows for a reduction in conversion time.

[0039] Level shifter 534 includes an input 534A coupled to the output 506A of successive approximation circuitry 506 and an output 534B coupled to switch 516. Level shifter 534 upwardly level shifts switch control signal 528 to the higher voltage required to drive switch 516. In analog-to-digital converter 500, level shifter 534 only drives the switches of section 512 (e.g., only the switches coupled to capacitor 514, where capacitor 514 samples the signal received at signal input terminal 520). All of the capacitors of CDAC 502 that sample the signal received at signal input terminal 520 are disposed in section 512. Switch 526 (and the switches of all sections other than section 512) is coupled to the output 506B of successive approximation circuitry 506 and is driven by low voltage control signal 531. Thus, most of the bit decisions eliminate the delay introduced by level shifter 534.

[0040] In integrated circuit 100, a single example of buffer circuit 510 and a single example of reference voltage terminal 513 are provided to generate a reference voltage 518 applied to SAR ADC 102 and SAR ADC 104, where SAR ADC 102 and SAR ADC 104 are embodiments of analog / digital converter 500. A single example of voltage divider 536 is provided to generate a divided reference voltage 519 by dividing reference voltage 518. A first example of buffer circuit 530 is coupled to voltage divider 536 to generate a reference voltage 532 for SAR ADC 102, and a second example of buffer circuit 530 is coupled to voltage divider 536 to generate a reference voltage 532 for SAR ADC 104. Thus, each example of analog / digital converter 500 provided on the integrated circuit includes an example of CDAC 502, an example of comparator 504, an example of successive approximation circuitry 506, an example of buffer circuit 530, and an example of level shifter 534, while multiple examples of analog / digital converter 500 on the integrated circuit share a single example of buffer circuit 510, reference voltage terminal 513, and voltage divider 536.

[0041] Within the scope of the claims, the described embodiments may be modified and other embodiments are possible.

Claims

1. An analog-to-digital converter, comprising: A low-voltage power supply rail; A high-voltage power supply rail; A successive approximation circuit system coupled to the low-voltage power supply rail; A level shifter coupled to the high-voltage power supply rail and including an input coupled to a first output of the successive approximation circuit system; A capacitive digital-to-analog converter CDAC, comprising: A first section, comprising: A first plurality of capacitors; and A first plurality of switches coupled to an output of the level shifter; and A second section, comprising: A second plurality of capacitors; and A second plurality of switches coupled to a second output of the successive approximation circuit system.

2. The analog-to-digital converter according to claim 1, wherein: The first plurality of switches are configured to operate at a voltage of the high-voltage power supply rail; and The second plurality of switches are configured to operate at a voltage of the low-voltage power supply rail.

3. The analog-to-digital converter according to claim 1, further comprising: A reference voltage terminal; A buffer circuit coupled to the high-voltage power supply rail and including an output coupled to the first plurality of switches and the reference voltage terminal.

4. The analog-to-digital converter according to claim 3, further comprising a voltage divider coupled to the output of the buffer circuit.

5. The analog-to-digital converter according to claim 4, wherein: The buffer circuit is a first buffer circuit; and And The analog-to-digital converter includes a second buffer circuit coupled to the low-voltage power supply rail and including: An input coupled to the voltage divider; And An output coupled to the second plurality of switches.

6. The analog-to-digital converter according to claim 4, wherein the voltage divider is configured to divide the output voltage of the buffer circuit by 4.

7. The analog-to-digital converter according to claim 1, further comprising a signal input terminal, wherein all capacitors of the CDAC coupled to the signal input terminal are disposed in the first section.

8. The analog-to-digital converter according to claim 1, further comprising a comparator coupled to the CDAC and the successive approximation circuit system.

9. The analog-to-digital converter according to claim 1, wherein the first section is configured to convert higher significant bits compared to the second section.

10. An analog-to-digital converter, comprising: A reference voltage terminal; A first buffer circuit including an output coupled to the reference voltage terminal; A voltage divider including an input coupled to the output of the first buffer circuit; A second buffer circuit including an input coupled to the output of the voltage divider; A successive approximation circuit system; A level shifter coupled to a first output of the successive approximation circuit system; A capacitive digital-to-analog converter CDAC, comprising: A first section, comprising: A first plurality of capacitors; and A first plurality of switches coupled to the output of the level shifter and the output of the first buffer circuit; A second section, comprising: A second plurality of capacitors; and A second plurality of switches coupled to a second output of the successive approximation circuit system and the output of the second buffer circuit.

11. The analog-to-digital converter according to claim 10, wherein the voltage divider is configured to divide the output voltage of the first buffer circuit by 4.

12. The analog-to-digital converter according to claim 10, further comprising: a low-voltage power supply rail; a high-voltage power supply rail; wherein: the first buffer circuit and the level shifter are coupled to the high-voltage power supply rail; and the second buffer circuit and the successive approximation circuitry are coupled to the low-voltage power supply rail.

13. The analog-to-digital converter according to claim 10, further comprising a signal input terminal; wherein all of the capacitors of the CDAC coupled to the signal input terminal are disposed in the first section.

14. The analog-to-digital converter according to claim 10, wherein the first section is configured to convert higher significant bits as compared to the second section.

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