Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device with a large on-state current and high reliability. A semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. Each of the first oxide and the fifth oxide contains at least one of the components contained in the second oxide. Each of the third oxide and the fourth oxide contains the element M. The third oxide and the fourth oxide have a region in which the concentration of the element M is higher than that of the second oxide.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Furthermore, another aspect of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, or storage devices are also types of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices sometimes include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the aforementioned technical fields. One aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Additionally, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Background Technology

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be applied to transistors. In addition, oxide semiconductors have attracted attention as other materials. Among oxide semiconductors, in addition to single-metal oxides such as indium oxide and zinc oxide, multi-metal oxides are also known. Among multi-metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) is particularly active.

[0005] Through research on IGZO, CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single-crystal nor amorphous, were discovered in oxide semiconductors (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 disclose a technique for manufacturing transistors using oxide semiconductors with CAAC structures. Furthermore, Non-Patent Documents 4 and 5 disclose oxide semiconductors with even lower crystallinity than CAAC and nc structures, yet still exhibiting minute crystals.

[0006] Transistors using IGZO as the active layer have extremely small off-state currents (see Non-Patent Document 6), and LSIs and displays that utilize this characteristic are known (see Non-Patent Documents 7 and 8).

[0007] [Preliminary Technology Documents]

[0008] [Non-patent literature]

[0009] [Non-Patent Literature 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186

[0010] [Non-Patent Literature 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, p. 04ED18-1-04ED18-10

[0011] [Non-Patent Literature 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, pp. 151-154

[0012] [Non-Patent Literature 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, pp. Q3012-Q3022

[0013] [Non-Patent Literature 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, pp. 155-164

[0014] [Non-Patent Literature 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7

[0015] [Non-Patent Literature 7] S. Matsuda et al., “2015 Symposium on VLSI Technology: Digest of Technical Papers”, 2015, pp. T216-T217

[0016] [Non-Patent Literature 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629 Summary of the Invention

[0017] The technical problem that the invention aims to solve

[0018] One objective of this invention is to provide a semiconductor device with a large on-state current. Another objective is to provide a semiconductor device with high frequency characteristics. Another objective is to provide a semiconductor device with high reliability. Another objective is to provide a semiconductor device capable of miniaturization or high integration. Another objective is to provide a semiconductor device with good electrical characteristics. Finally, another objective is to provide a semiconductor device with high productivity.

[0019] One objective of this invention is to provide a semiconductor device capable of retaining data for extended periods. Another objective of this invention is to provide a semiconductor device with fast information write speeds. Another objective of this invention is to provide a semiconductor device with high design freedom. Another objective of this invention is to provide a semiconductor device capable of suppressing power consumption. Another objective of this invention is to provide a novel semiconductor device.

[0020] Note that the description of the above objectives does not preclude the existence of other objectives. Furthermore, one embodiment of the present invention does not necessarily require achieving all of the above objectives. Additionally, objectives beyond these are readily apparent from the description, drawings, claims, etc., and can be derived from these descriptions.

[0021] means of solving technical problems

[0022] One aspect of the present invention is a semiconductor device comprising a first insulator, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide and a fourth oxide on the second oxide, a first conductor on the third oxide, a second conductor on the fourth oxide, a fifth oxide on the second oxide, a second insulator on the fifth oxide, and a third conductor on the second insulator. The fifth oxide is in contact with the top surface of the second oxide, the side surface of the first conductor, the side surface of the second conductor, the side surface of the third oxide, and the side surface of the fourth oxide. The second oxide comprises In, element M (M is Al, Ga, Y, or Sn), and Zn. The first oxide and the fifth oxide each comprise at least one of the constituent elements comprised in the second oxide. The third oxide and the fourth oxide each comprise element M. The third oxide and the fourth oxide have regions where the concentration of element M is higher than that of the second oxide.

[0023] Furthermore, in the above structure, it is preferable that the third oxide and the fourth oxide each have a region with a thickness of 0.5 nm or more and 5 nm or less.

[0024] Furthermore, in the above structure, it is preferable that the third oxide and the fourth oxide each have a region with a thickness of 1 nm or more and 3 nm or less.

[0025] Furthermore, in the above structure, the third oxide and the fourth oxide preferably each contain gallium.

[0026] Furthermore, in the above structure, the third oxide and the fourth oxide can each be crystallizable.

[0027] Furthermore, in the above structure, the second oxide can also be crystalline.

[0028] Furthermore, in the above structure, the compositions of the first oxide, third oxide, fourth oxide, and fifth oxide can also be substantially the same.

[0029] Invention Effects

[0030] According to one aspect of the present invention, a semiconductor device with a large on-state current can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high frequency characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high productivity can be provided.

[0031] Furthermore, a semiconductor device capable of retaining data for extended periods can be provided. Additionally, a semiconductor device with high data write speed can be provided. Furthermore, a semiconductor device with high design flexibility can be provided. Furthermore, a semiconductor device capable of suppressing power consumption can be provided. Furthermore, a novel semiconductor device can be provided.

[0032] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the invention does not necessarily require all of the aforementioned effects. Additionally, effects beyond these are readily apparent from the description, drawings, claims, etc., and can be derived from these descriptions.

[0033] Brief description of the attached figures

[0034] [Figure 1] Figure 1A This is a top view showing an example of the structure of a semiconductor device. Figure 1B and Figure 1C This is a cross-sectional view showing an example of the structure of a semiconductor device.

[0035] [Figure 2] Figure 2A This is a top view showing an example of the structure of a semiconductor device. Figure 2B and Figure 2C This is a cross-sectional view showing an example of the structure of a semiconductor device.

[0036] [Figure 3] Figure 3A and Figure 3B This is a cross-sectional view showing an example of the structure of a semiconductor device.

[0037] [Figure 4] Figure 4A This is a top view illustrating a method for manufacturing a semiconductor device. Figure 4B and Figure 4C This is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0038] [Figure 5] Figure 5A This is a top view illustrating a method for manufacturing a semiconductor device. Figure 5B and Figure 5C This is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0039] [Figure 6] Figure 6A This is a top view illustrating a method for manufacturing a semiconductor device. Figure 6B and Figure 6C This is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0040] [Figure 7] Figure 7A This is a top view illustrating a method for manufacturing a semiconductor device. Figure 7B and Figure 7C This is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0041] [Figure 8] Figure 8A This is a top view illustrating a method for manufacturing a semiconductor device. Figure 8B and Figure 8C This is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0042] [Figure 9] Figure 9A This is a top view illustrating a method for manufacturing a semiconductor device. Figure 9B and Figure 9C This is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0043] [Figure 10] Figure 10A This is a top view illustrating a method for manufacturing a semiconductor device. Figure 10B and Figure 10C This is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0044] [Figure 11] Figure 11A This is a top view illustrating a method for manufacturing a semiconductor device. Figure 11B and Figure 11C This is a cross-sectional view showing a method for manufacturing a semiconductor device.

[0045] [ Figure 12 ] Figure 12 This is a diagram illustrating the band structure of an oxide semiconductor.

[0046] [Figure 13] Figures 13A to 13C This is a schematic diagram illustrating the oxidation of a conductor disposed on an oxide semiconductor.

[0047] [Figure 14] Figures 14A to 14D This is a schematic diagram illustrating the oxidation of a conductor disposed on an oxide semiconductor.

[0048] [Figure 15] Figures 15A to 15C This is a schematic diagram illustrating the oxidation of a conductor disposed on an oxide semiconductor.

[0049] [ Figure 16 ] Figure 16 This is a cross-sectional view showing the structure of the storage device.

[0050] [ Figure 17 ] Figure 17 This is a cross-sectional view showing the structure of the storage device.

[0051] [Figure 18] Figure 18A This is a block diagram illustrating an example of the structure of a storage device. Figure 18B This is a schematic diagram illustrating an example of the structure of a storage device.

[0052] [Figure 19] Figures 19A to 19H This is a circuit diagram illustrating an example of the structure of a storage device.

[0053] [Figure 20] Figure 20A This is a block diagram illustrating an example of the structure of a semiconductor device. Figure 20B This is a schematic diagram illustrating an example of the structure of a semiconductor device.

[0054] [Figure 21] Figures 21A to 21E This is a schematic diagram illustrating an example of the structure of a storage device.

[0055] [Figure 22] Figures 22A to 22F This is a schematic diagram illustrating an electronic device.

[0056] [Figure 23] Figure 23A and Figure 23B This is a graph showing the heat treatment time dependence of the thin-film resistance of tantalum nitride in the embodiment.

[0057] [Figure 24] Figures 24A to 24C This is a graph showing the depth variation of the thin-film resistance of the oxide in the embodiment along the depth direction.

[0058] [Figure 25] Figures 25A to 25C This is a graph showing the depth variation of the thin-film resistance of the oxide in the embodiment along the depth direction.

[0059] [ Figure 26 ] Figure 26 This is a cross-sectional photograph of the sample from the embodiment.

[0060] [ Figure 27 ] Figure 27 This is a graph showing the results of the EDX linear analysis of an embodiment.

[0061] [ Figure 28 ] Figure 28 This is a graph showing the results of the EDX linear analysis of an embodiment.

[0062] [Figure 29] Figure 29A and Figure 29B This is a graph illustrating the stress-time dependence of ΔVsh in the +GBT stress test of an embodiment.

[0063] [ Figure 30 ] Figure 30 This is a graph illustrating the stress-time dependence of ΔVsh in the +GBT stress test of an embodiment.

[0064] [Figure 31] Figures 31A to 31C This is a graph showing the stress-time dependence of Ion, S values, and μFE in the +GBT stress test of the embodiment.

[0065] [ Figure 32 ] Figure 32This is a graph illustrating the stress-time dependence of ΔVsh in the +GBT stress test of an embodiment.

[0066] [Figure 33] Figures 33A to 33C This is a graph showing the stress-time dependence of Ion, S values, and μFE in the +GBT stress test of the embodiment.

[0067] [ Figure 34 ] Figure 34 This is a graph illustrating the normal probability distribution of Vsh in the embodiment.

[0068] [ Figure 35 ] Figure 35 This is a graph illustrating the normal probability distribution of Ion1 in the embodiment.

[0069] [ Figure 36 ] Figure 36 This is a graph illustrating the normal probability distribution of Ion2 in the embodiment.

[0070] [Figure 37] Figure 37A This is a circuit diagram used for calculations in the embodiment. Figure 37B This is a graph illustrating the calculation results of an embodiment.

[0071] [Figure 38] Figure 38A This is a graph illustrating the defect energy levels of an embodiment. Figure 38B This is a graph illustrating the calculation results of an embodiment.

[0072] [Figure 39] Figure 39A I is an example of an embodiment. D -V G Characteristic charts Figure 39B This is a graph showing the temperature dependence of the off-state current.

[0073] [ Figure 40 ] Figure 40 This is a graph illustrating the temperature dependence of the retention properties of the embodiment.

[0074] [ Figure 41 ] Figure 41 This is a diagram illustrating an energy band diagram of an embodiment.

[0075] [Figure 42] Figure 42A and Figure 42B This is a circuit diagram illustrating a TEG device for measuring retention characteristics according to an embodiment.

[0076] [ Figure 43 ] Figure 43 I is an example of an embodiment. D -V G A chart of characteristics.

[0077] [Figure 44] Figure 44A and Figure 44B This is a graph showing the leakage current evaluation results of an embodiment.

[0078] [ Figure 45 ] Figure 45 This is a graph showing the leakage current evaluation results of an embodiment.

[0079] Methods of implementing the invention

[0080] The embodiments will now be described with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the following embodiments.

[0081] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not necessarily limited to the dimensions described above. Furthermore, ideal examples are shown schematically in the drawings, and the invention is not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. Additionally, the same reference numerals are sometimes used across different drawings to denote the same parts or parts with the same function, omitting repeated descriptions. Furthermore, the same shading lines are sometimes used when indicating parts with the same function, without additional reference numerals.

[0082] Furthermore, especially in top views (also known as plan views) or perspective views, descriptions of some constituent elements are sometimes omitted to facilitate understanding of the invention. Additionally, descriptions of some hidden lines, etc., are sometimes omitted.

[0083] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," etc., are added for convenience, but they do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. In addition, the ordinal numbers described in this specification and other documents are sometimes inconsistent with the ordinal numbers used to specify one aspect of the present invention.

[0084] In this specification and other materials, for convenience, terms such as "upper" and "lower" are used to indicate configuration, referring to the accompanying drawings to illustrate the positional relationships of the constituent elements. Furthermore, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to that described in this specification and may be appropriately replaced as needed.

[0085] For example, in this specification, when it is explicitly stated as "X and Y are connected," it means the following: X and Y are electrically connected; X and Y are functionally connected; X and Y are directly connected. Therefore, connection relationships other than those shown in the figures or text are also included in the content disclosed in the figures or text, not limited to the specified connection relationships (e.g., the connection relationships shown in the figures or text).

[0086] Here, X and Y refer to objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films and layers, etc.).

[0087] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may sometimes be interchanged.

[0088] Furthermore, in this specification, depending on the transistor structure, the actual channel width (hereinafter also referred to as the "effective channel width") in the region forming the channel sometimes differs from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side of the semiconductor, sometimes the effect cannot be ignored because the effective channel width is greater than the apparent channel width. For example, in miniature transistors where the gate electrode covers the side of the semiconductor, sometimes the proportion of the channel formation region formed on the side of the semiconductor is increased. In this case, the effective channel width is greater than the apparent channel width.

[0089] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires assuming that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

[0090] In this specification, when simply described as "channel width," it sometimes refers to the visual channel width. Alternatively, in this specification, when simply described as "channel width," it sometimes refers to the effective channel width. Note that the values ​​of channel length, channel width, effective channel width, visual channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0091] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. Sometimes, the presence of impurities can cause, for example, an increase in the semiconductor's DOS (Density of States) or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, water sometimes also acts as an impurity. Furthermore, in an oxide semiconductor, the presence of impurities can sometimes lead to the creation of oxygen vacancies. Additionally, in the case of silicon, impurities that alter its properties include, for example, oxygen, and Group 1, Group 2, Group 13, and Group 15 elements (excluding hydrogen).

[0092] Note that in this specification, silicon oxynitride refers to a film in which the oxygen content is greater than the nitrogen content in its composition. Additionally, silicon oxynitride refers to a film in which the nitrogen content is greater than the oxygen content in its composition.

[0093] Additionally, in this specification, etc., "insulator" may be replaced with "insulating film" or "insulating layer". Furthermore, "conductor" may be replaced with "conductive film" or "conductive layer". Additionally, "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer".

[0094] In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and less than 10°. Therefore, it also includes a state where the angle is -5° or more and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is -30° or more and less than 30°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is 80° or more and less than 100°. Therefore, it also includes a state where the angle is 85° or more and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is 60° or more and less than 120°.

[0095] Note that in this specification, a barrier membrane refers to a membrane that has the function of inhibiting the permeation of impurities such as water and hydrogen, as well as oxygen. When the barrier membrane is conductive, it is sometimes called a conductive barrier membrane.

[0096] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when a metal oxide is used as the semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS FET or OS transistor can be referred to as a transistor that contains oxides or oxide semiconductors.

[0097] Note that in this specification, "normally off" means that the current flowing through the transistor per channel width of 1 μm at room temperature is 1 × 10⁻⁶ when the gate is not supplied with a potential or when the gate is supplied with a ground potential. -20 Below A, at 85℃, it is 1×10 -18 Below A, or 1×10 at 125℃ -16 Below A.

[0098] (Implementation Method 1)

[0099] The following describes an example of a semiconductor device including a transistor 200 according to one aspect of the present invention.

[0100] <Examples of semiconductor device structures>

[0101] Figure 1A , Figure 1B and Figure 1C This is a top view and cross-sectional view of a transistor 200 and its surroundings according to one aspect of the present invention.

[0102] Figure 1A This is a top view of a semiconductor device including transistor 200. Figure 1B and Figure 1C This is a cross-sectional view of the semiconductor device. Here, Figure 1B It is by Figure 1A The dashed lines A1-A2 in the figure show a cross-sectional view of the portion, which corresponds to a cross-sectional view of the transistor 200 along the channel length direction. Figure 1C It is by Figure 1A The section shown by the dashed lines A3-A4 is a cross-sectional view, which corresponds to a cross-sectional view of transistor 200 in the channel width direction. Note that, for clarity, in... Figure 1A Some constituent elements are omitted in the top view.

[0103] One aspect of the semiconductor device of the present invention includes an insulator 214 on a substrate (not shown), a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 274 on the insulator 282, and an insulator 281 on the insulator 274. Insulators 214, 280, 282, 274, and 281 are used as interlayer films. Furthermore, it includes conductors 240 (conductors 240a and 240b) electrically connected to the transistor 200 and used as connectors. It also includes insulators 241 (insulators 241a and 241b) in contact with the sides of the conductors 240 used as connectors. Additionally, conductors 246 (conductors 246a and 246b) electrically connected to the conductors 240 and used as wiring are provided on the insulator 281 and the conductors 240.

[0104] Furthermore, an insulator 241a is disposed in contact with the inner wall of the opening in insulators 272, 273, 280, 282, 274, and 281, a first conductor 240a is disposed in contact with its side surface, and a second conductor 240a is disposed inside it. Similarly, an insulator 241b is disposed in contact with the inner wall of the opening insulators 272, 273, 280, 282, 274, and 281, a first conductor 240b is disposed in contact with its side surface, and a second conductor 240b is disposed inside it. Here, the height of the top surface of the conductor 240 and the height of the top surface of the insulator 281 can be approximately the same. Furthermore, a structure in which the first conductor 240 and the second conductor 240 are stacked in the transistor 200 is shown, but the present invention is not limited thereto. For example, the conductor 240 may also have a single-layer structure or a stacked structure of three or more layers. In addition, when the structure has a stacked structure, ordinal numbers are sometimes assigned according to the order of formation for differentiation.

[0105] [Transistor 200]

[0106] like Figures 1A to 1CAs shown, transistor 200 includes an insulator 216 on an insulator 214, conductors 205 (conductors 205a and 205b) disposed in the insulator 216, an insulator 222 on the insulator 216 and conductors 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, oxides 243a and 243b on the oxide 230b, a conductor 242a on the oxide 243a, a conductor 242b on the oxide 243b, and an oxide 243a on the oxide 243a. The insulator 250 on oxide 230c, the conductor 260 (conductor 260a and conductor 260b) overlapping oxide 230c on insulator 250, a portion of the top surface of insulator 224, the side surface of oxide 230a, the side surface of oxide 230b, the side surface of oxide 243a, the side surface of oxide 243b, the side surface of conductor 242a, the top surface of conductor 242a, the side surface of conductor 242b, and the top surface of conductor 242b are in contact with the insulator 272, and the insulator 273 on insulator 272. Furthermore, oxide 230c is in contact with the side surface of oxide 243a, the side surface of oxide 243b, the side surface of conductor 242a, and the side surface of conductor 242b. Conductor 260 includes conductor 260a and conductor 260b, with conductor 260a arranged to surround the bottom and side surfaces of conductor 260b. Here, as Figure 1B As shown, the top surface of conductor 260 is approximately aligned with the top surface of insulator 250 and the top surface of oxide 230c. Furthermore, insulator 282 is in contact with the top surfaces of conductor 260, oxide 230c, insulator 250, and insulator 280, respectively.

[0107] Furthermore, insulators 222, 272, 273, and 282 preferably have the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). Furthermore, insulators 222, 272, 273, and 282 preferably have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the permeability of one or both of oxygen and hydrogen in insulators 222, 272, 273, and 282 is preferably lower than that of insulator 224. The permeability of one or both of oxygen and hydrogen in insulators 222, 272, 273, and 282 is preferably lower than that of insulator 250. The permeability of one or both of oxygen and hydrogen in insulators 222, 272, 273, and 282 is preferably lower than that of insulator 280.

[0108] like Figure 1BAs shown, insulator 272 preferably contacts the top and side surfaces of conductor 242a, conductor 242b, oxide 243a, oxide 243b, oxide 230a, oxide 230b, and the top surface of insulator 224. Furthermore, it is preferable to have insulator 273 disposed on insulator 272 in contact with it. Thus, insulator 280 is separated from insulator 224 and oxide 230 by insulator 272 and insulator 273.

[0109] Furthermore, oxide 230 preferably includes oxide 230a on insulator 224, oxide 230b on oxide 230a, and oxide 230c disposed on oxide 230b and at least a portion thereof in contact with the top surface of oxide 230b.

[0110] Note that in transistor 200, three layers of oxide 230a, oxide 230b, and oxide 230c are stacked in and around the channel forming region (hereinafter also referred to as the channel forming region), but the present invention is not limited to this. For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or a stacked structure of four or more layers can be provided. Furthermore, in transistor 200, conductor 260 has a two-layer stacked structure, but the present invention is not limited to this. For example, conductor 260 may also have a single-layer structure or a stacked structure of three or more layers.

[0111] Here, conductor 260 is used as the gate electrode of the transistor, and conductors 242a and 242b are each used as the source electrode or drain electrode. The transistor 200 is self-aligned in such a way that the conductor 260, which serves as the gate electrode, fills the opening formed in the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between conductors 242a and 242b without alignment.

[0112] In addition, it is preferable that the metal oxide (hereinafter, sometimes referred to as oxide semiconductor) used as an oxide semiconductor is used in the oxide 230 (oxide 230a, oxide 230b and oxide 230c) that includes the channel formation region in the transistor 200.

[0113] Since the transistor 200, which uses oxide semiconductor in the channel formation region, has extremely low leakage current (off-state current) in the non-conducting state, it can provide a low-power semiconductor device. Furthermore, since oxide semiconductor can be formed using methods such as sputtering, it can be used to construct transistors 200 that form highly integrated semiconductor devices.

[0114] The preferred oxide 230 is an In-M-Zn oxide (where element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). In particular, aluminum, gallium, yttrium, or tin can be used as element M. Furthermore, In-Ga oxide and In-Zn oxide can also be used as oxide 230.

[0115] Oxide 230 includes oxide 230a, oxide 230b on oxide 230a, and oxide 230c on oxide 230b. When oxide 230a is disposed under oxide 230b, the diffusion of impurities from the structure formed under oxide 230a to oxide 230b can be suppressed. When oxide 230c is disposed on oxide 230b, the diffusion of impurities from the structure formed above oxide 230c to oxide 230b can be suppressed.

[0116] Furthermore, oxide 230 preferably has a layered structure of oxides having different atomic ratios of each metal atom. Specifically, in the metal oxide used for oxide 230a, the atomic ratio of element M in the constituent elements is preferably greater than that in the metal oxide used for oxide 230b. Additionally, in the metal oxide used for oxide 230a, the atomic ratio of element M relative to In is preferably greater than that in the metal oxide used for oxide 230b. Furthermore, in the metal oxide used for oxide 230b, the atomic ratio of In relative to element M is preferably greater than that in the metal oxide used for oxide 230a. Additionally, oxide 230c can use a metal oxide that can be used for oxide 230a or oxide 230b.

[0117] Furthermore, the oxide 230b preferably has crystallinity. For example, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, oxygen extraction from the oxide 230b at the source or drain electrode can be suppressed. Thus, even with heat treatment, oxygen extraction from the oxide 230b can be reduced, and the transistor 200 remains stable against the high temperatures (so-called thermal budget) in the manufacturing process.

[0118] Preferably, the conduction band bottom energies of oxides 230a and 230c are higher than those of oxide 230b. In other words, the electron affinity of oxides 230a and 230c is preferably less than that of oxide 230b.

[0119] Here, at the junction of oxides 230a, 230b, and 230c, the energy level at the conduction band bottom changes gradually. In other words, the above situation can also be expressed as the energy level at the conduction band bottom of the junction of oxides 230a, 230b, and 230c changing continuously or continuously joining. For this purpose, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxides 230a and 230b, and at the interface between oxides 230b and 230c.

[0120] Specifically, for oxide 230a, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or 1:1:0.5 is acceptable. Furthermore, for oxide 230b, a metal oxide with an In:Ga:Zn ratio of 4:2:3 or 1:1:1 is acceptable. Additionally, for oxide 230c, a metal oxide with an In:Ga:Zn ratio of 1:3:4, a Ga:Zn ratio of 2:1, or a Ga:Zn ratio of 2:5 is acceptable. Furthermore, as specific examples of oxide 230c having a stacked structure, we can cite stacked structures with In:Ga:Zn = 1:3:4 [atomic ratio] and In:Ga:Zn = 4:2:3 [atomic ratio], stacked structures with Ga:Zn = 2:1 [atomic ratio] and In:Ga:Zn = 4:2:3 [atomic ratio], stacked structures with Ga:Zn = 2:5 [atomic ratio] and In:Ga:Zn = 4:2:3 [atomic ratio], and stacked structures with gallium oxide and In:Ga:Zn = 4:2:3 [atomic ratio].

[0121] At this point, the primary pathway for charge carriers is oxide 230b. By equipping oxides 230a and 230c with the aforementioned structure, the defect state density at the interfaces between oxides 230a and 230b, and between oxides 230b and 230c, can be reduced. Therefore, the influence of interface scattering on charge carrier conduction is reduced, resulting in transistor 200 exhibiting high on-state current and high frequency characteristics.

[0122] The oxide 230 is preferably a metal oxide used as an oxide semiconductor. For example, a metal oxide with a bandgap of 2 eV or more is preferred, and more preferably 2.5 eV or more is used. In this way, by using a metal oxide with a wider bandgap, the off-state current of the transistor can be reduced. By employing such a transistor, a low-power semiconductor device can be provided.

[0123] like Figure 12 As shown, the electron affinity, or conduction band bottom level Ec, can be calculated from the ionization potential Ip, the difference between the vacuum level Evac and the valence band top level Ev, and the band gap Eg. The ionization potential Ip can be measured, for example, using an ultraviolet photoelectron spectroscopy (UPS) device. The band gap Eg can be measured, for example, using a spectroellipsometer.

[0124] Furthermore, in transistors using oxide semiconductors, if impurities and oxygen vacancies exist in the channel formation region of the oxide semiconductor, the electrical characteristics are prone to variation, sometimes reducing reliability. Additionally, when oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor tends to exhibit always-on characteristics. Therefore, it is preferable to minimize oxygen vacancies in the channel formation region. For example, oxygen can be supplied to the oxide 230 through an insulator 250 to fill the oxygen vacancies. This suppresses variations in electrical characteristics, thereby providing a transistor with stable electrical characteristics and improved reliability.

[0125] Furthermore, when the conductor disposed near the oxide semiconductor is made of metal or alloy, the oxygen atoms constituting the oxide semiconductor sometimes cause oxidation of the conductor. When the conductivity of the conductor decreases due to oxidation, there is a high possibility of deviations in the electrical characteristics of the semiconductor device and a reduction in reliability.

[0126] Here, use Figures 13A to 15C This section explains the oxidation reaction of metal or alloy structures in contact with the oxide semiconductor caused by oxygen atoms contained in the oxide semiconductor. Specifically, the oxidation reaction is explained when In-Ga-Zn oxide is used as the oxide semiconductor and tantalum nitride is used as the conductor.

[0127] Figure 13A The diagram shows the region near the interface of a cross-section of a stack of an oxide semiconductor 10 made of In-Ga-Zn oxide and a conductor 20 made of tantalum nitride. Note that in the diagram, black circles in each structure represent oxygen atoms. Furthermore, white circles in the oxide semiconductor 10 represent oxygen vacancies generated in the oxide semiconductor.

[0128] Figure 13BThe initial process of the oxidation reaction of conductor 20 is shown. In conductor 20, the region with low concentrations of dissolved oxygen is designated as oxygen solution region 22. Furthermore, Figure 13C The growth process of oxide 30 formed by the oxidation reaction of conductor 20 is shown.

[0129] First, use Figures 14A to 14D The initial process of the oxidation reaction of conductor 20 is illustrated. The arrows in the attached figure indicate the migration direction of oxygen atoms. It is speculated that during the initial process of the oxidation reaction of conductor 20, the metal atoms tantalum at the interface of conductor 20 interact with the oxygen ions at the interface of oxide semiconductor 10.

[0130] like Figure 14A As shown in the attached figure, when the oxygen ions, indicated by black circles, reach the interface between the oxide semiconductor 10 and the conductor 20, they adsorb onto the tantalum metal atoms at the interface of the conductor 20.

[0131] like Figure 14B As shown, when heat treatment is performed while oxygen ions are adsorbed onto tantalum metal atoms, the oxygen ions diffuse into the conductor 20, forming an oxygen solid solution region 22 in the tantalum nitride (see reference). Figure 14B When the oxygen solid solution region 22 is formed, the oxidation reaction has not yet occurred, and the oxygen ions are in a solid solution state as impurities in the conductor 20. In addition, as oxygen ions diffuse into the conductor 20, oxygen vacancies are sometimes temporarily generated at the interface of the oxide semiconductor 10.

[0132] It is speculated that the capacity of the conductor 20 to dissolve oxygen depends on the crystallinity or density of the conductor 20. Furthermore, since oxygen ions at the interface of the oxide semiconductor 10 are dissolved in the conductor 20, oxygen atoms in the oxide semiconductor 10 fill the oxygen vacancies generated at the interface of the oxide semiconductor 10 (see reference). Figure 14C ).

[0133] Through repeated Figures 14A to 14C As shown in the process, the oxygen concentration in the oxygen solution region 22 increases. Here, when the oxygen in the oxygen solution region 22 becomes saturated, the oxidation of the tantalum metal atoms in the oxygen solution region 22 begins. Therefore, as... Figure 14D As shown, an oxide 30 containing tantalum oxide is formed between the oxide semiconductor 10 and the conductor 20.

[0134] Note that it is known that in the initial process of a metal oxidation reaction, oxide nucleation generally occurs. On the other hand, the heating temperature in the manufacturing process of a semiconductor device using oxide semiconductors is relatively low, so it can be inferred that an amorphous oxide film is formed at the interface between the oxide semiconductor 10 and the conductor 20.

[0135] Next, use Figures 15A to 15CThe growth process of oxide 30 formed between oxide semiconductor 10 and conductor 20 is described. Due to the formation of oxide 30, oxygen is lacking at the interface between oxide 30 and oxide semiconductor 10, and the interface is in a state of high oxygen vacancy concentration. That is, an oxygen vacancy concentration gradient can be considered to be generated in oxide semiconductor 10.

[0136] Therefore, as Figures 15A to 15C As shown, in oxide semiconductor 10, oxygen ions diffuse in order to achieve a uniform concentration of oxygen vacancies. It can be assumed that these oxygen ions reach the interface with oxide 30 (refer to...). Figure 15A Furthermore, the arriving oxygen ions are used in the growth reaction of tantalum oxide contained in oxide 30, and oxide 30 becomes thicker (see reference). Figure 15B and Figure 15C ).

[0137] When the effect of interface defects is not considered in the oxide 30 containing tantalum oxide, the oxidation reaction generally depends on the diffusion rate of metal and oxygen ions in the thin film of oxide 30.

[0138] Therefore, due to the diffusion of oxygen ions, an oxygen concentration gradient is generated in the oxide semiconductor 10 and oxide 30. It can be inferred that the diffusion rate of oxygen ions in oxide 30 is a factor determining the growth rate of tantalum oxide in oxide 30. In the case of oxygen ions, it can be assumed that oxygen ions diffuse into the tantalum oxide of oxide 30, reaching the interface between oxide 30 and conductor 20, thereby forming new tantalum oxide and thickening oxide 30. Furthermore, it can be assumed that during the growth process of this oxidation reaction, the oxygen solid solution region 22 of conductor 20 extends into conductor 20.

[0139] To suppress the oxidation reaction of the aforementioned conductor, in a transistor 200 according to one embodiment of the present invention, such as Figure 1B As shown, an oxide 243 (oxide 243a and oxide 243b) is disposed between the oxide 230b and the conductor 242 (conductor 242a and conductor 242b) used as a source electrode or drain electrode. Because the conductor 242 and the oxide 230b are not in contact, the absorption of oxygen from the oxide 230 by the conductor 242 can be suppressed. That is, by preventing the oxidation of the conductor 242, the decrease in the conductivity of the conductor 242 can be suppressed. Therefore, the oxide 243 preferably has the function of suppressing the oxidation of the conductor 242.

[0140] Therefore, oxide 243 preferably has the function of suppressing oxygen permeation. By distributing oxide 243, which has the function of suppressing oxygen permeation, between the conductor 242, which is used as the source electrode or drain electrode, and oxide 230b, the resistance between the conductor 242 and oxide 230b is reduced, which is therefore preferred. By adopting such a structure, the electrical characteristics and reliability of transistor 200 can be improved.

[0141] Metal oxides containing element M can also be used as oxide 243. In particular, aluminum, gallium, yttrium, or tin can be used as element M. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. Furthermore, gallium oxide can also be used as oxide 243. In addition, metal oxides such as In-M-Zn oxide can also be used as oxide 243. Specifically, the atomic ratio of element M relative to In in the metal oxide used for oxide 243 is preferably greater than that in the metal oxide used for oxide 230b. The thickness of oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. Furthermore, oxide 243 is preferably crystalline. When oxide 243 is crystalline, the release of oxygen in oxide 230 can be appropriately suppressed. For example, when oxide 243 has a hexagonal crystal structure, the release of oxygen in oxide 230 can sometimes be suppressed.

[0142] like Figure 1B and Figure 1C As shown, a transistor 200 according to one embodiment of the present invention has a structure in which insulator 282 and insulator 250 are in direct contact. By employing such a structure, oxygen contained in insulator 280 is less likely to be absorbed by conductor 260. Therefore, oxygen contained in insulator 280 is efficiently injected into oxides 230a and 230b via oxide 230c, thereby reducing oxygen vacancies in oxides 230a and 230b and improving the electrical characteristics and reliability of transistor 200. Furthermore, impurities such as hydrogen contained in insulator 280 can be suppressed from contaminating insulator 250, thereby suppressing negative impacts on the electrical characteristics and reliability of transistor 200. Silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide can be used as insulator 282.

[0143] Insulators 272 and 273 preferably have the function of suppressing the permeation of impurities such as hydrogen or water and oxygen.

[0144] Figure 3A It is along Figure 1A A magnified cross-section of the section marked with dashed lines A5-A6, corresponding to a cross-sectional view along the channel width of the source or drain region of transistor 200. (See attached image.) Figure 3AAs shown, the structure has an insulator 272 and an insulator 273 covering the top surface, side surface, side surface of oxide 230a, and side surface of conductor 242b, thus suppressing the diffusion of impurities such as hydrogen or water and oxygen from the side surface and top surface of conductor 242b into conductor 242b. Furthermore, because the bottom surface of conductor 242b is in contact with oxide 243b, oxygen in oxide 230b is blocked by oxide 243b, thereby suppressing the diffusion of oxygen into conductor 242b. Therefore, the diffusion of oxygen from the surrounding area of ​​conductor 242b into conductor 242b can be suppressed, thus suppressing the oxidation of conductor 242b. Conductor 242a has the same effect. Furthermore, the diffusion of impurities such as hydrogen or water from the side surface of oxide 230a and the side surface of oxide 230b into oxide 230a and oxide 230b can be suppressed. As insulator 272, for example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon oxide film, silicon nitride film, or silicon oxynitride film can be used. Additionally, as insulator 273, for example, aluminum oxide or hafnium oxide can be used.

[0145] Figure 3B yes Figure 1B A magnified view of the right half of transistor 200. The left side of conductor 240b. Figure 3B The portion surrounded by the dotted line in the diagram contacts oxide 230c, which can suppress the diffusion of impurities such as hydrogen or water, as well as oxygen, from insulator 250 to conductor 240b. Additionally, the right side of conductor 240b contacts insulator 272, which can suppress the diffusion of impurities such as hydrogen or water, as well as oxygen, from insulator 280 to conductor 240b. Conductor 240a has the same effect.

[0146] As described above, by employing a structure in which an insulator 272, an oxide 230c, and an oxide 243b, which have the function of suppressing impurities such as hydrogen or water and oxygen permeation, surrounds the conductor 242b, the oxidation of the conductor 240 can be suppressed, and the electrical characteristics and reliability of the transistor 200 can be improved.

[0147] like Figure 1C As shown, taking the bottom surface of insulator 224 as a standard, the height of the bottom surface of conductor 260 in the region where oxides 230a and 230b do not overlap with conductor 260 is preferably lower than the height of the bottom surface of oxide 230b. Furthermore, the difference between the height of the bottom surface of conductor 260 and the height of the bottom surface of oxide 230b in the region where oxides 230b and conductor 260 do not overlap is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0148] Thus, by employing a structure in which the conductor 260, used as the gate electrode, covers the sides and top of the oxide 230b in the channel formation region through the oxide 230c and the insulator 250, the electric field of the conductor 260 can easily act on the oxide 230b as a whole in the channel formation region. Therefore, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0149] As described above, a semiconductor device including transistors with large on-state current can be provided. Additionally, a semiconductor device including transistors with high frequency characteristics can be provided. Furthermore, a semiconductor device that suppresses electrical characteristic variations to achieve stable electrical characteristics and improves reliability can be provided. Additionally, a semiconductor device including transistors with small off-state current can be provided.

[0150] The detailed structure of a semiconductor device including a transistor 200 according to one aspect of the present invention will now be described.

[0151] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Furthermore, the conductor 205 is preferably disposed in a manner that fills within the insulator 214 and the insulator 216.

[0152] Here, conductor 260 is sometimes used as the first gate (also called the top gate) electrode. Furthermore, conductor 205 is sometimes used as the second gate (also called the bottom gate) electrode. In this case, the Vth of transistor 200 can be controlled by independently changing the potential supplied to conductor 205 without linking it to the potential supplied to conductor 260. In particular, by supplying a negative potential to conductor 205, the Vth of transistor 200 can be made greater than 0V, and the off-state current can be reduced. Therefore, compared to not supplying a negative potential to conductor 205, supplying a negative potential to conductor 205 reduces the drain current when the potential supplied to conductor 260 is 0V.

[0153] In addition, such as Figure 1A As shown, the conductor 205 is preferably larger than the regions in oxides 230a and 230b that do not overlap with conductors 242a and 242b. In particular, as... Figure 1CAs shown, conductor 205 preferably extends to the region outside the ends of oxides 230a and 230b that intersect the channel width direction. That is, preferably, conductor 205 and conductor 260 overlap with an insulator on the outer side of the side of oxides 230a and 230b in the channel width direction. Alternatively, by providing a larger conductor 205, localized charging (also known as charge up) can sometimes be mitigated during plasma processing in manufacturing steps after the formation of conductor 205. Note that one aspect of the invention is not limited to this. Conductor 205 overlaps at least with oxides 230a and 230b located between conductors 242a and 242b.

[0154] With the above structure, a region can be formed around the channel by the electric field of the conductor 260 used as the first gate electrode and the electric field of the conductor 205 used as the second gate electrode. In this specification, the structure of the transistor in which the electric fields of the first gate electrode and the second gate electrode form a region around the channel is referred to as a surround-channel (S-channel) structure.

[0155] Furthermore, the conductor 205a is preferably a conductor that suppresses the permeation of impurities such as water and hydrogen, as well as oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Additionally, the conductor 205b is preferably a conductive material with tungsten, copper, or aluminum as its main components. Note that the conductor 205 here is a two-layer structure, but a multi-layer structure with three or more layers can also be used.

[0156] Figures 2A to 2C An example of a five-layer conductor 205 is shown. As conductor 205, conductor 205c is formed in contact with the inner wall of the opening of insulator 216, and conductor 205d is formed inside it. Furthermore, conductor 205e is formed inside conductor 205d. Conductor 205f is formed in contact with the inner wall of conductor 205d and the top surface of conductor 205e, and conductor 205g is formed inside conductor 205f. Here, the height of the top surfaces of conductors 205c, 205d, 205f, and 205g can be approximately the same as the height of the top surface of insulator 216. Furthermore, conductor 205c is preferably made of the same material as conductor 205a, and conductors 205e and 205g are preferably made of the same material as conductor 205b.

[0157] Here, by forming oxide semiconductors, insulators or conductors located in the lower layer of oxide semiconductors, and insulators or conductors located in the upper layer of oxide semiconductors in a manner that does not expose them to the atmosphere, it is possible to form oxide semiconductor films with substantially high purity intrinsically, in which the concentration of impurities (especially hydrogen and water) is reduced, and therefore this is preferred.

[0158] For example, a film-forming apparatus having six processing chambers can be used to sequentially and continuously form an insulator 222, an insulating film becoming an insulator 224, an oxide film becoming an oxide 230a, an oxide film becoming an oxide 230b, a conductive film becoming a conductor 243, and a conductive film becoming a conductor 242 disposed on an insulator 216 and a conductor 205.

[0159] Insulators 214, 272, and 281 are preferably used as barrier insulating films to prevent impurities such as water or hydrogen from entering the transistor 200 from one side or above the substrate. Therefore, insulating materials that suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for these impurities to permeate) are preferably used as insulators 214, 272, and 281. Furthermore, insulating materials that suppress the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate) are preferably used.

[0160] For example, silicon nitride is preferably used as insulator 214, insulator 272, and insulator 281. This suppresses the diffusion of impurities such as water or hydrogen from the side closer to the substrate than insulator 214 to the transistor 200 side. Furthermore, it suppresses the diffusion of oxygen contained in insulator 224 and the like to the side closer to the substrate than insulator 214. Additionally, it suppresses the diffusion of impurities such as water and hydrogen from insulator 280 and / or conductor 246 disposed above insulator 272 to the transistor 200 side.

[0161] Additionally, it is sometimes preferable to reduce the resistivity of insulators 214, 272, and 281. For example, by setting the resistivity of insulators 214, 272, and 281 to 1 × 10⁻⁶. 13 The resistivity is approximately Ωcm. In semiconductor device manufacturing processes, insulators 214, 272, and 281 can mitigate charge buildup in conductors 205, 242, or 260 during plasma processing. The resistivity of insulators 214, 272, and 281 is preferably 1 × 10⁻⁶. 10 Ωcm or more and 1×10 15 Below Ωcm.

[0162] Alternatively, the insulator 214 can also employ a stacked structure. For example, a stacked structure of an aluminum oxide film and a silicon nitride film is preferably used for the insulator 214. The aluminum oxide film can supply oxygen to the underside of the insulator 214. In addition, the silicon nitride film can suppress the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 200 side.

[0163] Furthermore, the dielectric constants of insulators 216, 280, and 274 are preferably lower than that of insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen added, or porous silicon oxide can be appropriately used as insulators 216, 280, and 274.

[0164] Insulators 222 and 224 are used as gate insulators.

[0165] Here, in the insulator 224 that is in contact with the oxide 230, it is preferable to remove the oxygen by heating. In this specification, the oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulator 224. By providing an insulator containing oxygen in a manner that allows it to contact the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0166] Specifically, as the insulator 224, an oxide material that allows a portion of the oxygen to be removed by heating is preferably used. An oxide that allows oxygen to be removed by heating is defined as one in which the amount of oxygen molecules removed in TDS (Thermal Desorption Spectroscopy) analysis is 1.0 × 10⁻⁶. 18 molecule / cm 3 The preferred value is 1.0 × 10⁴. 19 molecule / cm 3 The above is further preferred to be 2.0×10 19 molecule / cm 3 Above, or 3.0 × 10 20 molecule / cm 3 The above-mentioned oxide film. Furthermore, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0167] Insulator 222 is preferably used as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into transistor 200 from the substrate side. For example, the hydrogen permeability of insulator 222 is preferably lower than that of insulator 224. By surrounding insulator 224 and oxide 230 with insulator 222 and insulator 272, impurities such as water or hydrogen from the outside can be prevented from entering transistor 200.

[0168] Furthermore, insulator 222 preferably has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate). For example, the oxygen permeability of insulator 222 is preferably lower than that of insulator 224. By enabling insulator 222 to inhibit the diffusion of oxygen or impurities, it is preferable to reduce the amount of oxygen present in oxide 230 that can diffuse to the underside of insulator 222. In addition, it is possible to suppress the reaction between conductor 205 and oxygen present in insulator 224 and oxide 230.

[0169] The insulator 222 is preferably an insulator containing an oxide of one or both of aluminum and hafnium as insulating materials. Alumina, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as insulators containing oxides of one or both of aluminum and hafnium. When this material is used to form the insulator 222, the insulator 222 serves as a layer to suppress the release of oxygen from the oxide 230 or the entry of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230.

[0170] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the insulator. Furthermore, the insulator can be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride can also be laminated onto the insulator.

[0171] Furthermore, as the insulator 222, insulators comprising so-called high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used, either as a single layer or in a stack. When miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0172] Alternatively, insulators 222 and 224 may also have a multilayer structure with two or more layers. In this case, it is not limited to a multilayer structure made of the same material, but may also be a multilayer structure made of different materials.

[0173] An oxide 243 is disposed on an oxide 230b, and a conductor 242 (conductor 242a and conductor 242b) which serves as a source electrode and a drain electrode is disposed on the oxide 243. The thickness of the conductor 242 is, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0174] As the conductor 242, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, so they are preferred.

[0175] Insulator 250 is used as a gate insulator. Insulator 250 is preferably disposed in contact with the top surface of oxide 230c. Insulator 250 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with added carbon and nitrogen, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0176] Similar to insulator 224, insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating in contact with the top surface of oxide 230c as insulator 250, oxygen can be effectively supplied to the channel formation region of oxide 230b. Similar to insulator 224, it is preferable to reduce the concentration of impurities such as water or hydrogen in insulator 250. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less.

[0177] Alternatively, a metal oxide may be disposed between the insulator 250 and the conductor 260. This metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By disposing of a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 caused by oxygen in the insulator 250 can be suppressed.

[0178] Furthermore, this metal oxide is sometimes used as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, a metal oxide that is a high-k material with a high relative permittivity is preferably used as the metal oxide. By making the gate insulator have a stacked structure of insulator 250 and this metal oxide, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential supplied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0179] Specifically, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as insulators containing one or both of aluminum and hafnium.

[0180] Alternatively, the metal oxide is sometimes used as part of the gate electrode. In this case, it is preferable to provide an oxygen-containing conductive material on one side of the channel formation region. By providing an oxygen-containing conductive material on one side of the channel formation region, oxygen detached from the conductive material can be easily supplied to the channel formation region.

[0181] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the metal oxide forming the channel is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen entering from external insulators or the like can sometimes be trapped.

[0182] Although Figures 1A to 1C In the conductor 260, there is a two-layer structure, but it can also have a single-layer structure or a stacked structure of three or more layers.

[0183] The conductor 260a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0184] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. As a conductive material with the function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, or ruthenium oxide are preferably used, for example.

[0185] Furthermore, conductive materials with tungsten, copper, or aluminum as the main components are preferably used as conductors 260b. Additionally, since conductor 260 is also used for wiring, a conductor with high conductivity is preferred. For example, conductive materials with tungsten, copper, or aluminum as the main components can be used. Furthermore, conductor 260b can have a multilayer structure, for example, a multilayer structure of titanium, titanium nitride, and the aforementioned conductive materials.

[0186] For example, the insulator 280 preferably comprises silicon oxide, silicon oxynitride, silicon oxynitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride are preferred because they possess thermal stability. Furthermore, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferred because they readily form regions containing oxygen released upon heating.

[0187] Furthermore, the concentration of impurities such as water or hydrogen in the insulator 280 is preferably reduced. In addition, the top surface of the insulator 280 can also be planarized.

[0188] Insulator 282 is preferably used as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into insulator 280 from above. As insulator 282, for example, insulators such as alumina, silicon nitride, or silicon oxynitride can be used.

[0189] Furthermore, it is preferable to provide an insulator 274, which serves as an interlayer film, on the insulator 282. Similar to insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 274 is reduced.

[0190] Conductors 240a and 240b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. Alternatively, conductors 240a and 240b may also have a laminated structure.

[0191] When the conductor 240 is constructed using a multilayer structure, a conductive material that inhibits the permeation of impurities such as water or hydrogen is preferably used as the conductor in contact with insulators 281, 274, 282, 280, 273, and 272. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are preferred. The conductive material that inhibits the permeation of impurities such as water or hydrogen can be used as a single layer or in multilayers. By using this conductive material, oxygen added to the insulator 280 can be prevented from being absorbed by conductors 240a and 240b. Furthermore, impurities such as water or hydrogen can be prevented from entering the oxide 230 from the layer above the insulator 281 through conductors 240a and 240b.

[0192] As insulators 241a and 241b, insulators such as aluminum oxide, silicon nitride, or silicon oxynitride can be used. Because insulators 241a and 241b are disposed in contact with insulators 272 and 273, impurities such as water or hydrogen from insulator 280 can be prevented from mixing into oxide 230 through conductors 240a and 240b.

[0193] Conductors 246 (conductors 246a and 246b) used for wiring can be configured to contact the top surfaces of conductors 240a and 240b. Conductors 246 are preferably made of conductive materials primarily composed of tungsten, copper, or aluminum. Furthermore, the conductor can have a multilayer structure, for example, a multilayer structure of titanium, titanium nitride, and the aforementioned conductive material. Additionally, the conductor can be embedded in an opening in an insulator.

[0194] Materials Constituting Semiconductor Devices

[0195] The following describes the constituent materials that can be used in semiconductor devices.

[0196] <Substrate>

[0197] For example, insulating substrates, semiconductor substrates, or conductive substrates can be used as substrates for forming the transistor 200. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples of insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators can also be used. Alternatively, substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0198] <Insulator>

[0199] As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0200] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, low voltage can be achieved during transistor operation while maintaining the physical thickness. On the other hand, by using a material with a relatively low permittivity as the insulator used as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0201] In addition, examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0202] In addition, examples of insulators with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide or resin with pores.

[0203] Furthermore, by surrounding a transistor using an oxide semiconductor with an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. For example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in single layers or in stacks. Specifically, as insulators suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, as well as metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxynitride, or silicon nitride can be used.

[0204] Furthermore, the insulator used as the gate insulator is preferably an insulator having regions containing oxygen that has been removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having regions containing oxygen that has been removed by heating is contacted with oxide 230, oxygen vacancies contained in oxide 230 can be filled.

[0205] <Conductor>

[0206] As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen, and are therefore preferred. Alternatively, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used.

[0207] Alternatively, multiple conductive layers formed from the above-described materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0208] Furthermore, when using oxides in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material is preferably used as the conductor serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0209] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the metal oxide forming the channel is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride and tantalum nitride can also be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Or, hydrogen entering from external insulators or the like can sometimes be trapped.

[0210] <Metal Oxides>

[0211] As oxide 230, a metal oxide that is used as an oxide semiconductor is preferred. Hereinafter, metal oxides that can be used in oxide 230 according to the present invention will be described.

[0212] The metal oxide preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. Additionally, it preferably contains aluminum, gallium, yttrium, or tin. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0213] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M can be aluminum, gallium, yttrium, or tin, etc. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of the above elements can sometimes be combined as element M.

[0214] Note that in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Furthermore, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0215] [Structure of metal oxides]

[0216] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS, a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0217] CAAC-OS exhibits c-axis orientation, with multiple nanocrystals linked along the ab-plane direction, resulting in a distorted crystal structure. Note that distortion refers to the portion of the lattice orientation that changes between regions with consistent lattice arrangement and other regions with consistent lattice arrangement within the region where multiple nanocrystals are linked.

[0218] Although nanocrystals are primarily hexagonal, they are not limited to regular hexagons and can be non-regular hexagonal. Furthermore, pentagonal or heptagonal lattice arrangements are sometimes observed in the distortion. Additionally, in CAAC-OS, well-defined grain boundaries (also known as grain boundaries) are difficult to observe even near the distortion. That is, it is known that lattice distortion can suppress grain boundary formation. This is because CAAC-OS can contain distortion due to the low density of oxygen atoms along the ab plane or changes in interatomic bonding distance caused by the substitution of metal elements.

[0219] Furthermore, CAAC-OS tends to have a layered crystal structure (also called a layered structure) consisting of layers containing indium and oxygen (hereinafter referred to as In layers) and layers containing elements M, zinc, and oxygen (hereinafter referred to as (M,Zn) layers). Additionally, indium and element M can be substituted for each other; when element M in a (M,Zn) layer is replaced by indium, the layer can also be represented as an (In,M,Zn) layer. Similarly, when indium in an In layer is replaced by element M, the layer can also be represented as an (In,M) layer.

[0220] CAAC-OS is a highly crystalline metal oxide. On the other hand, distinct grain boundaries are not easily observed in CAAC-OS, therefore it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. Furthermore, the crystallinity of metal oxides can sometimes decrease due to the incorporation of impurities or the formation of defects, therefore it can be said that CAAC-OS is a product of impurities or defects (oxygen vacancies (also known as V...)). O Metal oxides containing CAAC-OS have low oxygen vacancy and other oxygen vacancies. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS exhibit high heat resistance and high reliability.

[0221] In nc-OS, the atomic arrangement in tiny regions (e.g., regions above 1 nm and below 10 nm, particularly above 1 nm and below 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0222] Furthermore, indium gallium zinc oxide (hereinafter, IGZO), which is a metal oxide containing indium, gallium, and zinc, may have a stable structure when it is in the form of nanocrystals as described above. In particular, IGZO tends to not readily grow crystals in the atmosphere, so it may be structurally stable when IGZO is in the form of small crystals (e.g., the aforementioned nanocrystals) compared to when IGZO is in the form of large crystals (here, crystals a few mm or a few cm).

[0223] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0224] Oxide semiconductors (metal oxides) have various structures and properties. One embodiment of the present invention may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0225] Note that in one embodiment of the semiconductor device of the present invention, there are no particular restrictions on the structure of the oxide semiconductor (metal oxide), but crystallinity is preferred. For example, oxide 230 can adopt a CAAC-OS structure, and oxide 243 can adopt a hexagonal crystal structure. By adopting the above-described crystal structures as oxide 230 and oxide 243, a highly reliable semiconductor device can be realized. In addition, the compositions of oxides 230a, oxide 230c, and oxide 243 can be substantially the same.

[0226] [Impurities]

[0227] Here, we will explain the effects of various impurities in metal oxides.

[0228] Furthermore, when the metal oxide contains alkali metals or alkaline earth metals, defect states can sometimes be formed, resulting in charge carriers. Therefore, transistors using metal oxides containing alkali metals or alkaline earth metals as the channel formation region tend to exhibit always-on characteristics. Consequently, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of alkali metals or alkaline earth metals in the metal oxide, as measured by SIMS (concentration measured by Secondary Ion Mass Spectrometry), should be 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0229] Hydrogen contained in metal oxides reacts with oxygen bonded to the metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to the metal atoms, generating electrons as charge carriers. Therefore, transistors using hydrogen-containing metal oxides tend to have always-on characteristics.

[0230] Therefore, it is preferable to minimize the amount of hydrogen in metal oxides. Specifically, in metal oxides, the hydrogen concentration measured using SIMS is set to be below 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 By using metal oxides with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0231] As a semiconductor used in transistors, a metal oxide film with high crystallinity is preferred. Using this film can improve the stability or reliability of the transistor. Examples of such films include, for instance, single-crystal metal oxide films or polycrystalline metal oxide films. However, forming single-crystal or polycrystalline metal oxide films on a substrate requires high-temperature or laser heating processes. Therefore, the manufacturing process becomes more expensive and throughput decreases.

[0232] Non-Patent Literature 1 and Non-Patent Literature 2 report the discovery of In-Ga-Zn oxide (also known as CAAC-IGZO) with a CAAC structure in 2009. Both Non-Patent Literature 1 and Non-Patent Literature 2 report that CAAC-IGZO exhibits c-axis orientation, indistinct grain boundaries, and can be formed on substrates at low temperatures. Furthermore, transistors using CAAC-IGZO are reported to possess excellent electrical characteristics and reliability.

[0233] In addition, in 2013, an In-Ga-Zn oxide with an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Literature 3). It is reported here that the atomic arrangement of nc-IGZO in a small region (e.g., a region above 1 nm and below 3 nm) is periodic, and no regularity of crystal orientation is observed between different regions.

[0234] Non-patent documents 4 and 5 show the shift in average crystal size when the aforementioned CAAC-IGZO, nc-IGZO, and low-crystallinity IGZO films are irradiated with an electron beam, respectively. In the low-crystallinity IGZO film, approximately 1 nm of crystalline IGZO can be observed before electron beam irradiation. Therefore, it is reported that the presence of a completely amorphous structure could not be confirmed in the IGZO. Furthermore, it is disclosed that the CAAC-IGZO and nc-IGZO films exhibit higher stability relative to electron beam irradiation compared to the low-crystallinity IGZO film. Therefore, CAAC-IGZO or nc-IGZO films are preferably used as semiconductors for transistors.

[0235] Non-Patent Document 6 discloses a transistor using metal oxides with extremely low leakage current in the non-conducting state; specifically, the off-state current of the transistor is yA / μm per channel width of 1μm (10). -24 (A / μm) level (order). For example, a low-power CPU that utilizes the characteristic of low leakage current of transistors using metal oxides has been disclosed (see Non-Patent Document 7).

[0236] Furthermore, there are reports of applying transistors using metal oxide transistors to display devices, taking advantage of their low leakage current (see Non-Patent Document 8). In display devices, the displayed image is switched dozens of times per second. The number of image switches per second is called the refresh rate. The refresh rate is sometimes referred to as the drive frequency. Such high-speed image switching, which is difficult for the human eye to perceive, is considered a cause of eye fatigue. Therefore, a technique has been proposed to reduce the refresh rate of the display device to decrease the number of image rewrites. Additionally, a drive with a lower refresh rate can reduce the power consumption of the display device. This drive method is called Idle Stop (IDS) drive.

[0237] The discovery of CAAC and nc structures has contributed to improving the electrical characteristics and reliability of metal-oxide transistors using CAAC or nc structures, reducing manufacturing costs, and increasing throughput. Furthermore, research is underway to utilize the low leakage current of these transistors in display devices and LSIs.

[0238] <Methods for Manufacturing Semiconductor Devices>

[0239] Next, refer to Figures 4A to 11C illustrate Figures 1A to 1C The illustration shows a method for manufacturing a semiconductor device including a transistor 200 according to the present invention. Figures 4A to 11C In each figure, A shows a top view. Additionally, B in each figure shows a cross-sectional view along the dashed line A1-A2 in A, which corresponds to a cross-sectional view along the channel length direction of transistor 200. C in each figure shows a cross-sectional view along the dashed line A3-A4 in A, which corresponds to a cross-sectional view along the channel width direction of transistor 200. For clarity, some constituent elements are omitted in the top view of A in each figure.

[0240] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The insulator 214 can be formed using methods such as sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or atomic layer deposition (ALD).

[0241] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photo-CVD. Furthermore, CVD methods can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0242] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a film deposition method that reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes experience charge buildup due to receiving charge from plasma. This accumulated charge can sometimes damage these wiring, electrodes, and components. On the other hand, thermal CVD, which does not use plasma, avoids this plasma damage, thus improving the yield of semiconductor devices. Additionally, since thermal CVD does not generate plasma damage during film deposition, films with fewer defects can be obtained.

[0243] Furthermore, the ALD method leverages the self-regulating nature of atoms to deposit atoms in each layer, resulting in advantages such as the ability to form extremely thin films, films with high aspect ratios, films with few defects like pinholes, films with excellent coverage, and films formed at low temperatures. In addition, the ALD method includes plasma-enhanced ALD (PEALD). Using plasma allows for film formation at lower temperatures, making it sometimes preferred. Note that the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method sometimes contain more impurities such as carbon compared to films formed using other methods. Furthermore, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0244] Unlike film formation methods that deposit particles released from a target or similar material, CVD and ALD methods form films based on reactions on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed using ALD exhibit excellent step coverage and thickness uniformity, making ALD suitable for applications requiring the coverage of surfaces with high aspect ratio openings. Note that ALD has a relatively slow film formation rate, so it is sometimes preferable to combine it with other film formation methods with faster rates, such as CVD.

[0245] CVD and ALD methods allow control of the film composition by adjusting the source gas flow rate ratio. For example, when using CVD or ALD, films with arbitrary compositions can be formed by adjusting the source gas flow rate ratio. Furthermore, for example, when using CVD and ALD, films with continuously varying compositions can be formed by changing the source gas flow rate ratio simultaneously with film formation. When forming a film while changing the source gas flow rate ratio, the time required for pressure transfer and adjustment is eliminated, thus shortening the film formation time compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0246] In this embodiment, silicon nitride is formed as the insulator 214 using a CVD method. In this way, by using an insulator such as silicon nitride, which does not easily allow copper to pass through, as the insulator 214, even if a metal such as copper, which is easily diffused, is used as the conductor in the layer below the insulator 214 (not shown), the diffusion of the metal to the layer above the insulator 214 can be suppressed.

[0247] Next, insulator 216 is formed on insulator 214. Insulator 216 can be formed using sputtering, CVD, MBE, PLD or ALD methods.

[0248] Next, an opening leading to insulator 214 is formed in insulator 216. The opening may include, for example, a groove or a slit. Furthermore, the area where the opening is formed is sometimes referred to as an opening portion. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. As insulator 214, it is preferable to select an insulator that serves as an etch stop film when etching insulator 216 to form a groove. For example, when a silicon oxide film is used as the insulator 216 for forming the groove, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used as the insulator 214.

[0249] After the opening is formed, a conductive film 205 is formed. This conductive film preferably contains a conductor that inhibits oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film of the conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film 205 can be formed using sputtering, CVD, MBE, PLD, or ALD methods.

[0250] In this embodiment, a multilayer structure is adopted as the conductive film that serves as the conductor 205. First, tantalum nitride is deposited using a sputtering method, and titanium nitride is stacked on top of the tantalum nitride. By using this metal nitride as the lower layer of the conductive film that serves as the conductor 205, even if a metal that easily diffuses, such as copper, is used as the upper layer of the conductive film that serves as the conductor 205 (described later), the diffusion of this metal from the conductor 205 to the outside can be suppressed.

[0251] Next, a conductive film is formed as the upper layer of the conductive film that becomes the conductor 205. This conductive film can be formed using methods such as plating, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, a low-resistance conductive material such as copper is formed as the upper conductive film that becomes the conductor 205.

[0252] Next, a portion of the upper and lower layers of the conductive film that forms the conductor 205 are removed by CMP (Chemical Mechanical Polishing), exposing the insulator 216. As a result, the conductive film that forms the conductor 205 remains only at the opening. Thus, a conductor 205 with a flat top surface can be formed. Note that sometimes a portion of the insulator 216 is removed due to this CMP process (see [reference]). Figures 4A to 4C ).

[0253] The following will describe a method for forming the conductor 205 that differs from the above.

[0254] Next, a conductive film serving as a conductor 205 is formed on the insulator 214. The conductive film serving as the conductor 205 is formed using methods such as sputtering, CVD, MBE, PLD, or ALD. Furthermore, the conductive film serving as the conductor 205 can be a multilayer film. In this embodiment, tungsten is formed as the conductive film serving as the conductor 205.

[0255] Next, the conductive film, which becomes the conductor 205, is processed using photolithography to form the conductor 205.

[0256] In photolithography, a photoresist is first exposed through a mask. Then, a developer is used to remove or leave the exposed areas, forming a photoresist mask. Next, etching is performed through the photoresist mask to process conductors, semiconductors, or insulators into the desired shape. For example, a photoresist mask can be formed by exposing the photoresist with a KrF stimulated excimer laser, an ArF stimulated excimer laser, or EUV (Extreme Ultraviolet) light. Alternatively, immersion lithography can be used, where exposure is performed with liquid (e.g., water) filling the space between the substrate and the projection lens. Electron beams or ion beams can also be used instead of the aforementioned light. Note that a mask is not required when using electron or ion beams. Furthermore, when removing the photoresist mask, dry etching (such as ashing) or wet etching can be performed, or wet etching can be performed after dry etching, or dry etching can be performed after wet etching.

[0257] Alternatively, a hard mask made of an insulator or conductor can be used instead of a photoresist mask. When using a hard mask, an insulating or conductive film that serves as the hard mask material can be formed on the conductive film that serves as the conductor 205, and a photoresist mask can be formed on it. Then, the hard mask material can be etched to form a hard mask of the desired shape. The etching of the conductive film that serves as the conductor 205 can be performed either after removing the photoresist mask or without removing it. In the latter case, the photoresist mask may sometimes disappear during etching. Alternatively, the hard mask can be removed by etching after etching the conductive film that serves as the conductor 205. On the other hand, it is not necessary to remove the hard mask if the hard mask material does not affect subsequent processes or can be used in subsequent processes.

[0258] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used. The CCP etching apparatus including parallel planar electrodes can also employ a structure that supplies high-frequency power to one of the parallel planar electrodes. Alternatively, it can employ a structure that supplies multiple different high-frequency powers to one of the parallel planar electrodes. Alternatively, it can employ a structure that supplies the same high-frequency power to each of the parallel planar electrodes. Alternatively, it can employ a structure that supplies different high-frequency power to each of the parallel planar electrodes. Alternatively, a dry etching apparatus with a high-density plasma source can also be used. For example, as a dry etching apparatus with a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used.

[0259] Next, an insulating film, which becomes insulator 216, is formed on insulator 214 and conductor 205. Insulator 216 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. In this embodiment, silicon oxide is formed as the insulating film that becomes insulator 216 using CVD.

[0260] Here, the thickness of the insulating film that serves as insulator 216 is preferably greater than or equal to the thickness of conductor 205. For example, when the thickness of conductor 205 is 1, the thickness of the insulating film that serves as insulator 216 is 1 or more and 3 or less. In this embodiment, the thickness of conductor 205 is 150 nm, and the thickness of the insulating film that serves as insulator 216 is 350 nm.

[0261] Next, a portion of the insulating film that forms the insulator 216 is removed by CMP treatment, exposing the surface of the conductor 205. Thus, a conductor 205 and an insulator 216 with flat top surfaces can be formed. This is a method for forming the conductor 205 that differs from the method described above.

[0262] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. Preferably, the insulator 222 is an oxide containing one or both of aluminum and hafnium. Furthermore, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) are preferred as the insulator. The insulator containing one or both of aluminum and hafnium provides barrier properties against oxygen, hydrogen, and water. When the insulator 222 provides barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the surrounding structures of the transistor 200 through the insulator 222 to the inside of the transistor 200 can be suppressed, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0263] Insulator 222 can be formed by sputtering, CVD, MBE, PLD or ALD.

[0264] Next, an insulating film 224A is formed on the insulator 222. The insulating film 224A can be formed by sputtering, CVD, MBE, PLD or ALD, etc.

[0265] Next, a heat treatment is preferably performed. The heat treatment is performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the removed oxygen, in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas.

[0266] In this embodiment, the process is performed at 400°C for 1 hour under a nitrogen atmosphere, followed by a continuous process at 400°C for 1 hour under an oxygen atmosphere. This heat treatment removes impurities such as water and hydrogen contained in the insulating film 224A.

[0267] Alternatively, heat treatment can be performed after the insulator 222 has been formed. This heat treatment can be performed under the conditions described above.

[0268] To form an excess oxygen region in the insulating film 224A, oxygen-containing plasma treatment can be performed under reduced pressure. The oxygen-containing plasma treatment preferably employs a device including a power supply for generating high-density plasma using microwaves. Alternatively, it may include a power supply for supplying RF (Radio Frequency) to one side of the substrate. High-density oxygen radicals can be generated using high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulating film 224A by supplying RF to one side of the substrate. Alternatively, an oxygen-containing plasma treatment can be performed after a plasma treatment containing an inert gas using such a device to replenish the detached oxygen. Furthermore, by appropriately selecting the conditions of this plasma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. In this case, heating treatment may not be necessary.

[0269] Here, aluminum oxide can be formed on the insulating film 224A, for example, by sputtering, and CMP can be performed on the aluminum oxide until it reaches the insulating film 224A. This CMP process can planarize and smooth the surface of the insulating film 224A. By placing the aluminum oxide on the insulating film 224A and performing CMP, the endpoint of the CMP can be easily detected. Furthermore, sometimes the thickness of the insulating film 224A may become thinner due to polishing of a portion of it by CMP, but this can be corrected by adjusting the thickness during the film formation process. Planarizing and smoothing the surface of the insulating film 224A can sometimes prevent a decrease in the coverage of the oxide layer to be formed underneath and prevent a decrease in the yield of the semiconductor device. Moreover, since oxygen can be added to the insulating film 224A by sputtering, this is preferable.

[0270] Next, oxide film 230A and oxide film 230B are sequentially formed on insulating film 224A (refer to...). Figures 4A to 4C Preferably, the oxide film is formed continuously without exposure to the atmospheric environment. By forming the oxide film without exposure to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to oxide film 230A and oxide film 230B, thus keeping the area near the interface between oxide film 230A and oxide film 230B clean.

[0271] Oxide film 230A and oxide film 230B can be formed by sputtering, CVD, MBE, PLD or ALD.

[0272] For example, when forming oxide films 230A and 230B using sputtering, oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased. Furthermore, when forming the aforementioned oxide films using sputtering, the aforementioned In-M-Zn oxide target can be used, for example.

[0273] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas is sometimes supplied to the insulating film 224A. Therefore, the oxygen content in the sputtering gas of the oxide film 230A can be 70% or more, preferably 80% or more, and more preferably 100%.

[0274] Furthermore, when forming the oxide film 230B using sputtering, an oxygen-deficient oxide semiconductor is formed when the oxygen content in the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can have higher field-effect mobility.

[0275] In this embodiment, an oxide film 230A is formed using a sputtering method with an In:Ga:Zn ratio of 1:1:0.5 (2:2:1) or 1:3:4. Alternatively, an oxide film 230B is formed using a sputtering method with an In:Ga:Zn ratio of 4:2:4.1 or 1:1:1. The oxide films can be formed by appropriately selecting the film formation conditions and atomic ratios according to the desired characteristics of the oxide 230.

[0276] Next, heat treatment can be performed. The aforementioned heat treatment conditions can be used as the conditions for heat treatment. By performing heat treatment, impurities such as water and hydrogen in oxide films 230A and 230B can be removed. In this embodiment, the treatment is performed at 400°C for 1 hour under a nitrogen atmosphere, followed by continuous treatment at 400°C for 1 hour under an oxygen atmosphere.

[0277] Next, an oxide film 243A is formed on the oxide film 230B. The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, or ALD. Preferably, the ratio of Ga atoms relative to In in the oxide film 243A is larger than the ratio of Ga atoms relative to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using a target with an In:Ga:Zn ratio of 1:3:4. Next, a conductive film 242A is formed on the oxide film 243A. The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, or ALD (see reference). Figures 4A to 4C ).

[0278] Next, oxide films 230A, 230B, 243A, and 242A are processed into island shapes to form oxide 230a, oxide 230b, oxide layer 243B, and conductor layer 242B (see reference). Figures 5A to 5C Additionally, although not shown, in this process, the thickness of the region of the insulating film 224A that does not overlap with the oxide 230a sometimes becomes thinner.

[0279] Here, oxide 230a, oxide 230b, oxide layer 243B, and conductor layer 242B are formed such that at least a portion overlaps with conductor 205. Furthermore, the side surfaces of oxide 230a, oxide 230b, oxide layer 243B, and conductor layer 242B are preferably substantially perpendicular to the top surface of insulator 222. When the side surfaces of oxide 230a, oxide 230b, oxide layer 243B, and conductor layer 242B are substantially perpendicular to the top surface of insulator 222, a smaller area and higher density can be achieved when multiple transistors 200 are provided. Alternatively, a structure with a smaller angle formed between oxide 230a, oxide 230b, oxide layer 243B, and conductor layer 242B and the top surface of insulator 222 can also be used. In this case, the angle formed between the side surfaces of oxide 230a, oxide 230b, oxide layer 243B, and conductor layer 242B and the top surface of insulator 222 is preferably 60° or more and less than 70°. By adopting this shape, the coverage of insulators 272 and the like is improved in the following processes, and defects such as voids can be reduced.

[0280] Furthermore, a curved surface is provided between the side surface and the top surface of the conductive layer 242B. That is, the ends of the side surface and the top surface are preferably curved (hereinafter also referred to as rounded). For example, at the ends of the conductive layer 242B, the curved surface has a radius of curvature of 3 nm or more and 10 nm or less, more preferably 5 nm or more and 6 nm or less. When the ends do not have corners, the film coverage in subsequent film deposition processes can be improved.

[0281] Furthermore, the oxide film and conductive film can be fabricated using photolithography. Alternatively, this fabrication can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication.

[0282] Next, an insulating film 272A is formed on insulator 224, oxide 230a, oxide 230b, oxide layer 243B and conductor layer 242B (see reference). Figures 6A to 6C ).

[0283] The insulating film 272A can be formed by sputtering, CVD, MBE, PLD, or ALD. Preferably, the insulating film 272A is an insulating film with the function of inhibiting oxygen permeation. For example, aluminum oxide, silicon nitride, silicon oxide, or gallium oxide can be formed by sputtering or ALD.

[0284] Next, an insulating film 273A is formed on the insulating film 272A. The insulating film 273A can be formed by sputtering, CVD, MBE, PLD, or ALD. For example, alumina is preferably formed by ALD. In this embodiment, alumina is formed by ALD (see reference). Figures 6A to 6CAlternatively, a structure that does not form an insulating film 273A can be used.

[0285] Next, an insulating film becoming insulator 280 is formed on insulating film 273A. The insulating film becoming insulator 280 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. Next, the insulating film becoming insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see reference). Figures 7A to 7C ).

[0286] Next, a portion of insulator 280, a portion of insulating film 273A, a portion of insulating film 272A, a portion of oxide layer 243B, a portion of conductor layer 242B, and a portion of insulating film 224A are processed to form an opening reaching oxide 230b. This opening is preferably formed in a manner that overlaps with conductor 205. Through the formation of this opening, oxide 243a, oxide 243b, conductor 242a, conductor 242b, insulator 224, insulator 272, and insulator 273 (see reference) are formed. Figures 7A to 7C ).

[0287] Furthermore, a portion of the insulator 280, a portion of the insulating film 273A, a portion of the insulating film 272A, a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the insulating film 224A can be processed under different conditions. For example, a portion of the insulator 280 can be processed by dry etching, a portion of the insulating film 273A can be processed by wet etching, and a portion of the insulating film 272A, a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the insulating film 224A can be processed by dry etching.

[0288] During the aforementioned dry etching process, impurities such as etching gases sometimes adhere to or diffuse into the surface or interior of oxides 230a and 230b. Examples of such impurities include fluorine or chlorine.

[0289] To remove the aforementioned impurities, washing is performed. Washing methods include wet washing using a washing liquid, plasma treatment using plasma, and washing using heat treatment; combinations of these methods may also be appropriate.

[0290] As a wet cleaning method, an aqueous solution prepared by diluting oxalic acid, phosphoric acid, ammonia, or hydrofluoric acid with carbonated water or pure water can be used for washing. Alternatively, ultrasonic cleaning can be performed using pure water or carbonated water.

[0291] Next, heat treatment can be performed. The heat treatment can also be carried out under reduced pressure, during which an oxide film 230C is continuously formed without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is 200°C (see reference). Figures 8A to 8C ).

[0292] Here, the oxide film 230C is preferably disposed in contact with at least a portion of the side surface of oxide 230a, a portion of the side surface and a portion of the top surface of oxide 230b, a portion of the side surface of oxide 243, a portion of the side surface of conductor 242, the side surface of insulator 272, the side surface of insulator 273, and the side surface of insulator 280. Because conductor 242 is surrounded by oxide 243, insulator 272, and oxide film 230C, the decrease in conductivity caused by oxidation of conductor 242 in subsequent processes can be suppressed.

[0293] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, or ALD. The ratio of Ga atoms relative to In in the oxide film 230C is preferably larger than that in the oxide film 230B. In this embodiment, the oxide film 230C is formed by sputtering using a target with an In:Ga:Zn ratio of 1:3:4 [atomic ratio].

[0294] Note that the 230C oxide film can also be a stack. For example, it can be deposited by sputtering using a target with an In:Ga:Zn ratio of 1:3:4 [atomic number ratio], or continuously using a target with an In:Ga:Zn ratio of 4:2:4.1 [atomic number ratio].

[0295] In particular, during the formation of oxide film 230C, a portion of the oxygen contained in the sputtering gas is sometimes supplied to oxides 230a and 230b. Therefore, the oxygen content in the sputtering gas of oxide film 230C can be 70% or more, preferably 80% or more, and more preferably 100%.

[0296] Next, a heat treatment may be performed. This heat treatment can also be carried out under reduced pressure, during which an insulating film 250A is continuously formed without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxides 230a, 230b, and oxide film 230C are reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower (see reference). Figures 9A to 9C ).

[0297] The insulating film 250A can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. Silicon oxynitride is preferably formed using CVD as the insulating film 250A. The film-forming temperature for the insulating film 250A is preferably 350°C or higher and lower than 450°C, and particularly preferably around 400°C. By forming the insulating film 250A at a temperature of 400°C, an insulator with fewer impurities can be formed.

[0298] Next, conductive films 260Aa and 260Ab are formed. The conductive films 260Aa and 260Ab can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. For example, CVD is preferred. In this embodiment, conductive film 260Aa is formed using ALD, and conductive film 260Ab is formed using CVD (see reference). Figures 10A to 10C ).

[0299] Next, the oxide film 230C, insulating film 250A, conductive film 260Aa, and conductive film 260Ab are polished using CMP treatment until the insulator 280 is exposed, forming oxide 230c, insulator 250, and conductor 260 (conductor 260a and conductor 260b) (see reference). Figures 11A to 11C ).

[0300] Here, the conductor 242 is arranged to be surrounded by oxide 243, insulator 272, and oxide 230c, so that the decrease in conductivity caused by the oxidation of the conductor 242 can be suppressed.

[0301] Next, heat treatment can also be performed. In this embodiment, the treatment is carried out at a temperature of 400°C for 1 hour under a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in insulators 250 and 280.

[0302] Next, an insulating film forming insulator 282 can be formed on conductor 260, oxide 230c, insulator 250, and insulator 280. The insulating film forming insulator 282 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. For example, alumina is preferably formed by sputtering as the insulating film forming insulator 282. Thus, by forming insulator 282 in contact with the top surface of conductor 260, the absorption of oxygen contained in insulator 280 by conductor 260 during subsequent heat treatment can be suppressed, which is therefore preferred (see reference). Figures 11A to 11C ).

[0303] Next, a heat treatment can be performed. In this embodiment, the treatment is carried out at 400°C for 1 hour under a nitrogen atmosphere. By performing this heat treatment, oxygen added through the film formation of insulator 282 can be injected into insulator 280. Furthermore, this oxygen can be injected into oxides 230a and 230b via oxide 230c.

[0304] Next, an insulator that becomes insulator 274 can also be formed on insulator 282. The insulating film that becomes insulator 274 can be formed by sputtering, CVD, MBE, PLD, or ALD, etc. (see reference). Figures 11A to 11C ).

[0305] Next, an insulating film that becomes insulator 281 can be formed on insulator 274. The insulating film that becomes insulator 281 can be formed by sputtering, CVD, MBE, PLD, or ALD. For example, silicon nitride (see reference) is preferably formed by sputtering as the insulating film that becomes insulator 281. Figures 11A to 11C ).

[0306] Next, openings leading to conductors 242a and 242b are formed in insulators 272, 273, 280, 282, 274, and 281. These openings are formed using photolithography.

[0307] Next, an insulating film that becomes insulator 241 is formed, and the insulating film is anisotropically etched to form insulator 241. This insulating film can be formed using sputtering, CVD, MBE, PLD, or ALD methods. As the insulating film that becomes insulator 241, it is preferable to use an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide or silicon nitride is preferably formed by ALD. Furthermore, anisotropic etching, for example, dry etching, can be performed. By giving the sidewall portion of the opening this structure, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed next can be prevented. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from conductors 240a and 240b to the outside.

[0308] Next, conductive films serving as conductors 240a and 240b are formed. The conductive films serving as conductors 240a and 240b are preferably multilayer structures containing conductors that suppress the permeation of impurities such as water and hydrogen. For example, they can be multilayers of tantalum nitride, titanium nitride, tungsten, molybdenum, copper, etc. The conductive film serving as conductor 240 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0309] Next, a portion of the conductive film that forms conductors 240a and 240b is removed by CMP processing, exposing the insulator 281. As a result, the conductive film remains only at the aforementioned opening, thereby forming conductors 240a and 240b with flat top surfaces (see reference). Figures 1A to 1C Note that sometimes a portion of insulator 281 is removed due to this CMP process.

[0310] Next, a conductive film is formed to become a conductor 246. The conductive film to become a conductor 246 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0311] Next, the conductive film that becomes the conductor 246 is processed by photolithography to form conductor 246a, which is in contact with the top surface of conductor 240a, and conductor 246b, which is in contact with the top surface of conductor 240b (see reference). Figures 1A to 1C ).

[0312] Through the above processes, it is possible to manufacture including Figures 1A to 1C The semiconductor device shown is transistor 200. (As shown) Figures 4A to 11C As shown, transistor 200 can be manufactured by using the semiconductor device manufacturing method shown in this embodiment.

[0313] According to one aspect of the present invention, a semiconductor device with a large on-state current can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high frequency characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with a small off-state current can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high productivity can be provided.

[0314] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and other examples.

[0315] (Implementation Method 2)

[0316] In this embodiment, refer to Figure 16 and Figure 17 One way to describe a semiconductor device.

[0317] [Storage Device 1]

[0318] Figure 16 An example of a memory device using a semiconductor device as an embodiment of the present invention is shown. Figure 16 The storage device shown includes transistor 200, transistor 300, and capacitor 100. Transistor 200 is disposed above transistor 300, and capacitor 100 is disposed above both transistor 300 and transistor 200. Furthermore, transistor 200 can be any type of transistor as described in the above embodiment.

[0319] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because transistor 200 has a small off-state current, it can retain stored content for a long time when used in a storage device. In other words, since refresh operations are not required or occur at extremely low frequencies, the power consumption of the storage device can be significantly reduced.

[0320] exist Figure 16 In the semiconductor device shown, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Additionally, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100.

[0321] In addition, by Figure 16 The storage devices shown are configured in a matrix shape, which can form a storage cell array.

[0322] <Transistor 300>

[0323] Transistor 300 is disposed on substrate 311 and includes: a conductor 316 serving as a gate electrode, an insulator 315 serving as a gate insulator, a semiconductor region 313 formed by a portion of substrate 311; and low-resistance regions 314a and 314b serving as source or drain regions. Transistor 300 may be p-channel or n-channel.

[0324] Here, in Figure 16In the transistor 300 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductor 316 is provided such that it covers the side and top surfaces of the semiconductor region 313 with an insulator 315 in between. The conductor 316 can be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 300 is also called a FIN-type transistor. Alternatively, an insulator used to form a mask for the convex portion can be provided in contact with the upper surface of the convex portion. Furthermore, although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0325] Notice, Figure 16 The structure of transistor 300 shown is just an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0326] <Capacitor 100>

[0327] The capacitor 100 is disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric.

[0328] Alternatively, conductors 112 and 110 may be formed simultaneously on conductor 246. Additionally, conductor 112 serves as a plug or wiring for electrical connection to capacitor 100, transistor 200, or transistor 300.

[0329] exist Figure 16 In this embodiment, conductors 112 and 110 have a single-layer structure, but are not limited to this structure and may also have a stacked structure of two or more layers. For example, a conductor with high density between the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0330] In addition, the insulator 130 may be made of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, hafnium nitride, etc., and may be provided in a stacked or single layer.

[0331] For example, the insulator 130 preferably uses a multilayer structure of materials with high dielectric strength, such as silicon oxynitride, and materials with high dielectric constant (high-k). By adopting this structure, the capacitor 100 can include an insulator with high dielectric constant (high-k) to ensure sufficient capacitance, and can include an insulator with high dielectric strength to improve dielectric strength, thereby suppressing electrostatic damage to the capacitor 100.

[0332] Note that insulators that are high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0333] On the other hand, materials with high dielectric strength (relatively low dielectric constant) include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide or resin with pores.

[0334] <Wiring Layer>

[0335] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be provided depending on the design. Here, in conductive bodies that function as plugs or wiring, multiple structures are sometimes represented by the same reference numeral. Furthermore, in this specification, wiring and plugs electrically connected to wiring can also be considered as a single component. That is, a portion of the conductive body is sometimes used as wiring, and a portion of the conductive body is sometimes used as a plug.

[0336] For example, in transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductors 328 and 330, which are electrically connected to capacitor 100 or transistor 200, are embedded within insulators 320, 322, 324, and 326. Additionally, conductors 328 and 330 are used as connectors or wiring.

[0337] Furthermore, the insulator used as an interlayer film can be used as a planarization film covering the uneven shape beneath it. For example, to improve the flatness of the top surface of insulator 322, planarization can also be achieved by using a planarization process such as chemical mechanical polishing (CMP).

[0338] A wiring layer can also be provided on the insulator 326 and the conductor 330. For example, in Figure 16 In the structure, insulators 350, 352, and 354 are stacked sequentially. Furthermore, a conductor 356 is formed within insulators 350, 352, and 354. The conductor 356 serves as a plug or wiring.

[0339] Similarly, conductors 218 and conductors constituting transistor 200 are filled in insulators 210, 212, 214, and 216. Furthermore, conductors 218 serve as plugs or wiring for electrical connection with capacitor 100 or transistor 300. Moreover, insulators 150 are provided on conductors 120 and insulators 130.

[0340] Insulators that can be used as interlayer films include oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, all of which possess insulating properties.

[0341] For example, by using a material with a low relative permittivity as an insulator for use as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0342] For example, insulators with a low relative permittivity are preferably used for insulators 150, 212, 352, and 354. For example, the insulator preferably contains silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-containing silicon oxide, silicon oxide with carbon and nitrogen, porous silicon oxide, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-containing silicon oxide, silicon oxide with carbon and nitrogen, or porous silicon oxide and resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure with thermal stability and a low relative permittivity can be achieved. Examples of resins include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, or acrylics.

[0343] Furthermore, by surrounding the transistor using an oxide semiconductor with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, it is sufficient to use an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, such as insulator 210 and insulator 350.

[0344] As an insulator that suppresses impurities such as hydrogen and oxygen permeation, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used, either as a single layer or in layers. Specifically, as an insulator that suppresses impurities such as hydrogen and oxygen permeation, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, as well as silicon oxynitride or silicon nitride, can be used.

[0345] As a conductor suitable for wiring and plugs, it is preferable to use a material containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. Alternatively, highly conductive semiconductors such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0346] For example, conductors 328, 330, 356, 218, and 112 can be made of conductive materials such as metallic materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above-mentioned materials, either in a single layer or in layers. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred, with tungsten being particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0347] <Wires or connectors with oxide semiconductor layers>

[0348] Note that when an oxide semiconductor is used in a transistor 200, an insulator with an excess oxygen region is sometimes provided near the oxide semiconductor. In this case, it is preferable to provide a barrier insulator between the insulator with the excess oxygen region and the conductor provided in the insulator with the excess oxygen region.

[0349] For example, in Figure 16 Preferably, an insulator 276 is disposed between the insulator 224, which has excess oxygen, and the conductor 245. By displacing the insulator 276 in contact with insulators 222, 272, and 273, the insulator 224 and the transistor 200 can have a structure sealed by a barrier insulator. Furthermore, the insulator 276 is preferably in contact with the insulator 280. By employing this structure, the diffusion of oxygen and impurities can be further suppressed.

[0350] In other words, by providing insulator 276, the absorption of excess oxygen in insulator 224 by conductor 245 can be suppressed. Furthermore, by having insulator 276, the diffusion of hydrogen as an impurity through conductor 245 into transistor 200 can be suppressed.

[0351] Furthermore, as the insulator 276, an insulating material with the function of suppressing the diffusion of impurities such as water or hydrogen and oxygen is preferably used. For example, aluminum oxide or hafnium oxide is preferred. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, silicon oxynitride or silicon nitride can also be used.

[0352] The above is an explanation of the structural examples. By adopting this structure, reliability can be improved while suppressing electrical characteristic variations in semiconductor devices using transistors containing oxide semiconductors. Furthermore, a transistor containing an oxide semiconductor with a large on-state current can be provided. Additionally, a transistor containing an oxide semiconductor with a small off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0353] [Storage Device 2]

[0354] Figure 17 An example of a memory device using a semiconductor device as an embodiment of the present invention is shown. Figure 17 The storage device shown includes, in addition to Figure 16 In addition to the semiconductor devices shown, transistors 200, 300, and capacitor 100, transistor 400 is also included.

[0355] Transistor 400 can control the second gate voltage of transistor 200. For example, a structure can be adopted in which the first and second gates of transistor 400 are connected to a source diode, and the source of transistor 400 is connected to the second gate of transistor 200. When the second gate of transistor 200 is maintained at a negative potential in this structure, the voltage between the first gate and source of transistor 400 and the voltage between the second gate and source of transistor 400 become 0V. In transistor 400, since the drain current is very small when the second gate voltage and the first gate voltage are 0V, the negative potential of the second gate of transistor 200 can be maintained for a long time even when no power is supplied to transistors 200 and 400. Therefore, a storage device including transistors 200 and 400 can retain stored content for a long period.

[0356] Therefore, in Figure 17 In this configuration, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100. Wiring 1007 is electrically connected to the source of transistor 400, wiring 1008 is electrically connected to the first gate of transistor 400, wiring 1009 is electrically connected to the second gate of transistor 400, and wiring 1010 is electrically connected to the drain of transistor 400. Wiring 1006, 1007, 1008, and 1009 are also electrically connected.

[0357] In addition, by Figure 17The storage device shown is Figure 16 The illustrated memory device is also configured in a matrix shape, which can form a memory cell array. Note that one transistor 400 can control the second gate voltage of multiple transistors 200. Therefore, it is preferable that the number of transistors 400 is less than the number of transistors 200.

[0358] <Transistor 400>

[0359] Transistor 400 is formed on the same layer as transistor 200, thereby allowing them to be manufactured simultaneously. Transistor 400 includes: conductors 460 (conductors 460a and 460b) serving as a first gate electrode; conductor 405 serving as a second gate electrode; insulators 222, 224, and 450 serving as a gate insulating layer; oxide 430c including a region forming a channel; conductors 442a, oxides 443a, 432a, and 432b serving as one of the source and drain electrodes; conductors 442b, oxides 443b, 431a, and 431b serving as the other of the source and drain electrodes; and conductor 440 (conductors 440a and 440b).

[0360] In transistor 400, conductor 405 and conductor 205 are the same layer. Oxides 431a and 432a are the same layer as oxide 230a, and oxides 431b and 432b are the same layer as oxide 230b. Conductors 442a and 442b are the same layer as conductor 242. Oxides 443a and 443b are the same layer as oxide 243. Oxide 430c and oxide 230c are the same layer. Insulator 450 and insulator 250 are the same layer. Conductor 460 and conductor 260 are the same layer.

[0361] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing oxide film 230c.

[0362] Similar to oxide 230, the oxide 430c used as the active layer of transistor 400 has fewer oxygen vacancies and impurities such as hydrogen or water. Therefore, the threshold voltage of transistor 400 can be greater than 0V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are both 0V can be made very small.

[0363] <cut line>

[0364] The following describes the dicing lines (also called dividing lines, severing lines, or cut-off lines) used when dividing a large-area substrate into multiple semiconductor devices in the shape of a chip by dividing each semiconductor element. As a dicing method, for example, sometimes a groove (dicing line) for dividing the semiconductor element is first formed in the substrate, and then the substrate is cut off at the dicing line to obtain multiple semiconductor devices that have been divided (segmented).

[0365] Here, for example, such as Figure 17 As shown, it is preferable to design the area in contact with insulator 272 and insulator 222 as a cut line. That is, an opening is provided in insulator 224 near the area that forms a cut line, which is located at the edge of the memory cell including multiple transistors 200 and transistor 400. Furthermore, insulator 272 is provided to cover the side of insulator 224.

[0366] In other words, insulator 222 contacts insulator 272 within the opening provided in insulator 224. For example, insulator 222 and insulator 272 can be formed using the same material and the same method. Using the same material and the same method to form insulator 222 and insulator 272 improves the tightness of the seal. For example, alumina is preferably used.

[0367] By employing this structure, insulators 222 and 272 can surround insulator 224, transistor 200, and transistor 400. Since insulators 222 and 272 have the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips according to the circuit region where semiconductor elements are formed, as shown in this embodiment, impurities such as hydrogen or water can be prevented from mixing in and diffusing into transistor 200 and transistor 400 from the side direction of the truncated substrate.

[0368] By employing this structure, excess oxygen in insulator 224 can be prevented from diffusing to insulator 272 and the exterior of insulator 222. Therefore, excess oxygen in insulator 224 is efficiently supplied to the oxide forming the channel in transistor 200 or transistor 400. This oxygen reduces oxygen vacancies in the oxide forming the channel in transistor 200 or transistor 400. Consequently, the oxide forming the channel in transistor 200 or transistor 400 can become an oxide semiconductor with low defect state density and stable characteristics. In other words, reliability can be improved while suppressing variations in the electrical characteristics of transistor 200 or transistor 400.

[0369] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and other examples.

[0370] (Implementation Method 3)

[0371] In this embodiment, refer to Figures 18A to 19H The following describes a storage device (hereinafter sometimes referred to as an OS storage device) using an oxide-based semiconductor transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor, according to one embodiment of the present invention. An OS storage device is a storage device comprising at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Because the off-state current of an OS transistor is extremely small, an OS storage device has excellent retention characteristics and can therefore be used as a non-volatile memory.

[0372] <Example of storage device structure>

[0373] Figure 18A An example of the structure of an OS storage device is shown. Storage device 1400 includes peripheral circuitry 1411 and a storage cell array 1470. Peripheral circuitry 1411 includes row circuitry 1420, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460.

[0374] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is the wiring connected to the memory cells included in the memory cell array 1470, and its details are described below. The amplified data signal, as the data signal RDATA, is output to the outside of the memory device 1400 via the output circuit 1440. Furthermore, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to be accessed.

[0375] The storage device 1400 is supplied with a low power supply voltage (VSS), the peripheral circuit 1411 is supplied with a high power supply voltage (VDD), and the memory cell array 1470 is supplied with a high power supply voltage (VIL). In addition, the storage device 1400 receives external control signals (CE, WE, RE), address signals ADDR, and data signals WDATA. The address signal ADDR is input to the row decoder and column decoder, and WDATA is input to the write circuit.

[0376] The control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row and column decoders. CE is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other input signals can be processed as needed to generate control signals for the row or column decoder.

[0377] The memory cell array 1470 includes a plurality of memory cells MCs configured in a row and column configuration and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a column, etc. Furthermore, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a row, etc.

[0378] In addition, although Figure 18A An example is shown where the peripheral circuitry 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited thereto. For example, as Figure 18B As shown, the memory cell array 1470 can also be arranged overlapping a portion of the peripheral circuitry 1411. For example, the readout amplifier can also be arranged overlapping the memory cell array 1470.

[0379] exist Figures 19A to 19H The text describes a structural example of a memory cell that can be applied to the aforementioned memory cell MC.

[0380] [DOSRAM]

[0381] Figures 19A to 19C An example of the circuit structure of a DRAM memory cell is shown. In this specification and other materials, DRAM using a 1000 transistors and 1 capacitor type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Figure 19A The memory cell 1471 shown includes a transistor M1 and a capacitor CA. Additionally, the transistor M1 includes a gate (sometimes referred to as the front gate) and a back gate.

[0382] The first terminal of transistor M1 is connected to the first terminal of capacitor CA. The second terminal of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor CA is connected to wiring CAL.

[0383] Wiring BIL is used as the bit line, and wiring WOL is used as the word line. Wiring CAL is used to supply a specified potential to the second terminal of capacitor CA. During data writing and reading, it is preferable to supply a low-level potential to wiring CAL. Wiring BGL is used to supply a potential to the back gate of transistor M1. By supplying any potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0384] Furthermore, the memory cell MC is not limited to memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also adopt... Figure 19B The transistor M1 in the illustrated memory cell 1472 has a back gate that is connected to the wiring WOL instead of the wiring BGL. Alternatively, for example, the memory cell MC could also be as follows: Figure 19C The memory cell shown, 1473, is a memory cell composed of a single-gate transistor M1, i.e., a transistor M1 excluding the back gate.

[0385] When the semiconductor device shown in the above embodiment is used in memory cell 1471, transistor 200 can be used as transistor M1, and capacitor 100 can be used as capacitor CA. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be minimized. In other words, since the written data can be held by transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, the memory cell refresh operation can be eliminated. In addition, since the leakage current is minimal, multi-valued data or analog data can be stored in memory cells 1471, 1472, and 1473.

[0386] Furthermore, in DOSRAM, when the read amplifier is arranged in a manner overlapping the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance, thereby reducing the storage capacitance of the memory cells.

[0387] [NOSRAM]

[0388] Figures 19D to 19H This illustrates an example of a gain-cell type memory cell with 2 transistors and 1 capacitor. Figure 19D The memory cell 1474 shown includes transistor M2, transistor M3, and capacitor CB. Additionally, transistor M2 includes a front gate (sometimes simply referred to as the gate) and a back gate. In this specification and the like, a memory device including a gain-cell type memory cell that uses an OS transistor for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0389] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; transistor M2's gate is connected to wiring WOL; and transistor M2's back gate is connected to wiring BGL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0390] Wiring WBL is used as the write bit line, wiring RBL is used as the read bit line, and wiring WOL is used as the word line. Wiring CAL is used to supply a specified potential to the second terminal of capacitor CB. It is preferable to supply a low-level potential to wiring CAL during data writing, holding, and reading. Wiring BGL is used to supply a potential to the back gate of transistor M2. By supplying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0391] Furthermore, the memory cell MC is not limited to memory cell 1474, and its circuit structure can be appropriately modified. For example, the memory cell MC can also adopt... Figure 19E The transistor M2 in the illustrated memory cell 1475 has its back gate connected to the wiring BGL, but not to the wiring WOL. Alternatively, the memory cell MC could also be, for example, as... Figure 19F The memory cell 1476 shown is a memory cell composed of a single-gate transistor M2, i.e., a transistor M2 excluding the back gate. Furthermore, for example, the memory cell MC may also have... Figure 19G The storage cell 1477 shown has a structure that combines wiring WBL and wiring RBL into a wiring BIL.

[0392] When the semiconductor device shown in the above embodiment is used in memory cell 1474, transistor 200 can be used as transistor M2, transistor 300 can be used as transistor M3, and capacitor 100 can be used as capacitor CB. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be minimized. Therefore, since the written data can be held by transistor M2 for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, memory cell refresh operations can be eliminated. Moreover, due to the minimal leakage current, multi-valued data or analog data can be stored in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0393] Alternatively, transistor M3 can also be a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of a Si transistor can be n-channel or p-channel. The field-effect mobility of a Si transistor is sometimes higher than that of an OS transistor. Therefore, a Si transistor can also be used as the readout transistor for transistor M3. Furthermore, by using a Si transistor for transistor M3, transistor M2 can be stacked on top of transistor M3, thereby reducing the footprint of the memory cell and enabling high integration of the memory device.

[0394] Furthermore, transistor M3 can also be an OS transistor. When OS transistors are used for transistors M2 and M3, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0395] in addition, Figure 19H An example of a gain-cell type memory cell with 3 transistors and 1 capacitor is shown. Figure 19H The illustrated memory cell 1478 includes transistors M4 to M6 and capacitor CC. Capacitor CC can be appropriately configured. Memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. Wiring GNDL is a wiring that supplies a low-level potential. Alternatively, memory cell 1478 can be electrically connected to wirings RBL and WBL without being electrically connected to wiring BIL.

[0396] Transistor M4 is an OS transistor that includes a back gate, which is electrically connected to wiring BGL. Alternatively, the back gate and gate of transistor M4 can be electrically connected to each other. Or, transistor M4 may not include a back gate.

[0397] Alternatively, transistors M5 and M6 can each be either n-channel or p-channel Si transistors. Or, transistors M4 through M6 can all be OS transistors. In this case, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0398] When the semiconductor device shown in the above embodiment is used in the memory cell 1478, transistor 200 can be used as transistor M4, transistor 300 can be used as transistors M5 and M6, and capacitor 100 can be used as capacitor CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be minimized.

[0399] Note that the structure of the peripheral circuit 1411 and the memory cell array 1470 shown in this embodiment is not limited to the structure described above. The configuration or function of these circuits and the wiring and circuit elements connected to them can be changed, removed, or added as needed.

[0400] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and other examples.

[0401] (Implementation Method 4)

[0402] In this embodiment, refer to Figure 20A and Figure 20BAn example of a chip 1200 in which the semiconductor device of the present invention is mounted is described. Multiple circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating multiple circuits (systems) on a single chip is sometimes referred to as a System on Chip (SoC).

[0403] like Figure 20A As shown, the chip 1200 includes a central processing unit (CPU) 1211, a graphics processing unit (GPU) 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0404] A bump (not shown) is provided on chip 1200, and the bump is as follows: Figure 20B It is connected to the first side of the printed circuit board (PCB) 1201 as shown. In addition, a plurality of bumps 1202 are provided on the back side of the first side of the PCB 1201, which are connected to the motherboard 1203.

[0405] Alternatively, storage devices such as DRAM 1221 and flash memory 1222 can be provided on the motherboard 1203. For example, the DOSRAM shown in the above embodiment can be applied to the DRAM 1221. Furthermore, for example, the NOSRAM shown in the above embodiment can be applied to the flash memory 1222.

[0406] CPU 1211 preferably has multiple CPU cores. Furthermore, GPU 1212 preferably has multiple GPU cores. Additionally, CPU 1211 and GPU 1212 may each have a memory for temporary data storage. Alternatively, a memory shared by CPU 1211 and GPU 1212 may be provided on chip 1200. The aforementioned NOSRAM or DOSRAM can be used in this memory. Furthermore, GPU 1212 is suitable for parallel computation of multiple data sets, and can be used for image processing or product operations. By incorporating an image processing circuit or product operation circuit using the oxide semiconductor of the present invention as GPU 1212, image processing and product operations can be performed with low power consumption.

[0407] Furthermore, since the CPU1211 and GPU1212 are located on the same chip, the wiring between the CPU1211 and GPU1212 can be shortened, and data transfer from the CPU1211 to the GPU1212, data transfer between the memory of the CPU1211 and GPU1212, and transfer of the operation result from the GPU1212 to the CPU1211 after the operation in the GPU1212 is completed can be performed at high speed.

[0408] The analog arithmetic unit 1213 includes one or both of an analog-to-digital (A / D) conversion circuit and a digital-to-analog (D / A) conversion circuit. Alternatively, the aforementioned product summation circuit may also be provided in the analog arithmetic unit 1213.

[0409] The storage controller 1214 has circuitry that serves as a controller for the DRAM 1221 and circuitry that serves as an interface for the flash memory 1222.

[0410] Interface 1215 has interface circuitry for connecting to external devices such as display devices, speakers, microphones, video recording devices, and controllers. Controllers include mice, keyboards, and game console controllers. Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI) (registered trademark), etc., can be used as the aforementioned interface.

[0411] Network circuit 1216 includes network circuits such as local area network (LAN). Additionally, it may include network security circuits.

[0412] The aforementioned circuit (system) can be formed on chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, no additional manufacturing process is required, and chip 1200 can be manufactured at low cost.

[0413] The motherboard 1203, which includes a PCB 1201 with a chip 1200 having a GPU 1212, a DRAM 1221, and a flash memory 1222, can be referred to as a GPU module 1204.

[0414] The GPU module 1204 can reduce its size due to the presence of the chip 1200 using SoC technology. Furthermore, the GPU module 1204, with its high image processing capabilities, is suitable for use in portable electronic devices such as smartphones, tablets, laptops, and portable game consoles. Moreover, by utilizing the product-sum operation circuitry of the GPU 1212, operations such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN) can be performed. Therefore, the chip 1200 can be used as an AI chip, or the GPU module can be used as an AI system module.

[0415] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and other examples.

[0416] (Implementation Method 5)

[0417] In this embodiment, an application example of a storage device using the semiconductor device described in the above embodiments is explained. The semiconductor device described in the above embodiments can be applied, for example, to the storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book reader terminals, digital cameras (including camcorders), video recording devices, navigation systems, etc.). Note that here, "computer" includes tablet computers, notebook computers, desktop computers, and mainframe computers such as server systems. Alternatively, the semiconductor device described in the above embodiments can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB storage devices, and SSDs (solid-state drives). Figures 21A to 21E Several structural examples of removable storage devices are illustrated schematically. For example, the semiconductor devices shown in the above embodiments are fabricated into packaged memory chips and used in various storage devices or removable memories.

[0418] Figure 21A This is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed within the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device shown in the above embodiment can be assembled onto the substrate 1104, such as the memory chip 1105.

[0419] Figure 21B This is a schematic diagram of the SD card's appearance. Figure 21C This is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed within the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 1113. Thus, through wireless communication between the host device and the SD card 1110, data can be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be mounted on the substrate 1113, such as the memory chip 1114.

[0420] Figure 21D This is a schematic diagram of the SSD's appearance. Figure 21EThis is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor devices shown in the above embodiment can be assembled onto the memory chip 1154 on the substrate 1153.

[0421] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and other examples.

[0422] (Implementation Method 6)

[0423] In this embodiment, refer to Figures 22A to 22D , Figure 22E1 , Figure 22E2 as well as Figure 22F Specific examples of electronic devices in which a semiconductor device can be used according to one aspect of the present invention will be described.

[0424] More specifically, a semiconductor device according to one aspect of the present invention can be applied to processors or chips such as CPUs and GPUs. Figures 22A to 22D , Figure 22E1 , Figure 22E2 as well as Figure 22F Specific examples of electronic devices having a processor or chip such as a CPU or GPU according to one aspect of the present invention are shown.

[0425] <Electronic Devices and Systems>

[0426] The GPU or chip according to one aspect of the present invention can be installed in a wide variety of electronic devices. Examples of electronic devices include, in addition to television sets, desktop or laptop personal computers, monitors for computers, digital signage, and large game consoles such as pinball machines, which have large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices. Furthermore, by incorporating an integrated circuit or chip according to one aspect of the present invention into an electronic device, the electronic device can possess artificial intelligence.

[0427] An electronic device according to one aspect of the present invention may also include an antenna. By receiving signals through the antenna, images or information can be displayed on a display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0428] An electronic device according to one aspect of the present invention may also include a sensor (the sensor having the function of measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0429] An electronic device according to one aspect of the present invention can have various functions. For example, it can have the following functions: displaying various information (static images, animated images, text images, etc.) on a display unit; a touch panel; displaying a calendar, date, or time; executing various software (programs); performing wireless communication; reading programs or data stored in a storage medium; etc. Figures 22A to 22D , Figure 22E1 , Figure 22E2 as well as Figure 22F Examples of electronic devices are shown.

[0430] [Mobile phone]

[0431] Figure 22A A mobile phone (smartphone) is shown as one of the information terminals. The information terminal 5500 includes a housing 5510 and a display unit 5511. The display unit 5511 has a touch panel as an input interface, and buttons are provided on the housing 5510.

[0432] By applying a chip according to one aspect of the present invention to an information terminal 5500, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include applications that identify a session and display the content of that session on a display unit 5511, applications that identify text or graphics input by a user to a touch panel provided with the display unit 5511 and display that text or graphics on the display unit 5511, and applications that perform biometric identification such as fingerprints or voiceprints.

[0433] [Information Terminal 1]

[0434] Figure 22B The desktop information terminal 5300 is shown. The desktop information terminal 5300 includes an information terminal body 5301, a display 5302, and a keyboard 5303.

[0435] Similar to the aforementioned information terminal 5500, by applying a chip according to one aspect of the present invention to the desktop information terminal 5300, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include design support software, document proofreading software, and automatic menu generation software. Furthermore, by using the desktop information terminal 5300, novel artificial intelligence technologies can be developed.

[0436] Note that in the example above, Figure 22A and Figure 22B Examples of smartphones and desktop information terminals as electronic devices are shown, but one aspect of the invention can also be applied to information terminals other than smartphones and desktop information terminals. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), laptop information terminals, workstations, etc.

[0437] [Electrical Products]

[0438] Figure 22C An example of an electrical appliance is shown: an electric refrigerator / freezer 5800. The electric refrigerator / freezer 5800 includes an outer casing 5801, a refrigerator door 5802, and a freezer door 5803, etc.

[0439] By applying a chip according to one aspect of the present invention to an electric refrigerator / freezer 5800, an electric refrigerator / freezer 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator / freezer 5800 can automatically generate menus based on the food stored in the electric refrigerator / freezer 5800 or the shelf life of the food, and automatically adjust the temperature of the electric refrigerator / freezer 5800 according to the stored food.

[0440] In the above example, the electric refrigerator / freezer is described as an electrical appliance. However, other electrical appliances could include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners (including air conditioners with heating and cooling), washing machines, dryers, and audio-visual equipment.

[0441] [Game console]

[0442] Figure 22D A portable game console 5200 is shown as an example of a game console. The portable game console 5200 includes a casing 5201, a display unit 5202, and buttons 5203, etc.

[0443] By applying a GPU or chip according to one aspect of the present invention to a portable game console 5200, a low-power portable game console 5200 can be realized. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat generation on the circuitry itself, peripheral circuitry, and modules.

[0444] Furthermore, by applying a GPU or chip according to one aspect of the present invention to a portable game console 5200, a portable game console 5200 with artificial intelligence can be realized.

[0445] The progress of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are normally governed by the game's programming. However, by applying artificial intelligence to the portable game console 5200, it is possible to achieve performances that are not limited to the game's programming. For example, it is possible to display the content of the player's questions, the progress of the game, the time elapsed, and changes in the behavior of characters appearing in the game.

[0446] Furthermore, when playing games that require multiple players using the portable game console 5200, artificial intelligence can be used to create human-like game players. This allows one person to play a game that requires multiple players, and thus, one person can also play a game that requires multiple players.

[0447] Although Figure 22D A portable game console is shown as an example of a game console, but game consoles using GPUs or chips that apply one aspect of the present invention are not limited to this. Examples of game consoles using GPUs or chips that apply one aspect of the present invention include home consoles, arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.), and ball-shooting practice machines installed in sports facilities.

[0448] [Moving Object]

[0449] One embodiment of the present invention, the GPU or chip, can be applied to a car as a moving body and the area around the driver's seat of the car.

[0450] Figure 22E1 The diagram shows an example of a moving object, a car 5700. Figure 22E2 It is a diagram showing the area around the windshield inside a car. Figure 22E2 Display panels 5701, 5702, and 5703 are shown mounted on the dashboard, and display panel 5704 is mounted on the support column.

[0451] Display panels 5701 to 5703 can provide speedometer, tachometer, driving distance, fuel level, gear position, air conditioning settings, and various other information. Furthermore, users can customize the displayed content and layout according to their preferences, enhancing design flexibility. Display panels 5701 to 5703 can also be used as lighting devices.

[0452] By displaying images captured by a camera (not shown) installed on the vehicle 5700 on the display panel 5704, blind spots (obstructions to the view) can be filled. In other words, by displaying images captured by a camera installed on the exterior of the vehicle 5700, blind spots can be filled, thereby improving safety. Furthermore, by displaying images that fill in unseen areas, safety can be confirmed more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

[0453] Because the GPU or chip of one aspect of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in the autonomous driving system of a car 5700. The chip can also be used in systems for navigation, hazard prediction, etc. Furthermore, navigation, hazard prediction, and other information can be displayed on display panels 5701 to 5704.

[0454] While the automobile was used as an example of a mobile body in the above example, mobile bodies are not limited to automobiles. For example, trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets) can also be cited as mobile bodies, and the chip of one aspect of the present invention can be applied to these mobile bodies to provide a system utilizing artificial intelligence.

[0455] [Broadcasting and Television System]

[0456] One embodiment of the present invention, the GPU or chip, can be applied to broadcast television systems.

[0457] Figure 22F This illustration schematically depicts data transmission in a broadcast television system. Specifically, Figure 22F The diagram illustrates the path of radio waves (broadcast television signals) transmitted from broadcast television station 5680 to television receivers (TV) 5600 in each household. TV 5600 includes a receiver (not shown) through which broadcast television signals received by antenna 5650 are input to TV 5600.

[0458] Although Figure 22F The diagram shows an ultra-high frequency (UHF) antenna as antenna 5650, but BS, 110-degree CS antennas, CS antennas, etc. can be used as antenna 5650.

[0459] Radio waves 5675A and 5675B are terrestrial broadcast television signals. Radio tower 5670 amplifies the received radio wave 5675A and transmits radio wave 5675B. Individual households can receive radio wave 5675B using antenna 5650 and then watch terrestrial television broadcasts on TV 5600. Furthermore, the broadcast television system can be used for satellite broadcasting via artificial satellites, data broadcasting via optical routes, and is not limited to these methods. Figure 22F The image shows terrestrial broadcast television.

[0460] Furthermore, the chip according to one aspect of the present invention can also be applied to the aforementioned broadcast television system to realize a broadcast television system utilizing artificial intelligence. When broadcast television data is transmitted from broadcast television station 5680 to TV 5600 in each household, the broadcast television data is compressed using an encoder; when the antenna 5650 receives the broadcast television data, the broadcast television data is recovered using a decoder included in the TV 5600. By utilizing artificial intelligence, for example, the display model contained in the displayed image can be identified in variation compensation prediction, one of the compression methods of the encoder. In addition, intra-frame prediction using artificial intelligence can also be performed. For example, when TV 5600 receives low-resolution broadcast television data and displays it at high resolution, supplementary image processing such as upconversion can be performed during the recovery of the broadcast television data by the decoder.

[0461] The aforementioned broadcast television system utilizing artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting, which involves larger amounts of broadcast television data.

[0462] Furthermore, as an application of artificial intelligence on the TV5600 side, for example, an AI-enabled recording device can be installed within the TV5600. By adopting this structure, the AI-enabled recording device can learn the user's preferences and automatically record television programs that match those preferences.

[0463] The electronic device described in this embodiment, its functions, examples of artificial intelligence applications, and their effects can be implemented by appropriately combining them with descriptions of other electronic devices.

[0464] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and other examples.

[0465] [Example 1]

[0466] In this embodiment, the sheet resistance of a laminate formed by depositing a conductor on an oxide layer is measured. Tantalum nitride is used as the conductor on the oxide layer, and the sheet resistance of tantalum nitride is measured. The sample used for the measurement is described.

[0467] First, the manufacturing method of sample A is described. Under a hydrogen chloride (HCl) atmosphere, the surface of a silicon-containing substrate is heat-treated to form a silicon oxide film with a thickness of 100 nm. Next, a silicon oxynitride film with a thickness of 300 nm is formed on the silicon oxide film using CVD. Furthermore, oxygen is implanted into the silicon oxynitride film using ion implantation, so that the silicon oxynitride film can be used as an oxygen supply film. Next, a first oxide film with a thickness of 5 nm is formed on the silicon oxynitride film using a sputtering target with an In:Ga:Zn ratio of 4:2:4.1 [atomic ratio]. Then, a tantalum nitride film with a thickness of 5 nm is formed on the first oxide film using sputtering. The tantalum nitride film is formed at room temperature using a target containing Ta under an atmosphere containing argon and nitrogen.

[0468] Next, sample B will be described. As for sample B, a sample with a first oxide formed was used in the same manner as sample A. A second oxide with a thickness of 1 nm was formed on the first oxide using a sputtering method with an In:Ga:Zn target of 1:3:4 [atomic ratio]. Then, a tantalum nitride film was formed on the second oxide in the same manner as in sample A.

[0469] Next, sample C will be described. As sample C, a sample with a first oxide formed was used in the same manner as samples A and B. A second oxide with a thickness of 5 nm was formed on the first oxide using a sputtering method with an In:Ga:Zn target of 1:3:4 [atomic ratio]. Then, a tantalum nitride film was formed on the second oxide in the same manner as samples A and B.

[0470] Samples A, B, and C were each divided into eight groups: A1 to A8, B1 to B8, and C1 to C8. The heating temperatures under a nitrogen atmosphere were 150°C and 175°C, and the heating times were none, 1 hour, 10 hours, and 100 hours, for a total of eight conditions. Table 1 summarizes all the sample treatment conditions.

[0471] [Table 1]

[0472]

[0473] Figure 23A and Figure 23B A graph showing the heat treatment time dependence of the resistance of tantalum nitride thin film. Figure 23A This is a chart when the heat treatment temperature is 150℃. Figure 23BThis is a graph showing the results at a heat treatment temperature of 175°C. In all samples, it was confirmed that the longer the heat treatment time, the higher the film resistivity of tantalum nitride. However, in samples B and C, where a second oxide was inserted between the first oxide and tantalum nitride, the increase in film resistivity of tantalum nitride was further suppressed compared to the increase in film resistivity of sample A, which did not have a second oxide inserted. Furthermore, in... Figure 23A At the heating temperature of 150°C, there is no difference in the increase of tantalum nitride sheet resistance between sample B, with a second oxide thickness of 1 nm, and sample C, with a second oxide thickness of 5 nm. Figure 23B When the heating temperature shown is 175°C, the following results are obtained: compared with sample B with a second oxide thickness of 1 nm, the increase in the thin film resistance of tantalum nitride in sample C with a second oxide thickness of 5 nm is further suppressed.

[0474] This embodiment can be implemented in appropriate combination with other embodiments and the structures and methods shown in other embodiments.

[0475] [Example 2]

[0476] In this embodiment, the sheet resistance in the depth direction of the oxide layer of a stacked body formed by depositing a conductor on an oxide layer is measured. The sample used for the measurement is described.

[0477] First, the manufacturing method of sample D is described. A quartz substrate is prepared, and a first oxide with a thickness of 500 nm is formed on the quartz substrate by sputtering using a target material with an In:Ga:Zn ratio of 4:2:4.1 [atomic number ratio]. Then, it is heated at 400°C for 1 hour under a nitrogen atmosphere, followed by a heating treatment at 400°C for 1 hour under an oxygen atmosphere.

[0478] Next, a tantalum nitride film with a thickness of 20 nm was formed on the first oxide by sputtering. The tantalum nitride film was formed at room temperature using a target containing Ta in an atmosphere containing argon and nitrogen.

[0479] Next, sample E will be described. As sample E, a sample with a first oxide formed was used in the same manner as sample D described above. A second oxide with a thickness of 1 nm was formed on the first oxide using a sputtering target with an In:Ga:Zn ratio of 1:3:4 [atomic ratio]. Then, a heat treatment was performed at 400°C for 1 hour under a nitrogen atmosphere, followed by a heat treatment at 400°C for 1 hour under an oxygen atmosphere.

[0480] Next, a tantalum nitride film with a thickness of 20 nm was formed on the first oxide by sputtering. The tantalum nitride film was formed at room temperature using a target containing Ta in an atmosphere containing argon and nitrogen.

[0481] Next, sample F will be described. As sample F, a sample with a first oxide formed in the same manner as samples D and E described above was used. A second oxide with a thickness of 5 nm was formed on the first oxide using a sputtering target with an In:Ga:Zn ratio of 1:3:4 [atomic ratio]. Then, a heat treatment was performed at 400°C for 1 hour under a nitrogen atmosphere, followed by a heat treatment at 400°C for 1 hour under an oxygen atmosphere.

[0482] Next, a tantalum nitride film with a thickness of 20 nm was formed on the first oxide by sputtering. The tantalum nitride film was formed at room temperature using a target containing Ta in an atmosphere containing argon and nitrogen.

[0483] Samples D, E, and F were each divided into eight groups: samples D1 to D8, samples E1 to E8, and samples F1 to F8. Two conditions were used for heat treatment under a nitrogen atmosphere: 150°C and 175°C. Four conditions were used for heat treatment time: no treatment, 1 hour, 10 hours, and 100 hours. In total, each sample was treated under eight conditions. Table 2 summarizes all the sample treatment conditions.

[0484] [Table 2]

[0485]

[0486] Next, tantalum nitride was removed from each sample using dry etching. Then, the sheet resistance of the first oxide layer was measured for each sample (Step 1). Next, approximately 3 nm of the first oxide layer was etched away (Step 2). Next, the thickness of the remaining film of the first oxide layer was measured (Step 3). This process continued until the sheet resistance exceeded the measurement limit, reaching 6 × 10⁻⁶. 6 Steps 1 to 3 are repeated until Ω / □ is reached. Note that for samples E1 to E8 and F1 to F8, the sheet resistance of the second oxide may be measured in the initial step 1, but this measurement has little impact on the results of this embodiment.

[0487] Figures 24A to 24C as well as Figures 25A to 25C The variation of the resistance of the first oxide film along the depth direction is shown. Figures 24A to 24C This is a graph showing the heat treatment temperature at 150℃. Figure 24A The diagram shows the structure without the second oxide. Figure 24B This is a diagram of the structure of the second oxide with a thickness of 1 nm. Figure 24C This is a diagram of the structure of the second oxide with a thickness of 5 nm. Figures 25A to 25C This is a graph showing the heat treatment temperature at 175℃. Figure 25AThe diagram shows the structure without the second oxide. Figure 25B This is a diagram of the structure of the second oxide with a thickness of 1 nm. Figure 25C This is a diagram of the structure of the second oxide with a thickness of 5 nm.

[0488] from Figures 24A to 24C as well as Figures 25A to 25C It is known that by configuring a 5nm second oxide between the first oxide and the conductor, even after heating at 150°C and 175°C for 1 hour, 10 hours and 100 hours respectively, the development of the low-resistance region of the first oxide in the depth direction is further suppressed compared with the structure without the second oxide.

[0489] This embodiment can be implemented in appropriate combination with other embodiments and the structures and methods shown in other embodiments.

[0490] [Example 3]

[0491] In this embodiment, a sample with an insulating film 250A formed using the method described in "Method for Manufacturing a Semiconductor Device" was examined using a scanning transmission electron microscope (Hitachi HD-2700). Figure 3A The section shown is a cross-sectional observation and analysis using energy dispersive X-ray diffraction (EDX).

[0492] The structures of the manufactured samples are described below. Samples G1 and G2 have a structure without oxide 243 between oxide 230b and conductor 242. Samples H1 and H2 have a structure with oxide 243 disposed between oxide 230b and conductor 242, and the thickness of oxide 243 is 1 nm. Samples I1 and I2 have a structure with oxide 243 disposed between oxide 230b and conductor 242, and the thickness of oxide 243 is 2 nm. Samples J1 and J2 have a structure with oxide 243 disposed between oxide 230b and conductor 242, and the thickness of oxide 243 is 3 nm. All other structures of the samples are the same.

[0493] In this embodiment, oxide 230b is an oxide formed by sputtering using a target with an In:Ga:Zn ratio of 4:2:4.1, and oxide 243 is an oxide formed by sputtering using a target with an In:Ga:Zn ratio of 1:3:4. Furthermore, tantalum nitride formed by sputtering is used as the conductor 242.

[0494] Samples G1, H1, I1, and J1 were heated at 400°C for 4 hours under a nitrogen atmosphere. Samples G2, H2, I2, and J2 were heated at 400°C for 8 hours under a nitrogen atmosphere.

[0495] After the above heat treatment, cross-sectional observations were performed on each sample. As an example, Figure 26 A cross-sectional image of sample J1 is shown. It is confirmed that a stack of oxides 230a, oxide 230b, oxide 243 and conductor 242 is formed on insulator 224.

[0496] Next, EDX linearity analysis was performed on each sample. Figure 26 In the middle, arrows indicate the general analysis sections.

[0497] Figure 27 and Figure 28 This presents a summary of the EDX linear analysis of oxygen and gallium. The interface between the conductor and the oxide, i.e., the distance, is calculated from the distribution of the gallium linear analysis. Figure 27 In the image, the area around 29.1 nm is the interface between the conductor and the oxide. Figure 28 In the image, the area around 28.7 nm is the interface between the conductor and the oxide. Figure 27 These are the results of EDX linear analysis of oxygen and gallium in samples G1, H1, I1, and J1 after a 4-hour heat treatment. Figure 28 The results are from EDX linear analysis of oxygen and gallium in samples G2, H2, I2, and J2 after 8 hours of heat treatment.

[0498] exist Figure 27 Among the samples, regarding the intersection of oxygen distribution and quantitative value = 20 atomic %, sample G1, without oxide 243, had the smallest intersection distance, followed by sample H1 with an oxide 243 thickness of 1 nm, sample I1 with an oxide 243 thickness of 2 nm, and sample J1 with an oxide 243 thickness of 3 nm. This confirms that the greater the thickness of oxide 243, the more oxygen diffusion into the conductor 242 is suppressed. Furthermore, in Figure 28 In the middle, roughly the same tendency was also confirmed.

[0499] The results above show that oxide 243 has the function of inhibiting oxygen diffusion to conductor 242, and the greater the thickness of oxide 243, the more oxygen diffusion to conductor 242 is inhibited.

[0500] This embodiment can be implemented in appropriate combination with other embodiments and the structures and methods shown in other embodiments.

[0501] [Example 4]

[0502] In this embodiment, a sample including transistor 200 is manufactured using the method described in <Method for Manufacturing a Semiconductor Device>, and the reliability of transistor 200 is evaluated. Two types of samples are manufactured: sample K and sample L. The difference between sample K and sample L lies in the substrate temperature at which oxide 243 is formed.

[0503] The oxide 243 formation conditions for sample K were as follows: sputtering; using an In:Ga:Zn target with an atomic ratio of 1:3:4; substrate temperature of 200℃; and a thickness of 2 nm. The oxide 243 formation conditions for sample L were as follows: sputtering; using an In:Ga:Zn target with an atomic ratio of 1:3:4; substrate temperature of 250℃; and a thickness of 2 nm. Both samples J and K were heated at 400℃ for 8 hours under a nitrogen atmosphere.

[0504] Next, the reliability of samples K and L was evaluated. Reliability was assessed using a +GBT (Gate Bias Temperature) stress test. In the +GBT stress test, while heating the substrate, the potentials of conductor 242a (used as the source electrode of the transistor), conductor 242b (used as the drain electrode), and conductor 205 (used as the second gate electrode) were made the same. A higher potential than that supplied to conductors 242a, 242b, and 205 was supplied to conductor 260 (used as the first gate electrode) for a certain period of time.

[0505] In the +GBT stress test of this embodiment, the temperature is set to 150°C, and the drain potential Vd and source potential V are... S and bottom gate potential V BG The voltage is 0V, and the top gate potential is V. G The voltage is +3.63V. Stress tests were performed on two components for samples K and L respectively. The component with a channel length of 60 nm and a channel width of 60 nm (design value) was evaluated.

[0506] In the +GBT stress test, I is performed at regular intervals. D -V G Measurement. In I D -V G During the measurement, the drain potential Vd of the transistor was set to +1.2V, and the source potential Vd was set to +1.2V. S Set to 0V, and set the bottom gate potential V BG Set to 0V, and set the gate potential V G Scan from -3.3V to +3.3V. In I D -V GIn the measurements, a semiconductor parameter analyzer manufactured by Keysight Technologies was used. Furthermore, in the +GBT stress test, ΔVsh, representing the change in drift voltage Vsh from the start of the measurement, was used as an indicator of the variation in the electrical characteristics of the transistor. The drift voltage Vsh was defined as I... D -V G The tangent to the curve at its maximum slope intersects Id = 1.0 × 10 -12 The value of Vg at the intersection point A.

[0507] Figure 29A The results of the +GBT stress test for sample K are shown. Figure 29B The results of the +GBT stress test for sample L are shown. Figure 29A and Figure 29B In the figure, the horizontal axis represents stress time (hr), and the vertical axis represents ΔVsh (mV).

[0508] like Figure 29A As shown, even under the aforementioned stress conditions for 550 hours, the change in drift voltage ΔVsh of both elements in sample K is less than 100mV. Specifically, the ΔVsh of the first element (represented by the white circle) after 550 hours is 28mV, and the ΔVsh of the second element (represented by the white square) after 550 hours is 23mV.

[0509] like Figure 29B As shown, even under the aforementioned stress conditions for 550 hours, the change in drift voltage ΔVsh of the two elements in sample L is less than 100mV. Specifically, the ΔVsh of the first element (represented by the white circle) after 550 hours is 53mV, and the ΔVsh of the second element (represented by the white square) after 550 hours is 92mV.

[0510] The results above show that by configuring oxide 243 between oxide 230 and conductor 242, the ΔVsh in the +GBT stress test is suppressed to below 100mV after 550 hours of stress. Furthermore, it was confirmed that the ΔVsh in the +GBT stress test of sample K, with a substrate temperature of 200°C, is smaller than that of sample L, where the substrate temperature at which oxide 243 was formed was 250°C.

[0511] This embodiment can be implemented in appropriate combination with other embodiments and the structures and methods shown in other embodiments.

[0512] [Example 5]

[0513] In this embodiment, the reliability evaluation described in Example 4 is continued, and the results are explained when the stress time exceeds 1000 hours. The sample for which the reliability evaluation will continue is referred to as Sample K. The formation conditions of oxide 243 in Sample K are as follows: sputtering method; target material with In:Ga:Zn = 1:3:4 [atomic ratio]; substrate temperature of 200°C; and thickness of 2 nm. Similar to Example 4, the reliability evaluation is performed by a +GBT stress test at a stress temperature of 150°C. Note that in this stress test, the stress time when ΔVsh exceeds 100 mV is defined as the transistor's lifetime. Furthermore, the variations in Ion, S value, and μFE based on stress time are evaluated.

[0514] Ion(A) is the Id value when Vd = 1.2V and Vg = 3.3V. The S value (mV / dec) is the Vg value required for Id to change by one digit in the subthreshold region when Vd is set to 1.2V. μFE (cm 2 / Vs) is a value calculated using a formula that approximates a linear region using a gradually varying channel.

[0515] Figure 30 The results of the +GBT stress test are shown. Figure 30 In the graph, the horizontal axis represents stress time (hr), and the vertical axis represents ΔVsh (mV). For example... Figure 30 As shown, even after 1000 hours under stress, the drift voltage variation ΔVsh of sample K remains below 100mV, i.e., 97mV.

[0516] It is speculated that, compared to the +GBT stress test setting temperature of 125°C, the degradation is accelerated by approximately 24 times when the +GBT stress test setting temperature evaluated in this embodiment is 150°C. Therefore, the service life at a stress temperature of 125°C can be estimated to be over 20,000 hours.

[0517] Figure 31A This shows the stress-time-based variation of Ion. Figure 31B The variation of the S value based on stress time is shown. Figure 31C The stress-time-based variation of μFE is shown. For example... Figure 31A , Figure 31B and Figure 31C As shown, it was confirmed that the stress-time-based variations of Ion, S, and μFE are all small.

[0518] Based on the above results, it is confirmed that the transistor 200 of one embodiment of the present invention has high reliability.

[0519] This embodiment can be implemented in appropriate combination with other embodiments and the structures and methods shown in other embodiments.

[0520] [Example 6]

[0521] In this embodiment, a reliability evaluation is performed, and the results up to 2000 hours of stress time are described. The sample used for reliability evaluation is referred to as sample L. The oxide 243 of sample L was formed under the following conditions: sputtering method; using an In:Ga:Zn target with an atomic ratio of 1:3:4; substrate temperature of 200°C; and thickness of 2 nm. Similar to sample K, sample L was heat-treated at 400°C for 8 hours under a nitrogen atmosphere. As in Example 5, a reliability evaluation was performed by a +GBT stress test at a stress temperature of 150°C. Note that in this stress test, the stress time when ΔVsh exceeds 100 mV is defined as the transistor's lifetime. Furthermore, the variations in Ion, S value, and μFE based on stress time are evaluated.

[0522] Figure 32 The results of the +GBT stress test are shown. Figure 32 In the graph, the horizontal axis represents stress time (hr), and the vertical axis represents ΔVsh (mV). For example... Figure 32 As shown, after 1790 hours under applied stress, the drift voltage variation ΔVsh of sample L remained within ±100mV, i.e., ΔVsh = -92mV. However, after 1800 hours, the drift voltage variation ΔVsh exceeded ±100mV. Therefore, in the +GBT stress test at a stress temperature of 150℃, the transistor lifespan of sample L was 1790 hours.

[0523] It is speculated that, compared to the +GBT stress test setting temperature of 125°C, the degradation is accelerated by approximately 24 times when the +GBT stress test setting temperature evaluated in this embodiment is 150°C. Therefore, the service life at a stress temperature of 125°C can be estimated to be over 40,000 hours.

[0524] Figure 33A This shows the stress-time-based variation of Ion. Figure 33B The variation of the S value based on stress time is shown. Figure 33C The stress-time-based variation of μFE is shown. For example... Figure 33A , Figure 33B and Figure 33C As shown, it was confirmed that the stress-time-based variations of Ion, S, and μFE are all small.

[0525] Based on the above results, it is confirmed that the transistor 200 of one embodiment of the present invention has high reliability.

[0526] This embodiment can be implemented in appropriate combination with other embodiments and the structures and methods shown in other embodiments.

[0527] [Example 7]

[0528] In this embodiment, a sample M including a transistor 200 is manufactured using the method described in <Method for Manufacturing a Semiconductor Device>, and the transistor 200 is subjected to I / O testing. D -V G Measurements are used to evaluate deviations in electrical characteristics.

[0529] The oxide 243 of sample M was formed under the following conditions: sputtering was used; an In:Ga:Zn target with an atomic ratio of 1:3:4 was used; the substrate temperature was 200℃; and the thickness was 2nm. Sample M was heated at 400℃ for 4 hours under a nitrogen atmosphere.

[0530] Next, I was performed on sample M. D -V G Measurements were performed on 27 components with a channel length of 60 nm and a channel width of 60 nm (design value) and 9 components with a channel length of 350 nm and a channel width of 350 nm (design value).

[0531] in I D -V G During the measurement, the drain potential Vd of the transistor was set to +1.2V, and the source potential Vd was set to +1.2V. S Set to 0V, and set the bottom gate potential V BG Set to 0V, and set the gate potential V G Scan from -3.3V to +3.3V.

[0532] Figure 34 Show I D -V G The normal probability distribution of Vsh was calculated during the measurement. The standard deviation of Vsh was 71 mV when the design values ​​were 60 nm channel length and 60 nm channel width. The standard deviation of Vsh was 38 mV when the design values ​​were 350 nm channel length and 350 nm channel width. Small deviations were obtained for both the 60 nm and 350 nm channel length and width design values.

[0533] Figure 35 This shows the gate potential V G I when set to +3.3V DThe normal probability distribution of (Ion1) is given. The standard deviation of the Ion1 deviation is 0.8 μA when the design values ​​are a channel length of 60 nm and a channel width of 60 nm. The standard deviation of the Ion1 deviation is 0.2 μA when the design values ​​are a channel length of 350 nm and a channel width of 350 nm.

[0534] Figure 36 This shows the gate potential V G I when set to Vsh+2.5V D The normal probability distribution of (Ion2) is given. The standard deviation of the Ion2 deviation is 0.6 μA when the design values ​​are a channel length of 60 nm and a channel width of 60 nm. The standard deviation of the Ion2 deviation is 0.1 μA when the design values ​​are a channel length of 350 nm and a channel width of 350 nm.

[0535] This embodiment can be implemented in appropriate combination with other embodiments and the structures and methods shown in other embodiments.

[0536] [Example 8]

[0537] In this embodiment, considering that defects in the crystallization of oxide semiconductors are one of the causes of leakage current, the device calculation is used to estimate the temperature dependence and the impact of defects in CAAC-IGZO on the off-state current.

[0538] Regarding the model for evaluating transistors, it has Figures 1A to 1C The transistor 200 shown has a gate insulating film thickness of 6 nm (EOT), a gate length of 60 nm, and a channel width of 60 nm. Furthermore, based on analysis results from hard X-ray photoelectron spectroscopy (HX-PES), the energy level originating from oxygen vacancies near the bandgap center of the CAAC-IGZO bandgap is designated as a defect level. Device calculations confirm that, regarding V... D I at 1.2V D -V G Characteristics, and I without a defined defect energy level D -V G Compared to other characteristics, V G I in the lower region D The gradient is gentler. That is to say, it can be seen that, compared to I without a defined defect energy level,... D -V G Compared to V, the characteristics are different. G The negative change of I D The amount of change is smaller.

[0539] Furthermore, the increased transistor temperature and V were calculated. D When the voltage is 1.2V, I is given D -VG The impact of these characteristics. With transistor temperatures set to 85℃, 125℃, and 192℃, the calculation results are as follows: V G The off-state current at -2V and 85℃ is 6.5 × 10⁻⁶. -20 A / μm, V G The off-state current at -2V and 125℃ is 3.6 × 10⁻⁶. -18 A / μm, V G The off-state current at -2V and 192℃ is 7.0 × 10⁻⁶. -16 A / μm.

[0540] Next, based on the off-state current at each temperature calculated using the aforementioned device, the temperature dependence of the potential variation of the capacitor connected to the transistor is calculated. Figure 37A The circuit structure used for the calculation is shown. The drain of transistor M20 is connected to one electrode of capacitor CD. Additionally, the source of transistor M20 is grounded to GND. The other electrode of capacitor CD is also grounded to GND. In this calculation, the capacitance of capacitor CD is set to 1nF.

[0541] Set the initial state as follows: Capacitor CD is in a charging state, and V... G Setting it to -2 turns transistor M20 off, and sets the potential of the drain of transistor M20 and one electrode of capacitor CD to V. D =1.2V.

[0542] Figure 37B The calculation results are shown. It can be seen that, as... Figure 37B As shown, the higher the temperature, the greater the potential V over time. D The greater the reduction.

[0543] [Example 9]

[0544] In this embodiment, considering that defects in the crystal structure of the oxide semiconductor are one of the causes of leakage current, device calculations are used to estimate the temperature dependence and the impact of defects in CAAC-IGZO on the off-state current. Furthermore, a simple protection circuit is constructed, and the impact of this leakage current on the circuit's retention characteristics is verified through calculations. In addition, a TEG (Test Element Group) device for retention characteristic verification is manufactured, and the correspondence between the results and the measured results is investigated.

[0545] Regarding the model for evaluating transistors, it has Figures 1A to 1CThe transistor 200 shown has a gate insulating film thickness of 6 nm (EOT), a gate length of 60 nm, and a channel width of 60 nm. Furthermore, based on analysis results from hard X-ray photoelectron spectroscopy (HX-PES) and other methods, the energy level originating from oxygen vacancies near the bandgap center of the CAAC-IGZO bandgap is designated as a defect energy level. Figure 38A The distribution of defect energy levels is shown. E g This refers to the bandgap of oxide semiconductors, and is set to 2.9 eV, N D This refers to the peak density of the defect energy levels, and is set to 1×10⁻⁶. 21 / cm 3 ·eV, W D This refers to the standard deviation of the defect energy level, which is set to 0.25 eV. D This refers to the energy at the midpoint of the defect level, and is set to 1.4 eV and 1.5 eV. Furthermore, the temperature is set to 27°C.

[0546] Figure 38A The result of V calculated using the device is shown. D I at 1.2V D -V G Characteristics. Based on this result, it was confirmed that E... D The off-state current ratio set to 1.4eV will E D The off-state current is large when set to 1.5 eV. That is, the phenomenon of increased off-state current is confirmed when the energy at the middle position of the defect energy level is close to the conduction band bottom Ec.

[0547] Next, E g N D and W D Set E to the same value as above. D Set the voltage to 1.5 eV and set the temperature to 27°C, 85°C, 125°C, and 192°C. Figure 39A The V calculated by the device is shown. D I at 1.2V D -V G Features. Additionally... Figure 39B V is shown G A graph showing the relationship between the off-state current at -2V and the reciprocal of temperature.

[0548] Confirmed, regarding V D I at 1.2V D -V G Characteristics, and I without a defined defect energy level D -V G Compared to other characteristics, V G I in the lower region DThe gradient is gentler. That is to say, it can be seen that, compared to I without a defined defect energy level,... D -V G Compared to V, the characteristics are different. G The negative change of I D The variation is smaller. Furthermore, it can be seen that regardless of whether the defect energy level is set, the off-state current increases with higher temperature (refer to...). Figure 39A and Figure 39B ).

[0549] Next, a protection circuit with a simple structure was designed, and the impact of the off-state current on the holding characteristics was calculated. As a protection circuit with a simple structure, the same method as in Example 8 was used. Figure 37A The circuit shown. However, in this embodiment, the capacitance of capacitor CD is set to 10aF. The initial state is set as follows: V G Setting the voltage to -2 turns transistor M20 off and capacitor CD charging, thus setting the potential V of the drain of transistor M20 and one electrode of capacitor CD to... D Set to 1.2V. Set the temperature to 125℃ and 192℃.

[0550] Figure 40 The calculation results are shown. The graph represented by the dashed line shows the calculation results without setting the defect energy level, while the graph represented by the solid line shows the calculation results with setting the defect energy level. Based on these results, it is confirmed that under conditions of high temperature and a set defect energy level, the potential V over time... D The reduction is large, but the characteristics deteriorate. Furthermore, it was confirmed that under conditions of 125°C and without setting a defect energy level, at... Figure 40 Within the time range shown, almost no potential V occurred. D The decrease.

[0551] Next, we will examine the reasons why the off-state current increases while the characteristics deteriorate in the presence of such defective energy levels. Figure 41 The diagram shows the calculated energy band structure (Ec) of the source electrode, channel formation region, and drain electrode in the transistor's off state. The diagram with dashed lines shows the results without a defined defect energy level, while the diagram with solid lines shows the results with a defined defect energy level.

[0552] Calculations confirmed that the electron potential barrier is lower in the off-state with defective energy levels compared to the off-state without defective energy levels. This may be because, when a negative voltage is supplied to the top gate, a potential barrier of ΔE is initially generated; however, the increase in the barrier is suppressed due to Fermi level pinning, making it easier for electrons to overcome the barrier, thus increasing the off-state current. Figure 41 In this case, the potential barrier decreases partially by δE. This can be considered to correspond to... Figure 39A As shown in I D -V G The subthreshold region of the characteristic relative to V G The changes in I D The amount of change is small.

[0553] Next, a TEG device for holding characteristic measurement was manufactured, and the correspondence between the measured results and the actual results was investigated.

[0554] The TEG device for maintaining characteristic measurement includes a transistor 200, which is manufactured by the method described in <Method for Manufacturing a Semiconductor Device>.

[0555] Figure 42A and Figure 42B The circuit diagram of the TEG device used for holding characteristic measurements is shown. Figure 42A This is a circuit for TEG devices that can measure drain leakage current and top gate leakage current from their holding characteristics. Additionally, Figure 42B It is a circuit that can measure only the top gate leakage current of a TEG device from its retention characteristics.

[0556] like Figure 42A As shown, wiring 2000 is electrically connected to one of the source and drain terminals of transistor M30, wiring 2001 is electrically connected to the gate of transistor M30, and wiring 2002 is electrically connected to one terminal of the readout circuit R10. The other of the source and drain terminals of transistor M30 is electrically connected to the floating node FN, the other terminal of the readout circuit R10 is electrically connected to the floating node FN, and one of the source and drain terminals of transistor M22 is electrically connected to the floating node FN. Furthermore, wiring 2003 is electrically connected to the gate of transistor M22, wiring 2004 is electrically connected to the other of the source and drain terminals of transistor M22, and wiring 2005 is electrically connected to the back gate of transistor M22.

[0557] In addition, such as Figure 42B As shown, wiring 2000 is electrically connected to one of the source and drain terminals of transistor M30, wiring 2001 is electrically connected to the gate of transistor M30, and wiring 2002 is electrically connected to one terminal of the readout circuit R10. Additionally, the other of the source and drain terminals of transistor M30 is electrically connected to the floating node FN, the other terminal of the readout circuit R10 is electrically connected to the floating node FN, and the gate of transistor M22 is electrically connected to the floating node FN. Wiring 2006 is electrically connected to both the source and drain terminals of transistor M22, and wiring 2005 is electrically connected to the back gate of transistor M22.

[0558] Transistor M30 is a write transistor, and transistor M22 is a transistor for retaining the measured characteristics. Although Figure 42A and Figure 42BTransistor M22 is a single transistor, but it is composed of 20,000 transistors connected in parallel, each with a channel length of 60 nm and a channel width of 60 nm. In other words, transistor M22 is a transistor with a channel length of 60 nm and a channel width of 60 nm × 20,000 = 1.2 mm.

[0559] Next, the I-parameters of transistor M22 were measured using a semiconductor parameter analyzer for electrical measurements of semiconductor devices. D -V G Measurement. Figure 43 The I of transistor M22 is shown. D -V G A graph illustrating the characteristics. In measurements using a semiconductor parameter analyzer, even with a channel width of 1.2 mm, the off-state current is 1 × 10⁻⁶ times the lower limit of the semiconductor parameter analyzer's measurement capability. -16 Below A / μm.

[0560] Next, using Figure 42A The TEG device shown is used to estimate the drain leakage current and top gate leakage current based on its holding characteristics. First, a potential is set for wiring 2001 to turn on transistor M30. A potential of 1.2V is supplied to wiring 2000, accumulating charge in node FN to set the potential to 1.2V. Then, a potential of -3V is supplied to wiring 2001 to turn off transistor M30. The potential of wiring 2000 is set to 0V and the potential of wiring 2005 is set to -3V to turn off transistor M22. The potentials of wiring 2003, which is electrically connected to the gate, are set to -2V and -2.5V. This state is maintained for a certain period, and the time change of the potential at node FN is read out by the readout circuit R10. The drain leakage current and top gate leakage current are estimated from the read values.

[0561] Next, using Figure 42B The TEG device shown estimates the top-gate leakage current from its holding characteristics. First, a potential is set for wiring 2001 to turn on transistor M30, and a potential of 1.2V is supplied to wiring 2000 to accumulate charge in node FN and set the potential to 1.2V. Then, a potential of -3V is supplied to wiring 2001 to turn off transistor M30. Transistor M22 sets the potentials of wiring 2006 to 4.4V and 4.9V, and the potential of wiring 2005 to 1.2V. This state is maintained for a certain period, and the time change of the potential at node FN is read out by the readout circuit R10. The top-gate leakage current is estimated from the read value.

[0562] Figure 44A The I of transistor M22 is measured using a semiconductor parameter analyzer. D -V GThe V obtained above is plotted in the characteristic chart. G The drain leakage current and top gate leakage current values ​​at -2V and -2.5V, and V G The graph shows the gate leakage current values ​​at -2V and -2.5V. Furthermore, the straight line represented by the dashed line is the extrapolation line for the subthreshold region.

[0563] Figure 44B The I of transistor M22 is measured using a semiconductor parameter analyzer. D -V G The V obtained above is plotted in the characteristic chart. G The drain leakage current values ​​at -2V and -2.5V, and the value of drain leakage current minus V from the top gate leakage current value. G A graph showing the gate leakage current values ​​at -2V and -2.5V. That is, the drain leakage current excluding gate leakage. Furthermore, the straight line represented by the dashed line is the extrapolation line for the subthreshold region.

[0564] Figure 45 Yes Figure 44B I obtained through device calculations by adding additional defect energy levels D -V G A graph of characteristics. The curve represented by the dotted line indicates the I calculated from the device. D -V G Characteristics. This confirms that the off-state current deviates from the extrapolation line of the subthreshold region when a negative gate potential is supplied. This is similar to the Fermi level pinning behavior caused by defect levels, as confirmed by calculation.

[0565] [Symbol Explanation]

[0566] 10: Oxide semiconductor, 20: Conductor, 22: Oxygen solid solution region, 30: Oxide, 100: Capacitor, 110: Conductor, 112: Conductor, 120: Conductor, 130: Insulator, 150: Insulator, 200: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 205c: Conductor, 205d: Conductor, 205e: Conductor, 205f: Conductor, 205g: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 224A: Insulating film, 230: Oxide, 230a: Oxide, 230A: Oxide Film, 230b: Oxide, 230B: Oxide film, 230c: Oxide, 230C: Oxide film, 240: Conductor, 240a: Conductor, 240b: Conductor, 241: Insulator, 241a: Insulator, 241b: Insulator, 242: Conductor, 242a: Conductor, 242A: Conductive film, 242b: Conductor, 242B: Conductive layer, 243: Oxide, 243a: Oxide, 243A: Oxide film, 243b: Oxide, 243B: Oxide layer, 245: Conductor, 246: Conductor, 246a: Conductor, 246b: Conductor, 250: Insulator, 250A: Insulating film, 260: Conductor, 260a: Conductor, 26 0Aa: Conductive film, 260Ab: Conductive film, 260b: Conductor, 272: Insulator, 272A: Insulating film, 273: Insulator, 273A: Insulator, 274: Insulator, 276: Insulator, 280: Insulator, 281: Insulator, 282: Insulator, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 400: Crystal Body tube, 405: Conductor, 405a: Conductor, 405b: Conductor, 430c: Oxide, 431a: Oxide, 431b: Oxide, 432a: Oxide, 432b: Oxide, 440: Conductor, 440a: Conductor, 440b: Conductor, 442: Conductor, 442a: Conductor, 442b: Conductor, 443: Oxide, 443a: Oxide, 443b: Oxide, 450: Insulator, 460: Conductor, 460a: Conductor, 460b: Conductor, 1001: Wiring, 1002: Wiring, 1003: Wiring, 1004: Wiring, 1005: Wiring, 1006: Wiring, 1007: Wiring, 1008: Wiring1009: Wiring; 1010: Wiring.

Claims

1. A semiconductor device, comprising: First insulator; The first oxide on the first insulator; The second oxide on the first oxide; The third and fourth oxides on the second oxide; The first conductor on the third oxide; The second conductor on the fourth oxide; The fifth oxide on the second oxide; The second insulator on the fifth oxide; as well as The third conductor on the second insulator, The fifth oxide is in contact with the top surface of the second oxide, the side surface of the first conductor, the side surface of the second conductor, the side surface of the third oxide, and the side surface of the fourth oxide. The second oxide contains In, element M, and Zn. The element M is Al, Ga, Y, or Sn. The first oxide and the fifth oxide each comprise at least one of the constituent elements comprised of the second oxide. The third oxide and the fourth oxide each contain element M. Furthermore, the third oxide and the fourth oxide have regions where the concentration of element M is higher than that of the second oxide.

2. The semiconductor device according to claim 1, The third oxide and the fourth oxide each have a region with a thickness of 0.5 nm or more and 5 nm or less.

3. The semiconductor device according to claim 1 or 2, The third oxide and the fourth oxide each have a region with a thickness of more than 1 nm and less than 3 nm.

4. The semiconductor device according to claim 1 or 2, The third oxide and the fourth oxide each contain gallium.

5. The semiconductor device according to claim 1 or 2, The third oxide and the fourth oxide are each crystalline.

6. The semiconductor device according to claim 1 or 2, The second oxide is crystalline.

7. The semiconductor device according to claim 1 or 2, The first oxide, the third oxide, the fourth oxide, and the fifth oxide have the same composition.

8. A semiconductor device, comprising: First insulator; The first oxide on the first insulator; The second oxide on the first oxide; The third and fourth oxides on the second oxide; The first conductor on the third oxide; The second conductor on the fourth oxide; The fifth oxide on the second oxide; The second insulator on the fifth oxide; A third conductor on the second insulator; The first conductor and the third insulator on the second conductor; as well as The fourth insulator on the third insulator The fifth oxide is in contact with the top surface of the second oxide, the first side surface of the first conductor, the first side surface of the second conductor, the first side surface of the third oxide, the first side surface of the fourth oxide, and the side surface of the third insulator. The fifth oxide is in contact with the side of the opening provided in the fourth insulator. The third conductor is disposed in such a way that it fills the opening. The second oxide contains In, element M, and Zn. The element M is Al, Ga, Y, or Sn. The first oxide and the fifth oxide each comprise at least one of the constituent elements comprised of the second oxide. The third oxide and the fourth oxide each contain element M. Furthermore, the third oxide and the fourth oxide have regions where the concentration of element M is higher than that of the second oxide.

9. The semiconductor device according to claim 8, The third insulator is in contact with the second side of the first conductor, the second side of the second conductor, the second side of the third oxide, the second side of the fourth oxide, and the side of the second oxide.

10. The semiconductor device according to claim 8 or 9, The fifth oxide has a layered structure. Furthermore, the fifth oxide comprises the sixth oxide and the seventh oxide on the sixth oxide.

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