Clock control circuit and control method for I2C controller clock line

Abstract

The present invention discloses a clock control circuit and control method for an I2C controller clock line. The control circuit includes a first frequency-dividing module, a second frequency-dividing module, a first comparator, a second comparator, and a clock generation module. The first frequency-dividing module is connected to the clock generation module via the first comparator, and the second frequency-dividing module is connected to the clock generation module via the second comparator. The clock generation module is configured to adjust the frequency of the clock of the I2C controller clock line based on received high-level and low-level pulse signals. The control circuit generates corresponding pulse signals by receiving high-level and low-level comparison coefficients to effectively control the clock line frequency. The circuit has a simple structure and expands the scope of use of the I2C controller.

Description

Technical Field

[0001] The present invention relates to the technical field of intelligent robots, and in particular to a clock control circuit and a control method for an I2C controller clock line. Background Art

[0002] The I2C (Inter Integrated Circuit) bus is a two-wire serial bus developed by Philips for connecting microcontrollers and their peripherals. It is a widely adopted bus standard in the field of microelectronic communication and control. The two serial bus lines in I2C are the clock line (SCL) and the data line (SDA). I2C has three different modes: standard mode, fast mode, and overdrive mode. Overdrive mode allows bit rates up to 3.4 Mbit / s, while standard mode allows a maximum bit rate of 100 Kbit / s, with no lower limit. However, most existing I2C controllers only support a few common bit rates, such as 100 Kbit / s or 400 Kbit / s. This is acceptable if the I2C module will only communicate with a limited number of devices, but it becomes increasingly restrictive if it needs to communicate with many devices supporting different bit rates. Summary of the Invention

[0003] To address the above issues, the present invention provides a clock control circuit and control method for an I2C controller clock line, enabling the I2C controller clock line to output a clock line of any frequency without exceeding the counting clock frequency. The specific technical solutions of the present invention are as follows:

[0004] A clock control circuit for an I2C controller clock line includes a first frequency-dividing module, a second frequency-dividing module, a first comparator, a second comparator, and a clock generation module. The first frequency-dividing module is connected to the clock generation module via the first comparator, and the second frequency-dividing module is connected to the clock generation module via the second comparator. The first frequency-dividing module and the second frequency-dividing module are configured to count based on a received count clock and a detected clock line clock, and to send the count values ​​to the first and second comparators, respectively. The first comparator is configured to compare the received count value with a high-level comparison coefficient and, based on the comparison result, send a high pulse signal to the clock generation module. The second comparator is configured to compare the received count value with a low-level comparison coefficient and, based on the comparison result, send a low pulse signal to the clock generation module. The clock generation module is configured to adjust the frequency of the I2C controller clock line based on the received high and low pulse signals. The control circuit effectively controls the clock line frequency by generating corresponding pulse signals using the received high and low-level comparison coefficients. The circuit has a simple structure and extends the scope of use of the I2C controller.

[0005] In one or more embodiments of the present invention, the first frequency-dividing module and the second frequency-dividing module are connected to the same counting clock. The first frequency-dividing module begins counting after detecting a rising edge of the clock line, and counts based on the rising edge of the counting clock. The second frequency-dividing module begins counting after detecting a falling edge of the clock line, and counts based on the rising edge of the counting clock. Counting using the same counting clock makes the obtained values ​​more accurate.

[0006] In one or more embodiments of the present invention, the clock frequency of the clock line is determined by a high level comparison coefficient and a low level comparison coefficient. The frequency of SCL is controlled by the high level comparison coefficient and the low level comparison coefficient, which is highly flexible.

[0007] A method for controlling a clock control circuit of an I2C controller is provided. The method is used to control the clock control circuit of the clock line of the I2C controller. The control method specifically comprises the following steps: S1: a first frequency dividing module and a second frequency dividing module detect the level of the clock of the I2C controller clock line; S2: if the level of the clock line is a rising edge, the first frequency dividing module starts counting and sends the count value to a first comparator; if the level of the clock line is a falling edge, the second frequency dividing module starts counting and sends the count value to a second comparator; S3: the first comparator compares the received count value with a pre-received high-level comparison coefficient. If the count value is greater than the high-level comparison coefficient, the first comparator sends a high pulse signal to a clock generation module; the second comparator compares the received count value with a pre-received low-level comparison coefficient. If the count value is greater than the low-level comparison coefficient, the second comparator sends a low pulse signal to the clock generation module; S4: the clock generation module adjusts the frequency of the clock of the I2C controller clock line according to the received high pulse signal and low pulse signal. By comparing the high level comparison coefficient and the low level comparison coefficient after counting, a high pulse signal and a low pulse signal are generated to control the clock generation module to output the clock of the corresponding clock line. The counting is simple and fast, which expands the scope of use of the I2C controller.

[0008] In one or more solutions of the present invention, in step S2, the first frequency dividing module and the second frequency dividing module count according to the received counting clock. When the first frequency dividing module receives the rising edge of the counting clock, the count value of the first frequency dividing module is increased by 1; when the second frequency dividing module receives the rising edge of the counting clock, the count value of the second frequency dividing module is increased by 1.

[0009] In one or more embodiments of the present invention, in step S3, when the count value of the first frequency-dividing module is greater than the high-level comparison coefficient, the count value of the first frequency-dividing module is reset to zero; and when the count value of the second frequency-dividing module is greater than the low-level comparison coefficient, the count value of the second frequency-dividing module is reset to zero. By outputting a corresponding pulse signal for reset, the count value is prevented from affecting the re-counting of the first and second frequency-dividing modules.

[0010] In one or more embodiments of the present invention, in step S3, the generation time of the high pulse signal is determined by the counting clock and the high level comparison coefficient; the generation time of the low pulse signal is determined by the counting clock and the low level comparison coefficient.

[0011] In one or more embodiments of the present invention, in step S4, if the clock generation module receives a high pulse signal, it pulls the clock line low; if it receives a low pulse signal, it pulls the clock line high. Changing the time interval between pulling the clock line low and high also changes the number of oscillations per unit time. Frequency is the number of oscillations per unit time. By leveraging the characteristics of frequency, this method provides more accurate results.

[0012] In one or more embodiments of the present invention, in step S4 , the clock frequency of the clock line output by the clock generation module is determined by the time interval between when the clock line is pulled high and when it is pulled low.

[0013] In one or more aspects of the present invention, the clock line frequency is calculated as follows: the clock line frequency is equal to the frequency of the count clock divided by the sum of the high-level comparison coefficient and the low-level comparison coefficient. The clock line frequency is calculated by using the count clock, the high-level comparison coefficient, and the low-level comparison coefficient, resulting in high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic structural diagram of a clock control circuit for an I2C controller clock line of the present invention;

[0015] Figure 2 Flowchart of a method for controlling a clock control circuit of an I2C controller clock line according to the present invention;

[0016] Figure 3 Schematic diagram of the structure of the I2C controller data line generation circuit of the present invention;

[0017] Figure 4 is a timing diagram of the I2C controller of the present invention;

[0018] Figure 5 This is an implementation diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0020] In the description of the present invention, it should be noted that, for directional words, such as the terms "center", "horizontal", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and so on, indicating directions and positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and cannot be understood as limiting the specific scope of protection of the present invention.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. Therefore, the terms "first" and "second" may explicitly or implicitly include one or more of these features. Throughout the description of the present invention, "at least" means one or more than one, unless otherwise specifically defined.

[0022] In the present invention, unless otherwise specified or limited, the terms "assemble," "connect," and "connect" should be understood in a broad sense. For example, they may refer to fixed connection, detachable connection, or integral connection; mechanical connection; direct connection, connection through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0023] In the present invention, unless otherwise specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature therebetween. Furthermore, a first feature being "above," "below," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "above," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0024] The following is a further description of the specific embodiments of the present invention in conjunction with the accompanying drawings, so that the technical solutions and beneficial effects of the present invention are more clearly understood and defined. The following description of the embodiments with reference to the accompanying drawings is illustrative and intended to explain the present invention, but is not to be construed as limiting the present invention.

[0025] Refer to the attached Figure 1 A clock control circuit for an I2C controller clock line includes a first frequency divider module, a second frequency divider module, a first comparator, a second comparator, and a clock generation module. The first frequency divider module is connected to the clock generation module via the first comparator, and the second frequency divider module is connected to the clock generation module via the second comparator. The first frequency divider module and the second frequency divider module are configured to count based on a received count clock and a detected clock line clock, and transmit the count values ​​to the first comparator and the second comparator, respectively. The first comparator is configured to compare the received count value with a high-level comparison coefficient and transmit a high pulse signal to the clock generation module based on the comparison result. The second comparator is configured to compare the received count value with a low-level comparison coefficient and transmit a low pulse signal to the clock generation module based on the comparison result. The clock generation module is configured to adjust the frequency of the I2C controller clock line based on the received high pulse signal and low pulse signal. The control circuit effectively controls the frequency of the clock line by generating corresponding pulse signals through the received high-level comparison coefficient and low-level comparison coefficient. The structure is simple and the application range of the I2C controller is expanded.

[0026] In one embodiment, the first and second frequency-dividing modules are connected to the same counting clock. The first frequency-dividing module detects the rising edge of the clock line and begins counting based on the rising edge of the counting clock. The second frequency-dividing module detects the falling edge of the clock line and begins counting based on the rising edge of the counting clock. Using the same counting clock for counting increases the accuracy of the acquired values. The clock frequency of the clock line is determined by a high-level comparison coefficient and a low-level comparison coefficient. Using the high-level comparison coefficient and the low-level comparison coefficient to control the clock line frequency provides high flexibility. When the I2C controller is not needed, both the data line and the clock line of the I2C controller are in a high-level state, and the high-level comparison coefficient and the low-level comparison coefficient are input (assuming SHPG = SLPG = 63). When the I2C controller is needed, the data line generation module will pull the clock line low to generate a START signal. At this time, the clock generation module will pull the clock line low, and the second frequency divider module will detect a falling edge on the clock line and start working. The counter of the second frequency divider module will continue to count. When the count value is equal to 64 (greater than 63), the second comparator will generate a pulse signal, the clock line generation module will pull the clock line high, and the counter of the second frequency divider module will be cleared. At this time, the first frequency divider module detects a rising edge on the clock line and starts working. The working principle is similar to the previous one.

[0027] Refer to the attached Figure 2 It can be seen that a control method for the clock control circuit of an I2C controller is provided, which is used to control the clock control circuit of the above-mentioned I2C controller clock line. The control method specifically includes the following steps: S1: a first frequency division module and a second frequency division module detect the level of the clock of the I2C controller clock line; S2: if the level of the clock line is a rising edge, the first frequency division module starts counting and sends the count value to the first comparator; if the level of the clock line is a falling edge, the second frequency division module starts counting and sends the count value to the second comparator; S3: the first comparator compares the received count value with a pre-received high-level comparison coefficient. If the count value is greater than the high-level comparison coefficient, the first comparator sends a high pulse signal to the clock generation module; the second comparator compares the received count value with a pre-received low-level comparison coefficient. If the count value is greater than the low-level comparison coefficient, the second comparator sends a low pulse signal to the clock generation module; S4: the clock generation module adjusts the frequency of the clock of the I2C controller clock line according to the received high pulse signal and low pulse signal. By comparing the high level comparison coefficient and the low level comparison coefficient after counting, a high pulse signal and a low pulse signal are generated to control the clock generation module to output the clock of the corresponding clock line. The counting is simple and fast, which expands the scope of use of the I2C controller.

[0028] As one embodiment, the first frequency-dividing module and the second frequency-dividing module count according to the received counting clock. When the first frequency-dividing module receives the rising edge of the counting clock, the count value of the first frequency-dividing module is increased by 1; when the second frequency-dividing module receives the rising edge of the counting clock, the count value of the second frequency-dividing module is increased by 1. When the count value of the first frequency-dividing module is greater than the high-level comparison coefficient, the count value of the first frequency-dividing module is cleared to zero; when the count value of the second frequency-dividing module is greater than the low-level comparison coefficient, the count value of the second frequency-dividing module is cleared to zero. By outputting the corresponding pulse signal and then clearing it to zero, the count value is prevented from affecting the re-counting of the first frequency-dividing module and the second frequency-dividing module. The generation time of the high pulse signal is determined by the counting clock and the high-level comparison coefficient; the generation time of the low pulse signal is determined by the counting clock and the low-level comparison coefficient.

[0029] In one embodiment, if the clock generation module receives a high pulse signal, it pulls the clock line low; if it receives a low pulse signal, it pulls the clock line high. Changing the time interval between pulling the clock line low and high also changes the number of oscillations per unit time. Frequency is the number of oscillations per unit time. Implementing this method leverages the characteristics of frequency to achieve more accurate results. The clock frequency of the clock line output by the clock generation module is determined by the time interval between pulling the clock line high and low.

[0030] In one embodiment, the clock frequency of the clock line is calculated as follows: the clock frequency of the clock line is equal to the frequency of the counting clock divided by the sum of the high-level comparison coefficient and the low-level comparison coefficient. The clock frequency of the output clock line is obtained by using the counting clock, the high-level comparison coefficient, and the low-level comparison coefficient, which is highly practical.

[0031] The clock line generation circuit structure diagram is as follows Figure 3 As shown, the output of the counter of the clock line generation circuit is connected to one port of the comparator, and the other port of the comparator is connected to a clock line comparison coefficient (HDT_DAT).

[0032] When the falling edge detection circuit detects a falling edge on SCL, the counter begins counting. The counter continuously sends the count result to one end of the comparator for comparison until the count value exceeds the comparison coefficient. At this time, the clock line data is output. By adjusting the value of the clock line comparison coefficient (HDT_DAT), the phase of the clock line data output can be adjusted. The phase adjustment formula is as follows:

[0033] Holdtime = 1 / FCLK × (HDT_DAT) Formula 4

[0034] Holdtime is the time the clock line data is held, and FCLK is the frequency of CLK.

[0035] Figure 4 This is an I2C timing diagram. When transmitting addresses or data, the clock line changes only during the low level period of SCL. By adjusting the clock line comparison coefficient, the Holdtime can be adjusted, thereby adjusting the clock line phase. SCL_HT and SCL_LT are the duration of SCL high level and SCL low level respectively.

[0036] The timing diagram is as follows Figure 5 As shown, by adjusting the values ​​of the high-level comparison coefficient and the low-level comparison coefficient, clock lines of different frequencies can be output. The frequency calculation formula is as follows:

[0037] FSCL = FCLK ÷ (SHPG + SLPG) Formula 1

[0038] FSCL is the frequency of the clock line, FCLK is the frequency of the clock, and the duty cycle can be adjusted when the high level comparison coefficient (SHPG) and the low level comparison coefficient (SLPG) are different. The formula for the duty cycle is as follows:

[0039] N = SHPG / ( SHPG + SLPG)×100% Formula 2

[0040] According to formula 1, the duration of the high level and the duration of the low level of the clock line can also be deduced, as shown in formulas 3 and 4;

[0041] SCL_HT = TCLK × SHPG Formula 3

[0042] SCL_LT = TCLK × SLPG Formula 4

[0043] TCLK is the period of CLK, which is the reciprocal of FCLK. SCL_HT is the duration of the high level of the clock line, and SCL_LT is the duration of the low level of the clock line.

[0044] Assuming the clock CLK frequency FCLK is 50 MHz, then the TCLK duration is 1 / FCLK, or 20 ns. The required SCL frequency is 400 kHz, with a 50% duty cycle. For a 50% duty cycle, according to Formula 2, SHPG must equal SLPG. Using Formula 1, we can calculate SHPG = SLPG = 63. Using Formulas 3 and 4, we can calculate the SCL high and low durations: SCL_HT = SCL_LT = 20 ns × 63 = 1260 ns. Verification: Since both SCL_HT and SCL_LT are 1260 ns, the SCL period is 1260 × 2 = 2520 ns, resulting in a frequency of 1 / 2520 ns = 397 kHz, which is within an acceptable error range from the required 400 kHz.

[0045] In the description of the specification, reference to the terms "in one embodiment," "preferably," "example," "specific example," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. The schematic representations of the above terms in this specification do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. The connection method described in the description of the specification has obvious effects and practical effectiveness.

[0046] Through the description of the above structure and principle, technical personnel in the relevant technical field should understand that the present invention is not limited to the above specific implementation methods, and improvements and substitutions based on the present invention using the well-known technology in the field all fall within the scope of protection of the present invention and should be defined by the claims.

Claims

1. A method for controlling a clock control circuit of an I2C controller, the method being used to control a clock control circuit of a clock line of an I2C controller, characterized in that: The control method specifically includes the following steps: S1: The first frequency dividing module and the second frequency dividing module detect the clock level of the I2C controller clock line; S2: If the level of the clock line is a rising edge, the first frequency divider module starts counting and sends the count value to the first comparator; if the level of the clock line is a falling edge, the second frequency divider module starts counting and sends the count value to the second comparator; S3: The first comparator compares the received count value with the pre-received high-level comparison coefficient. If the count value is greater than the high-level comparison coefficient, the first comparator sends a high pulse signal to the clock generation module. The second comparator compares the received count value with the pre-received low-level comparison coefficient. If the count value is greater than the low-level comparison coefficient, the second comparator sends a low pulse signal to the clock generation module. S4: The clock generation module adjusts the frequency of the clock of the I2C controller clock line according to the received high pulse signal and low pulse signal; The clock control circuit of the I2C controller clock line includes: a first frequency dividing module, a second frequency dividing module, a first comparator, a second comparator and a clock generation module, wherein the first frequency dividing module is connected to the clock generation module via the first comparator, and the second frequency dividing module is connected to the clock generation module via the second comparator; The first frequency dividing module and the second frequency dividing module are used to count according to the received counting clock and the clock of the detected clock line, and send the count value to the first comparator and the second comparator respectively; The first comparator is used to compare the received count value with the high-level comparison coefficient and send a high pulse signal to the clock generation module according to the comparison result; the second comparator is used to compare the received count value with the low-level comparison coefficient and send a low pulse signal to the clock generation module according to the comparison result; The clock generation module is used to adjust the frequency of the clock of the I2C controller clock line according to the received high pulse signal and the low pulse signal; The first frequency dividing module and the second frequency dividing module are connected to the same counting clock. The first frequency dividing module starts counting after detecting the rising edge of the clock on the clock line, and counts according to the rising edge of the counting clock; the second frequency dividing module starts counting after detecting the falling edge of the clock on the clock line, and counts according to the rising edge of the counting clock; The clock frequency of the clock line is determined by a high level comparison coefficient and a low level comparison coefficient.

2. The method for controlling a clock control circuit of an I2C controller clock line according to claim 1, wherein: In step S2, the first frequency dividing module and the second frequency dividing module count according to the received counting clock. When the first frequency dividing module receives the rising edge of the counting clock, the count value of the first frequency dividing module is increased by 1. When the second frequency dividing module receives the rising edge of the counting clock, the count value of the second frequency dividing module is increased by 1.

3. The method for controlling a clock control circuit of an I2C controller clock line according to claim 1, wherein: In step S3, when the count value of the first frequency dividing module is greater than the high level comparison coefficient, the count value of the first frequency dividing module is cleared; when the count value of the second frequency dividing module is greater than the low level comparison coefficient, the count value of the second frequency dividing module is cleared.

4. The method for controlling a clock control circuit of an I2C controller clock line according to claim 1, wherein: Step S3: The generation time of the high pulse signal is determined by the counting clock and the high level comparison coefficient; the generation time of the low pulse signal is determined by the counting clock and the low level comparison coefficient.

5. The method for controlling a clock control circuit of an I2C controller clock line according to claim 1, wherein: In step S4, if the clock generation module receives a high pulse signal, the clock line is pulled low; If the clock generation module receives a low pulse signal, it pulls the clock line high.

6. The method for controlling a clock control circuit of an I2C controller clock line according to claim 5, wherein: In step S4, the clock frequency of the clock line output by the clock generation module is determined by the time interval between when the clock line is pulled high and when it is pulled low.

7. The method for controlling a clock control circuit of an I2C controller clock line according to claim 6, wherein: The calculation formula of the clock frequency of the clock line is: the clock frequency of the clock line is equal to the frequency of the counting clock divided by the sum of the high level comparison coefficient and the low level comparison coefficient.

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