Redundant memory access to rows or columns containing faulty memory cells in simulated neural memory in deep learning artificial neural networks

Abstract

The present invention discloses a number of embodiments for accessing redundant non-volatile memory cells instead of one or more rows or columns containing one or more failed non-volatile memory cells during program, erase, read, or neural read operations in an analog neural memory system used in a deep learning artificial neural network.

Description

[0001] Priority Declaration

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 696,778, filed on July 11, 2018, entitled “Redundant Memory Access for Rows or Columns Containing Faulty Memory Cells in Analog Neural Memory in Deep Learning Artificial Neural Network,” and U.S. Patent Application No. 16 / 151,259, filed on October 3, 2018, entitled “Redundant Memory Access for Rows or Columns Containing Faulty Memory Cells in Analog Neural Memory in Deep Learning Artificial Neural Network.” Technical Field

[0003] The present invention discloses a number of embodiments for accessing redundant non-volatile memory cells instead of one or more rows or columns containing one or more failed non-volatile memory cells during program, erase, read, or neural read operations in an analog neural memory system used in a deep learning artificial neural network. Background Art

[0004] Artificial neural networks simulate biological neural networks (e.g., the central nervous system of an animal, particularly the brain) and are used to estimate or approximate functions that may depend on a large number of inputs and are generally unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0005] Figure 1 An artificial neural network 100 is shown, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the input and learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on data received from the synapses, either individually or collectively.

[0006] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, that is, very high computational parallelism. In principle, such complexity can be achieved using digital supercomputers or clusters of dedicated graphics processing units. However, in addition to being high-cost, these approaches are also mediocre in energy efficiency compared to biological networks, which consume less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used in artificial neural networks, but given the large number of neurons and synapses, the synapses of most CMOS implementations are too large.

[0007] Applicant previously disclosed an artificial (simulated) neural network utilizing one or more nonvolatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439, which is incorporated herein by reference. The nonvolatile memory array operates as a simulated neuromorphic memory. A neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a source region and a drain region spaced apart formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed over and insulated from a first portion of the channel region; and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs.

[0008] Each nonvolatile memory cell used in an analog neuromorphic memory system must be erased and programmed to maintain a very specific and precise amount of charge in the floating gate. For example, each floating gate must maintain one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, and 64.

[0009] A unique characteristic of analog neuromorphic memory systems is that they must support two different types of read operations. In a normal read operation, individual memory cells are read, as in conventional memory systems. However, in a neural read operation, the entire array of memory cells is read at once, with each bit line outputting a current that is the sum of all the currents from the memory cells connected to that bit line.

[0010] Supporting both types of read operations presents several challenges. One challenge is how to provide redundancy for the system. In situations where multiple redundant rows or columns are being used (due to the presence of multiple failed rows or columns), the system must be able to activate all of the redundant rows or columns at once during a neural read operation. However, in conventional systems, a read or program operation will only operate on one row or sector of a row at any given time (rather than all rows), so only some of the redundant rows or columns will need to be asserted at any given time. Consequently, prior art decoding systems do not support neural read operations.

[0011] An improved decoding system is needed for use with analog neuromorphic memory to provide redundancy during program, erase, read, and neural read operations. Summary of the Invention

[0012] The present invention discloses a number of embodiments for accessing redundant non-volatile memory cells instead of one or more rows or columns containing one or more failed non-volatile memory cells during program, erase, read, or neural read operations in an analog neural memory system used in a deep learning artificial neural network. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 FIG. 1 is a schematic diagram showing an artificial neural network in the prior art.

[0014] Figure 2 FIG. 1 is a cross-sectional side view of a conventional 2-gate non-volatile memory cell.

[0015] Figure 3 FIG. 1 is a cross-sectional side view of a conventional 4-gate non-volatile memory cell.

[0016] Figure 4 FIG. 1 is a side cross-sectional view of a conventional 3-gate non-volatile memory cell.

[0017] Figure 5 FIG. 1 is a cross-sectional side view of another conventional 2-gate non-volatile memory cell.

[0018] Figure 6 A schematic diagram illustrating different stages of an exemplary artificial neural network utilizing a non-volatile memory array.

[0019] Figure 7 is a block diagram showing a vector multiplier matrix.

[0020] Figure 8 is a block diagram showing the various stages of the vector multiplier matrix.

[0021] Figure 9 Another implementation of a vector multiplier matrix is ​​depicted.

[0022] Figure 10 Another implementation of a vector multiplier matrix is ​​depicted.

[0023] Figure 11 Describes the Figure 10 The vector multiplier matrix performs the operation at the operating voltage.

[0024] Figure 12 Another implementation of a vector multiplier matrix is ​​depicted.

[0025] Figure 13 Describes the Figure 12 The vector multiplier matrix performs the operation at the operating voltage.

[0026] Figure 14 Another implementation of a vector multiplier matrix is ​​depicted.

[0027] Figure 15 Describes the Figure 14 The vector multiplier matrix performs the operation at the operating voltage.

[0028] Figure 16 Another implementation of a vector multiplier matrix is ​​depicted.

[0029] Figure 17 Describes the Figure 16 The vector multiplier matrix performs the operation at the operating voltage.

[0030] Figure 18 A memory system and a redundancy system including a vector multiplier matrix are depicted.

[0031] Figure 19 A prior art redundant system is depicted.

[0032] Figure 20 An implementation of a redundant system for a vector multiplier matrix is ​​depicted.

[0033] Figure 21 Another embodiment of a redundant system for a vector multiplier matrix is ​​depicted.

[0034] Figure 22 Another embodiment of a redundant system for a vector multiplier matrix is ​​depicted.

[0035] Figure 23 Another embodiment of a redundant system for a vector multiplier matrix is ​​depicted.

[0036] Figure 24 Embodiments of methods of accessing redundant memory cells rather than failed memory cells during program, read, or erase operations are described.

[0037] Figure 25 Embodiments of methods of accessing redundant memory cells rather than failed memory cells during a neural read operation are described.

[0038] Figure 26 An embodiment of a decoding system for use with a vector multiplier matrix is ​​depicted.

[0039] Figure 27 Another embodiment of a decoding system for use with a vector multiplier matrix is ​​depicted.

[0040] Figure 28 A prior art long short-term memory system is depicted.

[0041] Figure 29 Depicted are exemplary cells in a prior art long short-term memory system.

[0042] Figure 30 Depicts Figure 29 A specific implementation of an exemplary cell in a long short-term memory system.

[0043] Figure 31 A prior art gated recurrent unit system is depicted.

[0044] Figure 32 Depicted are exemplary cells in a prior art gated recurrent unit system.

[0045] Figure 33 Depicts Figure 32 A specific implementation of an exemplary cell in the gated recurrent unit system. DETAILED DESCRIPTION

[0046] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays.

[0047] Non-volatile memory cells

[0048] Digital non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("the '130 patent") discloses an array of split-gate non-volatile memory cells and is incorporated herein by reference for all purposes. Such memory cells are Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the electrical conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 16. A wordline terminal 22 (which is typically coupled to a wordline) has a first portion disposed over and insulated from (and controls the electrical conductivity of) a second portion of the channel region 18, and a second portion extending upward and over the floating gate 20. The floating gate 20 and wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0049] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on wordline terminal 22 , which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim tunneling from floating gate 20 to wordline terminal 22 .

[0050] Memory cell 210 is programmed by placing a positive voltage on wordline terminal 22 and a positive voltage on source 16 (where electrons are placed on the floating gate). Electron current will flow from source 16 to drain 14. When the electrons reach the gap between wordline terminal 22 and floating gate 20, they will accelerate and become heated. Due to the electrostatic attraction from floating gate 20, some of the heated electrons will be injected through gate oxide 26 onto floating gate 20.

[0051] Memory cell 210 is read by placing a positive read voltage on drain 14 and wordline terminal 22 (which turns on the channel region below the wordline terminal). If floating gate 20 is positively charged (i.e., electrons are erased and positively coupled to drain 16), the portion of the channel region below floating gate 20 is also turned on, and current will flow through channel region 18, which is sensed as an erased state or a "1" state. If floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below floating gate 20 is mostly or completely turned off, and no current (or very little current) will flow through channel region 18, which is sensed as a programmed state or a "0" state.

[0052] Table 1 shows typical voltage ranges that may be applied to the terminals of the memory cell 210 for performing read, erase, and program operations:

[0053] Table 1: Figure 2 Operation of the flash memory unit 210

[0054] WL BL SL Read 2V-3V 0.6V-2V 0V Erase About 11-13V 0V 0V programming 1V-2V 1-3μA 9V-10V

[0055] Other split-gate memory cell configurations are known. For example, Figure 3A quad-gate memory cell 310 is shown, comprising a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 28 (typically coupled to a word line) over a second portion of the channel region 18, a control gate 22 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating, meaning they are electrically connected or capable of being electrically connected to a voltage source. Programming is illustrated by heated electrons from the channel region 18 injecting themselves onto the floating gate 20. Erasing is illustrated by electrons tunneling from the floating gate 20 to the erase gate 30.

[0056] Table 2 depicts typical voltage ranges that may be applied to the terminals of the memory cell 310 for performing read, erase, and program operations:

[0057] Table 2: Figure 3 Operation of the flash memory unit 310

[0058] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0-2.6V 0-2.6V 0V Erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 1μA 8V-11V 4.5V-9V 4.5V-5V

[0059] Figure 4 A split gate tri-gate memory cell 410 is shown. The memory cell 410 is connected to Figure 3 The memory cell 310 is identical to the memory cell 410, except that the memory cell 410 does not have a separate control gate. The erase operation (erasing via the erase gate) and the read operation are the same as Figure 3 The operation is similar to that of , except that there is no control gate bias. The programming operation is also done without a control gate bias, so the programming voltage on the source line is higher to compensate for the lack of control gate bias.

[0060] Table 3 depicts typical voltage ranges that may be applied to the terminals of the memory cell 410 for performing read, erase, and program operations:

[0061] Table 3: Figure 4 Operation of the flash memory unit 410

[0062]

[0063]

[0064] Figure 5 A stacked gate memory cell 510 is shown. The memory cell 510 is similar to Figure 2 Memory cell 210 is shown, except that floating gate 20 extends over the entire channel region 18 and control gate 22 extends over floating gate 20, separated by an insulating layer. Erase, program, and read operations operate in a similar manner as previously described for memory cell 210.

[0065] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 510 for performing read, erase, and program operations:

[0066] Table 4: Figure 5 Operation of the flash memory unit 510

[0067] CG BL SL P-sub Read 2V-5V 0.6V-2V 0V 0V Erase -8V to -10V / 0V FLT FLT 8V-10V / 15-20V programming 8V-12V 3V-5V 0V 0V

[0068] In order to utilize a memory array comprising one of the above-described types of nonvolatile memory cells in an artificial neural network, two modifications were made. First, the circuitry was configured so that each memory cell could be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as explained further below. Second, continuous (analog) programming of the memory cells was provided.

[0069] Specifically, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage device is analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all cells in the memory array, and makes the memory array ideal for storing and fine-tuning the synaptic weights of neural networks.

[0070] Neural Networks Using Nonvolatile Memory Cell Arrays

[0071] Figure 6 A non-limiting example of a neural network utilizing a non-volatile memory array is conceptually illustrated. This example uses the non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a non-volatile memory array-based neural network.

[0072] For this example, S0 is the input, a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color, R, G, and B, with 5-bit precision per pixel). Synapse CB1 from S0 to C1 has both different sets of weights and shared weights, and scans the input image with a 3x3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, the values ​​of 9 pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are presented to synapse CB1, whereupon these 9 input values ​​are multiplied by the appropriate weights. After summing the outputs of these multiplications, a single output value is determined and provided by the first neuron of CB1 for use in generating the pixels of one layer, C1, of the feature map. The 3x3 filter is then shifted right by one pixel (i.e., the columns of three pixels on the right are added and the columns of three pixels on the left are released). The 9 pixel values ​​in this newly positioned filter are presented to synapse CB1, whereupon they are multiplied by the same weights and a second single output value is determined by the associated neuron. This process continues until the 3x3 filter has scanned all three colors and all bits (precision values) over the entire 32x32 pixel image. The process is then repeated using different sets of weights to generate different feature maps for C1 until all feature maps for layer C1 are calculated.

[0073] At C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, synapse CB1 is composed of a two-dimensional array of 16 layers (remember that the references to neuron layers and arrays in this article are logical, not necessarily physical, i.e., the arrays do not have to be oriented to be physical two-dimensional arrays). Each of the 16 feature maps is generated by one of sixteen different sets of synaptic weights applied to the filter scans. The C1 feature maps can all relate to different aspects of the same image features, such as edge recognition. For example, a first map (generated using a first set of weights, shared for all scans used to generate it) can identify circular edges, a second map (generated using a second set of weights different from the first) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0074] Before transitioning from C1 to S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling stage is to average neighboring locations (or use a max function), for example to reduce dependencies on edge locations, and to reduce the data size before entering the next stage. At S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). The synapses and associated neurons from S1 to C2 in CB2 scan the maps in S1 using a 4x4 filter, where the filter is shifted by 1 pixel. At C2, there are 22 12x12 feature maps. Before transitioning from C2 to S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. At S2, there are 22 6x6 feature maps. The activation function is applied to the synapse CB3 from S2 to C3, where each neuron in C3 is connected to each map in S2. At C3, there are 64 neurons. Synapse CB4 from C3 to output S3 fully connects S3 to C3. The output at S3 consists of 10 neurons, where the highest output neuron determines the class. For example, this output can indicate the recognition or classification of the content of the original image.

[0075] Each level of synapses is implemented using an array or portion of an array of non-volatile memory cells. Figure 7 A block diagram of a vector-matrix multiplication (VMM) array that includes nonvolatile memory cells and is used as a synapse between an input layer and the next layer. Specifically, VMM 32 includes a nonvolatile memory cell array 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the inputs of memory array 33. In this example, source line decoder 37 also decodes the outputs of the memory cell array. Alternatively, bit line decoder 36 can decode the outputs of the memory array. The memory array serves two purposes. First, it stores weights to be used by the VMM. Second, the memory array effectively multiplies the inputs with the weights stored in the memory array and each output line (source line or bit line) adds them together to produce an output that serves as the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient due to in-situ memory computation.

[0076] The output of the memory array is provided to a differential adder (such as an adding operational amplifier or an adding current mirror) 38, which sums the outputs of the memory cell array to create a single value for the convolution. The differential adder is to achieve the sum of positive weights and negative weights with the positive input. The summed output value is then provided to an activation function circuit 39, which corrects the output. The activation function may include a sigmoid, tanh, or ReLU function. The corrected output value becomes an element of the feature map of the next layer (e.g., C1 in the above description) and is then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the memory array constitutes a plurality of synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the summing operational amplifier 38 and the activation function circuit 39 constitute a plurality of neurons.

[0077] Figure 8 This is a block diagram of each level of the VMM. Figure 8 As shown, the input is converted from digital to analog by a digital-to-analog converter 31 and provided to an input VMM 32a. The converted analog input can be voltage or current. The D / A conversion of the input of the first layer can be accomplished by using a function or LUT (look-up table) that maps the input to the appropriate analog level for the matrix multiplier. The input conversion can also be performed by an A / A converter to convert the external analog input to the analog input mapped to the VMM. The output generated by the input VMM 32a is provided as the input of the next VMM (hidden level 1) 32b, which in turn generates an output provided as the input of the next VMM (hidden level 2) 32b, and so on. The various layers of VMM 32 serve as different layers of synapses and neurons in a convolutional neural network (CNN). Each VMM can be a separate non-volatile memory array, or multiple VMMs can utilize different portions of the same non-volatile memory array, or multiple VMMs can utilize overlapping portions of the same non-volatile memory array. Figure 8 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely exemplary and that, on the contrary, the system may include more than two hidden layers and more than two fully connected layers.

[0078] Vector-Matrix Multiplication (VMM) Array

[0079] Figure 9 A neuron VMM 900 is shown, which is particularly suitable for Figure 3Memory cells of the type shown, and used as synapses and components of neurons between the input layer and the next layer. VMM 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 (at the top of the array). Alternatively, another reference array can be placed at the bottom. In VMM 900, control gate lines (such as control gate line 903) extend in the vertical direction (so that reference array 902 is in the row direction orthogonal to the input control gate lines), and erase gate lines (such as erase gate line 904) extend in the horizontal direction. Here, input is provided on the control gate lines, and output appears on the source lines. In one embodiment, only even-numbered rows are used, and in another embodiment, only odd-numbered rows are used. The current placed on the source lines performs a summing function of all currents from the memory cells connected to the source lines.

[0080] As described herein for neural networks, flash memory cells are preferably configured to operate in the subthreshold region.

[0081] The memory cell described in this paper is weakly reverse biased:

[0082] Ids=Io*e (Vg-Vth) / kVt =w*Io*e (Vg) / kVt

[0083] w=e (-Vth) / kVt

[0084] For an I to V logarithmic converter that uses a memory cell to convert input current to input voltage:

[0085] Vg=k*Vt*log[Ids / wp*Io]

[0086] For a memory array used as a vector-matrix multiplier VMM, the output current is:

[0087] Iout=wa*Io*e (Vg) / kVt ,Right now

[0088] Iout=(wa / wp)*Iin=W*Iin

[0089] W=e (Vthp-Vtha) / kVt

[0090] The word line or control gate may be used as the input to the memory cell for the input voltage.

[0091] Alternatively, the flash memory cell can be configured to operate in the linear region:

[0092] Ids=beta*(Vgs-Vth)*Vds; beta=u*Cox*W / L

[0093] Wα(Vgs-Vth)

[0094] For an I to V linear converter, a memory cell operating in the linear region can be used to linearly convert an input / output current to an input / output voltage.

[0095] Other implementations of the ESF vector-matrix multiplier are described in US Patent Application No. 15 / 826,345, which is incorporated herein by reference. Either the source line or the bit line can be used as a neuron output (current summing output).

[0096] Figure 10 A neuron VMM 1000 is shown, which is particularly suitable for Figure 2 Memory cells of the type shown, and serve as synapses between the input layer and the next layer. VMM 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001, and a reference array 1002. Reference arrays 1001 and 1002 in the column direction of the array are used to convert current inputs flowing into terminals BLR0-3 into voltage inputs WL0-3. In practice, the reference memory cells are diodes connected through a multiplexer, into which the current inputs flow. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix. Memory array 1003 serves two purposes. First, it stores weights to be used by VMM 1000. Secondly, the memory array 1003 effectively multiplies the inputs (current inputs provided in terminals BLR0-3; reference arrays 1001 and 1002 convert these current inputs into input voltages to be provided to word lines WL0-3) by the weights stored in the memory array and then adds the results (memory cell currents) to produce an output, which will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power efficient. Here, the voltage input is provided on the word line and the output appears on the bit line during a read (inference) operation. The current placed on the bit line performs a summing function of all the currents from the memory cells connected to the bit line.

[0097] Figure 11 The operating voltages for VMM 1000 are shown. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for unselected cells, the bit line for a selected cell, the bit line for unselected cells, the source line for a selected cell, and the source line for unselected cells. The rows indicate read, erase, and program operations.

[0098] Figure 12 Depicted is a Neuron VMM 1200, which is particularly suitable for Figure 2Memory cells of the type shown serve as synapses and components between neurons in the input layer and the next layer. VMM 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201, and a reference array 1202. Reference arrays 1201 and 1202, extending in the row direction of array VMM 1200, are similar to VMM 1000, except that in VMM 1200, the word lines extend in a vertical direction. Here, input is provided on the word lines, and output appears on the source lines during a read operation. The current placed on the source lines performs a summing function of all the currents from the memory cells connected to the source lines.

[0099] Figure 13 Depicted are operating voltages for VMM 1200. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for unselected cells, the bit line for a selected cell, the bit line for unselected cells, the source line for a selected cell, and the source line for unselected cells. The rows indicate read, erase, and program operations.

[0100] Figure 14 Depicted is a Neuron VMM 1400, which is particularly suitable for Figure 3 Memory cells of the type shown are used as synapses and components of neurons between the input layer and the next layer. VMM 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401, and a reference array 1402. Reference arrays 1401 and 1402 are used to convert current inputs flowing into terminals BLR0-3 into voltage inputs CG0-3. In practice, the reference memory cells are diodes connected through a cascode multiplexer 1414, into which the current inputs flow. Multiplexer 1414 includes a multiplexer 1405 and a cascode transistor 1404 to ensure a constant voltage on the bit line of the reference cell being read. The reference cell is tuned to a target reference level. Memory array 1403 serves two purposes. First, it stores weights to be used by VMM 1400. Secondly, the memory array 1403 effectively multiplies the inputs (current inputs provided to terminals BLR0-3; reference arrays 1401 and 1402 convert these current inputs into input voltages to be provided to control gates CG0-3) by the weights stored in the memory array and then adds the results (cell currents) to produce an output, which will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient. Here, the inputs are provided on the word lines and the outputs appear on the bit lines during a read operation. The current placed on the bit lines performs a summing function of all the currents from the memory cells connected to the bit lines.

[0101] VMM 1400 implements unidirectional tuning for the memory cells in memory array 1403. That is, each cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (causing an incorrect value to be stored in the cell), the cell must be erased and the sequence of partial programming operations must be restarted. As shown, two rows sharing the same erase gate need to be erased together (called a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0102] Figure 15 The operating voltages for VMM 1400 are depicted. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0103] Figure 16 Depicted is a Neuron VMM 1600, which is particularly suitable for Figure 3 Memory cells of the type shown are used as synapses and components of neurons between the input layer and the next layer. VMM 1600 includes a memory array 1603 of nonvolatile memory cells, a reference array 1601, and a reference array 1602. The EG lines extend vertically, while the CG and SL lines extend horizontally. VMM 1600 is similar to VMM 1400, except that VMM 1600 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve the desired amount of charge on the floating gate. As shown, reference arrays 1601 and 1602 convert the input current in terminals BLR0-3 into control gate voltages CG0-3 to be applied to the memory cells in the row direction (through the action of the reference cells connected via the diodes of the multiplexer). The current output (neuron) is in the bit line, which sums all the currents from the memory cells connected to the bit line.

[0104] Figure 17The operating voltages for VMM 1600 are depicted. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0105] Prior art includes a concept known as long short-term memory (LSTM). LSTM cells are commonly used in neural networks. LSTM allows neural networks to remember information over arbitrary time intervals and use that information in subsequent operations. A typical LSTM cell consists of a cell, an input gate, an output gate, and a forget gate. These three gates regulate the flow of information into and out of the cell. VMMs are particularly useful in LSTM cells.

[0106] Figure 28 An exemplary LSTM 2800 is depicted. The LSTM in this example includes cells 2801, 2802, 2803, and 2804. Cell 2801 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 2802 receives an input vector x1, an output vector (hidden state) h0, and a cell state c0 from cell 2801, and generates an output vector h1 and a cell state vector c1. Cell 2803 receives an input vector x2, an output vector (hidden state) h1, and a cell state c1 from cell 2802, and generates an output vector h2 and a cell state vector c2. Cell 2804 receives an input vector x3, an output vector (hidden state) h2, and a cell state c2 from cell 2803, and generates an output vector h3. Additional cells can be used, and the LSTM with four cells is merely an example.

[0107] Figure 29 Describes the Figure 28 2801, 2802, 2803, and 2804 in LSTM cell 2900. LSTM cell 2900 receives an input vector x(t) and a cell state vector c(t-1) from the previous cell, and generates a cell state (t) and an output vector h(t).

[0108] LSTM cell 2900 includes sigmoid function devices 2901, 2902, and 2903, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed to pass directly to the output vector. LSTM cell 2900 also includes hyperbolic tangent devices 2904 and 2905 for applying a hyperbolic tangent function to the input vector, multiplier devices 2906, 2907, and 2908 for multiplying two vectors together, and addition device 2909 for adding two vectors together.

[0109] Figure 30 LSTM cell 3000 is depicted, which is an example of a specific implementation of LSTM cell 2900. For the convenience of the reader, Figure 30 and LSTM cells 3000 using Figure 29 Same number as LSTM cell 2900. Figure 30 As can be seen in FIG, the sigmoid function devices 2901, 2902, and 2903 and the hyperbolic tangent devices 2904 and 2905 each include a plurality of VMM arrays 3001. Therefore, it can be seen that the VMM array is particularly important in the LSTM cells used in certain neural network systems.

[0110] It will also be appreciated that an LSTM system will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as adder and activation circuit blocks, as well as high-voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0111] Similarly, the simulated VMM implementation can be used for GRU (Gated Recurrent Unit) systems. GRU is a gating mechanism in recurrent neural networks. GRU is similar to LSTM, with one notable difference being that GRU lacks an output gate.

[0112] Figure 31An exemplary GRU 3100 is depicted. The GRU in this example includes cells 3101, 3102, 3103, and 3104. Cell 3101 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 3102 receives an input vector x1, an output vector (hidden state) h0, and a cell state c0 from cell 3101, and generates an output vector h1 and a cell state vector c1. Cell 3103 receives an input vector x2, an output vector (hidden state) h1, and a cell state c1 from cell 3102, and generates an output vector h2 and a cell state vector c2. Cell 3104 receives an input vector x3, an output vector (hidden state) h2, and a cell state c2 from cell 3103, and generates an output vector h3. Additional cells can be used, and a GRU with four cells is merely an example.

[0113] Figure 32 Describes the Figure 31 00 . An exemplary implementation of a GRU cell 3200 for cells 3101, 3102, 3103, and 3104 in . The GRU cell 3200 receives an input vector x(t) and a cell state vector h(t-1) from the previous cell and generates a cell state h(t). The GRU cell 3200 includes sigmoid function devices 3201 and 3202, each of which applies a number between 0 and 1 to components from the cell state h(t-1) and the input vector x(t). The GRU cell 3200 also includes a hyperbolic tangent device 3203 for applying a hyperbolic tangent function to the input vector, multiplier devices 3204, 3205, and 3206 for multiplying two vectors together, an addition device 3207 for adding two vectors together, and a complement device 3208 for subtracting the input from 1 to generate an output.

[0114] Figure 33 Depicted is a GRU cell 3300, which is an example of a specific implementation of the GRU cell 3200. For the convenience of the reader, Figure 33 and GRU cells 3300 are used with Figure 32 Same number as GRU cell 3200. Figure 33 As can be seen in FIG, the sigmoid function devices 3201 and 3202 and the hyperbolic tangent device 3203 each include a plurality of VMM arrays 3301. Therefore, it can be seen that the VMM array is particularly useful in the GRU cells used in certain neural network systems.

[0115] It will also be appreciated that a GRU system will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as adder and activation circuit blocks, as well as high-voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0116] Figure 18 A VMM system 1800 is shown. The VMM system 1800 includes a VMM array 1807, a low voltage row decoder 1803, a high voltage row decoder 1805, a reference cell low voltage column decoder 1806 (shown for the reference array in the column direction, which means providing input to output conversion in the row direction), a bit line PE driver 1802, a bit line multiplexer 1808, an activation function circuit and adder 1809, control logic 1804, and an analog bias circuit 1801.

[0117] Low-voltage row decoder 1803 provides bias voltages for read and program operations and provides decoded signals to high-voltage row decoder 1805. High-voltage row decoder 1805 provides high-voltage bias signals for program and erase operations. Bitline PE driver 1801 provides control functions for bit lines during programming, verifying, and erasing. Bias circuit 1801 is a shared bias block that provides the multiple voltages required for various programming, erasing, program-verifying, and reading operations.

[0118] VMM system 1800 also includes redundant array 1810 and / or redundant array 1813. Redundant arrays 1810 and 1813 each provide array redundancy for replacing defective portions in array 1807, according to redundancy implementations described in more detail below.

[0119] The VMM system 1800 also includes an NVR (non-volatile register also known as information sector) sector 1811, which is an array sector used to store user information, device ID, password, security key, trim bits, configuration bits, manufacturing information, etc.

[0120] VMM system 1800 optionally includes reference sector 1812 and / or reference system 1850. Reference system 1850 includes reference array 1852, reference array low voltage row decoder 1851, reference array high voltage row decoder 1853, and reference array low voltage column decoder 1854. The reference system can be shared across multiple VMM systems.

[0121] Reference array low voltage row decoder 1851 provides bias voltages for read and program operations involving reference array 1852, and also provides decoding signals for reference array high voltage row decoder 1853. Reference array high voltage row decoder 1853 provides high voltage bias for programming and operations involving reference array 1852. Reference array low voltage column decoder 1854 provides decoding functionality for reference array 1852. Reference array 1852 is used, for example, to provide a reference target for program verification or cell margin fine-tuning (searching for marginal cells).

[0122] Figure 19 A prior art memory system 1900 is depicted that provides redundancy for rows containing one or more failed memory cells during program, erase, or read operations. Memory system 1900 includes an address comparator 1903, logic circuitry 1905, an array 1906, a redundant array 1907, a row decoder 1908, and a redundant row decoder 1909.

[0123] During the test or configuration phase, each row of memory cells in array 1906 is tested and verified. Any memory cells deemed to be faulty are identified, and the address of each row containing one or more faulty memory cells is stored in non-volatile memory (not shown). Thereafter, during operation of memory system 1900, address comparator 1903 compares each address 1901 used for a read or write operation with each address in a set of stored addresses corresponding to a row containing one or more faulty memory cells.

[0124] If the address comparator 1903 finds a match with any of the stored addresses, the enable signal 1904 is asserted, indicating that the received address is for the faulty row. The enable signal 1904 is received by the redundant array row decoder 1909, which then selects the row that has been assigned to the row containing the faulty memory cell. Thus, the program, erase, or read operation involves the redundant row, rather than the row containing the faulty memory cell.

[0125] If the address comparator 1903 does not find a match, the enable signal 1904 is deasserted and the row decoder 1908 is enabled by the output of the logic circuit 1905 (shown here as an inverter).In this case, the received address 1901 is used to access a row in the array 1906 for operation.

[0126] By design, only one of the allocated redundant rows can be active at any given time. Therefore, this prior art system cannot be used to perform neural read operations where all non-faulty rows and the allocated redundant rows are active.

[0127] Figure 20One embodiment of an improved memory system is depicted. Memory system 2000 provides redundancy for rows containing one or more bad memory cells. Unlike memory system 1900, memory system 2000 is capable of validating all assigned redundant rows during a neural read operation, and it can also perform program, erase, or read operations as in memory system 1900. Memory system 2000 includes the same components as memory system 1900, except that memory system 2000 uses a row decoder and redundant latch block 2008 instead of row decoder 1908. Row decoder and redundant latch block 2008 includes circuitry that enables all assigned redundant rows to be valid during a neural read operation.

[0128] Figure 21 Further details are depicted regarding an embodiment of the row decoder and redundant latch block 2008 (shown here as row decoder and redundant latch block 2101). Memory system 2100 includes row decoder and redundant latch block 2101, array 2102, redundant array 2103, and high voltage decoder 2104. Row decoder and redundant latch block 2101 includes multiple instances of sub-block 2105, where each instance of sub-block 2105 is coupled to a pair of word lines (here, word lines 2115 and 2116) in array 2102. Thus, in this embodiment, sub-block 2105 and similar sub-blocks are each coupled to a sector of memory in array 2102. In alternative embodiments, each sub-block can be coupled to more than two rows.

[0129] Row decoder and redundant latch block 2101 also includes a redundant sub-block 2113, which is coupled to a pair of word lines (here, word lines 2117 and 2118) in redundant array 2103. Additional redundant sub-blocks similar to redundant sub-block 2113 may be included in row decoder and redundant latch block 2101.

[0130] Sub-block 2105 includes NAND gates 2106 and 2107, inverters 2108 and 2109, NAND gates 2110 and 2111, inverters 2112 and 2113, and latch 2114. During the test or configuration phase, latch 2114 is programmed (or loaded with configuration data at power-up or in response to a redundant load command). If word line 2115 or 2116 is coupled to a row containing one or more faulty memory cells, a "1" will be programmed into latch 2114. Otherwise, latch 2114 will store a "0." During normal operation, when NAND gates 2106 or 2107 receive an address corresponding to word line 2115 or 2116, respectively, latch 2114 will disable the word line instead of enabling it. Therefore, word lines containing faulty memory cells will not be selected.

[0131] Redundant sub-block 2113 contains similar components as sub-block 2105. Here, latch 2119 is programmed during the test or configuration phase. If word line 2117 or 2118 is to be used, latch 2119 is programmed to have a "0". Otherwise, latch 2119 is programmed to have a "1". During normal operation, when the receiving "NAND" gate receives an address corresponding to word line 2117 or 2118, latch 2119 will enable that word line. Therefore, the word line containing the redundant memory cells will be selected. It is worth noting that multiple redundant rows can be selected at any given time (such as during a neural read operation) by configuring latches such as latch 2119 to have a "0".

[0132] Figure 22 Further details are depicted regarding another embodiment of the row decoder and redundant latch block 2008 (shown here as row decoder and redundant latch block 2201). Memory system 2200 includes row decoder and redundant latch block 2201, array 2202, redundant array 2203, and high voltage decoder 2204. Row decoder and redundant latch block 2201 includes multiple instances of sub-block 2205, where each instance of sub-block 2205 is coupled to a word line (here, word line 2211) in array 2202. Thus, in this embodiment, sub-block 2205 and similar sub-blocks are each coupled to a sector of memory in array 2202.

[0133] Row decoder and redundant latch block 2201 also includes a redundant block 2213 coupled to a redundant word line (here, word line 2212 ) in redundant array 2203 .

[0134] Sub-block 2205 includes a NAND gate 2206, an inverter 2207, a latch 2208, and switches 2209 and 2210. Here, redundant latch 2208 is programmed during the configuration phase of memory system 2200. If latch 2208 contains a "1," the corresponding row coupled to word line 2211 in array 2202 is not faulty. During normal operation, switch 2209 will be closed and switch 2210 will be open, and word line 2211 in array 2202 will be accessed when the appropriate address is received. If latch 2208 contains a "0," the corresponding row in array 2202 is faulty. During normal operation, switch 2209 will be open and switch 2210 will be closed, and word line 2211 in array 2202 will not be accessed when the appropriate address is received. Instead, redundant word line 2212 in array 2202 will be accessed via vertical line 2215.

[0135] Figure 23Another embodiment of the inventive concept is depicted. Memory system 2300 includes column decoder and redundant latch block 2301, array 2302, and redundant array 2303. Column decoder and redundant latch block 2301 includes multiple instances of sub-block 2304, where each instance of sub-block 2304 is selectively coupled to a bit line or group of bit lines (here, bit line 2308) in array 2302. Sub-block 2304 includes latch 2305, switch 2306, and switch 2307.

[0136] Latch 2305 is programmed during the test or configuration phase of memory system 2300. If latch 2305 contains a "1," the corresponding column coupled to bit line 2308 is not faulty. During normal operation, switch 2306 will be closed and switch 2307 will be open, and bit line 2308 will be accessed when the appropriate address is received. If latch 2305 contains a "0," the corresponding column in array 2302 is faulty. During normal operation, switch 2306 will be open and switch 2307 will be closed, and when the appropriate address is received, bit line 2308 in array 2302 will not be accessed. Instead, redundant bit line 2309 in redundant array 2303 will be accessed via horizontal line 2315.

[0137] Figure 24 A programming, program verify, and erase method 2400 is depicted. The process begins (step 2401). A program, program verify, or erase command is received (step 2402). The received address is compared to addresses for known error rows or columns in the memory array (step 2403).

[0138] If a match is found (step 2404), this means there is an erroneous address. The system will disable the erroneous address (step 2405) and enable the corresponding redundant address (step 2406). A program, program verify, or erase command is then executed using the redundant address (step 2407). The process is then complete (step 2408).

[0139] If no match is found (step 2404), the received address is enabled (step 2409). The received address is then used to execute a program, program verify, or erase command (step 2410). The process is then complete (step 2408).

[0140] Figure 25 An embodiment of a neural read process 2500 is depicted. The process begins (step 2501). Redundant latches are loaded or configured with redundant information (step 2502). A neural read operation occurs, thereby enabling the entire array and the redundant array except for the erroneous row or column (step 2503). The process completes (step 2504).

[0141] Figure 26 Describes the Figure 2 1. Decoding circuit 2600 for use with an array of memory cells of the type shown. Decoding circuit 2600 includes a word line decoder 2601, a high voltage source 2604, and a source line decoder 2606. Word line decoder 2601 includes a PMOS transistor 2603 and an NMOS transistor 2602 configured as shown. Source line decoder 2606 includes NMOS transistors 2607, 2608, and 2609, configured as shown. High voltage source 2604 includes a high voltage logic power supply 2605.

[0142] Figure 27 Describes the Figure 3 1 and 2. A decoding circuit 2700 is used with an array of memory cells of the type shown. Decoding circuit 2700 includes an erase gate line decoder 2701, a control gate decoder 2706, a source line decoder 2709, and a high voltage power supply 2704. Erase gate decoder 2701 includes a PMOS transistor 2703 and an NMOS transistor 2702, configured as shown. Control gate decoder 2706 includes a PMOS transistor 2708 and an NMOS transistor 2707. Source line decoder 2709 includes NMOS transistors 2710, 2711, and 2712, configured as shown. High voltage power supply 2704 includes a high voltage logic power supply 2705.

[0143] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening material, element, or space disposed therebetween) and "indirectly on" (intervening material, element, or space disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (no intervening material, element, or space disposed therebetween) and "indirectly adjacent" (intervening material, element, or space disposed therebetween), "mounted to" includes "directly mounted to" (no intervening material, element, or space disposed therebetween) and "indirectly mounted to" (intervening material, element, or space disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (no intervening material or element electrically connecting the elements together) and "indirectly electrically coupled to" (intervening material or element electrically connecting the elements together). For example, forming an element "above a substrate" may include forming the element directly on the substrate without an intervening material / element therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials / elements therebetween.

Claims

1. A method of performing a neural read operation in a memory system including a memory array and a redundant memory array, the method comprising: loading data into one or more latches; disabling a plurality of rows of memory cells in the memory array in response to the one or more latches; enabling a plurality of rows of memory cells in the redundant memory array; A concurrent read operation is performed of all memory cells in non-disabled rows in the memory array and all memory cells in a plurality of enabled rows in the redundant memory array, wherein all memory cells in the plurality of enabled rows in the redundant memory array are activated at once during the neural read operation.

2. The method according to claim 1, further comprising: receiving a current on each output line in the memory array and the redundant memory array, wherein the current on each output line includes a current consumed by each memory cell in a non-disabled row in the memory array coupled to the output line and each memory cell in an enabled row in the redundant memory array coupled to the output line during the concurrent read operation. The method of claim 2 , wherein the output line is a bit line. The method of claim 2 , wherein the output line is a source line. The method of claim 1 , wherein the disabling utilizes discrete logic components. The method of claim 1 , wherein the disabling utilizes one or more switches.

7. The method of claim 1, wherein each of the one or more latches is coupled to a word line for a sector of memory cells in the memory array.

8. The method of claim 1, wherein each of the memory cells in the memory array and each of the memory cells in the redundant memory array is a split gate flash memory cell.

9. The method of claim 1, further comprising performing an address comparison during a program or erase operation to determine if an address corresponds to a failed memory.

10. The method of claim 9, wherein if the address comparison identifies a match, the redundant memory array is enabled for a program or erase operation.

11. A method of performing a neural read operation in a memory system including a memory array and a redundant memory array, the method comprising: loading data into one or more latches; disabling a plurality of columns of memory cells in the memory array in response to the one or more latches; enabling a plurality of columns of memory cells in the redundant memory array; A concurrent read operation is performed of all memory cells in non-disabled columns in the memory array and all memory cells in a plurality of enabled columns in the redundant memory array, wherein all memory cells in the plurality of enabled columns in the redundant memory array are activated at once during the neural read operation.

12. The method according to claim 11, further comprising: receiving a current on each output line in the memory array and the redundant memory array, wherein the current on each output line includes a current consumed by each memory cell in a non-disabled column in the memory array coupled to the output line and each memory cell in an enabled column in the redundant memory array coupled to the output line during the read operation. The method of claim 12 , wherein the output line is a bit line. The method of claim 12 , wherein the output line is a source line.

15. The method of claim 11, wherein the disabling is performed by one or more switches.

16. The method of claim 11, wherein each of the memory cells in the memory array and each of the memory cells in the redundant memory array is a split gate flash memory cell.

17. The method of claim 11, further comprising performing an address comparison during a program or erase operation to determine if an address corresponds to a failed memory.

18. The method of claim 17, wherein if the address comparison identifies a match, the redundant memory array is enabled for a program or erase operation.

19. A memory system comprising: a memory array, the memory array comprising a plurality of sectors, each sector comprising a plurality of rows of memory cells; a redundant memory array, the redundant memory array comprising a plurality of redundant sectors, each redundant sector comprising a plurality of rows of memory cells; For each sector in the memory array, a control block includes a latch, wherein the latch is programmable to disable one or more rows in the sector in the memory array; For each sector in the redundant memory array, a control block includes a redundant latch, wherein the redundant latch is programmable to enable one or more rows in a redundant sector in the redundant memory array; wherein, during a neural read operation, a concurrent read operation of all memory cells in non-disabled rows in the memory array and all memory cells in multiple enabled rows in the redundant memory array is performed, wherein during the neural read operation, all memory cells in the multiple enabled rows in the redundant memory array are activated at once.

20. The system of claim 19, further comprising: A circuit for receiving a current on each bit line in the memory array and the redundant memory array, wherein the current on each bit line includes a current consumed by each memory cell in a non-disabled row in the memory array coupled to the bit line and each memory cell in an enabled row in the redundant memory array coupled to the bit line during the read operation.

21. The system of claim 19, further comprising: For each sector in the memory array, a discrete logic component is located between the latch and the memory array.

22. The system of claim 19, further comprising: For each sector in the memory array, one or more switches are located between the latch and the memory array.

23. The system of claim 19, wherein each of the memory cells in the memory array and each of the memory cells in the redundant memory array is a split gate flash memory cell.

24. The system of claim 19, wherein the memory array is a vector-by-matrix multiplication array in a long short-term memory system.

25. The system of claim 19, wherein the memory array is a vector-by-matrix multiplication array in a gated recurrent unit system.

26. A memory system comprising: a memory array comprising memory cells arranged in rows and columns, wherein each column of memory cells is coupled to a bit line; a redundant memory array comprising redundant memory cells arranged in rows and columns, wherein each column of redundant memory cells is coupled to a bit line; for each bit line in the memory array, a control block including a latch, wherein the latch is programmable to disable the column of memory cells coupled to the bit line in the memory array; for each bit line in the redundant memory array, a control block including a redundant latch, wherein the redundant latch is programmable to enable a column of memory cells coupled to the bit line in the redundant memory array; wherein, during a neural read operation, a concurrent read operation of all memory cells in non-disabled columns in the memory array and all memory cells in multiple enabled columns in the redundant memory array is performed, wherein during the neural read operation, all memory cells in the multiple enabled columns in the redundant memory array are activated at once.

27. The system of claim 26, further comprising: Circuitry for receiving a current on each bit line coupled to a non-disabled column in the memory array and each bit line coupled to an enabled column in the redundant memory array during a neural read operation.

28. The system of claim 26, further comprising: For each bit line in the memory array, one or more switches are located between the latch and the memory array.

29. The system of claim 26, wherein each of the memory cells in the memory array and each of the memory cells in the redundant memory array is a split gate flash memory cell.

30. The system of claim 26, wherein the memory array is a vector-by-matrix multiplication array in a long short-term memory system.

31. The system of claim 26, wherein the memory array is a vector-by-matrix multiplication array in a gated recurrent unit system.

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