Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device capable of achieving miniaturization or high integration. The semiconductor device of the present invention includes a transistor, a capacitor, an electrode, and an interlayer film. The transistor includes a semiconductor layer, a gate, a source, and a drain. The transistor and the capacitor are arranged in a manner of being buried in the interlayer film. One of the source and the drain contacts the electrode below the semiconductor layer, and the other of the source and the drain contacts one electrode of the capacitor above the semiconductor layer.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. Further, one aspect of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] Note that, in the present specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are also one aspect of semiconductor devices. Sometimes, it can be said that display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices sometimes include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification and the like relates to an object, a method, or a manufacturing method. Further, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Background Art

[0004] In recent years, development of semiconductor devices has been carried out mainly using LSIs, CPUs, and memories. A CPU is an aggregate of semiconductor integrated circuits (including at least transistors and memories) separated from a semiconductor wafer and formed with electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on a printed wiring board, for example, on a circuit board, and are used as one of the components of various electronic devices.

[0006] Further, a technique of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply referred to as display devices). As a semiconductor thin film that can be applied to a transistor, silicon-based semiconductor materials are widely known. In addition, as other materials, oxide semiconductors have attracted attention.

[0007] Further, it is known that the leakage current of a transistor using an oxide semiconductor is extremely low in a non-conducting state. For example, a low-power CPU and the like that utilize the characteristic of low leakage current of a transistor using an oxide semiconductor have been disclosed (see Patent Document 1). In addition, for example, a storage device and the like that achieve long-term retention of stored content by utilizing the characteristic of low leakage current of a transistor using an oxide semiconductor have been disclosed (see Patent Document 2).

[0008] In addition, in recent years, with the miniaturization and lightening of electronic devices, the requirement for higher density of integrated circuits has increased. In addition, an increase in the productivity of semiconductor devices including integrated circuits has also been demanded.

[0009] [Prior Art Documents]

[0010] [Patent Documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187

[0012] [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 Summary of the Invention

[0013] Technical Problem to be Solved by the Invention

[0014] One of the objects of one aspect of the present invention is to provide a semiconductor device capable of achieving miniaturization or high integration. One of the objects of one aspect of the present invention is to provide a semiconductor device having good electrical characteristics. One of the objects of one aspect of the present invention is to provide a semiconductor device having a large on-state current. One of the objects of one aspect of the present invention is to provide a semiconductor device having high frequency characteristics. One of the objects of one aspect of the present invention is to provide a semiconductor device having good reliability. One of the objects of one aspect of the present invention is to provide a semiconductor device having high productivity.

[0015] One of the objects of one aspect of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. One of the objects of one aspect of the present invention is to provide a semiconductor device having a fast data writing speed. One of the objects of one aspect of the present invention is to provide a semiconductor device having a high degree of design freedom. One of the objects of one aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption. One of the objects of one aspect of the present invention is to provide a novel semiconductor device.

[0016] Note that the description of the above objects does not preclude the existence of other objects. In addition, one aspect of the present invention does not need to achieve all of the above objects. Further, other objects than these are obvious from the description of the specification, drawings, claims, etc., and other objects than the above can be derived from the description of the specification, drawings, claims, etc.

[0017] Means for Solving the Technical Problem

[0018] One aspect of the present invention is a semiconductor device including a transistor, a capacitor, an electrode, and an interlayer film. The transistor includes a semiconductor layer, a gate, a source, and a drain. The transistor and the capacitor are disposed in a manner buried in the interlayer film. One of the source and the drain is in contact with the electrode below the semiconductor layer, and the other of the source and the drain is in contact with one electrode of the capacitor above the semiconductor layer.

[0019] In addition, in the above structure, it is preferable that an opening reaching the other of the source and the drain is provided in the interlayer film, and one electrode of the capacitor is disposed along the side surface and the bottom surface of the opening. In addition, in the above structure, an insulator may be provided between one electrode of the capacitor and the interlayer film. In addition, in the above structure, the semiconductor layer is preferably an oxide semiconductor.

[0020] Further, another aspect of the present invention is a semiconductor device including a first transistor and a capacitor. The first transistor includes first to fourth conductors, first to fourth insulators, first and second oxides. The first insulator is disposed on the first conductor, the first oxide is disposed on the first insulator, and a first opening reaching the first conductor is provided in the first insulator and the first oxide. The second conductor and the third conductor separated from each other are disposed on the first oxide. At least a part of the second conductor overlaps with the first opening and is in contact with the top surface of the first conductor. The second oxide is disposed on the first oxide in a manner that a part thereof overlaps with the region between the second conductor and the third conductor. The second insulator is disposed on the second oxide, the fourth conductor is disposed on the second insulator, the third insulator is disposed on the first insulator, the second conductor, and the third conductor, and the fourth insulator is disposed in contact with the top surface of the third insulator, the top surface of the second oxide, the top surface of the second insulator, and the top surface of the fourth conductor. A second opening reaching the third conductor is provided in the third insulator and the fourth insulator. The capacitor includes fifth and sixth conductors, and a fifth insulator. The fifth conductor is disposed in the second opening in contact with the top surface of the third conductor. The fifth insulator is disposed on the fifth conductor and the fourth insulator, and the sixth conductor is disposed on the fifth insulator.

[0021] In addition, in the above structure, a sixth insulator may be further included between the fifth conductor and the third insulator. In addition, in the above structure, the hydrogen permeability of the sixth insulator is preferably lower than that of the third insulator. In addition, in the above structure, in a plan view, it is preferable that the length of the fifth conductor in the channel width direction is shorter than the length of the first oxide in the channel width direction. In addition, in the above structure, the height of a part of the top surface of the fifth conductor may be substantially the same as the height of the top surface of the fourth insulator.

[0022] In addition, in the above structure, it is preferably further provided with a seventh conductor disposed under the first insulator and overlapping at least a part of the fourth conductor. In addition, in the above structure, the third conductor may also be in contact with the side surface of the first oxide in the first opening. In addition, in the above structure, it is preferably further provided with a seventh insulator disposed between the second conductor and the third conductor and the third insulator. In addition, in the above structure, the first oxide and the second oxide preferably contain In, element M (M is Al, Ga, Y or Sn), and Zn.

[0023] In addition, in the above structure, preferably, a second transistor is further provided under the first conductor, and the source or drain of the second transistor is electrically connected to the first conductor. In addition, in the above structure, the second transistor may also be formed on a silicon substrate. In addition, in the above structure, the second transistor may also contain a third oxide.

[0024] Advantages of the Invention

[0025] According to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device having a large on-state current can be provided. In addition, according to one aspect of the present invention, a semiconductor device having high-frequency characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device having good reliability can be provided. In addition, according to one aspect of the present invention, a semiconductor device having high productivity can be provided.

[0026] Alternatively, a semiconductor device capable of storing data for a long period can be provided. Alternatively, a semiconductor device having a fast data writing speed can be provided. Alternatively, a semiconductor device having a high degree of design freedom can be provided. Alternatively, a semiconductor device capable of suppressing power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. In addition, one aspect of the present invention does not necessarily have all of the above effects. In addition, effects other than these can be clearly understood from the description of the specification, drawings, claims, etc., and effects other than the above can be obtained from the description of the specification, drawings, claims, etc.

[0028] Brief Description of the Drawings

[0029] [Fig. 1](A)-(D) Top view and cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0030] Figure 2 Cross-sectional view of a semiconductor device according to one aspect of the present invention.​

[0031] [Figure 3](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0032] [Figure 4](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0033] [Figure 5](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0034] [Figure 6](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0035] [Figure 7](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0036] [Figure 8](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0037] [Figure 9](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0038] [Figure 10](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0039] [Figure 11](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0040] [Figure 12](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0041] [Figure 13](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0042] [Figure 14](A)-(D) show a top view and cross-sectional views of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

[0043] [Figure 15](A)-(D) are a top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.

[0044] [Figure 16](A)(B) are a top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.

[0045] Figure 17 ​A cross-sectional view showing the structure of a storage device according to one embodiment of the present invention.

[0046] Figure 18 A cross-sectional view showing the structure of a storage device according to one embodiment of the present invention.

[0047] Figure 19 A cross-sectional view showing the structure of a storage device according to one embodiment of the present invention.

[0048] Figure 20 A cross-sectional view showing the structure of a storage device according to one embodiment of the present invention.

[0049] Figure 21 A cross-sectional view showing the structure of a storage device according to one embodiment of the present invention.

[0050] [Fig. 22](A)(B) A block diagram showing an example of the structure of a storage device according to one embodiment of the present invention.

[0051] [Fig. 23](A)-(H) A circuit diagram showing an example of the structure of a storage device according to one embodiment of the present invention.

[0052] [Fig. 24](A)(B) A schematic diagram of a semiconductor device according to one embodiment of the present invention.

[0053] [Fig. 25](A)-(E) A schematic diagram of a storage device according to one embodiment of the present invention.

[0054] [Fig. 26](A)-(H) A diagram showing an electronic device according to one embodiment of the present invention.

[0055] Modes for Carrying Out the Invention

[0056] Hereinafter, embodiments will be described with reference to the accompanying drawings. However, those of ordinary skill in the art can easily understand the fact that the embodiments can be implemented in multiple different forms, and the modes and details can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following embodiments.

[0057] ​​​​In the drawings, for the sake of clear illustration, the sizes, thicknesses of layers, or regions are sometimes exaggerated. Therefore, the present invention is not necessarily limited to the above dimensions. In addition, in the drawings, ideal examples are schematically shown, and thus the present invention is not limited to the shapes, numerical values, etc. shown in the drawings. For example, in actual manufacturing processes, layers or resist masks, etc. may be unintentionally thinned due to processes such as etching, but sometimes this is not reflected in the drawings for the sake of understanding. Additionally, in the drawings, the same reference numerals are sometimes used commonly between different drawings to represent the same parts or parts having the same functions, and the repeated description thereof is omitted. Furthermore, when representing parts having the same functions, the same hatching is sometimes used without particularly attaching reference numerals.

[0058] In addition, especially in top views (also called plan views) or perspective views, etc., for the sake of understanding the invention, the description of some constituent elements is sometimes omitted. Additionally, the description of some hidden lines, etc. is sometimes omitted.

[0059] Moreover, in this specification, etc., for convenience, ordinal numbers such as first, second, etc. are added, and they do not indicate the process order or the stacking order. Therefore, for example, “first” can be appropriately replaced with “second” or “third”, etc. for explanation. In addition, the ordinal numbers described in this specification, etc. are sometimes inconsistent with the ordinal numbers used to specify one mode of the present invention.

[0060] In this specification, etc., for convenience, phrases indicating configuration such as “upper” and “lower” are used to describe the positional relationship of constituent elements with reference to the drawings. Additionally, the positional relationship of the constituent elements is appropriately changed according to the directions describing each constituent element. Therefore, it is not limited to the phrases described in this specification, and can be appropriately replaced according to the circumstances.

[0061] For example, in this specification, etc., when it is clearly described that “X is connected to Y”, it means the following situations: X is electrically connected to Y; X is functionally connected to Y; X is directly connected to Y. Therefore, it is not limited to the specified connection relationship (for example, the connection relationship shown in the drawings or in the text, etc.), and connection relationships other than those shown in the drawings or in the text are also included in the content described in the drawings or in the text.

[0062] Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, and layers, etc.).

[0063] In addition, in the case of using transistors with different polarities or when the current direction changes during the operation of a circuit, etc., the functions of the source and drain sometimes switch with each other. Therefore, in this specification, etc., the source and drain can sometimes be switched with each other.

[0064] In addition, in this specification and the like, depending on the structure of the transistor, the actual channel width (hereinafter also referred to as "effective channel width") in the region where the channel is formed and the channel width shown in the top view of the transistor (hereinafter also referred to as "apparent channel width") may be different. For example, when the gate electrode covers the side surface of the semiconductor, sometimes the effective channel width is greater than the apparent channel width, so its influence cannot be ignored. For example, in a miniaturized transistor where the gate electrode covers the side surface of the semiconductor, sometimes the proportion of the channel formation region formed on the side surface of the semiconductor increases. In this case, the effective channel width is greater than the apparent channel width.

[0065] In this case, it is sometimes difficult to estimate the effective channel width through actual measurement. For example, to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

[0066] In this specification, when simply described as "channel width", it sometimes refers to the apparent channel width. Or, in this specification, when simply described as "channel width", it sometimes refers to the effective channel width. Note that by analyzing a cross-sectional TEM image or the like, values such as the channel length, channel width, effective channel width, and apparent channel width can be determined.

[0067] Note that impurities in the semiconductor refer to elements other than the main component of the semiconductor. For example, an element with a concentration less than 0.1 atomic% can be said to be an impurity. Sometimes, due to the inclusion of impurities, for example, the DOS (Density of States) of the semiconductor becomes higher and the crystallinity decreases. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. When the semiconductor is an oxide semiconductor, sometimes water also acts as an impurity. In addition, when the semiconductor is an oxide semiconductor, sometimes, for example, the generation of oxygen vacancies is caused by the entry of impurities. Furthermore, when the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0068] Note that in this specification and the like, silicon oxynitride refers to a substance in which the oxygen content is greater than the nitrogen content. In addition, silicon nitride oxide refers to a substance in which the nitrogen content is greater than the oxygen content.

[0069] In this specification, etc., “insulator” may be referred to as “insulating film” or “insulating layer”. In addition, “conductor” may be referred to as “conductive film” or “conductive layer”. In addition, “semiconductor” may be referred to as “semiconductor film” or “semiconductor layer”.

[0070] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0071] Note that in this specification, a barrier film refers to a film having a function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, and when the barrier film has conductivity, it may be referred to as a conductive barrier film.

[0072] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS FET or an OS transistor can be referred to as a transistor containing an oxide or an oxide semiconductor.

[0073] Note that in this specification and the like, normally off means that when no potential is applied to the gate or a ground potential is applied to the gate, the current flowing through the transistor per channel width of 1 μm is 1×10 -20 Below A, 1×10 -18 A or less, or 1×10 -16 A or below.

[0074] (Implementation Method 1)

[0075] Next, an example of a semiconductor device including the transistor 200 and the capacitor 100 according to one embodiment of the present invention will be described.

[0076] <Structural Example of Semiconductor Device>

[0077] Figure 1A , Figure 1B , Figure 1C and Figure 1D1 and 2 are a top view and a cross-sectional view of a semiconductor device including a transistor 200 and a capacitor 100 according to one embodiment of the present invention.

[0078] Figure 1A 1 is a top view of a semiconductor device including a transistor 200 and a capacitor 100 . Figure 1B , Figure 1C and Figure 1D is a cross-sectional view of the semiconductor device. Figure 1B It is along Figure 1A The cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. 1 is equivalent to a cross-sectional view of the transistor 200 in the channel length direction. Figure 1C It is along Figure 1A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. 1 is equivalent to a cross-sectional view of the transistor 200 in the channel width direction. Figure 1D It is along Figure 1A The cross-sectional view of the portion of the dot-dash line A5-A6 in FIG. 1 is equivalent to a cross-sectional view of the source region or drain region of the transistor 200 in the channel width direction. Figure 1A Some components are omitted in the top view.

[0079] A semiconductor device according to one embodiment of the present invention includes an insulator 214 on a substrate (not shown), a transistor 200 on the insulator 214, an insulator 280 on an insulator 256 provided in the transistor 200, an insulator 282 on the insulator 280, and an insulator 281 on the insulator 282. The insulator 214, the insulator 280, the insulator 282, and the insulator 281 are used as interlayer films. As shown in FIG. 1 , at least a portion of the transistor 200 and the capacitor 100 are buried in the insulator 280.

[0080] Here, the transistor 200 includes a semiconductor layer, a first gate, a second gate, a source, and a drain. In addition, the conductor 247 is provided below the semiconductor layer of the transistor 200. One of the source and the drain of the transistor 200 contacts the conductor 247 below the semiconductor layer, and the other of the source and the drain of the transistor 200 contacts one electrode of the capacitor 100 above the semiconductor layer.

[0081] The capacitor 100 is provided in an opening formed in the insulators 256, 280, 282, and 281 and reaching the other of the source and the drain of the transistor 200. The capacitor 100 includes a conductor 110 in contact with the top surface of the other of the source and the drain of the transistor 200 in the opening, an insulator 130 disposed on the conductor 110 and the insulator 281, and a conductor 120 disposed on the insulator 130. Here, the conductor 110 is preferably disposed along the side surface and the bottom surface of the opening.

[0082] In addition, an insulator 241 is preferably provided between the conductor 110 and the insulator 280. The insulator 241 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.). In addition, the insulator 241 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). For example, the permeability of one or both of oxygen and hydrogen in the insulator 241 is preferably lower than that of the insulator 280.

[0083] [Transistor 200]

[0084] Hereinafter, a typical structure of the transistor 200 will be described. Note that the structure of the transistor 200 below is merely one mode according to an embodiment of the present invention, and the present invention is not limited thereto. The structure of the transistor 200 can be appropriately changed according to the functions required for the semiconductor device.

[0085] As shown in FIG. 1, the transistor 200 includes: an insulator 216 on an insulator 214; a conductor 205 disposed in a buried manner in the insulator 216; an insulator 222 on the insulator 216 and the conductor 205; an insulator 224 on the insulator 222; an oxide 230a on the insulator 224; an oxide 230b on the oxide 230a; a conductor 242a and a conductor 242b on the oxide 230b; an oxide 230c on the oxide 230b; an insulator 250 on the oxide 230c; a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping the oxide 230c; an insulator 256 in contact with a part of the top surface of the insulator 224, the side surfaces of the oxide 230a, the side surfaces of the oxide 230b, the side surface of the conductor 242a, the top surface of the conductor 242a, the side surface of the conductor 242b, and the top surface of the conductor 242b. In addition, the oxide 230c is in contact with the side surfaces of the conductor 242a and the conductor 242b. The conductor 260 includes the conductor 260a and the conductor 260b, and the conductor 260a is disposed so as to surround the bottom surface and the side surfaces of the conductor 260b. Here, as Figure 1B shown, the height of the top surface of the conductor 260 is substantially the same as the height of the top surface of the insulator 250, the top surface of the oxide 230c, and the top surface of the insulator 280. In addition, the insulator 282 is in contact with the top surface of each of the conductor 260, the oxide 230c, the insulator 250, and the insulator 280.

[0086] In addition, an opening is formed in the insulator 216, and the above-mentioned conductor 247 is disposed in the opening. At least a part of the top surface of the conductor 247 protrudes from the insulator 216, and the height of the top surface of the conductor 247 and the height of the top surface of the insulator 216 are preferably substantially the same.

[0087] Here, the conductor 247 is used as a plug or wiring that electrically connects circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, wirings, electrodes, or terminals of a layer provided below the insulator 214 to the transistor 200. For example, a structure in which the conductor 247 is electrically connected to the gate, source, or drain of a transistor of a layer provided below the insulator 214 can be employed.

[0088] In addition, openings are formed in the insulator 222, insulator 224, oxide 230a, and oxide 230b to expose at least a part of the conductor 247. The conductor 242a is disposed on the oxide 230b and contacts at least a part of the top surface of the conductor 247 through the opening. In addition, the conductor 242a may also contact the side surfaces of the oxide 230a and the oxide 230b in the opening. Thus, by connecting the conductor 242a to the conductor 247, the resistance between the source or drain of the transistor 200 and the conductor 247 can be reduced. By adopting the above structure, the frequency characteristics and electrical characteristics of the semiconductor device including the transistor 200 can be improved.

[0089] In addition, at least a part of the circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, wirings, electrodes, or terminals electrically connected to the conductor 247 preferably overlaps the oxide 230. Thereby, the occupied area in plan view of the transistor 200, the above circuit elements, wirings, electrodes, or terminals can be reduced, and thus miniaturization or high integration of the semiconductor device according to the present embodiment can be achieved.

[0090] In addition, the semiconductor device shown in the present embodiment can be used as a storage cell of a storage device. At this time, the conductor 247 is sometimes electrically connected to a sense amplifier. When the parasitic capacitance of the conductor 247 and the wiring connecting the conductor 247 and the sense amplifier is much larger than the electrostatic capacitance of the capacitor 100, the sense amplifier sometimes does not function.

[0091] However, in the semiconductor device according to the present embodiment, since the conductor 247 is provided under the oxide 230, the parasitic capacitance is reduced compared to the case where the conductor 247 is provided on the conductor 242a. When the conductor 247 is provided under the oxide 230, it is not necessary to route the wiring on the transistor 200, so the wiring connecting the conductor 247 and the sense amplifier can be shortened and the parasitic capacitance of the wiring can be reduced. And, by providing the conductor 247 under the oxide 230, the parasitic capacitance generated between the conductor 247 and the conductor 260 and the parasitic capacitance generated between the conductor 247 and the conductor 120 can be reduced.

[0092] Thus, by reducing the parasitic capacitance of the conductor 247 and the wiring connected to the conductor 247, the required capacitance of the capacitor 100 can be made smaller. Thereby, the size of the capacitor 100 can be reduced. For example, as Figure 1A shown, the capacitor 100 can be arranged such that it is within the range of the oxide 230b in a plan view. At this time, the length of the conductor 110 in the channel width direction is smaller than the length of the oxide 230b in the channel width direction. Therefore, in a plan view, the capacitor 100 can be arranged without increasing the occupied area, and thus miniaturization or high integration of the semiconductor device according to the present embodiment can be achieved.

[0093] In addition, although the structure in which the conductor 247 is provided under the conductor 242a is adopted in Figure 1A and Figure 1B , the semiconductor device shown in the present embodiment is not limited thereto. For example, a structure in which the conductor 247 is provided under the conductor 242b can be adopted, or a structure in which the conductor 247 is provided under both the conductor 242a and the conductor 242b can be adopted.

[0094] In addition, the insulators 214, 222, 256, 282, and 281 preferably have a function of suppressing the diffusion of at least one of hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). In addition, the insulators 214, 222, 256, 282, and 281 preferably have a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the permeability of one or both of oxygen and hydrogen of the insulators 214, 222, 256, 282, and 281 is preferably lower than that of any one of the insulators 224, 250, or 280.

[0095] As Figure 1B shown, the conductors 242a and 242b are provided on the oxide 230b, and the insulator 256 preferably contacts the top surface and side surfaces of the conductor 242a, the top surface and side surfaces of the conductor 242b, the side surfaces of the oxide 230b, the side surfaces of the oxide 230a, and the top surface of the insulator 224. In addition, the insulator 256 can have a single-layer structure or a stacked structure. Thereby, in the portions other than the above openings, that is, on the peripheral side surfaces, the side surfaces of the oxide 230a and the oxide 230b do not contact the conductors 242a and 242b. The insulator 280 is separated from the insulator 256, the insulator 224, the oxide 230a, and the oxide 230b.

[0096] The conductor 260 is used as the gate electrode of the transistor, and the conductors 242a and 242b are used as the source electrode or the drain electrode, respectively. In the transistor 200, the conductor 260 used as the gate electrode is formed self-alignedly in such a manner as to fill the opening formed in the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be surely disposed in the region between the conductors 242a and 242b without alignment.

[0097] In addition, the oxide 230 preferably includes an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b and at least a part of which contacts the top surface of the oxide 230b.

[0098] Note that in the transistor 200, in the region where the channel is formed (hereinafter, also referred to as the channel formation region) and in its vicinity, the oxide 230 has a stacked structure of three layers of the oxides 230a, 230b, and 230c, but the present invention is not limited thereto. For example, the oxide 230 may have a single-layer structure of the oxide 230b, a two-layer structure of the oxides 230b and 230a, a two-layer structure of the oxides 230b and 230c, or a stacked structure of four or more layers. In addition, the oxides 230a, 230b, and 230c may each have a stacked structure of two or more layers.

[0099] In addition, it is preferable to use, in the transistor 200, a metal oxide (hereinafter, sometimes referred to as an oxide semiconductor) to be used as the oxide semiconductor for the oxide 230 (the oxides 230a, 230b, and 230c) including the channel formation region.

[0100] Since the transistor 200 using the oxide semiconductor for the channel formation region has an extremely small leakage current (off-state current) in the non-conducting state, a semiconductor device with low power consumption can be provided. In addition, since the oxide semiconductor can be formed by a sputtering method or the like, it can be used for the transistor 200 constituting a highly integrated semiconductor device.

[0101] For example, as the oxide 230, a metal oxide such as In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, etc.) is preferably used. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. In addition, In-Ga oxide or In-Zn oxide may also be used as the oxide 230.

[0102] Here, when there are impurities such as hydrogen, nitrogen, or metal elements in the oxide 230, sometimes the carrier density increases and the resistance decreases. Further, when the oxygen concentration of the oxide 230 decreases, sometimes the carrier density increases and the resistance decreases.

[0103] When the conductor 242 (conductor 242a and conductor 242b) used as the source electrode or the drain electrode is provided in contact with the oxide 230b and has a function of absorbing oxygen of the oxide 230 or has a function of supplying impurities such as hydrogen, nitrogen, or metal elements to the oxide 230, sometimes a low-resistance region is partially formed in the oxide 230. The conductor 242 is formed on the oxide 230b, and in a portion other than the opening reaching the conductor 247, that is, on the peripheral side surface, the conductor 242 does not contact the side surfaces of the oxide 230a and the oxide 230b or the insulator 224. Thereby, oxidation of the conductor 242 by oxygen contained in at least one of the oxide 230a, the oxide 230b, and the insulator 224 can be suppressed. Further, oxygen contained in the oxide 230a and the oxide 230b, particularly oxygen contained in the channel formation region and its vicinity, can be suppressed from being absorbed by the conductor 242 from the side surfaces of the oxide 230a and the oxide 230b.

[0104] The insulator 256 is provided so that the side surfaces of the oxide 230a and the oxide 230b do not directly contact the insulator 280. Further, the insulator 256 is provided to suppress oxidation of the conductor 242. However, when the conductor 242 is an oxidation-resistant material or even if the conductor 242 absorbs oxygen, its conductivity does not significantly decrease, the insulator 256 does not necessarily have an effect of suppressing oxidation of the conductor 242.

[0105] By providing the insulator 256, supply of oxygen contained in the insulator 280 from the side surfaces of the oxide 230a and the oxide 230b can be suppressed.

[0106] Here, Figure 2 shows Figure 1B an enlarged view of the vicinity of the channel formation region in

[0107] As Figure 2 shown, the conductor 242 is provided in contact with the oxide 230b, and regions 249 (regions 249a and 249b) are formed as low-resistance regions at the interface between the oxide 230 and the conductor 242 and in the vicinity thereof. The oxide 230 includes a region 234 used as the channel formation region of the transistor 200, regions 231 (regions 231a and 231b) used as the source region or the drain region, and regions 232 (regions 232a and 232b) between the region 234 and the region 231. Here, the region 231 includes the region 249. Further, inFigure 2 An example where the oxide 230c has a single-layer structure is shown, but the present embodiment is not limited thereto. The oxide 230c may also have a stacked structure of two or more layers.

[0108] In the region 231 used as a source region or a drain region, particularly in the region 249, the carrier concentration increases and the resistance decreases because the oxygen concentration is low or impurities such as hydrogen, nitrogen, or metal elements are contained. In other words, the region 231 is a region with a higher carrier density and a lower resistance compared to the region 234. In addition, the region 234 used as a channel formation region has a higher oxygen concentration or a lower impurity concentration compared to the region 231, particularly compared to the region 249, so it is a high-resistance region with a low carrier density. In addition, the oxygen concentration in the region 232 is preferably equal to or higher than the oxygen concentration in the region 231, and preferably equal to or lower than the oxygen concentration in the region 234. Alternatively, the impurity concentration in the region 232 is preferably equal to or lower than the impurity concentration in the region 231, and preferably equal to or higher than the impurity concentration in the region 234.

[0109] That is, since the region 232 has a resistance value similar to that of the region 234 due to the concentration of oxygen or impurities contained therein, the region 232 may sometimes be used as a channel formation region in the same manner as the region 234, sometimes be used as a low-resistance region having a resistance value similar to that of the region 231, or sometimes be used as a low-resistance region having a resistance higher than that of the region 231 and lower than that of the region 234. In particular, when a part of the oxide 230 has CAAC-OS described later, the impurities contained in the region 231 tend to diffuse in the a-b plane direction, and the region 232 sometimes has a lower resistance.

[0110] In addition, when the region 249 as a low-resistance region contains a metal element, the region 249 preferably contains one or more of metal elements such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum in addition to the metal elements contained in the oxide 230.

[0111] In addition, in Figure 2 ..., the region 249 is formed near the interface between the oxide 230b and the conductor 242 in the thickness direction of the oxide 230b, but the present embodiment is not limited thereto. For example, the thickness of the region 249 may be substantially the same as the thickness of the oxide 230b, and the region 249 may also be formed in the oxide 230a. In addition, in Figure 2In this case, the region 249 is only formed in the region 231, but the present embodiment is not limited thereto. As described above, when diffusing in the a-b plane direction of the impurity, the region 249 may be formed in the regions 231 and 232, may be formed in a part of the regions 231 and 232, or may be formed in a part of the regions 231, 232, and 234.

[0112] In the oxide 230, it is sometimes difficult to clearly observe the boundaries of the respective regions. The concentrations of the metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not have to change stepwise for each region, and may gradually change (also referred to as gradation) in each region. That is, the concentrations of the metal elements and impurity elements such as hydrogen and nitrogen may be smaller as approaching the channel formation region.

[0113] In order to selectively reduce the resistance of the oxide 230, as the conductor 242, a material containing at least one of the metal elements and impurities that improve conductivity such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum is preferably used. Alternatively, when forming the conductive film 242A that becomes the conductor 242, a material or film formation method that injects impurities such as elements that form oxygen vacancies or elements captured by oxygen vacancies into the oxide 230 may be used. For example, as such elements, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and rare gas elements can be cited. In addition, as typical examples of the rare gas elements, helium, neon, argon, krypton, and xenon can be cited.

[0114] Here, in a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the region where the channel is formed in the oxide semiconductor, the electrical characteristics are likely to change, and the reliability sometimes decreases. In addition, when the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor tends to have a normally-on characteristic. Therefore, the oxygen vacancies in the channel formation region 234 are reduced as much as possible.

[0115] In order to suppress the normally-on state of the transistor, it is preferable that the insulator 250 adjacent to the oxide 230 contains oxygen in excess of the stoichiometric composition (also referred to as excess oxygen). The oxygen contained in the insulator 250 diffuses into the oxide 230, reducing the oxygen vacancies in the oxide 230, thereby suppressing the normally-on state of the transistor.

[0116] In other words, by diffusing the oxygen contained in the insulator 250 into the region 234 of the oxide 230, the oxygen vacancies in the region 234 of the oxide 230 can be reduced. Additionally, by diffusing the oxygen contained in the insulator 280 through the oxide 230c into the region 234 of the oxide 230, the oxygen vacancies in the region 234 of the oxide 230 can be reduced. At this time, a stacked structure is adopted for the oxide 230c, and a material through which oxygen easily permeates is used for the layer of the oxide 230c that contacts the insulator 280. Thereby, the oxygen contained in the insulator 280 can be easily diffused into the region 234 of the oxide 230 through this layer of the oxide 230c. Furthermore, by using a material that does not easily permeate oxygen for the layer of the oxide 230c that does not contact the insulator 280, the oxygen contained in the insulator 280 can be prevented from diffusing into the insulator 250 or the conductor 260, and the oxygen of the insulator 280 can be efficiently supplied to the region 234 of the oxide 230.

[0117] By adopting the above structure, the supply amount of oxygen to the oxide 230 can be controlled, and a transistor with high reliability and suppressed normally-on characteristics can be obtained.

[0118] In the transistor 200 according to one embodiment of the present invention, as Figure 1B and Figure 1C shown, the insulator 282 is in direct contact with the insulator 250. By adopting this structure, the oxygen contained in the insulator 280 is not easily absorbed by the conductor 260. Therefore, the oxygen contained in the insulator 280 is efficiently supplied to the oxide 230a and the oxide 230b through the oxide 230c. Thus, the oxygen vacancies in the oxide 230a and the oxide 230b can be reduced, and thereby the electrical characteristics and reliability of the transistor 200 can be improved. In addition, since impurities such as hydrogen contained in the insulator 280 can be prevented from mixing into the insulator 250, the negative impact on the electrical characteristics and reliability of the transistor 200 can be suppressed. As the insulator 282, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide can be used. As the insulator 282, silicon nitride is preferably used. This silicon nitride can appropriately block impurities (e.g., hydrogen, water, etc.) that may enter from the outside.

[0119] The insulator 256 preferably has a function of suppressing the permeation of impurities such as hydrogen or water and oxygen. The insulator 256 can be a single layer or a laminated structure of two or more layers. As the insulator 256, for example, alumina, hafnium oxide, silicon oxide film, silicon nitride film, or silicon oxynitride film can be used. In addition, when the laminated insulator 256 is adopted, the upper layer and the lower layer can use the same material or different materials. When the laminated insulator 256 is adopted and the upper layer and the lower layer use the same material, different film formation methods can also be used to form the upper layer and the lower layer of the insulator 256. For example, the lower layer of the insulator 256 can be formed by a sputtering method, and the upper layer of the insulator 256 can be formed by an ALD (Atomic Layer Deposition) method. In addition, the lower layer of the insulator 256 can be formed by an ALD method, and the upper layer of the insulator 256 can be formed by a sputtering method. In addition, as the insulator 256, the material that can be used for the oxide 230 can also be used. At this time, as the insulator 256, a metal oxide of In:Ga:Zn = 1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio], which is an oxide that is not easily permeable to oxygen, can be used.

[0120] Figure 1D is along Figure 1A the cross-sectional view of the part along the dotted line A5 - A6 in, and this cross-sectional view corresponds to the cross-sectional view in the channel width direction of the source region or the drain region of the transistor 200. As Figure 1D shown, since the top surface and the side surface of the conductor 242b are covered by the insulator 256, diffusion of impurities such as hydrogen or water and oxygen from the side surface and the top surface direction of the conductor 242b into the conductor 242b can be suppressed. Therefore, since diffusion of oxygen from the periphery of the conductor 242b into the conductor 242b can be suppressed, oxidation of the conductor 242b can be suppressed. Note that the same effect also applies to the conductor 242a. In addition, diffusion of impurities such as hydrogen or water from the side surface direction of the oxide 230a and the side surface direction of the oxide 230b into the oxide 230a and the oxide 230b can be suppressed.

[0121] As Figure 1C shown, with the bottom surface of the insulator 224 as a standard, the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is preferably lower than the height of the bottom surface of the oxide 230b. In addition, the difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230b does not overlap with the conductor 260 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0122] In this way, the conductor 260 used as the gate electrode covers the side and top surfaces of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250. This structure makes it easy for the electric field of the conductor 260 to act on the entire oxide 230b in the channel formation region. Therefore, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0123] As described above, a semiconductor device that realizes miniaturization or high integration can be provided. Alternatively, a semiconductor device including a transistor with a large on-state current can be provided. In addition, a semiconductor device including a transistor with high frequency characteristics can be provided. In addition, a semiconductor device that suppresses the variation of electrical characteristics and realizes a stable electrical characteristic and improves reliability can be provided. In addition, a semiconductor device including a transistor with a small off-state current can be provided.

[0124] Next, a detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

[0125] The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably provided so as to be buried in the insulator 216.

[0126] Here, the conductor 260 is sometimes used as a first gate (also called a top gate) electrode. In addition, the conductor 205 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the Vth of the transistor 200 can be controlled by independently changing the potential supplied to the conductor 205 without linking it with the potential supplied to the conductor 260. In particular, by supplying a negative potential to the conductor 205, the Vth of the transistor 200 can be made greater than 0V and the off-state current can be reduced. Therefore, compared with when a negative potential is not applied to the conductor 205, when a negative potential is applied to the conductor 205, the drain current when the potential supplied to the conductor 260 is 0V can be reduced.

[0127] In addition, if Figure 1A As shown in FIG. 1 , the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap the conductors 242a and 242b. In particular, Figure 1CAs shown, the conductor 205 preferably extends to a region outside the end of the oxide 230 that intersects the channel width direction. That is, preferably outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 overlap with each other with an insulator therebetween. Alternatively, by providing a larger conductor 205, in a plasma treatment in a manufacturing process after the formation of the conductor 205, local charging (also referred to as charge up) can sometimes be alleviated. Note that one aspect of the present invention is not limited thereto. The conductor 205 only needs to overlap at least the oxide 230 located between the conductor 242a and the conductor 242b.

[0128] By having the above structure, the channel formation region can be electrically surrounded by the electric field of the conductor 260 used as the first gate electrode and the electric field of the conductor 205 used as the second gate electrode. In the present specification, the structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0129] In addition, as the first conductor of the conductor 205, a conductor that suppresses the permeation of impurities such as water, hydrogen, and oxygen is preferably used. For example, a single layer or a stacked layer of titanium, titanium nitride, tantalum, or tantalum nitride can be used. As the second conductive layer of the conductor 205, a conductor having high adhesion to the first conductive layer and the third conductive layer may be used. As the third conductive layer of the conductor 205, a conductive material mainly composed of tungsten, copper, or aluminum is preferably used. Note that here the conductor 205 has three layers, but a single layer structure or a two-layer structure can be adopted, or a multi-layer structure of four or more layers can also be adopted.

[0130] The insulators 214, 256, 282, and 281 are preferably used as barrier insulating films that suppress the entry of impurities such as water or hydrogen from the substrate side or from above into the transistor 200. Therefore, as the insulators 214, 256, 282, and 281, an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (not easily permeable to the above impurities) is preferably used. In addition, an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not easily permeable to the above oxygen) is preferably used.

[0131] As the insulators 214, 256, 282, and 281, alumina, hafnium oxide, silicon nitride, or the like is preferably used. For example, alumina may be used as the insulators 214, 256, and 282, and aluminum nitride may be used as the insulator 281. Thereby, diffusion of impurities such as water or hydrogen into the insulator 224, the oxide 230, and the insulator 250 can be suppressed.

[0132] In addition, it is sometimes preferable to reduce the resistivity of the insulators 214, 256, 282, and 281. For example, by setting the resistivity of the insulators 214, 256, 282, and 281 to about 1×10 13 Ωcm, in a process such as plasma treatment in the semiconductor device manufacturing process, the insulators 214, 256, 282, and 281 can mitigate charge accumulation in the conductors 205, 242, or 260. The resistivity of the insulators 214, 256, 282, and 281 is preferably 1×10 10 Ωcm or more and 1×10 15 Ωcm or less.

[0133] In addition, the insulator 214 may have a stacked structure. For example, it is preferable to use an alumina film for the upper layer of the insulator 214 and a silicon nitride film for the lower layer of the insulator 214. The alumina film can supply oxygen below the insulator 214. In addition, the silicon nitride film can suppress diffusion of impurities such as hydrogen and water from the substrate side to the transistor 200 side.

[0134] Furthermore, the dielectric constants of the insulators 216 and 280 are preferably lower than that of the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, as the insulators 216 and 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine - added silicon oxide, carbon - added silicon oxide, carbon - and - nitrogen - added silicon oxide, or silicon oxide with voids, etc. may be appropriately used.

[0135] The insulators 222 and 224 are used as gate insulators.

[0136] Here, in the insulator 224 in contact with the oxide 230, it is preferable to remove oxygen by heating. In this specification, the oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride, etc. may be appropriately used as the insulator 224. By providing an oxygen - containing insulator in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0137] Specifically, as the insulator 224, an oxide material in which a part of oxygen is removed by heating is preferably used. The oxide in which oxygen is removed by heating means that the amount of oxygen desorbed and converted into oxygen molecules in TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 molecules / cm 3 or more, preferably 1.0×10 19 molecules / cm 3 or more, more preferably 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 or more of the oxide. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0138] The insulator 222 is preferably used as a barrier insulating film for suppressing the mixing of impurities such as water or hydrogen from the substrate side into the transistor 200. For example, the oxygen permeability of the insulator 222 is preferably lower than that of the insulator 224. By surrounding the insulator 224 and the oxide 230, etc. with the insulator 222 and the insulator 256, the intrusion of impurities such as water or hydrogen from the outside into the transistor 200 can be suppressed.

[0139] Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (it is not easy for the above oxygen to permeate). For example, the oxygen permeability of the insulator 222 is preferably lower than that of the insulator 224. By making the insulator 222 have a function of suppressing the diffusion of oxygen or impurities, the oxygen contained in the oxide 230 diffusing to below the insulator 222 can be reduced, so it is preferable. In addition, the reaction between the conductor 205 and the oxygen contained in the insulator 224 and the oxide 230 can be suppressed.

[0140] The insulator 222 is preferably an insulator using an oxide containing one or both of aluminum and hafnium as an insulating material. As the insulator using an oxide containing one or both of aluminum and hafnium, alumina, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When using such a material to form the insulator 222, the insulator 222 is used as a layer for suppressing the release of oxygen from the oxide 230 or the entry of impurities such as hydrogen from the peripheral part of the transistor 200 into the oxide 230.

[0141] Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-described insulator. In addition, the above-described insulator may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above-described insulator.

[0142] In addition, as the insulator 222, for example, an insulator including a so-called high-k material such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) may be used as a single layer or a laminate. When miniaturizing and highly integrating a transistor, problems such as leakage current sometimes occur due to thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0143] In addition, the insulator 222 and the insulator 224 may also have a laminated structure of two or more layers. At this time, it is not limited to a laminated structure composed of the same material, and a laminated structure composed of different materials may also be used.

[0144] Similar to the conductor 205, the conductor 247 may also adopt a structure including a first conductive layer, a second conductive layer disposed inside the first conductive layer, and a third conductive layer disposed inside the second conductive layer. As the first conductive layer of the conductor 247, a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, titanium, titanium nitride, tantalum, or tantalum nitride may be used. As the second conductive layer of the conductor 247, a conductor having high adhesion to the first conductive layer and the third conductive layer may be used. As the third conductive layer of the conductor 247, a conductive material mainly composed of tungsten, copper, or aluminum is preferably used. Note that here the conductor 247 has three layers, but it may also adopt a single-layer structure or a two-layer structure, or a multi-layer structure of four or more layers.

[0145] In addition, an insulator that suppresses the diffusion of impurities such as hydrogen or water and oxygen, such as the insulator 241, may be provided on the side surface of the conductor 247.

[0146] The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. Here, the oxide 230c is disposed such that at least a part thereof overlaps with the region between the conductor 242a and the conductor 242b. When the oxide 230a is provided under the oxide 230b, diffusion of impurities from the structure formed under the oxide 230a to the oxide 230b can be suppressed. When the oxide 230c is provided on the oxide 230b, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.

[0147] In addition, the oxide 230 preferably has a stacked structure of oxides in which the atomic ratios of the respective metal atoms are different from each other. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is preferably greater than the atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of the element M relative to In is preferably greater than the atomic ratio of the element M relative to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In relative to the element M is preferably greater than the atomic ratio of In relative to the element M in the metal oxide used for the oxide 230a. In addition, as the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

[0148] In addition, the oxide 230b preferably has crystallinity. For example, the following CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used. An oxide having crystallinity such as CAAC-OS has a highly crystalline and dense structure with few impurities and defects (such as oxygen vacancies). Therefore, it is possible to suppress the source electrode or the drain electrode from extracting oxygen from the oxide 230b. Therefore, even when a heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is also stable with respect to a high temperature (so-called thermal budget) in the manufacturing process.

[0149] Preferably, the energy of the bottom of the conduction band of the oxides 230a and 230c is higher than the energy of the bottom of the conduction band of the oxide 230b. In other words, the electron affinity of the oxides 230a and 230c is preferably smaller than the electron affinity of the oxide 230b.

[0150] Here, at the junction of the oxides 230a, 230b, and 230c, the energy level of the bottom of the conduction band changes smoothly. In other words, the above situation can also be expressed as the energy level of the bottom of the conduction band of the junction of the oxides 230a, 230b, and 230c changing continuously or being continuously joined. For this purpose, it is preferable to reduce the density of defect states in the mixed layer formed at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c.

[0151] Specifically, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] can be used as the oxide 230a. In addition, a metal oxide with In:Ga:Zn = 4:2:3 [atomic ratio] or 1:1:1 [atomic ratio] can be used as the oxide 230b. In addition, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio], In:Ga:Zn = 4:2:3 [atomic ratio], Ga:Zn = 2:1 [atomic ratio], or Ga:Zn = 2:5 [atomic ratio] can be used as the oxide 230c. In addition, as a specific example in the case where the oxide 230c has a stacked structure, a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] for the lower layer of the oxide 230c and In:Ga:Zn = 1:3:4 [atomic ratio] for the upper layer of the oxide 230c, a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] for the lower layer of the oxide 230c and Ga:Zn = 2:1 [atomic ratio] for the upper layer of the oxide 230c, a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] for the lower layer of the oxide 230c and Ga:Zn = 2:5 [atomic ratio] for the upper layer of the oxide 230c, a stacked structure of In:Ga:Zn = 4:2:3 [atomic ratio] for the lower layer of the oxide 230c and gallium oxide for the upper layer of the oxide 230c, etc. can be cited.

[0152] At this time, the main path of carriers is the oxide 230b. By making the oxide 230a and the oxide 230c have the above structures, the density of defect states at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and thus the transistor 200 can obtain a large on-state current and high-frequency characteristics. In addition, when the oxide 230c has a stacked structure, an effect of reducing the density of defect states at the interface between the oxide 230b and the oxide 230c and an effect of suppressing the diffusion of constituent elements contained in the oxide 230c to the insulator 250 side are expected. More specifically, when the oxide 230c has a stacked structure, since an oxide that does not contain In or has a reduced In concentration is located in the upper layer of the stacked structure, In that would diffuse to the insulator 250 side can be suppressed. Since the insulator 250 is used as a gate insulator, the characteristics of the transistor deteriorate when In diffuses therein. Thus, by making the oxide 230c have a stacked structure, a semiconductor device with high reliability can be provided.

[0153] In addition, since the oxide 230c has a stacked structure, sometimes the main path of carriers is at the interface between the oxide 230b and the lower layer of the oxide 230c and in its vicinity.

[0154] In addition, since the lower layer of the oxide 230c is in contact with the side surface of the insulator 280, oxygen contained in the insulator 280 can be supplied to the channel formation region of the transistor 200 through the lower layer of the oxide 230c. In addition, a material that does not easily transmit oxygen is preferably used for the upper layer of the oxide 230c. By using the above materials, it is possible to suppress oxygen contained in the insulator 280 from passing through the upper layer of the oxide 230c and being absorbed by the insulator 250 or the conductor 260, and thus oxygen can be efficiently supplied to the channel formation region.

[0155] In addition, the oxide 230 includes a region 231 and a region 234. Note that at least a part of the region 231 is in contact with the region of the conductor 242.

[0156] Note that when the transistor 200 is in the on state, one of the regions 231a and 231b is used as the source region and the other is used as the drain region. On the other hand, at least a part of the region 234 is used as the region for forming a channel.

[0157] Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting requirements according to circuit design.

[0158] As the oxide 230, a metal oxide used as an oxide semiconductor is preferably used. For example, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. Thus, by using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced. By adopting such a transistor, a low-power semiconductor device can be provided.

[0159] The electron affinity or the bottom energy level Ec of the conduction band can be calculated from the ionization potential Ip, which is the difference between the vacuum level and the energy level Ev of the valence band top, and the band gap Eg. The ionization potential Ip can be measured using, for example, an ultraviolet photoelectron spectroscopy (UPS) apparatus. The band gap Eg can be measured using, for example, a spectroscopic ellipsometer.

[0160] A conductor 242 (conductor 242a and conductor 242b) used as a source electrode and a drain electrode is provided on the oxide 230b. The thickness of the conductor 242 is, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0161] As the conductor 242, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal element as a component, or an alloy combining the above metal elements, etc. are preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred.

[0162] The insulator 250 is used as a gate insulator. The insulator 250 is preferably disposed in contact with the top surface of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores. In particular, silicon oxide and silicon oxynitride have thermal stability, so they are preferred.

[0163] Similar to the insulator 224, the insulator 250 can also be formed of an insulator that releases oxygen by heating. By setting the insulator that releases oxygen by heating as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be efficiently supplied to the channel formation region of the oxide 230b. Similar to the insulator 224, it is preferable to reduce the concentration of impurities such as water or hydrogen in the insulator 250. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0164] In addition, a metal oxide can be provided between the insulator 250 and the conductor 260. This metal oxide preferably inhibits the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that inhibits oxygen diffusion, the oxygen diffusion from the insulator 250 to the conductor 260 is inhibited. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be inhibited. In addition, oxidation of the conductor 260 caused by oxygen in the insulator 250 can be inhibited.

[0165] In addition, the metal oxide is sometimes used as part of the gate insulator. Therefore, in the case where silicon oxide or silicon oxynitride is used for the insulator 250, a metal oxide as a high-k material having a high relative dielectric constant is preferably used as the metal oxide. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, a laminated structure having thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0166] Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used. In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators as oxides containing one or both of aluminum and hafnium, are preferably used.

[0167] Alternatively, the metal oxide is sometimes used as part of the gate electrode. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0168] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the metal oxide forming the channel is preferably used. In addition, a conductive material containing the above metal element and nitrogen can also be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon can be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, it is sometimes possible to capture hydrogen contained in the metal oxide forming the channel. Or, it is sometimes possible to capture hydrogen entering from an external insulator or the like.

[0169] In addition, in the transistor 200, the conductor 260 has a two-layer laminated structure, but the present invention is not limited thereto. For example, the conductor 260 can also have a single-layer structure or a laminated structure of three or more layers.

[0170] As the conductor 260a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. is preferably used. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is preferably used.

[0171] In addition, when the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity caused by the oxidation of the conductor 260b by the oxygen contained in the insulator 250. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0172] In addition, as the conductor 260b, a conductive material mainly composed of tungsten, copper, or aluminum is preferably used. In addition, since the conductor 260 is also used as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. In addition, the conductor 260b can have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above conductive material.

[0173] For example, the insulator 280 preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores, etc. In particular, since silicon oxide and silicon oxynitride have thermal stability, they are preferred. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferred because they easily form regions containing oxygen that is released by heating. In order to supply the oxygen contained in the insulator 280 to the lower layer of the oxide 230b through the oxide 230c or the oxide 230c, the insulator 280 preferably contains further oxygen, for example, the insulator 280 preferably contains more oxygen than the stoichiometric ratio. In order to increase the oxygen concentration contained in the insulator 280, the deposition gas used for the formation of the insulator 280 preferably contains oxygen.

[0174] The impurity concentration of water or hydrogen, etc. in the insulator 280 is preferably reduced. In particular, by forming the insulator 280 by the sputtering method, an insulator 280 with a reduced impurity concentration of water or hydrogen, etc. can be obtained, so it is preferred. For example, compared with silicon oxide and silicon oxynitride formed by the CVD method using a deposition gas containing hydrogen, the hydrogen concentration in the film of silicon oxide formed by the sputtering method using a target containing silicon or silicon oxide and a gas containing argon or oxygen is lower, so it is preferred as the insulator 280. In addition, considering the deposition rate when forming the insulator 280 and the coverage of the step portions formed by the oxide 230a, the oxide 230b, and the opening reaching the conductor 247, etc., the insulator 280 can be formed by the CVD method. In addition, although not shown, the insulator 280 can have a laminated structure of two or more layers, and a laminate including silicon oxide formed by the sputtering method as the first layer and silicon oxynitride formed by the CVD method as the second layer can be adopted. In addition, the top surface of the insulator 280 can also be planarized.

[0175] The insulators 282 and 281 are preferably used as barrier insulating films for suppressing impurities such as water or hydrogen from mixing into the insulator 280 from above. As the insulators 282 and 281, insulators such as alumina, silicon nitride, or silicon oxynitride can be used. For example, alumina can be used as the insulator 282 and silicon nitride can be used as the insulator 281. Oxygen can be supplied to the insulator 280 by the alumina used for the insulator 282. In addition, impurities such as hydrogen and water can be suppressed from diffusing from above to the transistor 200 side by the silicon nitride film used for the insulator 281.

[0176] In addition, an insulator such as silicon oxide or silicon oxynitride used as an interlayer film can also be provided between the insulator 282 and the insulator 281. By providing this insulator and adjusting the height of the capacitor 100, the capacitance of the capacitor 100 can be adjusted. Similar to the insulator 224, etc., it is preferable that the concentration of impurities such as water or hydrogen in this insulator is reduced.

[0177] [Capacitor 100]

[0178] The capacitor 100 is disposed in an opening formed in the insulators 256, 280, 282, and 281, and includes a conductor 110 in contact with the top surface of the conductor 242b, an insulator 130 on the conductor 110 and the insulator 281, and a conductor 120 on the insulator 130. Here, at least a part of the conductor 110, the insulator 130, and the conductor 120 is disposed in the opening formed in the insulators 256, 280, 282, and 281.

[0179] The conductor 110 is used as the lower electrode of the capacitor 100, the conductor 120 is used as the upper electrode of the capacitor 100, and the insulator 130 is used as the dielectric of the capacitor 100. The capacitor 100 has a structure in which the upper electrode and the lower electrode are opposed to each other with a dielectric not only on the bottom surface but also on the side surfaces in the opening of the insulators 256, 280, 282, and 281, so that the capacitance per unit area can be increased. Therefore, the deeper the depth of this opening, the larger the capacitance of the capacitor 100 can be. Thus, by increasing the capacitance per unit area of the capacitor 100, miniaturization or high integration of the semiconductor device can be promoted.

[0180] In addition, the shape of the opening formed in the insulators 256, 280, 282, and 281 when viewed from above can be a quadrangle, a polygon other than a quadrangle, a polygon with an arc-shaped corner, or a circular shape such as an ellipse. Here, it is preferable that the area of the opening overlapping with the transistor 200 is large when viewed from above. For example, as Figure 1AAs shown, the capacitor 100 is preferably arranged such that, in a plan view, the capacitor 100 is within the range of the oxide 230b. At this time, the length of the conductor 110 in the channel width direction is smaller than the length of the oxide 230b in the channel width direction. By adopting such a structure, the occupied area of the semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0181] The conductor 110 is arranged along the opening formed in the insulators 256, 280, 282, and 281. The height of a part of the top surface of the conductor 110 is preferably substantially the same as the height of the top surface of the insulator 281. In addition, the bottom surface of the conductor 110 is in contact with the top surface of the conductor 242b. The conductor 110 is preferably formed by the ALD method, the CVD method, or the like, and a conductor that can be used for the conductor 205 or the conductor 242 can be used. For example, by using the same conductive material as the conductor 242b for the conductor 110, the contact resistance between the conductor 110 and the conductor 242b can be reduced. For example, tantalum nitride formed by the ALD method can be used as the conductor 110.

[0182] The insulator 130 is arranged so as to cover the conductor 110 and a part of the insulator 281. For example, the insulator 130 is preferably formed by the ALD method, the CVD method, or the like. As the insulator 130, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, etc. are used, and a stacked structure or a single-layer structure can be adopted. For example, as the insulator 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked can be used.

[0183] For example, the insulator 130 is preferably made of a material with high dielectric strength such as silicon oxynitride or a high-k material (a material with a relatively high relative dielectric constant). In addition, a stacked structure of a material with high dielectric strength and a high-k material can also be used.

[0184] Note that as the insulator of the high-k material, there are gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium, etc. By using such a high-k material, even if the insulator 130 is thickened, the capacitance of the capacitor 100 can be sufficiently ensured. By thickening the insulator 130, the leakage current generated between the conductor 110 and the conductor 120 can be suppressed.

[0185] On the other hand, as materials with high dielectric strength, there are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin, etc. For example, SiO formed by ALD method can be used. x In addition, for example, SiN formed by ALD method can be used and stacked in sequence. x , SiO formed by PEALD method x , and SiN formed by ALD method x . By adopting such an insulator with high dielectric strength, the dielectric strength can be improved and the electrostatic breakdown of the capacitor 100 can be suppressed.

[0186] The conductor 120 is disposed so as to fill the openings formed in the insulators 256, 280, 282, and 281. Here, the conductor 120 preferably has a region overlapping with the insulator 281 with the insulator 130 therebetween. By adopting such a structure, the conductor 120 and the conductor 110 can be surely insulated with the insulator 130 therebetween. In addition, the portion of the conductor 120 above the insulator 281 can be led to form a wiring shape. The conductor 120 is preferably formed by ALD method or CVD method, etc., and a conductor that can be used for the conductor 205 can be used. For example, as the conductor 120, a stacked film of titanium nitride formed by ALD method and tungsten formed by CVD method on the titanium nitride can be used. In addition, when the adhesion of tungsten to the insulator 130 is very high, a single-layer film of tungsten formed by CVD method can also be used as the conductor 120.

[0187] In addition, a conductor used as a wiring can be disposed in contact with the top surface of the conductor 120. This conductor preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. In addition, this conductor can have a stacked structure. For example, it can have a stacked structure of titanium, titanium nitride, and the above conductive material. In addition, this conductor can be formed in a manner of filling the opening of the insulator.

[0188] In addition, the insulator 241 is preferably disposed in contact with the side surfaces of the openings formed in the insulators 256, 280, 282, and 281. The conductor 110 is disposed in contact with the inner side surfaces of the insulator 241, the insulator 130 is disposed in contact with the inner side surfaces of the conductor 110, and the conductor 120 is disposed in contact with the inner side surfaces of the insulator 130.

[0189] As the insulator 241, an insulator such as alumina, silicon nitride, or silicon oxynitride can be used. Since the insulator 241 is provided in contact with the insulators 281, 282, 280, and 256, impurities such as water or hydrogen from the insulator 280 or the like can be prevented from mixing into the oxide 230 through the conductor 110. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 110.

[0190] <Constituent Materials of Semiconductor Devices>

[0191] Hereinafter, constituent materials that can be used for semiconductor devices will be described.

[0192] <Substrate>

[0193] As the substrate for forming the transistor 200, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttrium-stabilized zirconia substrate), a resin substrate, etc. can be cited, for example. In addition, as the semiconductor substrate, a semiconductor substrate made of silicon, germanium, etc., or a compound semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be cited, for example. Furthermore, a semiconductor substrate having an insulator region inside the above semiconductor substrate can also be cited, such as a SOI (Silicon On Insulator) substrate, etc. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Or, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. Furthermore, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can also be cited. Or, a substrate provided with elements on these substrates can also be used. As the elements provided on the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a storage element, etc. can be cited.

[0194] <Insulator>

[0195] As the insulator, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrides having insulating properties, etc.

[0196] For example, when miniaturizing and highly integrating transistors, due to the thinning of the gate insulator, problems such as leakage current sometimes occur. By using a high-k material as the insulator used as the gate insulator, low voltage operation of the transistor can be achieved while maintaining the physical thickness. On the other hand, by using a material with a relatively low relative dielectric constant for the insulator used as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulator.

[0197] In addition, examples of insulators with a relatively high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium, etc.

[0198] In addition, examples of insulators with a relatively low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin, etc.

[0199] Furthermore, by surrounding a transistor using an oxide semiconductor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, and metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxynitride, or silicon nitride can be used.

[0200] In addition, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that can be removed by heating. For example, by adopting a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that can be removed by heating is brought into contact with the oxide 230, the oxygen vacancies contained in the oxide 230 can be filled.

[0201] <Conductor>

[0202] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, etc., an alloy composed of the above metal elements, or an alloy combining the above metal elements, etc. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferable. In addition, a semiconductor with a high conductivity represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0203] In addition, a plurality of conductive layers formed of the above materials may be stacked. For example, a stacked structure combining a material containing the above metal element and a conductive material containing oxygen may be employed. In addition, a stacked structure combining a material containing the above metal element and a conductive material containing nitrogen may be used. In addition, a stacked structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be adopted.

[0204] In addition, in the case where an oxide is used for the channel formation region of a transistor, a stacked structure combining a material containing the above metal element and a conductive material containing oxygen is preferably used as the conductor serving as the gate electrode. In this case, it is preferable to dispose the conductive material containing oxygen on the channel formation region side. By disposing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.

[0205] In particular, as the conductor serving as the gate electrode, a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel is preferably used. In addition, a conductive material containing the above metal element and nitrogen may also be used. For example, a nitrogen-containing conductive material such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may be used. In addition, indium gallium zinc oxide containing nitrogen may also be used. By using the above materials, it is sometimes possible to capture hydrogen contained in the metal oxide forming the channel. Or, it is sometimes possible to capture hydrogen entering from an external insulator or the like.

[0206] <Metal Oxide>

[0207] As the oxide 230, a metal oxide used as an oxide semiconductor is preferably used. Hereinafter, the metal oxides applicable to the oxide 230 according to the present invention will be described.

[0208] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition to this, it is preferably further contains aluminum, gallium, yttrium, or tin, etc. Or, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.

[0209] Here, consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, or tin, etc. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. Note that as element M, sometimes a plurality of the above elements may be combined.

[0210] Note that in this specification and the like, a metal oxide containing nitrogen is sometimes also referred to as a metal oxide. In addition, a metal oxide containing nitrogen can also be referred to as a metal oxynitride.

[0211] [Structure of Metal Oxide]

[0212] Oxide semiconductors (metal oxides) are classified into single-crystalline oxide semiconductors and non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS, a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0213] CAAC-OS has a c-axis orientation, and its multiple nanocrystals are connected in the a-b plane direction, and the crystal structure has distortion. Note that distortion refers to the part where the direction of the lattice arrangement changes between the regions where the lattice arrangements are consistent in the region where multiple nanocrystals are connected and other regions where the lattice arrangements are consistent.

[0214] Although the nanocrystals are basically hexagonal, they are not limited to regular hexagons, and there are cases where they are not regular hexagons. In addition, pentagonal or heptagonal lattice arrangements may sometimes be present in the distortion. Also, in CAAC-OS, it is difficult to observe a clear grain boundary (also called a grain boundary) even near the distortion. That is, it can be seen that the formation of grain boundaries can be suppressed due to the lattice arrangement distortion. This is because CAAC-OS can accommodate the distortion due to the low density of oxygen atom arrangement in the a-b plane direction or the change in the interatomic bonding distance due to the substitution of metal elements.

[0215] In addition, CAAC-OS tends to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. In addition, indium and element M can replace each other. When indium replaces element M in the (M,Zn) layer, this layer can also be represented as an (In,M,Zn) layer. When element M replaces indium in the In layer, this layer can also be represented as an (In,M) layer.

[0216] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is not easy to observe a clear grain boundary in CAAC-OS, so it can be said that a decrease in electron mobility due to grain boundaries is not likely to occur. In addition, the crystallinity of metal oxides sometimes decreases due to the entry of impurities or the generation of defects, so it can be said that CAAC-OS is resistant to impurities or defects (oxygen vacancies (also called V O: metal oxides with few (such as oxygen vacancies, etc.). Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide containing CAAC-OS has high heat resistance and high reliability.

[0217] In nc-OS, the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less) has periodicity. In addition, no regularity in crystal orientation is observed among different nanocrystals in nc-OS. Therefore, no orientation is observed in the entire film. So, sometimes nc-OS shows no difference from a-like OS or amorphous oxide semiconductors in some analysis methods.

[0218] In addition, indium-gallium-zinc oxide (hereinafter, IGZO), which is one kind of metal oxide containing indium, gallium, and zinc, may have a stable structure when it is the above-mentioned nanocrystal. In particular, IGZO has a tendency that crystal growth is not easy to occur in the atmosphere. Therefore, compared with the case where IGZO is a large crystal (here, a crystal of several mm or a crystal of several cm), IGZO may be structurally more stable when it is a small crystal (for example, the above-mentioned nanocrystal).

[0219] a-like OS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is to say, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS.

[0220] Oxide semiconductors (metal oxides) have various structures and various properties. The oxide semiconductor of one embodiment of the present invention may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0221] Note that in the semiconductor device of one embodiment of the present invention, the structure of the oxide semiconductor (metal oxide) is not particularly limited, and the oxide semiconductor preferably has crystallinity. For example, the structure of the oxide 230 may be a CAAC-OS structure. By adopting the above-mentioned crystalline structure as the structure of the oxide 230, a semiconductor device with high reliability can be obtained.

[0222] [Impurities]

[0223] Here, the influence of each impurity in the metal oxide is described.

[0224] In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, defect states are sometimes formed to generate carriers. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal as a channel formation region tends to have a normally-on characteristic. Thus, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide measured by SIMS (the concentration measured by Secondary Ion Mass Spectrometry (SIMS)) is 1×10 18 atoms / cm 3 Hereinafter, it is preferably 2×10 16 atoms / cm 3 or less.

[0225] The hydrogen contained in the metal oxide reacts with the oxygen bonded to the metal atom to generate water, so oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons serving as carriers are sometimes generated. In addition, sometimes electrons serving as carriers are generated because a part of the hydrogen bonds to the oxygen bonded to the metal atom. Therefore, a transistor using a metal oxide containing hydrogen tends to have a normally-on characteristic.

[0226] Thus, it is preferable to reduce the hydrogen in the metal oxide as much as possible. Specifically, in the metal oxide, the hydrogen concentration measured by SIMS is set to be less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , further preferably less than 1×10 18 atoms / cm 3 . By using a metal oxide with sufficiently reduced impurities for the channel formation region of the transistor, the transistor can have stable electrical characteristics.

[0227] Note that, as one aspect of the present invention, an example is shown in which an oxide semiconductor is used as the semiconductor layer of the transistor 200, but one aspect of the present invention is not limited thereto. Depending on the situation or condition, in one aspect of the present invention, various semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor can be used as the semiconductor layer of the transistor 200.

[0228] <Method of manufacturing a semiconductor device>

[0229] Next, a method for manufacturing the semiconductor device including the transistor 200 and the capacitor 100 shown in FIG. 1 will be described with reference to FIGS. 3 to 14. In FIGS. 3 to 14, A in each drawing shows a top view. In addition, B in each drawing shows a cross-sectional view of a portion along the dotted line A1 - A2 in A, and this cross-sectional view corresponds to a cross-sectional view in the channel length direction of the transistor 200. C in each drawing shows a cross-sectional view of a portion along the dotted line A3 - A4 in A, and this cross-sectional view corresponds to a cross-sectional view in the channel width direction of the transistor 200. In addition, D in each drawing shows a cross-sectional view of a portion along the dotted line A5 - A6 in A, and this cross-sectional view corresponds to a cross-sectional view in the channel width direction in the source region or the drain region of the transistor 200. For clarity, some constituent elements are omitted in the top view of A in each drawing.

[0230] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The insulator 214 can be formed by a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, an ALD method, or the like.

[0231] Note that the CVD method can be classified into a plasma enhanced CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD method using light, and the like. Furthermore, the CVD method can be classified into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0232] By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since no plasma is used, the thermal CVD method is a film-forming method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device sometimes generate charge accumulation due to receiving charges from the plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device are sometimes damaged due to the accumulated charges. On the other hand, since the above plasma damage does not occur in the thermal CVD method without using plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so a film with fewer defects can be obtained.

[0233] In addition, the ALD method can deposit atoms of each layer by utilizing the self-regulating property of atoms, thereby achieving effects such as being able to form an extremely thin film, being able to form a film on a structure with a high aspect ratio, being able to form a film with fewer defects such as pinholes, being able to form a film with excellent coverage, and being able to form a film at a low temperature. In addition, the ALD method also includes a film-forming method using plasma, the PEALD (Plasma Enhanced ALD; Plasma Enhanced Atomic Layer Deposition) method. By utilizing plasma, film formation can be carried out at a lower temperature, so it is sometimes preferred. Note that the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, the film formed by the ALD method sometimes contains more impurities such as carbon compared to the film formed by other film-forming methods. In addition, the quantification of impurities can be carried out using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

[0234] Different from the film-forming method in which particles released from a target or the like are deposited, the CVD method and the ALD method are film-forming methods in which a film is formed due to a reaction on the surface of the object to be processed. Therefore, the film formed by the CVD method and the ALD method is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the film formed by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for cases where it is necessary to cover the surface of an opening with a high aspect ratio, etc. Note that the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to be used in combination with other film-forming methods with a high deposition rate such as the CVD method.

[0235] The CVD method and the ALD method can control the composition of the obtained film by adjusting the flow rate ratio of the source gas. For example, when using the CVD method or the ALD method, a film with an arbitrary composition can be formed by adjusting the flow rate ratio of the source gas. In addition, for example, when using the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gas while forming the film. When forming a film while changing the flow rate ratio of the source gas, since the time required for transferring and adjusting the pressure is not required, the film-forming time can be shortened compared to the case of forming a film using multiple film-forming chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0236] In the present embodiment, silicon nitride is formed by the CVD method as the insulator 214. Thus, by using an insulator such as silicon nitride that does not easily allow copper to pass through as the insulator 214, even if a metal such as copper that easily diffuses is used as the conductor in the layer (not shown) below the insulator 214, the diffusion of the metal to the layer above the insulator 214 can be suppressed.

[0237] Next, an insulator 216 is formed on the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0238] Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening includes, for example, a groove or a slit. In addition, the region where the opening is formed is sometimes referred to as an opening portion. When forming this opening, a wet etching method can be used, but a dry etching method is preferred for microfabrication. As the insulator 214, an insulator that serves as an etch stop film when etching the insulator 216 to form a groove is preferably selected. For example, when a silicon oxide film is used as the insulator 216 for forming the groove, the insulator 214 is preferably a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

[0239] After forming the opening, a conductive film that becomes the conductor 205 and the conductor 247 is formed. The conductive film preferably contains a conductor having a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film with tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film that becomes the conductor 205 and the conductor 247 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0240] In the present embodiment, the conductive film that becomes the conductor 205 and the conductor 247 has a multilayer structure. First, tantalum nitride is formed as the conductive film that becomes the conductor 205a and the conductor 247a by a sputtering method, and titanium nitride is formed on the tantalum nitride as the conductive film that becomes the conductor 205b and the conductor 247b by a CVD method. By using such a metal nitride as the layer below the conductive film that becomes the conductor 205 and the conductor 247, even if a metal such as copper that easily diffuses is used as the conductive film that becomes the conductor 205c and the conductor 247c described later, diffusion of the metal from the conductor 205 and the conductor 247 to the outside can be suppressed.

[0241] Next, a conductive film that becomes the conductor 205c and the conductor 247c is formed. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, a low-resistance conductive material such as tungsten or copper is formed as the conductive film that becomes the conductor 205c and the conductor 247c. It is sufficient to form tungsten as the conductive film that becomes the conductor 205c and the conductor 247c by a CVD method.

[0242] Next, a CMP (Chemical Mechanical Polishing) process is performed to remove a portion of the conductive film that will become the conductor 205 and the conductor 247, thereby exposing the insulator 216. As a result, the conductive film that will become the conductor 205 and the conductive film that will become the conductor 247 remain only in the opening. Thus, the conductor 205 and the conductor 247 can be formed with flat top surfaces (see FIG. 3). Note that a portion of the insulator 216 may be removed by the CMP process.

[0243] Next, a method for forming the conductor 205 and the conductor 247 which is different from the above-described method will be described.

[0244] A conductive film that becomes the conductor 205 and the conductor 247 is formed on the insulator 214. The conductive film is formed by sputtering, CVD, MBE, PLD, ALD, or the like. The conductive film may be a multilayer film. In this embodiment, tungsten is formed as the conductive film.

[0245] Next, the conductive film is processed using a photolithography method to form the conductor 205 and the conductor 247 .

[0246] In addition, in the photolithography method, the resist is first exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor or insulator into a desired shape. For example, a resist can be exposed using KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. to form a resist mask. In addition, a liquid immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above light. Note that a mask is not required when an electron beam or an ion beam is used. In addition, when removing the resist mask, a dry etching process such as an ashing process or a wet etching process can be performed, or a wet etching process can be performed after a dry etching process, or a dry etching process can be performed after a wet etching process.

[0247] Alternatively, a hard mask made of an insulator or a conductor can be used instead of the resist mask. When using a hard mask, an insulating film or a conductive film that becomes the hard mask material can be formed on the conductive films that become the conductor 205 and the conductor 247, and a resist mask can be formed thereon, and then the hard mask material can be etched to form a hard mask having a desired shape. The etching of the conductive films that become the conductor 205 and the conductor 247 can be performed either after removing the resist mask or without removing the resist mask. In the latter case, the resist mask may disappear during etching. Alternatively, the hard mask can be removed by etching after the etching of the conductive film. On the other hand, when the hard mask material does not affect the subsequent processes or can be used in the subsequent processes, it is not necessary to remove the hard mask.

[0248] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus including parallel plate electrodes can also adopt a structure in which high-frequency power is applied to one of the parallel plate electrodes. Alternatively, a structure in which different multiple high-frequency powers are applied to one of the parallel plate electrodes can also be adopted. Alternatively, a structure in which high-frequency power having the same frequency is applied to each of the parallel plate electrodes can also be adopted. Alternatively, a structure in which high-frequency powers having different frequencies are applied to each of the parallel plate electrodes can also be adopted. Alternatively, a dry etching apparatus having a high-density plasma source can be used. For example, as a dry etching apparatus having a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0249] Next, an insulating film that becomes the insulator 216 is formed on the insulator 214, the conductor 205, and the conductor 247. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide is formed by the CVD method as the insulating film that becomes the insulator 216.

[0250] Here, the thickness of the insulating film that becomes the insulator 216 is preferably equal to or greater than the thickness of the conductor 205 and the conductor 247. For example, when the thickness of the conductor 205 and the conductor 247 is 1, the thickness of the insulating film that becomes the insulator 216 is 1 or more and 3 or less. In the present embodiment, the thickness of the conductor 205 and the conductor 247 is 150 nm, and the thickness of the insulating film that becomes the insulator 216 is 350 nm.

[0251] Next, a part of the insulating film that becomes the insulator 216 is removed by performing CMP processing on the insulating film that becomes the insulator 216, exposing the surfaces of the conductor 205 and the conductor 247. Thereby, the conductor 205, the conductor 247, and the insulator 216 with a flat top surface can be formed. The above is a different formation method of the conductor 205 and the conductor 247.

[0252] Next, an insulator 222 is formed on the insulator 216, the conductor 205, and the conductor 247. As the insulator 222, an insulator containing one or both of aluminum and hafnium oxides is preferably formed. In addition, as the insulator containing one or both of aluminum and hafnium oxides, alumina, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. The insulator containing one or both of aluminum and hafnium oxides has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, it is possible to suppress the diffusion of hydrogen and water contained in the structures around the transistor 200 through the insulator 222 into the inside of the transistor 200, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0253] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0254] Next, an insulator 224 is formed on the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0255] Next, a heat treatment is preferably performed. The heat treatment is carried out at 250 °C or higher and 650 °C or lower, preferably at 300 °C or higher and 500 °C or lower, and more preferably at 320 °C or higher and 450 °C or lower. The heat treatment is carried out in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment can also be carried out under a reduced pressure state. Alternatively, the heat treatment can be carried out in a nitrogen or inert gas atmosphere, and then, in order to fill the escaped oxygen, the heat treatment is carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.

[0256] In the present embodiment, a treatment is carried out at a temperature of 400 °C for 1 hour in a nitrogen atmosphere, and then continuously a treatment is carried out at a temperature of 400 °C for 1 hour in an oxygen atmosphere. By performing this heat treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed.

[0257] In addition, the heat treatment can also be carried out after forming the insulator 222. The heat treatment can adopt the conditions of the above heat treatment.

[0258] Here, in order to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may also be performed under a reduced pressure state. The plasma treatment containing oxygen preferably uses, for example, a device including a power source for generating a high-density plasma using microwaves. Alternatively, it may also include a power source for applying RF (Radio Frequency) to one side of the substrate. By using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to one side of the substrate, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using such a device, a plasma treatment containing oxygen may be performed to fill the detached oxygen. In addition, by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. At this time, a heat treatment may not be performed.

[0259] Here, an alumina film may also be formed on the insulator 224 by, for example, a sputtering method, and the alumina is subjected to a CMP treatment until the insulator 224 is reached. By performing this CMP treatment, planarization and smoothing of the surface of the insulator 224 can be performed. By disposing the alumina on the insulator 224 and performing a CMP treatment, the end point of the CMP treatment can be easily detected. In addition, sometimes a part of the insulator 224 is polished by the CMP treatment and the thickness of the insulator 224 becomes thinner, but the thickness can be adjusted when the insulator 224 is formed. By performing planarization and smoothing of the surface of the insulator 224, sometimes a reduction in the coverage rate of the oxide film formed below can be prevented and a reduction in the yield of the semiconductor device can be prevented. In addition, by forming an alumina film on the insulator 224 by a sputtering method, oxygen can be added to the insulator 224, so it is preferable.

[0260] Next, an oxide film 230A and an oxide film 230B (see FIG. 3) are sequentially formed on the insulator 224. It is preferable to continuously form the above oxide films without being exposed to the atmospheric environment. By forming the oxide films in a manner not exposed to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, so the vicinity of the interface between the oxide film 230A and the oxide film 230B can be kept clean.

[0261] The oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0262] For example, in the case of forming the oxide film 230A and the oxide film 230B by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. In addition, in the case of forming the above-mentioned oxide film by sputtering, for example, the above-mentioned In-M-Zn oxide target can be used.

[0263] In particular, when forming the oxide film 230A, sometimes a part of the oxygen contained in the sputtering gas is supplied to the insulator 224. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230A can be 70% or more, preferably 80% or more, and more preferably 100%.

[0264] In addition, in the case of forming the oxide film 230B by sputtering, when the ratio of oxygen contained in the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. A transistor using the oxygen-deficient oxide semiconductor for the channel formation region can have a high field-effect mobility.

[0265] In the present embodiment, the oxide film 230A is formed by sputtering using a target of In:Ga:Zn = 1:1:0.5 (2:2:1) [atomic ratio] or 1:3:4 [atomic ratio]. In addition, the oxide film 230B is formed by sputtering using a target of In:Ga:Zn = 4:2:4.1 [atomic ratio] or 1:1:1 [atomic ratio]. The above-mentioned oxide film can be formed by appropriately selecting the film formation conditions and the atomic ratio according to the required characteristics of the oxide 230.

[0266] Next, a heat treatment can also be performed. As the conditions for the heat treatment, the above-mentioned heat treatment conditions can be used. By performing the heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In the present embodiment, a treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere, and then continuously a treatment is performed at a temperature of 400°C for 1 hour in an oxygen atmosphere.

[0267] Next, an opening for exposing at least a part of the conductor 247 is formed in the oxide film 230B, the oxide film 230A, the insulator 224, and the insulator 222 by photolithography (refer to FIG. 4). When forming this opening, wet etching can be used, but dry etching is preferably used for microfabrication.

[0268] Next, a conductive film 242A that contacts the conductor 247 inside the opening is formed. Here, the conductive film 242A can be formed by sputtering, CVD method, MBE method, PLD method, ALD method, etc. (refer to FIG. 4).

[0269] Next, the oxide films 230A, 230B and the conductive film 242A are processed into island shapes to form the oxides 230a, 230b and the conductor layer 242B (see FIG. 5). In addition, in this process, the thickness of the region in the insulator 224 that does not overlap with the oxide 230a sometimes becomes thinner.

[0270] Note that the oxides 230a, 230b and the conductor layer 242B are formed such that at least a part thereof overlaps with the conductor 205. Alternatively, the sides of the oxides 230a, 230b and the conductor layer 242B may be substantially perpendicular to the top surface of the insulator 222. When the sides of the oxides 230a, 230b and the conductor layer 242B are substantially perpendicular to the top surface of the insulator 222, miniaturization and high density can be achieved when a plurality of transistors 200 are provided. Alternatively, a structure in which the angle formed by the sides of the oxides 230a, 230b and the conductor layer 242B and the top surface of the insulator 222 is small may be employed. In this case, the angle formed by the sides of the oxides 230a, 230b and the conductor layer 242B and the top surface of the insulator 222 is preferably 60° or more and less than 70°. By adopting such a shape, the coverage of the insulator 256 etc. in the subsequent process can be improved, and defects such as voids can be reduced.

[0271] In addition, the processing of the oxide film and the conductive film can be performed by photolithography. In addition, as this processing, dry etching or wet etching can be used. Processing using dry etching is suitable for microfabrication.

[0272] In addition, it is preferable that a curved surface is provided between the side surface and the top surface of the conductor layer 242B. That is, the ends of the side surface and the top surface are preferably curved (hereinafter, also referred to as rounded). For example, at the end of the conductor layer 242B, the curved surface has a radius of curvature of 3 nm or more and 10 nm or less, more preferably 5 nm or more and 6 nm or less. When the end does not have a corner, the coverage of the film in the subsequent film formation process can be improved.

[0273] In addition, the processing of the conductive film can be performed by photolithography. In addition, as this processing, dry etching or wet etching can be used. Processing using dry etching is suitable for microfabrication.

[0274] Next, an insulator 256 is formed on the insulator 224, the oxides 230a, 230b and the conductor layer 242B (see FIG. 6).

[0275] In addition, the insulator 256 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. As the insulator 256, an insulating film having a function of suppressing oxygen permeation is preferably used. For example, silicon nitride, silicon oxide, or aluminum oxide is formed by sputtering. In addition, as the insulator 256, a material that can be used for the oxide 230a and the oxide 230b can be used. For example, as the insulator 256, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] is preferably used.

[0276] The insulator 256 may have a stacked structure. The insulator 256 can be formed by the above methods. The upper layer and the lower layer of the insulator 256 can be formed by the same method or by different methods. In addition, as the insulator 256, the above materials can be used. The upper layer and the lower layer of the insulator 256 can be made of the same material or different materials. For example, preferably, an aluminum oxide film is formed by sputtering as the lower layer of the insulator 256, and an aluminum oxide film is formed by ALD as the upper layer of the insulator 256. In addition, an aluminum oxide film can be formed by sputtering as the lower layer of the insulator 256, and a silicon nitride film can be formed by ALD as the upper layer of the insulator 256 (see FIG. 6).

[0277] Next, an insulating film that becomes the insulator 280 is formed on the insulator 256. The insulating film that becomes the insulator 280 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In order to make the insulator 280 contain more oxygen, it is preferable that the deposition gas used for the formation of the insulator 280 contains oxygen. In addition, in order to reduce the hydrogen concentration of the insulator 280, it is preferable that the deposition gas used for the formation of the insulator 280 does not contain hydrogen or contains hydrogen at an extremely low level. For example, it is preferable to form silicon oxide using a target containing silicon or silicon oxide and a gas containing argon or oxygen. In addition, the insulator 280 may have a stacked structure of two or more layers. Silicon oxide can be formed by sputtering as the first layer and oxynitride can be formed by CVD as the second layer. Next, the insulating film that becomes the insulator 280 is subjected to CMP processing to form the insulator 280 with a flat top surface (see FIG. 6).

[0278] Next, a part of the insulator 280, a part of the insulator 256, and a part of the conductor layer 242B are processed to form an opening exposing the oxide 230b. The opening is preferably formed so as to overlap with the conductor 205. Due to the formation of the opening, the conductors 242a and 242b are formed. In addition, due to the formation of the opening, the thickness of a part of the insulator 224 may be reduced (see FIG. 7). Further, a part of the top surface of the oxide 230b exposed between the conductor 242a and the conductor 242b may be removed.

[0279] In addition, a part of the insulator 280, a part of the insulator 256, and a part of the conductor layer 242B may be processed under different conditions. For example, a part of the insulator 280 may be processed by a dry etching method, a part of the insulator 256 may be processed by a wet etching method, and a part of the conductor layer 242B may be processed by a dry etching method.

[0280] At this time, the opening formed in the insulator 280 overlaps with the region between the conductors 242a and 242b. Thereby, the conductor 260 can be self-alignedly disposed between the conductors 242a and 242b in a subsequent process.

[0281] Due to the treatment such as the above-mentioned dry etching, impurities such as etching gas may adhere to or diffuse into the surface or inside of the oxide 230a, the oxide 230b, etc. Examples of the impurities include fluorine, chlorine, etc.

[0282] In order to remove the above-mentioned impurities, etc., washing is performed. As the washing method, there are wet washing using a washing liquid, etc., plasma treatment using plasma, and washing using heat treatment, etc., and the above-mentioned washing may be appropriately combined.

[0283] As the wet washing, a washing treatment may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, ammonia water, hydrofluoric acid, etc. with carbonated water or pure water. Alternatively, ultrasonic washing may be performed using pure water or carbonated water.

[0284] Next, heat treatment may also be performed. The heat treatment may be performed under reduced pressure, and the oxide film 230C may be continuously formed without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen attached to the surface of the oxide 230b, etc. can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In the present embodiment, the temperature of the heat treatment is 200°C (see FIG. 8).

[0285] Here, the oxide film 230C is preferably disposed in such a manner as to contact at least a part of the side surface of the oxide 230a, a part of the side surface of the oxide 230b, a part of the top surface of the oxide 230b, a part of the side surface of the conductor 242, the side surface of the insulator 256, and the side surface of the insulator 280. Since the conductor 242 is surrounded by the insulator 256 and the oxide film 230C, a decrease in conductivity due to oxidation of the conductor 242 can be suppressed in subsequent processes.

[0286] The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C can be formed by the same film formation method as that of the oxide film 230A or the oxide film 230B according to the required characteristics of the oxide film 230C. In the present embodiment, the oxide film 230C is formed by a sputtering method using a target material of In:Ga:Zn = 1:3:4 [atomic ratio] or 4:2:4.1 [atomic ratio].

[0287] In addition, the oxide film 230C can also be a laminate. For example, film formation can be performed using a target material of In:Ga:Zn = 4:2:4.1 [atomic ratio] by a sputtering method, and then film formation can be continuously performed using a target material of In:Ga:Zn = 1:3:4 [atomic ratio].

[0288] In particular, when the oxide film 230C is formed, a part of the oxygen contained in the sputtering gas is sometimes supplied to the oxide 230a and the oxide 230b. Therefore, the ratio of oxygen contained in the sputtering gas of the oxide film 230C can be 70% or more, preferably 80% or more, and more preferably 100%.

[0289] Next, a heat treatment can also be performed. The heat treatment can also be performed under reduced pressure, and the insulating film 250A is continuously formed in such a manner as not to be exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the oxide film 230C and the like can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower (see FIG. 8).

[0290] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, silicon oxynitride is preferably formed by a CVD method. The deposition temperature when forming the insulating film 250A is preferably 350°C or higher and lower than 450°C, and particularly preferably about 400°C. By forming the insulating film 250A at a temperature of 400°C, an insulator with few impurities can be formed.

[0291] Next, a conductive film 260A and a conductive film 260B are formed. The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, the CVD method is preferably used. In the present embodiment, the conductive film 260A is formed by the ALD method, and the conductive film 260B is formed by the CVD method (see FIG. 8).

[0292] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP processing until the insulator 280 is exposed, to form an oxide 230c, an insulator 250, and a conductor 260 (conductor 260a and conductor 260b) (see FIG. 9).

[0293] Next, a heat treatment may also be performed. In the present embodiment, the treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere. By this heat treatment, the moisture concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.

[0294] Here, since the conductor 242 is disposed so as to be surrounded by the insulator 256 and the oxide 230c, a decrease in conductivity due to oxidation of the conductor 242 can be suppressed.

[0295] Next, an insulating film that becomes the insulator 282 may also be formed on the conductor 260, on the oxide 230c, on the insulator 250, and on the insulator 280 (see FIG. 10). The insulating film that becomes the insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that becomes the insulator 282, for example, alumina is preferably formed by a sputtering method. Thus, by forming the insulator 282 in contact with the top surface of the conductor 260, absorption of oxygen contained in the insulator 280 by the conductor 260 can be suppressed in a subsequent heat treatment, which is preferable.

[0296] Next, a heat treatment may also be performed. In the present embodiment, the treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere. By performing this heat treatment, oxygen added by the film formation of the insulator 282 can be supplied to the insulator 280. In addition, this oxygen can be supplied to the oxide 230a and the oxide 230b through the oxide 230c.

[0297] Next, an insulator that becomes the insulator 281 may also be formed on the insulator 282. The insulating film that becomes the insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that becomes the insulator 281, for example, silicon nitride is preferably formed using a sputtering method. (see FIG. 10).

[0298] Next, an opening 290 reaching the conductor 242b is formed in the insulators 256, 280, 282, and 281 (see FIG. 11). The opening 290 can be formed by photolithography. Since the aspect ratio of the opening 290 is high, anisotropic etching is preferably performed, for example, dry etching can be performed. In this dry etching, for example, a mixed gas of one or more of C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, Cl2 gas, BCl3 gas, and SiCl4 gas can be used. Alternatively, oxygen gas, helium gas, argon gas, or hydrogen gas can be appropriately added to the above gases. These etching gases can be appropriately switched according to the etching target (insulators 256, 280, 282, and 281).

[0299] Next, an insulating film that becomes the insulator 241 is formed. At this time, the insulating film is formed so as to contact at least the side surface of the opening 290. For example, the insulating film may be formed along the side surface and the bottom surface of the opening 290. This insulating film can be formed by sputtering, CVD, MBE, PLD, or ALD methods. As the insulating film that becomes the insulator 241, an insulating film having a function of suppressing the permeation of impurities such as water and hydrogen or oxygen is preferably used. For example, it is preferable to form aluminum oxide or silicon nitride by ALD.

[0300] Next, the above insulating film is anisotropically etched to form the insulator 241 in contact with the side surface of the opening 290 (see FIG. 11). Here, at least a part of the top surface of the conductor 242b is exposed by removing at least a part of the above insulating film. In addition, as the anisotropic etching, for example, a dry etching method or the like can be used. By making the side wall portion of the opening 290 have such a structure, the permeation of oxygen from the outside can be suppressed, and the oxidation of the conductor 110 to be formed next can be prevented. In addition, the diffusion of impurities such as water and hydrogen from the conductor 110 to the outside can be prevented.

[0301] Next, a conductive film 110A is formed so as to cover the insulator 281 and the opening 290. At this time, the conductive film 110A is preferably formed in contact with the side surface and the bottom surface of the opening 290 having a high aspect ratio. Therefore, the conductive film 110A is preferably formed by a deposition method with high coverage such as ALD or CVD. For example, tantalum nitride can be formed by ALD.

[0302] Next, a filler 288 is formed on the conductive film 110A (see FIG. 12). The opening 290 may be filled with the filler 288 to such an extent that CMP processing can be performed in a subsequent process. Therefore, voids or the like may be formed in the opening 290. The filler 288 can be either an insulator or a conductor. For example, silicon oxide can be formed as the filler 288 by APCVD.

[0303] Next, a CMP process is performed to remove the layer on the insulator 281 to form the conductor 110 (see FIG. 13). Here, the insulator 281 is preferably used as a stop layer for the CMP process of the conductive film 110A. In addition, sometimes a part of the insulator 281 is removed due to this CMP process.

[0304] Next, an etching process is performed to remove the filler 288 in the opening 290. As the etching process, a wet etching method or a dry etching method can be used, but when using the wet etching method, it is possible to more easily remove the filler 288 in the opening 290. In the case of using wet etching, a hydrofluoric acid-based solution or the like can be used as the etchant. Here, since the insulator 280 is covered by the insulator 281, the insulator 241, and the conductor 110, the insulator 280 can be prevented from being etched.

[0305] Next, an insulating film 130A is formed on the conductor 110 and the insulator 281 (see FIG. 14). The insulating film 130A is preferably formed in contact with the conductor 110 provided inside the opening 290 having a high aspect ratio. Therefore, the insulating film 130A is preferably formed by a deposition method with high coverage such as ALD method or CVD method. For example, silicon oxide is formed by the ALD method. In addition, silicon oxide can also be formed by the PEALD method.

[0306] By forming the insulating film 130A by a deposition method such as the ALD method to cover the conductor 110 with high coverage, short-circuiting between the upper electrode and the lower electrode of the capacitor 100 can be prevented.

[0307] Next, a conductive film 120A is formed on the insulating film 130A (see FIG. 14). At least the conductive film 120A is preferably formed in contact with the insulating film 130A provided inside the opening 290 having a high aspect ratio. Therefore, the conductive film 120A is preferably formed by a deposition method with high embedding property such as ALD method or CVD method. For example, titanium nitride is formed by the ALD method and tungsten is formed thereon by the CVD method.

[0308] In this way, by forming the conductive film 120A, the upper electrode of the capacitor 100 can be formed in the opening 290 with high embedding property, so the electrostatic capacitance of the capacitor 100 can be increased.

[0309] Next, the conductive film 120A and the insulating film 130A are processed by photolithography to form the conductor 120 and the insulator 130 (see FIG. 1). Note that the insulating film 130A may not be processed into the insulator 130 and the insulating film 130A may be maintained. In addition, the conductor 120 can be formed in such a way that the portion above the insulator 281 is used as a wiring, or a conductor used as a wiring can be formed in the upper layer of the conductor 120.

[0310] Through the above processes, a semiconductor device including the transistor 200 and the capacitor 100 shown in FIG. 1 can be manufactured. As shown in FIGS. 3 to 14, the transistor 200 and the capacitor 100 can be manufactured by using the manufacturing method of the semiconductor device shown in the present embodiment.

[0311] According to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device having a large on-state current can be provided. In addition, according to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device having good reliability can be provided. In addition, according to one aspect of the present invention, a semiconductor device having a small off-state current can be provided. Through one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to one aspect of the present invention, a semiconductor device with high productivity can be provided.

[0312] <Modification examples of semiconductor devices>

[0313] Next, an example of a semiconductor device according to one aspect of the present invention different from the <structural example of the semiconductor device> described above will be described with reference to FIGS. 15 and 16.

[0314] In FIGS. 15 and 16, A in each drawing shows a top view. In addition, B in each drawing shows a cross-sectional view of a portion along the dotted line A1 - A2 in A, and this cross-sectional view corresponds to a cross-sectional view in the channel length direction of the transistor 200. Figure 15C Shows a cross-sectional view of a portion along Figure 15A the dotted line A3 - A4 in, and this cross-sectional view corresponds to a cross-sectional view in the channel width direction of the transistor 200. In addition, Figure 15D Shows a cross-sectional view of a portion along Figure 15A the dotted line A5 - A6 in, and this cross-sectional view corresponds to a cross-sectional view in the channel width direction in the source region or drain region of the transistor 200. For clarity, some constituent elements are omitted in the top view of A in each drawing.

[0315] Note that in the semiconductor device shown in FIGS. 15 and 16, the same reference numerals are given to the constituent elements having the same functions as those of the semiconductor device (refer to FIG. 1) shown in the <structural example of the semiconductor device>. Note that in this section, the materials described in detail in the <structural example of the semiconductor device> can be used as the constituent materials of the transistor 200 and the capacitor 100.

[0316] <Modified Example 1 of Semiconductor Device>

[0317] In the semiconductor device shown in FIG. 1, the insulator 241 is provided in contact with the side surface of the opening where the capacitor 100 is provided, but the present embodiment is not limited thereto. As in the semiconductor device shown in FIG. 15, a structure in which the insulator 241 is not provided in the capacitor 100 may also be employed.

[0318] At this time, the conductor 110 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.). In addition, the conductor 110 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). The permeability of one or both of oxygen and hydrogen in the conductor 110 is preferably lower than that of the insulator 280. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, etc. are preferably used as the conductor 110. By adopting such a structure, impurities such as hydrogen or excess oxygen can be prevented from diffusing from the insulator 280 through the conductor 110 to the oxide 230b.

[0319] <Modified Example 2 of Semiconductor Device>

[0320] Figure 16A and Figure 16B The semiconductor device shown includes a transistor 200a and a capacitor 100a, and a transistor 200b and a capacitor 100b.

[0321] In the semiconductor device shown in FIG. 16, except that the conductor 247, the oxide 230a, the oxide 230b, and the conductor 242 are commonly used by the transistor 200a and the transistor 200b, the structures of the transistor 200a and the transistor 200b are the same as those of the transistor 200. Therefore, the detailed content can be referred to the above description. In addition, except that the conductor 120 and the insulator 130 are commonly used by the capacitor 100a and the capacitor 100b, the structures of the capacitor 100a and the capacitor 100b are the same as those of the capacitor 100. Therefore, the detailed content can be referred to the above description.

[0322] As Figure 16A and Figure 16B shown, by adopting a structure in which the conductor 247 is commonly used by the transistor 200a and the transistor 200b, the occupied area of each transistor when viewed from above can be reduced, and thus the semiconductor device can be further highly integrated.

[0323] In addition, in the semiconductor device shown in FIG. 16, a conductor 292 used as a wiring is provided in contact with the bottom surface of the conductor 247. As Figure 16AAs shown, the conductors 120 and 292 used as wirings can be formed to extend in the A1 - A2 direction, and the conductors 260 and 205 used as wirings can be formed to extend in the A3 - A4 direction. Thus, the semiconductor devices shown in FIG. 16 can be arranged in the A1 - A2 direction and the A3 - A4 direction and set in a matrix form.

[0324] In addition, as Figure 16B shown, a stacked structure of an insulator 214a and an insulator 214b can also be used as the insulator 214. For example, silicon nitride can be used for the insulator 214a and aluminum oxide can be used for the insulator 214b. At this time, it is preferable to use silicon nitride for the insulator 281 and aluminum oxide for the insulator 282. By adopting such a structure, the transistors 200a and 200b can be sandwiched by silicon nitride that is less likely to diffuse impurities such as water or hydrogen, thereby suppressing the diffusion of impurities such as water or hydrogen into the oxide 230.

[0325] The structures, methods, etc. shown in the present embodiment can be implemented in appropriate combination with the structures, methods, etc. shown in other embodiments.

[0326] (Embodiment 2)

[0327] In the present embodiment, one mode of the semiconductor device will be described with reference to Figures 17 to 21 this.

[0328] [Storage device 1]

[0329] Figure 17 An example of a semiconductor device (storage device) using transistors and capacitors as one mode of the present invention is shown. In the semiconductor device of one mode of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 200. At least a part of the capacitor 100 or the transistor 300 preferably overlaps the transistor 200. Thus, the occupied area of the capacitor 100, the transistor 200, and the transistor 300 when viewed from above can be reduced, and miniaturization or high integration of the semiconductor device according to the present embodiment can be achieved. The semiconductor device according to the present embodiment can be applied to, for example, a logic circuit represented by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), or a storage circuit represented by a DRAM (Dynamic Random Access Memory) or an NVM (Non - Volatile Memory).

[0330] Note that, as the transistor 200 and the capacitor 100, the transistor 200 and the capacitor 100 described in the above embodiments can be used. Therefore, regarding the transistor 200, the capacitor 100, and the layer including them, reference can be made to the description of the above embodiments. Additionally, in Figure 17 the semiconductor device shown, the transistor 200 and the capacitor 100 have the same structure as the transistor 200 and the capacitor 100 shown in FIG. 1, but are not limited thereto. For example, in Figure 17 the semiconductor device shown, the structure shown in FIG. 15 or FIG. 16 can also be used, Figures 18 to 20 and the same applies to the semiconductor device shown.

[0331] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, by using this transistor for a storage device, the stored content can be retained for a long time. In other words, since no refresh operation or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced. In addition, compared with a transistor using silicon as a semiconductor layer, the transistor 200 has good electrical characteristics at high temperatures. For example, even in the temperature range of 125°C to 150°C, the transistor 200 has good electrical characteristics. Further, in the temperature range of 125°C to 150°C, the transistor 200 has an on-off ratio of 10 digits or more. In other words, compared with a transistor using silicon as a semiconductor layer, the transistor 200 has characteristics such that the on-state current, frequency characteristics, etc., which are examples of transistor characteristics, are improved more in a higher temperature environment.

[0332] In Figure 17 the semiconductor device shown, the wiring 1001 is electrically connected to the source of the transistor 300, the wiring 1002 is electrically connected to the drain of the transistor 300, and the wiring 1007 is electrically connected to the gate of the transistor 300. In addition, the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. Furthermore, the other of the source and the drain of the transistor 200 is electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. Additionally, a structure in which the wiring 1003 is electrically connected to the wiring 1001, the wiring 1002, or the wiring 1007 can also be adopted.

[0333] Figure 17The semiconductor device shown has the characteristic that the charge charged in one electrode of the capacitor 100 can be held by the switching of the transistor 200, so that data can be written, held, and read out. In addition, the transistor 200 is an element provided with a back gate in addition to the source, gate (front gate), and drain. That is, compared with two-terminal elements represented by MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), phase change memory, etc. that utilize MTJ (Magnetic Tunnel Junction) characteristics, the four-terminal element transistor 200 has the feature of being able to easily perform independent control of input and output. In addition, sometimes MRAM, ReRAM, and phase change memory generate atomic-level structural changes when rewriting information. On the other hand, Figure 17 The semiconductor device shown operates by using the charging or discharging of electrons in the transistor and the capacitor when rewriting information, so it has good repeated rewriting durability and little structural change.

[0334] In addition, by Figure 17 arranging the semiconductor device shown in a matrix form, a memory cell array can be formed. At this time, the transistor 300 can be used as a sense amplifier, a read circuit, a drive circuit, etc. connected to the memory cell array. When the transistor 300 is used as part of the sense amplifier, a structure in which the wiring 1003 is electrically connected to the wiring 1001, the wiring 1002, or the wiring 1007 is preferably adopted. When Figure 17 the semiconductor device shown is used as a memory element, for example, an operating frequency of 200 MHz or more can be achieved under the conditions that the drive voltage is 2.5 V and the evaluation ambient temperature is in the range of -40°C to 85°C.

[0335] As shown in the above embodiments, by arranging the conductor 247 below the transistor 200, the parasitic capacitance of the conductor 247 and the wiring connected to the conductor 247 can be reduced. Thereby, even when the transistor 300 is used as a sense amplifier, the required electrostatic capacitance of the capacitor 100 can be made smaller. Therefore, miniaturization of the capacitor 100 can be achieved and miniaturization or high integration of the semiconductor device according to the present embodiment can be achieved.

[0336] <Transistor 300>

[0337] The transistor 300 is disposed on a substrate 311 and includes: a conductor 316 serving as a gate electrode, an insulator 315 serving as a gate insulator, a semiconductor region 313 formed of a part of the substrate 311; and low-resistance regions 314a and 314b serving as a source region or a drain region.

[0338] Here, the insulator 315 is disposed on the semiconductor region 313, and the conductor 316 is disposed on the insulator 315. In addition, the respective transistors 300 formed in the same layer are electrically separated by an insulator 312 serving as an element isolation insulating layer. The same insulator as the insulator 326 described later can be used as the insulator 312. The transistor 300 can be a p-channel type or an n-channel type.

[0339] In the substrate 311, the channel-forming region of the semiconductor region 313 or the region near it, the low-resistance regions 314a and 314b serving as a source region or a drain region, etc. preferably contain a semiconductor such as a silicon-based semiconductor, and more preferably contain single-crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. can also be used for formation. Silicon that applies stress to the crystal lattice, changes the lattice plane spacing, and controls the effective mass can be used. In addition, the transistor 300 can also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0340] In the low-resistance regions 314a and 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements such as arsenic and phosphorus that impart n-type conductivity or an element such as boron that imparts p-type conductivity are also contained.

[0341] As the conductor 316 serving as a gate electrode, a conductive material such as a semiconductor material such as silicon containing elements such as arsenic and phosphorus that impart n-type conductivity or an element such as boron that imparts p-type conductivity, a metal material, an alloy material, or a metal oxide material can be used.

[0342] In addition, since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. In order to have both conductivity and embedding properties, a laminate of a metal material such as tungsten or aluminum is preferably used as the conductor, and tungsten is particularly preferably used in terms of heat resistance.

[0343] Here, in Figure 17In the transistor 300 shown, the semiconductor region 313 (a part of the substrate 311) where the channel is formed has a convex shape. In addition, a conductor 316 is provided so as to cover the side surface and the top surface of the semiconductor region 313 with an insulator 315 interposed therebetween. Since the convex portion of the semiconductor substrate is utilized, such a transistor 300 is also referred to as a FIN type transistor. In addition, an insulator that functions as a mask for forming the convex portion may be provided in contact with the upper surface of the convex portion. Further, although a case where a part of the semiconductor substrate is processed to form the convex portion is shown here, an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0344] Note that Figure 17 the structure of the transistor 300 shown is merely an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or the driving method.

[0345] In addition, as Figure 17 shown, the semiconductor device is provided with a stack of the transistor 300 and the transistor 200. For example, the transistor 300 may be formed of a silicon-based semiconductor material, and the transistor 200 may be formed of an oxide semiconductor. In this way, Figure 17 the semiconductor device shown may have a silicon-based semiconductor material and an oxide semiconductor formed in different layers, respectively. Further, Figure 17 the semiconductor device shown may be manufactured by the same process as that used for manufacturing devices when a silicon-based semiconductor material is employed, and high integration can be achieved.

[0346] <Wiring layer>

[0347] A wiring layer including an interlayer film, wirings, plugs, etc. may also be provided between the respective structures. In addition, the wiring layer may be provided in multiple layers according to the design. Here, in a conductor having the function of a plug or a wiring, the same reference numeral is sometimes used to denote a plurality of structures. Further, in this specification, etc., a wiring and a plug electrically connected to the wiring may also be one component. That is, a part of the conductor is sometimes used as a wiring, and a part of the conductor is sometimes used as a plug.

[0348] For example, on the transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as an interlayer film. In addition, conductors 328 and 330 are formed in the insulators 320, 322, 324, and 326. In addition, the conductors 328 and 330 are used as plugs or wirings. For example, as Figure 17As shown, the conductor 328 and the conductor 330 can be used as at least one of the wirings connecting the wiring 1001 and the source of the transistor 300, the wiring connecting the wiring 1002 and the drain of the transistor 300, and the wiring connecting the wiring 1007 and the gate of the transistor 300.

[0349] In addition, the insulator used as the interlayer film can be used as a planarization film covering the uneven shape below it. For example, in order to improve the flatness of the top surface of the insulator 322, its top surface can also be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0350] In addition, a wiring layer can also be formed on the insulator 326 and the conductor 330. For example, in Figure 17 the insulator 350, the insulator 352, and the insulator 354 are stacked in sequence. In addition, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 is used as a plug or a wiring. For example, as Figure 17 shown, the conductor 356 can be used as at least one of the wirings connecting the wiring 1001 and the source of the transistor 300, the wiring connecting the wiring 1002 and the drain of the transistor 300, and the wiring connecting the wiring 1007 and the gate of the transistor 300.

[0351] The insulator 360 is disposed on the insulator 354, the insulator 362 is disposed on the insulator 360, the insulator 364 is disposed on the insulator 362, and the insulator 210 is disposed on the insulator 364.

[0352] An opening is formed in the insulator 364, and a conductor 366 connected to the wiring 1003 is disposed in the opening. The conductor 366 contacts the bottom surface of the conductor 247. That is, the conductor 366 is used as a wiring connecting one of the source and the drain of the transistor 200 and the wiring 1003. As the conductor 366, an insulator that can be used for the conductor 356 or the like can be used.

[0353] In addition, when the transistor 300 is used as a part of the sense amplifier, a structure in which the conductor 366 passes through the insulator 362 and the insulator 360 and contacts the conductor 356 can also be adopted. That is, a structure in which the wiring 1003 is connected to at least one of the wiring 1001, the wiring 1002, and the wiring 1007 can also be adopted. By adopting such a structure, the distance of the wiring connecting the transistor 200 and the transistor 300 can be shorter than the case where the wiring is led on the transistor 200, and the parasitic capacitance of the wiring can be reduced. As a result, even when the transistor 300 is used for the sense amplifier, the required electrostatic capacitance of the capacitor 100 can be made smaller. Therefore, miniaturization of the capacitor 100 can be achieved and miniaturization or high integration of the semiconductor device according to the present embodiment can be achieved.

[0354] The conductors 247 in contact with the conductor 366 and the conductors (conductors 205) constituting the transistor 200 are embedded in the insulators 210, 212, 214, and 216. The conductor 247 is used as a plug or wiring electrically connected to the transistor 200.

[0355] In addition, a wiring layer may be provided on the capacitor 100. Figure 17 In the semiconductor device shown, the insulators 150, 154, and 156 are sequentially stacked so as to cover the insulator 281. Conductors 245 are formed in the insulators 150 and 154 so as to contact the other electrode of the capacitor 100. A conductor 153 used as a terminal connected to the wiring 1005 is provided so as to contact the top surface of the conductor 245. The conductor 153 is covered with the insulator 156.

[0356] Note that insulators that can be used as interlayer films include oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides having insulating properties. For example, by using a material with a low relative dielectric constant for the insulator used as the interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator.

[0357] For example, as the insulators 320, 322, 326, 352, 354, 362, 364, 212, 150, and 156, etc., insulators with a low relative dielectric constant are preferred. For example, this insulator preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin, etc. Or, this insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores and resin. Since silicon oxide and silicon oxynitride are thermally stable, a thermally stable and low relative dielectric constant laminated structure can be achieved by combining with resin. As the resin, for example, polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, or acrylic resin, etc. can be cited.

[0358] In addition, the resistivity of the insulator provided above or below the conductor 153 is 1.0×10 12 Ωcm or more and 1.0×10 15 Ωcm or less, preferably 5.0×10 12 Ωcm or more and 1.0×10 14below Ωcm, more preferably 1.0×10 13 Ωcm or more and 5.0×10 13 Ωcm or less. By setting the resistivity of the insulator provided above or below the conductor 153 within the above range, the insulator can maintain its insulation property and disperse the charges accumulated between wirings such as the transistors 200, 300, the capacitor 100, and the conductor 153, thereby suppressing characteristic degradation or electrostatic breakdown of the transistors and the semiconductor device including the transistors caused by such charges, and thus is preferable. As such an insulator, silicon nitride or silicon oxynitride can be used. For example, it is sufficient to set the resistivity of the insulator 281 within the above range.

[0359] By surrounding a transistor using an oxide semiconductor with an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, as the insulators 324, 350, 360, 210, 154, etc., an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen can be used.

[0360] As an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, for example, a single layer or a stacked layer of an insulator containing one or more of metal elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon oxynitride, silicon nitride, etc. can be used.

[0361] As a conductor that can be used for wirings and plugs, a material containing one or more of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium, etc. is preferably used. In addition, a semiconductor having a high conductivity represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0362] For example, as the conductors 328, 330, 356, 366, 247, 245, 153, etc., a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials can be used in a single layer or a stacked layer. Specifically, a high melting point material such as tungsten or molybdenum having both heat resistance and conductivity is preferably used, and tungsten is particularly preferably used. Alternatively, a low resistance conductive material such as aluminum or copper is preferably used. By using a low resistance conductive material, the wiring resistance can be reduced.

[0363] The above is the description of the structural example. By adopting this structure, miniaturization or high integration of a semiconductor device using a transistor including an oxide semiconductor can be achieved. In addition, in a semiconductor device using a transistor including an oxide semiconductor, electrical property variations can be suppressed and reliability can be improved. In addition, a transistor including an oxide semiconductor having a large on-state current can be provided. In addition, a transistor including an oxide semiconductor having a small off-state current can be provided. In addition, a semiconductor device with reduced power consumption can be provided.

[0364] Note that in Figure 17 , an example of the transistor 300 whose channel region is formed in the substrate 311 is shown, but the semiconductor device shown in this embodiment is not limited thereto. For example, as Figure 18 shows, a structure in which a transistor 400 including an oxide semiconductor is provided under the transistor 200 may also be adopted. Except for the point that the transistor 400 is provided instead of the transistor 300, Figure 18 the semiconductor device shown has the same structure as the Figure 17 semiconductor device shown.

[0365] Different from the Figure 17 semiconductor device shown, in the Figure 18 semiconductor device shown, an insulator 412, an insulator 414, an insulator 416, an insulator 422, an insulator 480, an insulator 482, an insulator 481, and a transistor 400 formed in these layers are included between the substrate 311 and the insulator 352. Here, the insulator 412 corresponds to the insulator 212, the insulator 414 corresponds to the insulator 214, the insulator 416 corresponds to the insulator 216, the insulator 422 corresponds to the insulator 222, the insulator 480 corresponds to the insulator 280, the insulator 482 corresponds to the insulator 282, the insulator 481 corresponds to the insulator 281, and the transistor 400 corresponds to the transistor 200.

[0366] That is, the transistor 400 and the layer including the transistor 400 have the same structure as the above-described transistor 200 and the layer including the transistor 200. Therefore, the details of the transistor 400 and the layer including the transistor 400 can be referred to the above description.

[0367] A conductor 445 is provided so as to fill the openings formed in the insulator 480, the insulator 482, and the insulator 481. The conductor 445 is used as a plug connecting the wiring 1001 and the source of the transistor 400, a plug connecting the wiring 1002 and the drain of the transistor 400, and a plug connecting the wiring 1007 and the gate of the transistor 400, respectively.

[0368] The conductor 445 preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. In addition, the conductor 445 may also have a laminated structure.

[0369] When a laminated structure is adopted for the conductor 445, a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen is preferably used as the lower conductor. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, etc. are preferably used. The conductive material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen can be used in a single layer or in a laminate. By using this conductive material, the oxygen added to the insulator 480 can be prevented from being absorbed by the conductor 445. In addition, impurities such as water or hydrogen can be prevented from entering the transistor 400 from the upper layer of the insulator 481 through the conductor 445.

[0370] Note that when an oxide semiconductor is used for the transistor 400, an insulator having an excess oxygen region is sometimes provided near the oxide semiconductor. In this case, it is preferable to provide a blocking insulator between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.

[0371] For example, as Figure 18 shown, it is preferable to provide an insulator 476 between the insulator 480 containing excess oxygen and the conductor 445. Here, the structure of the insulator 476 may be the same as the structure of the insulator 241 shown in the above embodiment. By providing the insulator 476, the excess oxygen contained in the insulator 480 can be suppressed from being absorbed by the conductor 445. In addition, by having the insulator 476, diffusion of hydrogen as an impurity to the transistor 400 through the conductor 445 can be suppressed.

[0372] [Storage device 2]

[0373] Figure 19 An example of a semiconductor device (storage device) using a semiconductor device as one mode of the present invention is shown. Similar to the Figure 17 shown semiconductor device, Figure 19 the shown semiconductor device includes a transistor 200, a transistor 300, and a capacitor 100. However, Figure 19 the difference between the shown semiconductor device and the Figure 17 shown semiconductor device is as follows: The transistor 200 is electrically connected to the transistor 300 through one of the conductors 247 and 366.

[0374] In a semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistor 200. At least a part of the capacitor 100 or the transistor 300 preferably overlaps the transistor 200. Thereby, the occupied area of the capacitor 100, the transistor 200, and the transistor 300 when viewed from above can be reduced, and miniaturization or high integration of the semiconductor device according to the present embodiment can be achieved.

[0375] Note that the above-described transistors 200 and 300 can be used as the transistor 200 and the transistor 300. Therefore, reference can be made to the above description regarding the transistor 200, the transistor 300, and the layers including them.

[0376] In Figure 19 In the semiconductor device shown, a wiring 2001 is electrically connected to the source of the transistor 300, and a wiring 2002 is electrically connected to the drain of the transistor 300. Further, a wiring 2003 is electrically connected to one of the source and the drain of the transistor 200, a wiring 2004 is electrically connected to the first gate of the transistor 200, and a wiring 2006 is electrically connected to the second gate of the transistor 200. Furthermore, the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 2005 is electrically connected to the other electrode of the capacitor 100. Note that hereinafter, the node connected to the gate of the transistor 300, the other of the source and the drain of the transistor 200, and one electrode of the capacitor 100 may be referred to as a node FG.

[0377] Figure 19 The semiconductor device shown has a characteristic that the potential of the gate (node FG) of the transistor 300 can be held by the switching of the transistor 200, and thus data can be written, held, and read out. In addition, by Figure 19 configuring the semiconductor device shown in a matrix form, a memory cell array can be formed.

[0378] In Figure 19 In the semiconductor device shown, conductors 247 and 366 are arranged so as to overlap below the other of the source and the drain of the transistor 200 and one electrode of the capacitor 100. The conductors 247 and 366 are used as a part of the node FG and can electrically connect the gate of the transistor 300, the other of the source and the drain of the transistor 200, and one electrode of the capacitor 100.

[0379] In addition, in Figure 19 the semiconductor device shown, the other of the source and the drain of the transistor 200 is sometimes formed in a recessed manner. At this time, as Figure 19As shown, the capacitor 100 is sometimes formed in such a manner as to fill the recess that buries the other of the source and drain of the transistor 200.

[0380] Note that in Figure 19 an example of a transistor 300 whose channel region is formed in a substrate 311 is shown, but the semiconductor device shown in this embodiment is not limited thereto. For example, as Figure 20 shown, a structure in which a transistor 400 including an oxide semiconductor is provided under the transistor 200 may also be employed. Except for the point that the transistor 400 is provided instead of the transistor 300, Figure 20 the semiconductor device shown in Figure 19 has the same structure as the semiconductor device shown in Figure 18 In addition, the transistor 400 has the same structure as the semiconductor device shown in

[0381] In addition, Figures 17 to 20 the semiconductor devices shown in Figure 21 may also be provided mixed together on the same substrate. For example, as Figure 17 shown, a structure in which a semiconductor device 500A corresponding to the semiconductor device shown in Figure 20 and a semiconductor device 500B corresponding to the semiconductor device shown in

[0382] are provided on the same substrate may also be employed. The semiconductor device 500A includes a transistor 300A, a transistor 200A, and a capacitor 100A. In addition, the semiconductor device 500B includes a transistor 400B, a transistor 200B, and a capacitor 100B. Here, the transistor 300A has the same structure as the transistor 300. In addition, the transistor 200A and the transistor 200B have the same structure as the transistor 200. In addition, the capacitor 100A and the capacitor 100B have the same structure as the capacitor 100. In addition, the transistor 400B has the same structure as the transistor 400. Therefore, the detailed content of these structures can be referred to the above description.

[0383] Note that a structure in which the wiring 1003 and the wiring 1001 shown in Figure 17 in the semiconductor device 500A are connected is shown.

[0384] In addition, a structure in which a plug connected to the wiring 2003 is provided on the transistor 200B in the semiconductor device 500B is shown. Here, the plug connected to one of the source and drain of the transistor 200B may have the same structure as the above-described conductor 445, and it is preferable to provide an insulator similar to the insulator 476. By adopting such a structure, it is easy to form the plug in the same layer as the capacitor 100A and the capacitor 100B.

[0385] This embodiment can be implemented by appropriately combining the structures described in other embodiments and the like.

[0386] (Embodiment 3)

[0387] In this embodiment, with reference to FIGS. 22 and 23, a storage device (hereinafter sometimes referred to as an OS storage device) using an oxide for a transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor according to one aspect of the present invention will be described. The OS storage device is a storage device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS storage device has excellent retention characteristics and can thus be used as a non-volatile memory.

[0388] <Structural example of the storage device>

[0389] Figure 22A An example of the structure of the OS storage device is shown. The storage device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0390] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from the memory cell. Note that the above-mentioned wiring is a wiring connected to the memory cells included in the memory cell array 1470, and details thereof will be described below. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA through the output circuit 1440. In addition, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to be accessed.

[0391] A low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the storage device 1400 from the outside. In addition, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside. The address signal ADDR is input to the row decoder and the column decoder, and the WDATA is input to the write circuit.

[0392] The control logic circuit 1460 processes the input signals (CE, WE, RE) from the outside to generate control signals for the row decoder and the column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0393] The memory cell array 1470 includes a plurality of memory cells MC configured in a row and column pattern and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MC, the number of memory cells MC included in one column, and the like. In addition, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MC, the number of memory cells MC included in one row, and the like.

[0394] In addition, although an example is shown in Figure 22A where the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, the present embodiment is not limited thereto. For example, as shown in Figure 22B the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a structure may be adopted in which the sense amplifier is provided so as to overlap under the memory cell array 1470.

[0395] An example of the structure of a memory cell suitable for the above-mentioned memory cell MC is described in FIG. 23.

[0396] [DOSRAM]

[0397] Figures 23A to 23C An example of the circuit structure of a memory cell of a DRAM is shown. In this specification and the like, a DRAM using a 1OS transistor 1 capacitor type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Figure 23A The memory cell 1471 shown includes a transistor M1 and a capacitor CA. In addition, the transistor M1 includes a gate (sometimes referred to as a front gate) and a back gate.

[0398] The first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the capacitor CA is connected to the wiring CAL.

[0399] The wiring BIL is used as a bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring for applying a specified potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0400] Here, Figure 23AThe memory cell 1471 shown corresponds to Figure 17 and Figure 18 the memory device shown. That is, the transistor M1 corresponds to the transistor 200, the capacitor CA corresponds to the capacitor 100, the wiring BIL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, and the wiring CAL corresponds to the wiring 1005. Note that Figure 17 and Figure 18 the transistor 300 described in Figure 22B corresponds to the transistor provided in the peripheral circuit 1411 of the memory device 1400 shown. For example, Figure 17 and Figure 18 the transistor 300 described in forms a sense amplifier included in the peripheral circuit 1411.

[0401] In addition, the memory cell MC is not limited to the memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also adopt a structure in which the back gate of the transistor M1 is not connected to the wiring BGL but to the wiring WOL as in the memory cell 1472 shown in Figure 23B . In addition, for example, the memory cell MC can also be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 that does not include a back gate, as in the memory cell 1473 shown in Figure 23C .

[0402] When the semiconductor device shown in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. In other words, since the written data can be held by the transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can also be omitted. In addition, since the leakage current is extremely small, multivalued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0403] In addition, in the DOSRAM, when a structure in which a sense amplifier is provided so as to overlap the memory cell array 1470 as described above is adopted, the bit line can be shortened. As a result, the bit line capacitance is reduced, and thus the storage capacitance of the memory cell can be reduced.

[0404] [NOSRAM]

[0405] Figures 23D to 23H An example of the circuit structure of a gain cell type memory cell of 2 transistors and 1 capacitor is shown. Figure 23DThe storage cell 1474 shown includes a transistor M2, a transistor M3, and a capacitor CB. In addition, the transistor M2 includes a front gate (sometimes simply referred to as the gate) and a back gate. In this specification and the like, a storage device including a gain cell type storage cell using an OS transistor for the transistor M2 is sometimes referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0406] The first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the capacitor CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor CB.

[0407] The wiring WBL is used as a write bit line, the wiring RBL is used as a read bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring for applying a specified potential to the second terminal of the capacitor CB. During data writing, holding, and reading, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0408] Here, Figure 23D the storage cell 1474 shown corresponds to Figure 19 and Figure 20 the storage device shown. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 2003, the wiring WOL corresponds to the wiring 2004, the wiring BGL corresponds to the wiring 2006, the wiring CAL corresponds to the wiring 2005, the wiring RBL corresponds to the wiring 2002, and the wiring SL corresponds to the wiring 2001.

[0409] In addition, the storage cell MC is not limited to the storage cell 1474, and its circuit structure can be appropriately changed. For example, the storage cell MC can also adopt a structure such as Figure 23E the storage cell 1475 shown, in which the back gate of the transistor M2 is not connected to the wiring BGL but to the wiring WOL. In addition, for example, the storage cell MC can also be a storage cell such as Figure 23F the storage cell 1476 shown, which is composed of a transistor with a single-gate structure, that is, a transistor M2 that does not include a back gate. In addition, for example, the storage cell MC can also have a structure such as Figure 23GA structure in which a wiring WBL and a wiring RBL are combined into a single wiring BIL, such as the memory cell 1477 shown.

[0410] When the semiconductor device shown in the above embodiment is used for a memory cell 1474 or the like, transistor 200 can be used as transistor M2, transistor 300 can be used as transistor M3, and capacitor 100 can be used as capacitor CB. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be made extremely small. Thus, since the written data can be held by transistor M2 for a long time, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can also be omitted. Further, since the leakage current is extremely small, multi-valued data or analog data can be held in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0411] In addition, transistor M3 can also be a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as an Si transistor). The conductivity type of the Si transistor can be an n-channel type or a p-channel type. The field-effect mobility of the Si transistor is sometimes higher than that of the OS transistor. Therefore, an Si transistor can also be used as transistor M3, which is used as a sense transistor. Further, by using an Si transistor for transistor M3, transistor M2 can be provided stacked on transistor M3, thereby reducing the occupied area of the memory cell and enabling high integration of the memory device.

[0412] In addition, transistor M3 can also be an OS transistor. When OS transistors are used for transistors M2 and M3, only n-type transistors can be used to form a circuit in the memory cell array 1470.

[0413] In addition, Figure 23H An example of a gain cell type memory cell of a 3-transistor 1-capacitor is shown. Figure 23H The memory cell 1478 shown includes transistors M4 to M6 and capacitor CC. Capacitor CC can be appropriately provided. Memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. Wiring GNDL is a wiring for supplying a low-level potential. In addition, memory cell 1478 can also be electrically connected to wirings RBL and WBL without being electrically connected to wiring BIL.

[0414] Transistor M4 is an OS transistor including a back gate, which is electrically connected to wiring BGL. In addition, the back gate and the gate of transistor M4 can also be electrically connected to each other. Alternatively, transistor M4 may not include a back gate.

[0415] In addition, each of the transistors M5 and M6 can be an n-channel Si transistor or a p-channel Si transistor. Alternatively, all of the transistors M4 to M6 are OS transistors. In this case, only n-type transistors can be used to form a circuit in the memory cell array 1470.

[0416] When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0417] Note that the structures of the peripheral circuit 1411 and the memory cell array 1470 shown in this embodiment are not limited to the above structures. Additionally, they can be changed, removed, or added as needed, and the configurations or functions of these circuits, the wirings connected to the circuits, and circuit elements can also be changed.

[0418] This embodiment can be implemented by appropriately combining the structures described in other embodiments and the like.

[0419] (Embodiment 4)

[0420] In this embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted will be described with reference to FIG. 24. A plurality of circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a System on Chip (SoC).

[0421] As Figure 24A shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0422] Bumps (not shown) are provided on the chip 1200, and the bumps are connected to the first surface of a Printed Circuit Board (PCB) 1201 as Figure 24B shown. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and the bumps 1202 are connected to a motherboard 1203.

[0423] In addition, memory devices such as a DRAM 1221 and a flash memory 1222 can be provided on the motherboard 1203. For example, the DOSRAM shown in the above embodiment can be applied to the DRAM 1221. Additionally, for example, the NOSRAM shown in the above embodiment can be applied to the flash memory 1222.

[0424] The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. In addition, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory shared by the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above NOSRAM or DOSRAM can be applied to this memory. In addition, the GPU 1212 is suitable for parallel computing of a plurality of data, and can be used for image processing or multiplication and accumulation operations. By providing the image processing circuit or the multiplication and accumulation circuit of the oxide semiconductor of the present invention as the GPU 1212, image processing and multiplication and accumulation operations can be performed with low power consumption.

[0425] In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, and transfer of the operation result from the GPU 1212 to the CPU 1211 after the operation in the GPU 1212 can be performed at high speed.

[0426] The analog operation unit 1213 has one or both of an analog / digital (A / D) conversion circuit and a digital / analog (D / A) conversion circuit. In addition, the above multiplication and accumulation circuit may be provided in the analog operation unit 1213.

[0427] The memory controller 1214 has a circuit serving as a controller for the DRAM 1221 and a circuit serving as an interface for the flash memory 1222.

[0428] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, an image capturing device, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As the above interface, a universal serial bus (USB), a high-definition multimedia interface (HDMI) (registered trademark), etc. can be used.

[0429] The network circuit 1216 has a network circuit such as a local area network (LAN). In addition, it may have a network security circuit.

[0430] The above circuit (system) can be formed on the chip 1200 through the same manufacturing process. Thus, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0431] A motherboard 1203 including a PCB 1201 provided with a chip 1200 having a GPU 1212, a DRAM 1221, and a flash memory 1222 may be referred to as a GPU module 1204.

[0432] The GPU module 1204 can reduce its size due to the chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for use in portable electronic devices such as smart phones, tablet terminals, laptop personal computers, and portable (portable) game consoles due to its high image processing ability. In addition, by using the sum-of-products operation circuit using the GPU 1212, operations such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN) can be performed. Thus, the chip 1200 can be used as an AI chip, or the GPU module can be used as an AI system module.

[0433] The structure shown in this embodiment can be implemented in appropriate combination with the structures shown in other embodiments.

[0434] (Embodiment 5)

[0435] In this embodiment, an application example of a storage device using the semiconductor device shown in the above embodiment is described. The semiconductor device shown in the above embodiment can be applied, for example, to storage devices of various electronic devices (for example, information terminals, computers, smart phones, e-book reader terminals, digital cameras (including video cameras), video playback devices, navigation systems, etc.). Note that here, computers include tablet computers, notebook computers, desktop computers, and large computers such as server systems. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives). FIG. 25 schematically shows several structural examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used for various storage devices or removable memories.

[0436] Figure 25A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a lid 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device shown in the above embodiment can be assembled on the memory chip 1105 or the like on the substrate 1104.

[0437] Figure 25BIt is a schematic diagram of the appearance of an SD card. Figure 25C It is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function can be provided on the substrate 1113. Thus, by wireless communication between the host device and the SD card 1110, reading and writing of data in the memory chip 1114 can be performed. The semiconductor device shown in the above embodiment can be assembled on the memory chip 1114 or the like on the substrate 1113.

[0438] Figure 25D It is a schematic diagram of the appearance of an SSD. Figure 25E It is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled on the memory chip 1154 or the like on the substrate 1153.

[0439] This embodiment can be implemented by appropriately combining the structures described in other embodiments or the like.

[0440] (Embodiment 6)

[0441] The semiconductor device according to one aspect of the present invention can be applied to processors or chips such as CPUs and GPUs. FIG. 26 shows a specific example of an electronic device having a processor or chip such as a CPU or GPU according to one aspect of the present invention.

[0442] <Electronic Devices and Systems>

[0443] A GPU or chip according to one embodiment of the present invention can be installed in various electronic devices. As examples of electronic devices, in addition to electronic devices with relatively large screens such as television sets, displays for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, portable information terminals, and sound reproduction devices can also be cited. In addition, by providing a GPU or chip according to one embodiment of the present invention in an electronic device, the electronic device can be made to have artificial intelligence.

[0444] An electronic device according to one embodiment of the present invention may also include an antenna. By receiving a signal by the antenna, an image, information, or the like can be displayed on the display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for non-contact power transmission.

[0445] An electronic device according to one embodiment of the present invention may also include a sensor (the sensor having a function of measuring factors such as force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays).

[0446] An electronic device according to one embodiment of the present invention can have various functions. For example, it can have functions such as a function of displaying various information (still images, moving pictures, character images, etc.) on the display unit; a function of a touch panel; a function of displaying a calendar, date, time, etc.; a function of executing various software (programs); a function of performing wireless communication; a function of reading a program or data stored in a storage medium; and the like. FIG. 26 shows an example of an electronic device.

[0447] [Information Terminal]

[0448] Figure 26A A mobile phone (smartphone), which is one example of an information terminal, is shown. The information terminal 5100 includes a housing 5101 and a display unit 5102, has a touch panel in the display unit 5102 as an input interface, and buttons are provided on the housing 5101.

[0449] By applying the chip of one embodiment of the present invention to the information terminal 5100, an application program using artificial intelligence can be executed. As an application program using artificial intelligence, for example, there can be mentioned an application program that recognizes a conversation and displays the content of the conversation on the display unit 5102, an application program that recognizes text or graphics input by a user to the touch panel provided in the display unit 5102 and displays the text or the graphics on the display unit 5102, an application program that performs biometric identification such as fingerprint or voiceprint, etc.

[0450] Figure 26B Fig. shows a notebook-type information terminal 5200. The notebook-type information terminal 5200 includes an information terminal main body 5201, a display unit 5202, and a keyboard 5203.

[0451] Similar to the above-mentioned information terminal 5100, by applying the chip of one embodiment of the present invention to the notebook-type information terminal 5200, an application program using artificial intelligence can be executed. As an application program using artificial intelligence, for example, there can be mentioned design support software, text proofreading software, menu automatic generation software, etc. In addition, by using the notebook-type information terminal 5200, novel artificial intelligence can be developed.

[0452] Note that in the above examples, Figure 26A and Figure 26B respectively show a smart phone and a notebook-type information terminal as examples of electronic devices, but information terminals other than smart phones and notebook-type information terminals can also be applied. As information terminals other than smart phones and notebook-type information terminals, for example, there can be mentioned a PDA (Personal Digital Assistant), a desktop information terminal, a workstation, etc.

[0453] [Game console]

[0454] Figure 26C Fig. shows a portable game console 5300 as an example of a game console. The portable game console 5300 includes a casing 5301, a casing 5302, a casing 5303, a display unit 5304, a connection part 5305, operation keys 5306, etc. The casing 5302 and the casing 5303 can be detached from the casing 5301. By installing the connection part 5305 provided in the casing 5301 to another casing (not shown), the image output to the display unit 5304 can be output to another video display device (not shown). At this time, the casing 5302 and the casing 5303 can be used as controllers respectively. Thus, a plurality of game players can play games simultaneously. The chip shown in the above embodiment can be embedded in a chip, etc. provided on the substrates of the casing 5301, the casing 5302, and the casing 5303.

[0455] In addition, Figure 26DA stationary game console 5400 of one of the game consoles is shown. The stationary game console 5400 is connected to a controller 5402 wirelessly or by wire.

[0456] By applying the GPU or chip of one aspect of the present invention to game consoles such as the portable game console 5300 and the stationary game console 5400, a game console with low power consumption can be realized. In addition, due to the low power consumption, the heat generation from the circuit can be reduced, and thus the negative impacts on the circuit itself, the peripheral circuit, and the module caused by the heat can be reduced.

[0457] Furthermore, by applying the GPU or chip of one aspect of the present invention to the portable game console 5300, a portable game console 5300 with artificial intelligence can be realized.

[0458] The performance of the progress of the game, the words and deeds of the creatures appearing in the game, the phenomena occurring in the game, etc. are originally defined by the program possessed by the game. However, by applying artificial intelligence to the portable game console 5300, a performance not limited to the program of the game can be realized. For example, the content of the questions asked by the game player, the progress of the game, the timing of the events occurring in the game, the words and deeds of the characters appearing in the game, etc. can be changed and presented without being limited to the program in the game.

[0459] In addition, when playing a game that requires multiple game players using the portable game console 5300, anthropomorphic game players can be constructed using artificial intelligence. Thus, the artificial intelligence game players can be regarded as opponents, and a single person can play a game for multiple players.

[0460] Although Figure 26C and Figure 26D the portable game console and the stationary game console are shown as an example of game consoles, the game consoles to which the GPU or chip of one aspect of the present invention is applied are not limited thereto. As game consoles to which the GPU or chip of one aspect of the present invention is applied, for example, arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, etc. can be cited.

[0461] [Mainframe computer]

[0462] The GPU or chip of one aspect of the present invention can be applied to a mainframe computer.

[0463] Figure 26E A supercomputer 5500 shown as an example of a mainframe computer is shown. Figure 26F A rack mount computer 5502 included in the supercomputer 5500 is shown.

[0464] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. Note that the plurality of computers 5502 are accommodated in the rack 5501. In addition, the computers 5502 are provided with a plurality of substrates 5504, on which the GPUs or chips described in the above embodiments can be mounted.

[0465] The supercomputer 5500 is a large computer mainly used for scientific computing. Scientific computing requires performing huge operations at high speed, so it has high power consumption and high heat generation of chips. By applying the GPU or chip of one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. In addition, with low power consumption, the heat generation from the circuit can be reduced, and thus the negative impacts on the circuit itself, peripheral circuits, and modules caused by heat can be reduced.

[0466] In Figure 26E and Figure 26F a supercomputer is shown as an example of a large computer, however, the large computer applying the GPU or chip of one embodiment of the present invention is not limited thereto. As a large computer applying the GPU or chip of one embodiment of the present invention, for example, computers providing services (servers), large general-purpose computers (mainframes), etc. can be cited.

[0467] [Mobile body]

[0468] The GPU or chip of one embodiment of the present invention can be applied to an automobile as a mobile body and the periphery of the driver's seat of the automobile.

[0469] Figure 26G is a view of the periphery of the front windshield inside an automobile showing an example of a mobile body. Figure 26G Shows a display panel 5701, a display panel 5702, a display panel 5703 mounted on the instrument panel, and a display panel 5704 mounted on the pillar.

[0470] By displaying a speedometer, a tachometer, a driving distance, a fuel gauge, a gear position state, a setting of an air conditioner, etc., the display panels 5701 to 5703 can provide various information. In addition, the user can appropriately change the display content and layout, etc. displayed on the display panel according to preferences, and the designability can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

[0471] By displaying the images captured by a camera device (not shown) provided in the vehicle on the display panel 5704, the field of view (blind spot) blocked by the pillar can be compensated for. That is, by displaying the images captured by the camera device provided outside the vehicle, the blind spot can be compensated for, thereby improving safety. In addition, by displaying the images that make up for the parts that cannot be seen, safety can be confirmed more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

[0472] Since the GPU or chip of one aspect of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in the vehicle's autonomous driving system. The chip can also be used in systems for navigation, danger prediction, etc. In addition, information such as navigation and danger prediction can be displayed on the display panels 5701 to 5704.

[0473] Although a vehicle is illustrated as an example of the moving body in the above example, the moving body is not limited to a vehicle. For example, as the moving body, a tram, a monorail, a ship, a flying object (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc. can also be cited, and the chip of one aspect of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0474] [Electrical appliance product]

[0475] Figure 26H An electric refrigerator-freezer 5800 showing an example of an electrical appliance product. The electric refrigerator-freezer 5800 includes a cabinet 5801, a refrigerator door 5802, a freezer door 5803, etc.

[0476] By applying the chip of one aspect of the present invention to the electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 with artificial intelligence can be realized. By using artificial intelligence, the electric refrigerator-freezer 5800 can be made to have a function of automatically generating a menu based on the food stored in the electric refrigerator-freezer 5800 or the expiration date of the food, and a function of automatically adjusting the temperature of the electric refrigerator-freezer 5800 according to the stored food.

[0477] An electric refrigerator-freezer is illustrated as an example of an electrical appliance product, but as other electrical appliance products, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water dispenser, a heating and cooling air conditioner including an air conditioner, a washing machine, a dryer, an audio-visual device, etc. can be cited.

[0478] The electronic device, the functions of the electronic device, the application examples of artificial intelligence, and their effects, etc. described in the present embodiment can be implemented by appropriately combining with the descriptions of other electronic devices.

[0479] This embodiment can be implemented by appropriately combining the structures described in other embodiments and the like.

[0480] [Symbol Explanation]

[0481] 100: Capacitor, 100a: Capacitor, 100A: Capacitor, 100b: Capacitor, 100B: Capacitor, 110: Conductor, 110A: Conductive film, 120: Conductor, 120A: Conductive film, 130: Insulator, 130A: Insulating film, 150: Insulator, 152: Conductor, 153: Conductor, 154: Insulator, 156: Insulator, 200: Transistor, 200a: Transistor, 200A: Transistor, 200b: Transistor, 200B: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 205c: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 214a: Insulator, 214b: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230c: Oxide, 230C: Oxide film, 231: Region, 231a: Region, 231b: Region, 232: Region, 232a: Region, 232b: Region, 234: Region, 241: Insulator, 242: Conductor, 242a: Conductor, 242A: Conductive film, 242b: Conductor, 242B: Conductor layer, 245: Conductor, 247: Conductor, 247a: Conductor, 247b: Conductor, 247c: Conductor, 249: Region, 249a: Region, 249b: Region, 250: Insulator, 250A: Insulating film, 256: Insulator, 260: Conductor, 260a: Conductor, 260A: Conductive film, 260b: Conductor, 260B: Conductive film, 280: Insulator, 281: Insulator, 282: Insulator, 288: Filler, 290: Opening, 292: Conductor.

Claims

1. A semiconductor device, comprising: a transistor, a capacitor, an electrode, and an interlayer film, wherein the transistor includes a semiconductor layer, a gate, a source, and a drain, the transistor and the capacitor are arranged in a manner of being embedded in the interlayer film, one of the source and the drain is in contact with the electrode below the semiconductor layer, the other of the source and the drain is in contact with one electrode of the capacitor above the semiconductor layer, wherein an opening reaching the other of the source and the drain is provided in the interlayer film, and one electrode of the capacitor is arranged along the side surface and the bottom surface of the opening.

2. The semiconductor device according to claim 1, Among them, an insulator is provided between the one electrode of the capacitor and the interlayer film.

3. The semiconductor device according to claim 1, Among them, the semiconductor layer is an oxide semiconductor.

4. A semiconductor device, comprising: a first transistor and a capacitor, wherein the first transistor includes: a first to fourth conductor, a first to fourth insulator, and a first and a second oxide, wherein the first insulator is arranged on the first conductor, the first oxide is arranged on the first insulator, a first opening reaching the first conductor is provided in the first insulator and the first oxide, the second conductor and the third conductor separated from each other are arranged on the first oxide, at least a part of the second conductor overlaps with the first opening and is in contact with the top surface of the first conductor, the second oxide is arranged on the first oxide in a manner that at least a part of it overlaps with the region between the second conductor and the third conductor, the second insulator is arranged on the second oxide, the fourth conductor is arranged on the second insulator, the third insulator is arranged on the first insulator, the second conductor, and the third conductor, the fourth insulator is arranged in contact with the top surface of the third insulator, the top surface of the second oxide, the top surface of the second insulator, and the top surface of the fourth conductor, a second opening reaching the third conductor is provided in the third insulator and the fourth insulator, the capacitor includes: a fifth and a sixth conductor, and a fifth insulator, wherein the fifth conductor is arranged in contact with the top surface of the third conductor in the second opening, the fifth insulator is arranged on the fifth conductor and the fourth insulator, and the sixth conductor is arranged on the fifth insulator.

5. The semiconductor device according to claim 4, Among them, a sixth insulator is further included between the fifth conductor and the third insulator.

6. The semiconductor device according to claim 5, Among them, the sixth insulator has a lower hydrogen permeability than the third insulator.

7. The semiconductor device according to claim 4, Among them, when viewed from above, the length of the fifth conductor in the channel width direction is shorter than the length of the first oxide in the channel width direction.

8. The semiconductor device according to claim 4, Among them, The height of a part of the top surface of the fifth conductor is the same as the height of the top surface of the fourth insulator.

9. The semiconductor device according to claim 4, further comprising: A seventh conductor disposed under the first insulator and overlapping at least a part thereof with the fourth conductor.

10. The semiconductor device according to claim 4, Among them, The third conductor is in contact with the side surface of the first oxide in the first opening.

11. The semiconductor device according to claim 4 further comprises: A seventh insulator disposed between the second conductor, the third conductor and the third insulator.

12. The semiconductor device according to claim 4, Among them, The first oxide and the second oxide contain In, element M and Zn, where M is Al, Ga, Y or Sn.

13. The semiconductor device according to claim 4, Among them, A second transistor is further provided under the first conductor, and a source or a drain of the second transistor is electrically connected to the first conductor.

14. The semiconductor device according to claim 13, Among them, The second transistor is formed on a silicon substrate.

15. The semiconductor device according to claim 13, Among them, The second transistor contains a third oxide.

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