storing contingent branch predictions to reduce latency of error prediction recovery

Abstract

A branch predictor predicts a first outcome for a first branch in a first block of instructions. Fetch logic fetches instructions for speculative execution along a first path indicated by the first outcome. In response to taking the first predicted outcome, information representing a remainder of the first block is stored. In response to not taking the first branch instruction, the branch predictor is restarted based on the remainder block. In some cases, an address of the first block is used as an index into a branch prediction structure to access an entry corresponding to a second block along a speculative path from the first block. A corresponding set of instances of branch condition logic are used to simultaneously predict outcomes for branch instructions in the second block, and in response to a misprediction, the predicted outcomes are used in combination with the remainder block to restart the branch predictor.

Description

Background Technology

[0001] The processing unit uses branch prediction to guess the outcome of branch instructions, allowing it to speculatively execute subsequent instructions along the predicted branch before evaluating the branch instruction itself. The processing unit uses information in the branch prediction structure to predict the outcome of branch instructions. For example, the processing unit can predict the outcome of conditional branch instructions that implement software constructs such as if-then-else and case statements. Examples of branch prediction structures include: an indirect branch predictor that redirects program flow to arbitrary instructions; a return address stack containing the return addresses of subroutines executed on the processing unit; a conditional branch predictor that predicts the direction (take or not take) of conditional branches; and a branch destination buffer containing information about the location, type, and destination address of the predicted branch instruction.

[0002] Some implementations of branch prediction structures use branch history—the result of branch instructions executed by procedures previously or currently executing on a processing unit—as part of the prediction algorithm. For example, if a branch instruction previously directed program flow to a first address 90% of the time and to a second address 10% of the time, the corresponding entry in the branch prediction structure predicts that the branch instruction will direct program flow to the first address, allowing the process to speculatively execute instructions along a branch starting at the first address without waiting for the branch instruction to be evaluated. If the predicted branch result is incorrect when the branch instruction is evaluated, speculative execution along the incorrectly predicted branch is paused, and the state of the processing unit is rolled back to the state at the time of the branch instruction to begin execution along the correct branch. More specifically, both the branch prediction unit and the fetch unit roll back to process from the correct target of the branch or from an address after the branch (if the branch is not used). Attached Figure Description

[0003] By referring to the accompanying drawings, those skilled in the art can better understand this disclosure and appreciate its numerous features and advantages. The same reference numerals are used in different drawings to indicate similar or identical items.

[0004] Figure 1 It is a block diagram of a processing system based on some implementation schemes.

[0005] Figure 2 It is a block diagram of a processing system, including a processor core, according to some implementation schemes.

[0006] Figure 3 It is a block diagram of a prediction block based on some implementation schemes and a set of blocks corresponding to different possible results of branch instructions in the prediction block.

[0007] Figure 4It is a block diagram of a processing system that includes a branch target buffer and a branch prediction structure, according to some implementation schemes.

[0008] Figure 5 This is a flowchart of a method for recovering from branch prediction errors using stored prediction information based on some implementation schemes, in order to reduce the latency of branch prediction recovery.

[0009] Figure 6 This is a block diagram of a processing system that implements "advance prediction" branch prediction based on some implementation schemes.

[0010] Figure 7 This is a flowchart of the first part of a method for recovering from branch error predictions using stored prediction information according to some implementation schemes, in order to reduce the latency of branch prediction recovery used for "predicting" branch predictions.

[0011] Figure 8 This is a flowchart of the second part of a method for recovering from branch error predictions using stored prediction information according to some implementation schemes, in order to reduce the latency of branch prediction recovery used for "early prediction" of branch predictions. Detailed Implementation

[0012] Some implementations of the processing unit execute multiple instructions simultaneously. For example The processing unit can execute 4 to 8 instructions per cycle. Therefore, the branch predictor simultaneously predicts the results of multiple branch instructions within an instruction block (referred to here as the prediction block). The prediction block begins at a start address, such as the boundary address of the previous branch instruction or the destination address. The prediction block ends at an end address, such as the address of the subsequent boundary instruction. For example The prediction block ends at the address corresponding to the 64-byte cache line boundary or the address of the first branch instruction adopted in the prediction block. If the branch predictor is configured to predict the results of two branch instructions simultaneously, the branch predictor uses the address of the prediction block as an index into a prediction structure (such as a branch target buffer BTB) that stores the addresses of the two branches, the types of the two branches, the target address of the adopted branch, and an indication of whether there are any additional branch instructions in the prediction block.

[0013] The branch predictor instructs the fetch logic to fetch instructions along the path predicted by the results of the two branch instructions. For example, if the first branch instruction is not used, the branch predictor instructs the fetch logic to fetch instructions along the path that includes the second branch instruction, causing the program flow to proceed sequentially to the second branch instruction. The branch predictor then instructs the fetch logic to fetch subsequent instructions based on the prediction of the second branch instruction. However, if the branch predictor predicts that the first branch instruction will be used, the program does not flow to the second branch instruction and discards the prediction information generated for the second branch instruction. In some cases, the branch predictor incorrectly predicts the result of the first branch instruction, causing the processing unit to roll back to the state at the branch instruction and subsequently execute instructions along the sequential path that includes the second branch instruction. However, the second branch prediction information is no longer available to the branch predictor, and the branch predictor must recalculate the prediction result of the second branch instruction. Recalculating the prediction result of the second branch instruction increases the latency in the branch prediction pipeline.

[0014] In the "pre-prediction" technique, the address of the first block is used as an index to access information in the branch prediction structure and the branch predictor storage. This information includes a set of entries corresponding to a set of possible subsequent blocks, which are the targets of the branch instructions in the first block. In response to the branch predictor predicting the result of the branch instructions in the first block, a subset of entries is selected from this set. The prediction result indicates that the second block includes branch instructions corresponding to the subset of entries, which includes branch prediction information for the branch instructions in the second block. Before determining whether the result of the first block was correctly predicted, the branch predictor uses the information in the subset of entries to predict the result of the branch instructions in the second block. The prediction address of the second block is used as an index to information used to predict the result of the branch instructions in the third block at the address predicted as the result of one of the branch instructions in the second block. If the branch result or target of the first block is incorrectly predicted, the processing unit rolls back to the state at the end of the incorrectly predicted branch instruction in the first block and begins execution along the correct path. If the incorrect prediction is that the branch instruction is "not adopted" and the actual branch result is "adopted," the correct path begins at another point in the set of possible subsequent blocks that are the target of the branch instruction in the first block. If the incorrect prediction is that the branch instruction is "adopted" and the actual branch result is "not adopted," the remainder of the first block is predicted and extracted before proceeding to the second block. Therefore, if the initial branch prediction for the first block is incorrect, the processing unit is required to roll back the branch predictor based on the correct path and recalculate the prediction result for the second block, which increases the latency of the branch predictor.

[0015] Figures 1 to 8A technique for reducing branch prediction latency by simultaneously predicting a first result of a first branch instruction and a second result of a second branch instruction is disclosed. The branch predictor instructs the fetch logic to begin fetching instructions for speculative execution along the path indicated by the first result. The branch predictor also stores the second prediction result, which is also referred to herein as the remainder block prediction. In the absence of a second branch instruction, the remainder block prediction stores information indicating that no additional branches are added in the remainder block up to subsequent memory boundaries. In response to an incorrect prediction of the first result of the first branch instruction, the fetch unit restarts at the correct target of the first branch, and the branch predictor restarts based on the target of the stored second prediction result, saving time by eliminating the need to re-predict the second branch. The remainder block prediction is injected into the later stages of the branch prediction pipeline so that it can be passed to the rest of the processor logic for fetching, decoding, and acknowledging the branch prediction according to conventional mechanisms. Furthermore, the remainder block is generated and stored as a byproduct of the pipeline flow used to execute the original branch prediction. Thus, the branch prediction pipeline can be rolled back and restarted without requiring the branch predictor to initiate additional flows along the pipeline simultaneously with the main flow or in response to incorrect predictions.

[0016] In some implementations, the first and second branch instructions are in a prediction block processed by an instance of a branch predictor that processes both instructions simultaneously. In response to a first result indicating a prediction along an "adopted" path excluding the second branch instruction, the remaining block, including the second prediction result, is stored. In response to an incorrect prediction, the branch predictor begins branch prediction at one of three addresses: (1) the target address of the second branch instruction if the second result indicates an adopted branch, (2) the address of the instruction following the second branch instruction in the prediction block if the third branch instruction is in the prediction block, and (3) a subsequent memory boundary if no additional branch instruction is in the prediction block. Some implementations of the branch predictor store information indicating whether the third branch instruction is in the prediction block. The fetch unit is restarted at the correct target of the first branch, in this case, the sequential address of the first branch.

[0017] In some implementations, the branch predictor uses the address of the first block as an index to access information in the branch prediction structure and the branch predictor storage. This information includes a set of entries corresponding to a set of second blocks, which may be the target of the first block or, if the prediction does not take all branches in the first block, the branch instructions in the block immediately following the first block. The branch predictor predicts that the result of the branch instructions in the first block will be one of the second blocks, and the processing unit begins to execute the instructions in the predicted second block. However, instead of a single copy of the branch predictor's conditional logic that only predicts the result of the predicted second block, multiple copies of the branch predictor's conditional logic are instantiated to simultaneously predict the results of the predicted second block and the branch instructions in the alternative second blocks in the set. For each possible result of the first block, there is an alternative second block. In some implementations, each block holds up to two branches and the first block has three possible prediction results: (1) the first branch is taken, (2) the first branch is not taken and the second branch is taken, or (3) neither the first branch nor the second branch is taken. The three possible second blocks correspond to three prediction results.

[0018] Once the first block has been predicted, one of three possible second blocks is selected as the predicted second block, and the other two are considered alternative predictions. Multiple instances of the conditional logic for the branch prediction structure use branch prediction information from the set of entries corresponding to the second block set to predict (predict and substitute) the results of branch instructions in the second block before determining the prediction of the first block. The prediction result of the branch instructions in the first block indicates the predicted second block, and the address of the predicted second block is used as an index to the branch prediction results in the branch predictor storage for the third block. The branch predictor also stores alternative predictions for the second block. In response to an incorrect prediction of the result of the first block discovered by the execution unit, the fetch unit is restarted at the correct target of the first block, and the branch predictor is restarted based on the target of the stored alternative second block prediction results, which saves time by eliminating the need to re-predict the remaining first and second block predictions. The remaining first block predictions (if applicable) and second block predictions are injected into the later stages of the branch prediction pipeline so that they can be passed to the rest of the processor logic for fetching, decoding, and acknowledging the branch predictions according to conventional mechanisms. If the prediction is to use the first block, but it is determined at execution not to use the first block, then the first block has the predictions of the remaining blocks.

[0019] Figure 1This is a block diagram of a processing system 100 according to some embodiments. The processing system 100 includes or has access to memory 105 or other storage components implemented using non-transitory computer-readable media such as dynamic random access memory (DRAM). However, in some cases, memory 105 is implemented using other types of memory including static random access memory (SRAM), non-volatile RAM, etc. Because memory 105 is implemented outside the processing units implemented in the processing system 100, it is referred to as external memory. The processing system 100 also includes a bus 110 to support communication between entities implemented in the processing system 100, such as memory 105. Some embodiments of the processing system 100 include those not shown for clarity. Figure 1 Other buses, bridges, switches, routers, etc., are shown in the diagram.

[0020] Processing system 100 includes a graphics processing unit (GPU) 115 that renders images for presentation on display 120. For example, GPU 115 renders objects to produce pixel values ​​provided to display 120, which uses these pixel values ​​to display an image representing the rendered object. GPU 115 implements multiple processor cores 121, 122, 123 (collectively referred to herein as "processor cores 121-123") that execute instructions simultaneously or in parallel. The number of processor cores 121-123 implemented in GPU 115 is a design choice. Some implementations of GPU 115 are used for general-purpose computing. GPU 115 executes instructions, such as program code 125, stored in memory 105, and GPU 115 stores information, such as the results of the executed instructions, in memory 105.

[0021] The processing system 100 also includes a central processing unit (CPU) 130, which is connected to bus 110 and thus communicates with GPU 115 and memory 105 via bus 110. CPU 130 implements multiple processor cores 131, 132, and 133 (collectively referred to herein as "processor cores 131-133"), which execute instructions simultaneously or in parallel. The number of processor cores 131-133 implemented in CPU 130 is a design choice. Processor cores 131-133 execute instructions stored in memory 105, such as program code 135, and CPU 130 stores information (such as the results of executed instructions) in memory 105. CPU 130 is also capable of initiating graphics processing by issuing a draw call to GPU 115. Some implementations of CPU 130 implement multiple processor cores (not referred to herein for clarity). Figure 1 (As shown in the figure), it executes instructions simultaneously or in parallel.

[0022] Input / output (I / O) engine 145 handles input or output operations associated with display 120 and other components of processing system 100, such as keyboard, mouse, printer, external disk, etc. I / O engine 145 is coupled to bus 110, enabling it to communicate with memory 105, GPU 115, or CPU 130. In the illustrated embodiment, I / O engine 145 reads information stored on external storage device 150, which is implemented using a non-transitory computer-readable medium (such as optical disc (CD), digital video disc (DVD), etc.). I / O engine 145 is also capable of writing information, such as the results of processing by GPU 115 or CPU 130, to external storage device 150.

[0023] Figure 2 This is a block diagram of a portion 200 of a processing system including a processor core 205, according to some implementation schemes. The processor core 205 is used to implement... Figure 1 Some implementations of processor cores 121-123 and 131-133 are shown. The processing system portion 200 also includes memory 210, which is used to implement... Figure 1 Some embodiments of the memory 105 are shown. The processor core 200 includes a branch prediction unit 215, which includes a conditional branch predictor memory and conditional branch prediction logic. The conditional branch predictor memory stores the address of a location in memory 210, and the conditional branch prediction logic predicts the result of a branch instruction, as discussed in detail below. Copies of some of the information stored in memory 210 are also stored in cache 220. For example, frequently accessed instructions are stored in cache lines or cache blocks of cache 220.

[0024] The extraction unit 225 extracts information, such as instructions, from memory 210 or cache 220 based on the address received from branch prediction unit 215. The extraction unit 225 reads bytes representing instructions from cache 220 or memory 210 and sends the instructions to decoding unit 230. Decoding unit 230 examines the instruction bytes and determines the function of the instruction. Decoding unit 230 translates (…). Right now The processor (decodes) instructions to generate a series of operations to be executed by processor core 205. These operations are written to scheduler 235. Scheduler 235 determines when the source values ​​for the operations are ready and sends the source values ​​to one or more execution units 231, 232, 233, collectively referred to herein as "execution units 231-233", to execute the operations. The results are written back to register file 240.

[0025] Some implementations of the branch prediction unit 215 include entries associated with branch instructions that have previously been executed by the current process or a process previously executed on processor core 205. Branch prediction information stored in each entry of the branch prediction unit 215 indicates the likelihood that the branch instruction will direct program flow to the address of the instruction. Entry in the branch prediction unit 215 is accessed based on the address of the corresponding branch instruction. For example, the value of a bit (or a subset thereof) representing the physical address, virtual address, or cache line address of the branch instruction is used as an index to the branch prediction unit 215. As another example, a hash value of a bit (or a subset thereof) is used as an index to the branch prediction unit 215. Examples of branch prediction structures include indirect branch predictors, return address stacks, branch target buffers, conditional branch predictors, branch history, or any other predictor structure used to store branch prediction information.

[0026] Scheduler 235 schedules instruction execution performed by processor core 205. Some implementations of scheduler 235 perform speculative execution of instructions following branch instructions, which redirect program flow to the instruction at the address in memory 210 (or associated cache 220) indicated by the branch instruction. Branch instructions include conditional branch instructions, which redirect program flow to the address based on whether a condition is true or false. For example, conditional branch instructions are used to implement software constructs such as if-then-else and case statements. Branch instructions also include unconditional branch instructions, which always redirect program flow to the address indicated by the instruction. For example, the JMP instruction always jumps to the address indicated by the instruction. In some cases, the target address is located in a register or memory location, so the target can be different each time the branch is executed. Such branches are called indirect branches.

[0027] Some implementations of scheduler 235 use the returned branch prediction information to predict the destination address of branch instructions. Processor core 205 is then able to speculatively execute the instruction at the destination address, along with subsequent instructions along the predicted branch in the program flow. If the predicted branch result is incorrect when evaluating the branch instruction, speculative execution along the incorrectly predicted branch is paused, and the state of processor core 205 is rolled back to the state at the branch instruction to begin execution along the correct branch.

[0028] The conditional prediction logic in branch prediction unit 215 simultaneously predicts the results of branch instructions within the prediction block. In some embodiments, branch prediction unit 215 simultaneously predicts the first and second results of the first and second branches in the first instruction block. Extraction unit 225 extracts instructions for speculative execution along the first path indicated by the first result. If branch prediction unit 215 predicts the adoption of the first branch instruction, the program flow will not encounter the second branch instruction, and the prediction result of the second branch instruction is typically discarded. However, in the illustrated embodiment, in response to the adoption of the first result, the second result is stored in the alternative prediction memory array in branch prediction unit 215. In response to an incorrect prediction by branch prediction unit 215, Right now If branch prediction unit 215 predicts that a first branch instruction will be used, but the actual result is that the first branch instruction is not used, branch prediction unit 215 will restart based on the stored second prediction result. In some embodiments, the conditional branching logic in branch prediction unit 215 uses the address of the first block as an index to the conditional branch predictor storage device to access entries in the conditional branch predictor storage device that correspond to the second block along the speculative path from the first or second branch instruction. Branch prediction unit 215 then uses the corresponding set of instances of the branch conditional prediction logic to simultaneously predict the results of the branch instructions in the second block set. Alternative predictions for the second block are stored in the alternative prediction storage array in branch prediction unit 215 and are used to restart branch prediction unit 215 in response to erroneous predictions, as discussed in detail below.

[0029] Figure 3 This is a block diagram of a prediction block 300 according to some implementation schemes and a set of blocks 305, 310, and 315 corresponding to different possible outcomes of branch instructions in prediction block 300. Prediction block 300 includes branch instructions 320, 325 and instructions 330, 335. Some implementations of prediction block 300 include additional branch instructions (not shown in the diagram for clarity). Figure 3 (As shown in the diagram). Blocks 305, 310, and 315 include instructions 340, 345, 350, 355, 360, and 365, respectively. Block 305 is identified by a first address, which is the target of branch instruction 320; block 310 is identified by a second address, which is the target of branch instruction 325; and block 315 is identified by a third address, which follows branch instruction 325. In the illustrated embodiment, the third address is used for subsequent instructions, such as instruction 360, at boundaries, such as cache line boundaries between blocks 300 and 315. In other embodiments, the third address is used for subsequent instructions within block 300, such as instruction 335.

[0030] Branch prediction structures, such as Figure 2The branch prediction unit 215 shown simultaneously predicts the results of multiple branch instructions within the prediction block. In the illustrated embodiment, the branch prediction structure simultaneously predicts the results of branch instructions 320 and 325. The possible results of branch instruction 320 are "adopted," in which case the program flow branches to the target address of instruction 340 in block 305, or "not adopted," in which case the program flow sequentially continues to instruction 330 in prediction block 300. The possible results of branch instruction 325 are "adopted," in which case the program flow branches to the target address of instruction 350 in block 310, or "not adopted," in which case the program flow sequentially continues to instruction 335 in prediction block 300.

[0031] The prediction results for branch 325 are stored in the alternative prediction storage array. For example ,exist Figure 2 The branch prediction unit 215 shown is implemented in an array. Some implementations of the branch prediction structure store the prediction result in response to the prediction result of branch instruction 320. In that case, execution is speculatively directed to instruction 340 in block 305, and the program flow does not encounter branch instruction 325. However, if the prediction result is incorrectly predicted, instruction fetching rolls back to the incorrectly predicted branch instruction 320 and the branch predictor is restarted using the stored prediction result of branch instruction 325. Since the branch predictor does not need to re-predict the result of branch instruction 325, the latency required to recover from incorrect prediction is reduced.

[0032] Instructions 340, 345, 350, 355, 360, and 365 in blocks 305, 310, and 315 may include one or more branch instructions. In some implementations, multiple instances of conditional prediction logic are used to simultaneously predict the results of the branch instructions in blocks 305, 310, and 315. For example, the address of block 300 may be used to access information in the conditional branch predictor storage, such as prediction information for blocks 305, 310, and 315. Multiple instances of the conditional prediction logic use the accessed information to predict the results of the branch instructions in blocks 305, 310, and 315. As discussed in detail below, speculative execution proceeds along the path of one block that includes the predictions in blocks 305, 310, and 315, and stores the prediction results of the branch instructions in other blocks 305, 310, and 315. In response to an incorrect prediction of one or more of branch instructions 320 and 325, the stored results are used to restart the conditional prediction logic, as discussed in detail below.

[0033] Figure 4This is a block diagram of a portion of a branch prediction unit 215, including a branch target buffer and a conditional branch predictor, according to some embodiments. Address 405 indicates the starting address of an instruction block. Entries in the branch target buffer are indexed by the starting address of the block associated with the entry. In the illustrated embodiment, index 410 to an entry 415 of the branch target buffer, which includes branch prediction information for branch instructions within the block, includes a value equal to address 405. Therefore, index 410 is used to access entry 415 of the branch target buffer. For example, Figure 3 The address of block 300 shown is used as an index in the entry to the branch target buffer corresponding to branches 320 and 325 in block 300.

[0034] Entry 415 includes branch prediction information for the two branch instructions. For example, entry 415 includes an offset 420 indicating the location of the first branch instruction relative to address 405 and an offset 425 indicating the location of the second branch instruction relative to address 405. The entry also includes information identifying the types 430, 440 of the first and second branch instructions, and the target addresses 435, 445 of the first and second branch instructions. If the first branch instruction is used, the program flow branches from the first branch instruction to the target address 435. Otherwise, the program flow continues sequentially from instruction to instruction within the block until it reaches the second branch instruction. If the second branch instruction is used, the program flow branches from the second branch instruction to the target address 445; otherwise, the program flow continues sequentially from instruction to instruction within the block. An overflow indicator 450 indicates whether an additional branch instruction exists before the next sequence boundary. In some embodiments, the sequence boundary matches the instruction cache line boundary. In other embodiments, the sequence boundary is set at other aligned addresses. Figure 4 Entry 415 shown is an example of an entry in the branch target buffer. Some implementations of entry 415 include different branch prediction information organized or constructed in different ways.

[0035] The branch prediction structure includes a conditional branch predictor storage device 460 and conditional prediction logic 465. The conditional branch predictor storage device 460 stores information for predicting the results of branch instructions. An index 410 is provided to the conditional branch predictor storage device 460 to access the stored information associated with the block indicated by address 405. In some embodiments, additional information such as branch history information 455 is provided to the conditional branch predictor storage device 460. Access information associated with the block starting at address 405 is provided to the conditional prediction logic 465, which also receives branch prediction information for branch instructions within the block from entry 415. The conditional prediction logic 465 uses the information accessed from entry 415 and the conditional branch predictor storage device 460 to predict the results of branch instructions within the block. In the illustrated embodiment, the conditional prediction logic 465 predicts that the first branch instruction is not adopted and the second branch instruction is adopted. Therefore, the conditional prediction logic 465 predicts that the end of the first block is at the location of the second branch instruction (OFFSET_2), and the target address of the second branch instruction is T_ADDR_2.

[0036] Some embodiments of the branch predictor storage device 460 also include an alternative predictor storage array 462, which stores branch prediction information for the remaining blocks if the prediction "takes" one or more branches. The branch prediction information includes information or a similar representation describing the branches in the remaining blocks (if any), the conditional results of the prediction for the branches, the prediction targets for the branches, and the location of the ends of the remaining blocks. The branch prediction information associated with each prediction block in the alternative predictor storage array 462 is indexed based on the corresponding prediction block number. As discussed herein, in the event of a misprediction, the branch prediction information stored in the alternative predictor storage array 462 is used to restart the branch predictor.

[0037] Figure 5 This is a flowchart of method 500, which uses stored prediction information to recover from branch error predictions and restart the branch prediction structure according to some implementation schemes. Method 500 is... Figure 1 The processing system 100 shown and Figure 2 This is implemented in some embodiments of a portion 200 of the processing system shown.

[0038] At box 505, the branch predictor simultaneously predicts the results of the first branch and the second branch in the first block, which is called the prediction block. The prediction blocks are also assigned prediction block numbers, which are allocated in ascending order. When the maximum number of stored prediction blocks is exceeded, the prediction block number is reset to zero. Then, method 500 flows to decision box 510.

[0039] At decision box 510, the branch predictor determines whether to predict whether to use the first branch instruction or the second branch instruction. For example The program flow is predicted to branch to the target address of either the first branch instruction or the second branch instruction. If so, method 500 flows to block 515 and preserves the prediction for the remaining blocks. For example, if the prediction uses the first branch instruction, even if the program flow will not encounter the second branch instruction if the branch predictor correctly predicts the result of the first branch instruction, the remaining blocks will still include the prediction result of the second branch instruction. The branch prediction information for the remaining blocks is written to the alternative prediction memory array. Then, method 500 flows to block 520. If the prediction uses neither the first nor the second branch instruction, method 500 flows directly to block 520.

[0040] At box 520, the extraction unit is instructed to begin extracting instructions to perform speculative execution along the path predicted by the branch predictor.

[0041] At decision box 525, the processing system determines whether the results of the first branch instruction and the second branch instruction in the first block have been incorrectly predicted. If not, and the branch predictor correctly predicted the results of the first branch instruction and the second branch instruction, method 500 proceeds to box 530 and completes the processing of the first block performed by the branch predictor. If at least one of the results of the first branch instruction and the second branch instruction in the first block has been incorrectly predicted, method 500 proceeds to decision box 535.

[0042] At decision box 535, the processing system determines whether the incorrectly predicted branch was actually used. For example If the branch predictor predicts that one of the branch instructions will not be used, and the actual result is that the branch instruction is used and the program flow branches to the target address of the branch instruction. If not, the branch predictor predicts that the branch will be used, and the actual result is that the branch is not used. Then, method 500 flows to block 540. If the branch predictor predicts that the branch will not be used, and the actual result is that the branch is used. Then, method 500 flows to block 545.

[0043] At box 540, program flow rolls back to the incorrectly predicted branch instruction. For example, if the branch predictor predicts that the first branch instruction will be taken, and the actual result is that the first branch instruction is not taken, program flow rolls back to the first branch instruction, and the fetch unit begins fetching instructions where the next instruction follows the first branch instruction in the prediction block. The remaining blocks stored (from box 515) are read from the alternative prediction memory array using the prediction block number of the incorrectly predicted branch. The branch predictor is restarted based on the target of the stored second prediction result, which saves time by eliminating the need to re-predict the second branch. The remaining block predictions are injected later in the branch prediction pipeline so that they can be passed to the rest of the processor logic for fetching, decoding, and acknowledging the branch predictions as usual. Thus, the branch predictor begins prediction at the next block, which is the block at the target address of the second branch instruction if the prediction is to take it, or the block following the second branch instruction if the prediction is not to take it. The block following the second branch instruction includes a block with additional branch instructions from the predicted block (if the predicted block includes more than two branch instructions); or a block that begins at the boundary of the next block after the predicted block (if there are no additional branch instructions in the predicted block).

[0044] At box 545, program flow is rolled back to the mispredicted branch instruction, and both branch prediction and instruction fetching begin at the actual target of the mispredicted branch instruction. For example, if the branch predictor predicts that the first branch instruction will not be used and the actual result of the first branch instruction is used, program flow rolls back to the first branch instruction and the fetch unit begins fetching the instruction at the target address of the first branch instruction. The branch predictor also begins predicting the result of the instruction at the block that begins at the target address.

[0045] Figure 6 This is a block diagram of a processing system 600 that implements "advance prediction" branch prediction according to some implementation schemes. Processing system portion 600 is used to implement... Figure 1 The processing system 100 shown and Figure 2 Some embodiments of a portion 200 of the processing system shown. A portion 600 of the processing system uses the address of a previous block as an index 605 to the branch target buffer memory 610 to perform "advance prediction" branch prediction to access branch prediction information for blocks associated with the prediction results of branch instructions within the previous block. In the illustrated embodiment, portion 600 simultaneously predicts the results of two branch instructions for each block. However, some embodiments of portion 600 simultaneously predict the results of more branch instructions for each block.

[0046] Index 605 is used to access entries in the branch target buffer memory 610 for three blocks associated with the results of two branch instructions in the previous block. For example, for the first block, there are three possible predicted results: (1) take the first branch, (2) do not take the first branch and take the second branch, or (3) do not take either the first or the second branch. These three possible results correspond to the three blocks associated with index 605. For example, block 305 corresponds to the... Figure 3 In block 300, the first branch is used at branch instruction 320. Block 310 corresponds to... Figure 3 In block 300 shown, the first branch is not used at branch instruction 320, and the second branch is used at branch instruction 325. Block 315 corresponds to... Figure 3 In block 300 shown, neither the first branch nor the second branch is used at branch instructions 320 and 325.

[0047] Some implementations of the branch target buffer memory 610 implement associative access to branch target buffer entries. For example, if the branch target buffer is 4-way set-associative, four entries are read from the branch target buffer memory 610 based on index 605. Multiple instances of the branch target buffer hit logic 615 are used to compare the tags of the blocks associated with the results of branch instructions in the previous block with the tags in the entries read from the branch target buffer memory 610. Each instance of the branch target buffer hit logic 615 compares the tags of one block in the block to identify the predicted next (second) block and two alternative following (second) blocks. The second block is provided to the corresponding instance of the conditional prediction logic 620.

[0048] Part 600 includes a conditional branch predictor storage device 625 that stores information for predicting the results of branch instructions. An index 605 is provided to the conditional branch predictor storage device 625 to access stored information associated with a second block indicated by the address of a previous block included in index 605. In some embodiments, additional information such as branch history information 630 is provided to the conditional branch predictor storage device 625. Access information associated with the set of second blocks is provided to multiple instances of conditional prediction logic 620, which also receives branch prediction information for branch instructions in the corresponding second block from multiple instances of branch target buffer hit logic 615. Instances of conditional prediction logic 620 use the information received from the branch target buffer hit logic 615 and the corresponding instances of conditional branch predictor storage device 625 to predict the result 635 of the branch instructions in the second block. As discussed herein, the result 635 indicates whether the branch instructions in each block of the block should be adopted or not, the end address of the second block, and, if the branch instructions should be adopted, the address of subsequent instructions, such as the target address.

[0049] Some embodiments of the branch predictor storage device 625 include an alternative prediction storage array 627 for storing branch prediction information for the prediction block and the remaining blocks of the alternative block. The branch prediction information includes information or similar representations describing branches (if any) in the remaining blocks, the conditional results of the branch prediction, the prediction target of the branch, and the position of the end of the remaining block. Similar information is stored for use with the alternative block. For example, the alternative prediction storage array 627 may store information or similar representations describing branches, the conditional results of the branch prediction, the target of the branch, and the position of the end of the block. Additionally, indications are stored to indicate the results of the first block predicted corresponding to the second block of the alternative. The branch prediction information in the alternative prediction storage array 627 is indexed based on the corresponding prediction block number. As discussed below, the branch prediction information stored in the alternative prediction storage array 627 is used to restart the branch predictor in the event of a misprediction.

[0050] Figure 7 This is a flowchart of the first part 700 of a method for rolling back the program flow and branch predictor in response to branch prediction errors during "advance prediction" branch prediction, according to some implementation schemes. The first part 700 of the method is... Figure 1 The processing system 100 shown and Figure 2 This is implemented in some embodiments of part 200 of the processing system shown.

[0051] At box 705, the branch predictor simultaneously predicts the results of the first branch and the second branch in the first block. As discussed herein, different combinations of the results of the first branch and the second branch in the first block correspond to different destination second blocks. The branch predictor identifies one of the second blocks as the "predicted" second block based on the prediction results of the first branch and the second branch. The second block corresponding to other results is identified as the "alternative" second block. Part 700 of the method then flows to decision box 710.

[0052] At decision box 710, the branch predictor determines whether to predict whether to use the first branch instruction or the second branch instruction. For exampleThe method predicts the target address of either the first branch instruction or the second branch instruction in the program flow. If so, part 700 of the method flows to box 715 and retains the prediction of the remaining blocks. For example, if the prediction is to take the first branch instruction, the remaining blocks will include the prediction of the second branch instruction even if the program flow does not encounter the second branch instruction if the branch predictor correctly predicts the result of the first branch instruction. Information about the remaining blocks is retained by writing entries in an alternative prediction memory array corresponding to their prediction block numbers. Then, part 700 of the method flows to box 720. If neither the first nor the second branch instruction is predicted to be taken, part 700 of the method flows directly to box 720.

[0053] At block 720, multiple instances of conditional prediction logic are used to predict the results of first and second branch instructions in the predicted second block and the alternative second block. In some embodiments, a first instance of the conditional prediction logic predicts the results of the first and second branch instructions in the predicted second block, a second instance predicts the results of the first and second branch instructions in one of the alternative second blocks, and a third instance predicts the results of the first and second branch instructions in the other of the alternative second blocks. However, in other embodiments, some or all of the second blocks include more or fewer branch instructions.

[0054] At box 725, the prediction of the result of the branch instruction in the alternative second block is preserved by writing information to an entry in the alternative prediction storage array corresponding to the prediction block number of the first prediction block. The stored information is information or a similar representation describing the branch, the prediction condition result of the branch, the target of the branch, and the position of the end of the block. Additionally, an indication is stored to indicate the result of the first block corresponding to the prediction of the alternative second block.

[0055] At box 730, the extraction unit is instructed to begin extracting instructions for speculative execution along the path predicted by the branch predictor. In the illustrated embodiment, the extraction unit begins extracting instructions along the path that includes the predicted second block.

[0056] At decision box 730, the processing system determines whether the results of the first branch instruction and the second branch instruction in the first block have been incorrectly predicted. If not, and the branch predictor correctly predicted the results of the first branch instruction and the second branch instruction, part 700 of the method flows to box 740 and completes the processing of the first block by the branch predictor. If at least one of the results of the first branch instruction and the second branch instruction in the first block has been incorrectly predicted, part 700 of the method flows to node 1.

[0057] Figure 8This is a flowchart of the second part 800 of a method, according to some implementation schemes, for rolling back the program flow and restarting the branch predictor in response to a branch prediction error during the "advance prediction" prediction period. The second part 800 of the method is... Figure 1 The processing system 100 shown and Figure 2 This is implemented in some embodiments of part 200 of the processing system shown. The second part 800 of the method begins at node 1, which corresponds to... Figure 7 Node 1 is shown.

[0058] At box 805, the program flow rolls back to the error-predicted branch instruction, which can be either the first branch instruction or the second branch instruction in the first block.

[0059] At decision box 810, the processing system determines whether the incorrectly predicted branch was actually used. For example If the branch predictor predicts that one of the branch instructions in the first block will not be used, and the actual result is that the branch instruction is used, the program flow branches to the target address of the branch instruction. If not, and the branch predictor predicts that the branch will be used, but the actual result is that the branch is not used, then part 800 of the method flows to block 815.

[0060] At box 815, the remaining blocks (derived from the memory used for the first block) are read from the alternative prediction memory array using the predicted block number of the incorrectly predicted branch. Figure 7 (See box 715 in the original text). The remaining block predictions are injected into the later stages of the branch prediction pipeline, so they can be passed to the rest of the processor logic for extraction, decoding, and confirmation of the branch predictions as per the conventional mechanism. Therefore, the branch predictor begins prediction at the next block, which is one of the replacements for the second block. For example If a second branch instruction is predicted to be used, the block is located at the target address of the second branch instruction; otherwise, if a second branch instruction is not predicted to be used, the block is located after the second branch instruction. The block following the second branch instruction includes blocks with additional branch instructions from the first block (if the first block contains more than two branch instructions); or blocks that begin at the boundary of the next block after the first block (if no additional branch instructions exist in the first block).

[0061] If a mispredicted branch is actually used (as determined at decision box 810) and the branch predictor predicts that no branch will be used but the actual result is that a branch is used, then part 800 of the method flows to box 820.

[0062] At block 820, the prediction of the result of the branch instruction in the second block, which corresponds to the branch actually adopted from the first block, is injected into the later part of the branch prediction pipeline (but only after the prediction of the rest of the pipeline, if applicable), because it can be passed to the rest of the processor logic for fetching, decoding, and acknowledging the branch prediction according to the normal mechanism. Therefore, the branch predictor does not need to repeat the prediction of the second block in response to a branch misprediction.

[0063] At box 825, the branch predictor begins predicting the result of a branch instruction in the block following the second block of the substitution. Some implementations of the branch predictor begin predicting the result of a branch instruction in the block corresponding to the target address of the branch instruction in the second block of the substitution (if the predicted branch instruction is to be used), the address of a subsequent branch instruction in the second block of the substitution (if an additional branch instruction exists in the second block of the substitution and the predicted branch instruction is not used), or the address of a subsequent branch instruction in the block following the second block of the substitution (if no additional branch instruction exists in the second block of the substitution and the predicted branch instruction is not used).

[0064] accomplish Figure 7 and Figure 8 The processing system of the illustrated embodiment of the method stores predictions for the second block of all alternatives. In other embodiments, fewer than all predictions are stored. For example, the processing system may store predictions for the second block of a single alternative. The second block of an alternative selected for storage is chosen based on the probability that the second block of the alternative will be located on the actual path of the program flow, a confidence measure, or by using arbitrary selection criteria (such as selecting the second block of the first alternative in all cases). If, in such an embodiment, error prediction recovery does not find an alternative prediction for the second block in the alternative prediction storage array, the branch predictor restarts at the target of the first block, not at the target of the second block.

[0065] As disclosed herein, a method includes: predicting a first result of a first branch instruction in a first instruction block at a branch predictor; instructing fetching logic to begin fetching instructions for speculative execution along a first path indicated by the first prediction result; storing a remaining block, representing the remainder of the first block, in response to using the first prediction result; and restarting the branch predictor based on the remaining block in response to not using the first branch instruction. In one aspect, predicting the first result of the first branch includes simultaneously predicting the first result of the first branch instruction in the first instruction block and a second result of a second branch instruction. In another aspect, storing the remaining block includes storing a remaining block including information indicating the second prediction result in response to using the first prediction result and the first path not including the second branch instruction. In yet another aspect, restarting the branch predictor includes restarting the branch predictor based on the information in the remaining block indicating the second prediction result.

[0066] On another front, restarting the branch predictor includes restarting the branch predictor to begin branch prediction at a second block identified by one of the following: the target address of the second branch instruction in response to a second prediction result indicating that the second branch instruction is adopted; the address of the instruction following the second branch instruction in response to a second prediction result indicating that the second branch instruction is not adopted and the first block includes at least one third branch instruction; and the boundary of the first block in response to a second prediction result indicating that the second branch instruction is not adopted and the first block does not include the at least one third branch instruction. On yet another front, the first block does not include the second branch instruction before a subsequent memory boundary, and the remaining blocks include information indicating that the first block does not include the second branch instruction before the subsequent memory boundary. On yet another front, restarting the branch predictor includes restarting the branch predictor at the subsequent memory boundary indicated in the remaining blocks. On yet another front, the address of the first block is used as an index to access information in the branch prediction structure, wherein the information includes a set of entries corresponding to the second block set along a predicted path from the first block.

[0067] As disclosed herein, an apparatus includes: a branch predictor configured to predict a first result of a first branch instruction in a first instruction block; extraction logic for extracting instructions for speculative execution along a first path indicated by the first prediction result; and an alternative prediction storage array in the branch predictor for storing information representing the remainder of the first block in response to adopting the first prediction result, wherein the branch predictor is restarted based on the information representing the remainder in response to not adopting the first branch instruction. In one aspect, the branch predictor is configured to simultaneously predict the first result of the first branch instruction in the first instruction block and a second result of a second branch instruction. In another aspect, the alternative prediction storage array is configured to store the remainder of the block, including information indicating the second prediction result, in response to adopting the first prediction result and the first path not including the second branch instruction. In yet another aspect, the branch predictor is restarted based on the information in the remainder of the block indicating the second prediction result.

[0068] In another aspect, the branch predictor is restarted to begin branch prediction at a second block identified by one of the following: the target address of the second branch instruction in response to a second prediction result indicating that the second branch instruction is adopted; the address of the instruction following the second branch instruction in response to a second prediction result indicating that the second branch instruction is not adopted and the first block includes at least one third branch instruction; and the boundary of the first block in response to a second prediction result indicating that the second branch instruction is not adopted and the first block does not include the at least one third branch instruction. In another aspect, the first block does not include the second branch instruction up to a subsequent memory boundary, and wherein the remaining blocks include information indicating that the first block does not include the second branch instruction up to a subsequent memory boundary. In yet another aspect, the branch predictor is configured to restart at the subsequent memory boundary indicated in the remaining blocks. In yet another aspect, the device includes a branch prediction structure configured to store a set of entries corresponding to a set of second blocks along a predicted path from the first block, wherein the branch predictor is configured to access the branch prediction structure using the address of the first block as an index.

[0069] As disclosed herein, a method includes: predicting a first result of a first branch instruction in a first instruction block at a branch predictor; selectively storing a remaining block in an alternative prediction memory array in the branch predictor based on whether the first result should be adopted or not, wherein the remaining block indicates the remainder of the first block; and restarting the branch predictor based on the remaining block in response to actual results of the predictions of adopting and not adopting the first branch instruction. In one aspect, selectively storing the remaining block includes storing at least one of information indicating a second prediction result of a second branch instruction in the first block and information indicating that the first block does not contain any branch instructions up to a subsequent memory boundary.

[0070] In some implementations, the devices and techniques described above are used in systems including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips) (such as those described in the above references). Figures 1 to 8 The described processing system is implemented within this system. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used for the design and fabrication of these IC devices. These design tools are typically represented as one or more software programs. These one or more software programs include code executable by a computer system to manipulate the computer system to operate on code representing a circuit of one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system to fabricate the circuit. This code may include instructions, data, or a combination of instructions and data. Software instructions representing design or fabrication tools are typically stored in a computer-readable storage medium accessible by a computing system. Similarly, code representing one or more stages of the design or fabrication of an IC device may be stored in and accessed from the same computer-readable storage medium or different computer-readable storage media.

[0071] Computer-readable storage media may include any non-transitory storage medium or a combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact optical discs (CDs), digital versatile optical discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard disks), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. Computer-readable media may be embedded in a computing system (e.g., system RAM or ROM), permanently attached to a computing system (e.g., a magnetic hard disk drive), removably attached to a computing system (e.g., an optical disc or a USB-based flash memory), or coupled to a computer system via a wired or wireless network (e.g., network accessible storage (NAS)).

[0072] In some implementations, certain aspects of the techniques described above may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by one or more processors, instruct one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, disk or optical disk storage devices, solid-state storage devices such as flash memory, cache, random access memory (RAM), or one or more other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may be in the form of source code, assembly language code, object code, or other instruction formats that are interpreted by one or more processors or can be executed in other ways.

[0073] It should be noted that not all activities or elements described in the general description above are necessary. A particular activity or apparatus may be unnecessary and may perform one or more other activities, or may include elements other than those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Additionally, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, this specification and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure.

[0074] The benefits, other advantages, and solutions to the problems described above with reference to specific embodiments have been explained. However, the benefits, advantages, solutions to the problems, and any features that may bring about or make more prominent any benefit, advantage, or solution to the problems should not be construed as key, essential, or necessary features of any or all claims. Moreover, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways that will be readily apparent to those skilled in the art who have benefited from the teachings herein. No limitation is intended to be made on the details of the construction or design shown herein other than those described in the appended claims. Therefore, it is apparent that the specific embodiments disclosed above may be altered or modified, and all such variations are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.

Claims

1. A method comprising: predicting, at a branch predictor, a first outcome for a first branch instruction in a first instruction block and a second outcome for a remainder of the first instruction block; directing fetch logic to begin fetching instructions for speculative execution along a first path indicated by the predicted first outcome; selectively storing the predicted second outcome in an alternative prediction storage array of the branch predictor, wherein selectively storing comprises storing the predicted second outcome in response to predicting that the first outcome is to be taken; and in response to predicting that the first branch instruction is to be taken and not being taken, restarting the branch predictor based on the predicted second outcome.

2. The method of claim 1, wherein predicting the first outcome for the first branch instruction comprises predicting the first outcome for the first branch instruction and the second outcome simultaneously, wherein the predicted second outcome is for a second branch instruction in the first instruction block.

3. The method of claim 2, wherein storing the predicted second outcome comprises storing information associated with the remainder of the first instruction block that includes information indicating the predicted second outcome in response to at least the first path not including the second branch instruction.

4. The method of claim 1, wherein storing the predicted second outcome comprises storing the predicted second outcome in an alternative prediction storage array of the branch predictor.

5. The method of claim 2, wherein restarting the branch predictor comprises restarting the branch predictor to begin branch prediction at a second block identified by one of: a target address of the second branch instruction in response to the predicted second outcome indicating that the second branch instruction is to be taken; an address of an instruction after the second branch instruction in response to the predicted second outcome indicating that the second branch instruction is not to be taken and the first instruction block including at least one third branch instruction; and a boundary of the first instruction block in response to the predicted second outcome indicating that the second branch instruction is not to be taken and the first instruction block not including the at least one third branch instruction.

6. The method of claim 1, wherein: the first instruction block does not include a second branch instruction before a subsequent memory boundary, and wherein the remainder of the block includes information indicating that the first instruction block does not include the second branch instruction before the subsequent memory boundary; and restarting the branch predictor comprises restarting the branch predictor at the subsequent memory boundary indicated in the remainder of the block.

7. The method of claim 1, further comprising: using an address of the first instruction block as an index to access information in a branch prediction structure, wherein the information includes a set of entries corresponding to a second set of blocks along a speculative path from the first instruction block.

8. An apparatus comprising: a branch predictor configured to predict a first outcome for a first branch instruction in a first instruction block and to predict a second outcome for a remainder of the first instruction block; fetch logic to fetch instructions for speculative execution along a first path indicated by a predicted first result; and an alternative prediction storage array in the branch predictor to selectively store a predicted second result in response to predicting that the first branch instruction is to be taken with the predicted first result, wherein in response to predicting that the first branch instruction is to be taken and not actually taken, the branch predictor is restarted based on the predicted second result.

9. The apparatus of claim 8, wherein the branch predictor is configured to simultaneously predict the first result for the first branch instruction and the second result, wherein the predicted second result is for a second branch instruction in the first instruction block.

10. The apparatus of claim 9, wherein the alternative prediction storage array is configured to store the predicted second result in response to at least the first path not including the second branch instruction.

11. The apparatus of claim 9, wherein the branch predictor is restarted based on the predicted second result.

12. The apparatus of claim 9, wherein the branch predictor is restarted to start branch prediction at a second block identified by one of: a target address of the second branch instruction in response to the predicted second result indicating that the second branch instruction is to be taken; an address of an instruction after the second branch instruction in response to the predicted second result indicating that the second branch instruction is not to be taken and the first instruction block including at least one third branch instruction; and a boundary of the first instruction block in response to the predicted second result indicating that the second branch instruction is not to be taken and the first instruction block not including the at least one third branch instruction.

13. The apparatus of claim 9, wherein the first instruction block does not include a second branch instruction until a subsequent memory boundary, and wherein the remainder block includes information indicating that the first instruction block does not include the second branch instruction until the subsequent memory boundary.

14. The apparatus of claim 13, wherein the branch predictor is configured to restart at the subsequent memory boundary indicated in the remainder block.

15. The apparatus of claim 8, further comprising: a branch prediction structure configured to store a set of entries corresponding to a second set of blocks along a speculative path from the first instruction block, wherein the branch predictor is configured to access the branch prediction structure using an address of the first instruction block as an index.

16. A method comprising: predicting, at a branch predictor, a first result for a first branch instruction in a first instruction block and a second result for a remainder block of the first instruction block; selectively storing the predicted second result in an alternative prediction storage array in the branch predictor, wherein the remainder block indicates a remainder of the first instruction block; and responsive to predicting that the first branch instruction is to be taken and an actual result of not taking the first branch instruction, restarting the branch predictor based on the predicted second result.

17. The method of claim 16, wherein selectively storing the predicted second result comprises storing at least one of: the remainder block including information indicating the predicted second result, or the remainder block including information indicating that the first instruction block does not include any branch instructions until a subsequent memory boundary.

Images