Cache system for main and speculation threads of a processor

Abstract

A cache system has a cache set, and the cache set has a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system also has a control register and a mapping circuit coupled to the control register to map respective physical outputs of the cache set to a first logical cache and a second logical cache according to a state of the control register. The first logical cache can be a normal or main cache for non-speculative execution by a processor, and the second logical cache can be a shadow cache for speculative execution by the processor.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 528,489, filed July 31, 2019, entitled “Cache Systems for Main and Speculative Threads of Processors,” the entire disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] At least some of the embodiments disclosed herein generally relate to cache architectures, and more specifically, but not limited to, cache architectures for main execution and speculative execution performed by a computer processor. Background Technology

[0004] A cache is a memory component that stores data closer to the processor than main memory, so that data stored in the cache can be accessed by the processor. Data can be stored in the cache because of earlier computations or accesses to data in main memory. A cache hit occurs when the data requested by the processor using a memory address is found in the cache, and a cache miss occurs when the data cannot be found in the cache.

[0005] Generally, a cache is a memory that stores data recently used by the processor. The memory blocks placed in the cache are correspondingly constrained by the cache lines of the placement strategy. There are three generally known placement strategies: direct mapping, fully associative, and set associative. In a direct mapping cache structure, the cache is organized into multiple sets with a single cache line per set. Based on the address of the memory block, it may occupy only a single cache line. For a direct mapping cache, the cache can be designed as an (n*1) column matrix. In a fully associative cache structure, the cache is organized into a single cache set with multiple cache lines. Memory blocks may occupy any one of the cache lines in a single cache set. A cache with a fully associative structure can be designed as a (1*m) row matrix.

[0006] Set-associative caches are intermediate-design caches with a structure that is intermediately grounded between direct-mapped caches and fully associative caches. A set-associative cache can be designed as an (n*m) matrix, where neither n nor m is 1. The cache is divided into n cache sets, each containing m cache lines. Memory blocks can be mapped to cache sets and then placed into any cache line of those sets. When considering the hierarchy of set associativity, a set-associative cache can encompass a range from directly mapped to fully associative caches. For example, a direct-mapped cache can also be described as a unidirectional set-associative cache, and a fully associative cache with m blocks can be described as an m-directional set-associative cache. Directed-mapped caches, bidirectional set-associative caches, and four-directional set-associative caches are common in caching systems.

[0007] Speculative execution is a computational technique in which a processor executes one or more instructions based on speculation that they need to be executed under certain conditions, before a definitive result is available regarding whether such instructions should be executed.

[0008] Memory addresses in a computing system identify memory locations within the system. A memory address is a fixed-length sequence of numbers that are typically displayed and manipulated as unsigned integers. The length of the sequence of numbers or bits can be considered the width of the memory address. Memory addresses are used in certain structures of the Central Processing Unit (CPU), such as the instruction pointer (or program counter) and memory address registers. The size or width of this CPU structure typically determines the length of the memory addresses used within that CPU. Attached Figure Description

[0009] The embodiments are illustrated by way of example rather than limitation in the accompanying drawings, in which similar reference numerals indicate similar elements.

[0010] Figures 1A to 1E Various ways of segmenting a memory address into multiple parts that can be used with an execution type to control the operation of a cache, according to some embodiments of the present disclosure, are shown.

[0011] Figure 2 , 3A Examples of computing devices according to some embodiments of the present disclosure are shown in 3B, each computing device including a cache system having interchangeable caches for first type and second type of execution.

[0012] Figure 4 , 5A5B illustrates an example aspect of an example computing device according to some embodiments of the present disclosure, each computing device specifically including a cache system having interchangeable caches for main-type and speculative-type execution.

[0013] Figure 6 , 7A 7B, 8A, 8B, 9A and 9B illustrate example aspects of example computing devices according to some embodiments of the present disclosure, each computing device including a cache system having interchangeable cache sets for first type and second type execution (e.g., primary type and speculative type execution).

[0014] Figure 10 This section illustrates instance aspects of an instance computing apparatus that specifically includes a cache system having an interchangeable cache set for main-type and speculative-type execution, according to some embodiments of the present disclosure.

[0015] Figure 11A and 11B This description describes a background synchronization circuitry system according to some embodiments of the present disclosure for synchronizing content between a main cache and a shadow cache to store content cached in the main cache for receiving content in the shadow cache.

[0016] Figure 12 Demonstrating some embodiments according to this disclosure Figure 11A and 11B Example operation of synchronous circuit system.

[0017] Figure 13 , 14A 14B, 14C, 15A, 15B, 15C and 15D illustrate example aspects of an instance computing device having an interchangeable cache system with an alternate cache set including a set of spare caches for accelerating speculative execution, according to some embodiments of the present disclosure.

[0018] Figure 16 and 17 Example aspects of an instance computing device are shown, according to some embodiments of the present disclosure, having an interchangeable cache system with extended tags for different types of execution (e.g., speculative and non-speculative execution) performed by the processor.

[0019] Figure 18 Examples of computing devices are shown, according to some embodiments of the present disclosure, having an interchangeable cache set with circuitry that maps physical cache set outputs to logical cache set outputs.

[0020] Figure 19 , 20And 21 show some embodiments of the present disclosure having the advantages shown in Figure 18 The circuitry in the example represents an instance of a cache system that maps the outputs of a physical cache set to the outputs of a logical cache set, representing an instance aspect of a computing device.

[0021] Figure 22 and 23 This invention illustrates a method for using interchangeable cache sets for speculative and non-speculative execution performed by a processor, according to some embodiments of the present disclosure. Detailed Implementation

[0022] This disclosure includes techniques for interchangeably using multiple caches or cache sets of caches with different types of execution performed by a connected processor. The types of execution can include speculative and non-speculative execution threads. Non-speculative execution can be referred to as main execution or normal execution.

[0023] For enhanced security, when the processor performs conditional speculative execution of an instruction, the processor may be configured to use a shadow cache during the speculative execution of the instruction, wherein the shadow cache is separate from the main cache used during the main or normal execution of the instruction. Some techniques for using shadow caches to improve security can be found in U.S. Patent Application No. 16 / 028,930, filed July 6, 2018, entitled “Shadow Cache for Securing Conditional Speculative Instruction Execution,” the entire disclosure of which is hereby incorporated by reference. This disclosure includes techniques that allow: a cache to be dynamically configured as a shadow cache or a main cache; a unified set of cache resources to be dynamically allocated to the shadow cache or the main cache; and the allocation to be changed during instruction execution.

[0024] In some embodiments, the system may include a memory system (e.g., including main memory), a processor, and a cache system coupled between the processor and the memory system. The cache system may have a cache set. Furthermore, the caches in the cache set can be designed in various ways. For example, the caches in the cache set may include a cache set associated with a cache set (which may include physical or logical cache set associations).

[0025] In some embodiments, the system cache may be variable between being configured for a first type of processor-to-instruction execution and being configured for a second type of processor-to-instruction execution. The first type may be non-speculative execution of processor-to-instructions. The second type may be speculative execution of processor-to-instructions.

[0026] In some embodiments, the cache set of the cache can be variable between being configured for a first type of processor-to-instruction execution and being configured for a second type of processor-to-instruction execution. The first type can be non-speculative execution of processor-to-instructions. And the second type can be speculative execution of processor-to-instructions.

[0027] In some embodiments, speculative execution is where the processor executes one or more instructions based on speculation that they need to be executed under certain conditions, before a determination of whether such instructions should be executed is available. Non-speculative execution (or primary execution, or normal execution) is the case where instructions are executed sequentially according to a program sequence of instructions.

[0028] In some embodiments, the system's cache set may include at least a first cache and a second cache. In such instances, the system may include a command bus configured to receive read or write commands from the processor. The system may also include an address bus configured to receive memory addresses from the processor for accessing memory in response to read or write commands. Furthermore, a data bus may be included configured to: transmit data to the processor for reading; and receive data from the processor for writing into memory. Memory access requests from the processor may be defined by the command bus, address bus, and data bus.

[0029] In some embodiments, a common command and address bus may replace the command and address bus described herein. Furthermore, in such embodiments, a common connection to the common command and address bus may replace the corresponding connection to the command and address bus described herein.

[0030] The system may also include an execution type signal line configured to receive the execution type from the processor. The execution type may be an indication of normal or non-speculated execution, or an indication of speculative execution.

[0031] The system may also include configurable data bits that are configured to be set to a first state (e.g., "0") or a second state (e.g., "1") to change the use of the first and second caches relative to non-speculated execution and speculative execution.

[0032] The system may further include logic circuitry configured to select a first cache for a memory access request from the processor when the configurable data bit is set to a first state and the execution type signal line receives an indication of non-speculated execution. The logic circuitry may also be configured to select a second cache for a memory access request from the processor when the configurable data bit is set to the first state and the execution type signal line receives an indication of speculative execution. The logic circuitry may also be configured to select a second cache for a memory access request from the processor when the configurable data bit is set to a second state and the execution type signal line receives an indication of non-speculated execution. The logic circuitry may also be configured to select a first cache for a memory access request from the processor when the configurable data bit is set to the second state and the execution type signal line receives an indication of speculative execution.

[0033] The system may also include a speculative state signal line configured to receive speculative states from the processor. The speculative state may be an acknowledgment or rejection of a condition with nested instructions, which are initially executed speculatively and subsequently by non-speculative execution when the speculative state is an acknowledgment of the condition.

[0034] The logic circuit can also be configured to select a second cache as identified by a first state of the configurable data bits and restrict or change the use of the first cache as identified by a first state of the configurable data bits when the signal received by the execution type signal line changes from an indication of non-speculated execution to an indication of speculative execution.

[0035] Furthermore, the logic circuitry can be configured to change the configurable data bits from a first state to a second state, and select a second cache for a memory access request when the execution type signal line receives an indication of non-speculated execution. This can occur when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of non-speculated execution, and upon confirmation that the speculative state is a condition received by the speculative state signal line.

[0036] The logic circuitry can also be configured to maintain a first state of the configurable data bits and select a first cache for a memory access request when the execution type signal line receives an indication of non-speculated execution. This can occur when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of non-speculated execution and when a conditional rejection is received from the speculative state signal line. Furthermore, the logic circuitry can be configured to invalidate and discard the contents of a second cache when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of non-speculated execution and when a conditional rejection is received from the speculative state signal line.

[0037] The system may also include a second command bus configured to transmit read or write commands to main memory connected to the cache system. The cache system may receive read or write commands from the processor. The system may also include a second address bus configured to transmit memory addresses to main memory. The cache system may receive memory addresses from the processor. The system may also include a second data bus configured to transmit data to main memory for writing into memory and to receive data from main memory for transmission to the processor for reading. Memory access requests to main memory from the cache system may be defined by the second command bus, the second address bus, and the second data bus.

[0038] As mentioned, caches within a cache set can be designed in several ways, and one of those ways involves partitioning the cache set into cache sets through cache set associativity (which can include physical or logical cache set associativity). The benefit of cache design using set associativity is that a single cache with set associativity can have multiple cache sets within a single cache, and therefore, different portions of a single cache can be allocated for processor use instead of allocating the entire cache. This allows for more efficient use of a single cache. This is especially true when the processor executes multiple types of threads or has multiple execution types. For example, cache sets within a single cache can be interchanged with different execution types, rather than using interchangeable caches. Common instances of cache partitioning include having two, four, or eight cache sets within a single cache.

[0039] Furthermore, set-associative cache designs outperform other common cache designs when the processor executes both the main thread and speculative threads. Because speculative execution uses less additional cache capacity than normal or non-speculative execution, the selection mechanism can be implemented at the cache set level, thus reserving less space than the entire cache used for speculative execution (i.e., a portion of the cache). Set-associative caches can have multiple cache sets within a set (e.g., partitions of two, four, or eight cache sets within a cache). For example, such as... Figure 7A As shown, the cache system contains at least four cache sets (see, for example, cache sets 702, 704, and 706). Normal or non-speculated execution, which typically requires most of the cache capacity, can have a larger number of cache sets delegated to it. Furthermore, speculative execution, which modifies non-speculated execution, can use one cache set or a smaller number of cache sets, because speculative execution generally involves fewer instructions than non-speculated execution.

[0040] like Figure 6As shown in Figure 10, the cache system may contain multiple caches for the processor (e.g., ...). Figure 6 The caches described herein (602a, 602b, and 602c) and the cache system's cache may contain a cache set (e.g., Figure 6 The cache sets 610a, 610b, and 610c described in the document are used to further categorize the organization of the cache system. This example contains cache systems with set associations.

[0041] At the cache set hierarchy of caches, the first cache set (for example, see...) Figure 7A , Figure 8A and 9A The cache set 702 described herein can store contents for use with either a first type of execution or a second type of execution performed by the processor. For example, the first cache set can store contents for use with either a non-speculated or speculative type of execution performed by the processor. Furthermore, the second cache set (see, for example, see...) Figure 7A , Figure 8A and 9A The cache set 704 or 706 described herein can hold contents for use with the first type of execution or the second type of execution performed by the processor.

[0042] For example, in a first-time instance, a first cache set is used for normal or non-speculated execution, and a second cache set is used for speculative execution. In a second-time instance, a second cache set is used for normal or non-speculated execution, and a first cache set is used for speculative execution. The manner in which cache sets are delegated / swapped for non-speculated and speculative execution can utilize set associativity via cache set indices within or outside the memory address label, or via cache set indicators within the memory address label that differ from cache set indices (e.g., see [link to relevant documentation]). Figure 7A , 7B (8A, 8B, 9A and 9B).

[0043] Such as at least Figure 1B , 1C As shown in 1D, 1E, 7A, 7B, 8A, 8B, 9A, and 9B, cache set indexes or cache set indicators can be included in cache block addressing to implement cache set addressing and associativity. Cache block addressing can be stored in memory (e.g., SRAM, DRAM, etc., depending on the design of the computing device, i.e., the design of processor registers, cache system, another intermediate memory, main memory, etc.).

[0044] like Figure 6 , 7AAs shown in 7B, 8A, 8B, 9A, 9B, and 10, each cache set (e.g., L1, L2, or L3 cache) has a corresponding register (e.g., shown in...). Figure 6 and 10 Registers 612a, 612b, or 612c in the diagram, or shown in... Figure 7A , 7B Registers 712, 714, or 716 in 8A, 8B, 9A, and 9B) and set indices (for example, see the diagram shown in...) Figure 7A , 7B One of the set indices 722, 724, 726, and 728 in 8A, 8B, 9A, and 9B, which can be swapped between corresponding registers to implement a swapping of cache sets for non-speculating and speculative execution of the processor (or, generally, for the first and second types of execution of the processor). For example, relative to Figure 7A and 7B During the first time period, execution of the first type can use cache sets 702 and 704, and execution of the second type can use cache set 706. Then, during the second time period, execution of the first type can use cache sets 704 and 706, and execution of the second type can use cache set 702. It should be noted that this is only one instance of cache set usage, and it should be understood that, depending on the time period or the set index or indicator stored in the register, any cache set without predetermined restrictions can be used by either the first or second type of execution.

[0045] In some embodiments, several cache sets may be initially allocated for a first type of execution (e.g., non-speculated execution). During a second type of execution (e.g., speculative execution), one of the cache sets initially allocated to the first type of execution or not (e.g., a reserved cache set) may be available for the second type of execution. Essentially, the cache set allocated to the second type of execution may initially be an idle cache set awaiting use, or selected from several cache sets used for the first type of execution (e.g., cache sets less likely to be further used for another first type of execution).

[0046] Generally, in some embodiments, a cache system includes multiple cache sets. The multiple cache sets may include a first cache set, a second cache set, and multiple registers associated with each of the multiple cache sets. The multiple registers may include a first register associated with the first cache set and a second register associated with the second cache set. The cache system may also include connections to a command bus coupled between the cache system and the processor, connections to an address bus coupled between the cache system and the processor, and connections to a data bus coupled between the cache system and the processor. The cache system may also include logic coupled to the processor to control the multiple cache sets according to the multiple registers.

[0047] In such embodiments, the cache system can be configured to be coupled between the processor and the memory system. Furthermore, when the connection to the address bus receives a memory address from the processor, the logic circuitry can be configured to generate a set index from at least the memory address (e.g., see illustrations shown in [references to be inserted here]). Figure 7A , 7B The set indices in 8A, 8B, 9A, and 9B generate 730, 732, 830, 832, 930, and 932, respectively. Furthermore, when a memory address is received from the processor via the connection to the address bus, the logic circuitry can be configured to determine whether the generated set index matches the content stored in a first register or the content stored in a second register. Furthermore, the logic circuitry can be configured to execute a command received in the connection to the command bus via a first cache set in response to the generated set index matching the content stored in the first register, and to execute the command via a second cache set in response to the generated set index matching the content stored in the second register. Furthermore, in response to determining that the dataset of the memory system associated with the memory address is not currently cached in the cache system, the logic circuitry can be configured to allocate the first cache set for caching the dataset and store the generated set index in the first register. The generated set index may contain a pre-defined segment of the memory address.

[0048] The cache system may also include a connection to an execution type signal line from the processor that identifies the execution type (see, for example, see...). Figure 6 and 10 (as depicted in connection 604d). In such embodiments, a generated set index may be further generated based on the type identified by the execution type signal line. Furthermore, the generated set index may include a pre-defined bit segment in the memory address and bits representing the type identified by the execution type signal line (e.g., the generated set index may include or originate from a pre-defined bit segment in memory address 102e and bits representing the type shown in...). Figure 1E(One or more bits of the type identified by the execution type signal line in execution type 110e).

[0049] Furthermore, when the first and second registers are in a first state, the logic circuitry can be configured to: when the execution type is a first type, implement commands received from the command bus for accessing the memory system via a first cache set; and when the execution type is a second type, implement commands received from the command bus for accessing the memory system via a second cache set. Furthermore, when the first and second registers are in a second state, the logic circuitry can be configured to: when the execution type is a first type, implement commands received from the command bus for accessing the memory system via another cache set among the multiple cache sets besides the first cache set; and when the execution type is a second type, implement commands received from the command bus for accessing the memory system via yet another cache set among the multiple cache sets besides the second cache set. In this example, each of the multiple registers can be configured to store a set index, and when the execution type changes from the second type to the first type, the logic circuitry can be configured to change the contents stored in the first register and the contents stored in the second register.

[0050] In some embodiments, the first type is configured to instruct the processor to perform non-speculatory execution of instructions; and the second type is configured to instruct the processor to perform speculative execution of instructions. In such embodiments, the cache system may further include a connection to a speculative state signal line from the processor, the speculative state signal line identifying the state of speculative execution of instructions by the processor (e.g., see illustration). Figure 10 (See connection 1002 in the diagram). The connection to the speculative state signal line can be configured to receive the state of speculative execution, and the state of speculative execution can indicate whether the result of speculative execution will be accepted or rejected. Each of the plurality of registers can be configured to store a set index, and when the execution type changes from the second type to the first type, the logic circuit can be configured to change the contents stored in the first register and the contents stored in the second register if the state of speculative execution indicates that the result of speculative execution will be accepted (e.g., see the diagram shown in the diagram). Figure 7A and Figure 7B Between, displayed Figure 8A and Figure 8B Between and displayed in Figure 9A and Figure 9B (Changes to the contents stored in the registers between the two types). Furthermore, when the execution type changes from the second type to the first type, the logic circuit can be configured to maintain the contents stored in the first register and the contents stored in the second register without changing them, even if the state indication of the speculative execution will reject the result of the speculative execution.

[0051] Additionally, the cache systems described herein (e.g., cache systems 200, 400, 600, and 1000) may each include or be connected to a background synchronization circuit system (e.g., see the diagram shown). Figure 11A and 11B (The background synchronization circuitry system 1102 in the system). The background synchronization circuitry system can be configured to synchronize the cache or cache set before reconfiguring the shadow cache as the primary cache and / or reconfiguring the primary cache as the shadow cache.

[0052] For example, the contents of a cache or cache set initially delegated for speculative execution (e.g., additional caches or spare cache sets delegated for speculative execution) can be synchronized with the corresponding cache or cache set used by normal or non-speculative execution (to have the cache contents of normal execution) such that, if the speculation is confirmed, the cache or cache set initially delegated for speculative execution can be immediately added to the cache set of the main execution or non-speculative execution. Furthermore, the initial cache set corresponding to the cache or cache set initially delegated for speculative execution can be removed from the cache set set used for the main execution or non-speculative execution. In such embodiments, circuitry (e.g., circuitry including a background synchronization circuitry system) can be configured to synchronize caches or cache sets in the background to reduce the impact of cache set synchronization on the processor's cache usage. Furthermore, synchronization of the cache or cache set can continue until speculation is abandoned, or until speculation is confirmed and synchronization is complete. Synchronization may optionally include synchronization with memory (e.g., write-back).

[0053] In some embodiments, the cache system may include a first cache and a second cache, and connections to a command bus coupled between the cache system and the processor, a connection to an address bus coupled between the cache system and the processor, a connection to a data bus coupled between the cache system and the processor, and a connection to an execution type signal line from the processor that identifies the execution type (e.g., see cache systems 200 and 400). Such a cache system may also include logic circuitry coupled to control the first and second caches according to the execution type, and the cache system may be configured to be coupled between the processor and the memory system. Furthermore, when the execution type is a first type instructing the processor to perform non-speculated execution of instructions and the first cache is configured to serve commands from the command bus for accessing the memory system, the logic circuitry may be configured to copy a portion of the contents cached in the first cache to the second cache (e.g., see operation 1202). Additionally, the logic circuitry may be configured to copy a portion of the contents cached in the first cache to the second cache independently of the current command received in the command bus.

[0054] Additionally, when the execution type is a first type instructing the processor to perform non-speculative execution of instructions and the first cache is configured to serve commands from the command bus for accessing the memory system, the logic circuitry can be configured to use a second cache to serve subsequent commands from the command bus in response to a change in the execution type from the first type to a second type instructing the processor to perform speculative execution of instructions (e.g., see operation 1208). In this example, the logic circuitry can be configured to complete partial synchronization of content from the first cache to the second cache after the execution type changes from the first type to the second type but before serving subsequent commands (e.g., see...). Figure 12 The logic circuit can also be configured to continue the synchronization of parts of the content from the first cache to the second cache while serving subsequent commands (e.g., see operation 1210).

[0055] In such embodiments, the cache system may further include configurable data bits, wherein logic circuitry is further coupled to control a first cache and a second cache based on the configurable data bits. Furthermore, in such embodiments, the cache system may further include multiple cache sets. For example, the first cache and the second cache may collectively include multiple cache sets, and the multiple cache sets may include both the first cache set and the second cache set. The cache system may also include multiple registers, each associated with one of the multiple cache sets. The multiple registers may include a first register associated with the first cache set and a second register associated with the second cache set. And, in such embodiments, logic circuitry may be further coupled to control the multiple cache sets based on the multiple registers.

[0056] In some embodiments, the cache system may include multiple cache sets, the multiple cache sets including a first cache set and a second cache set. The cache system may also include multiple registers associated with the multiple cache sets, the multiple registers including a first register associated with the first cache set and a second register associated with the second cache set. In such embodiments, the cache system may include multiple caches, the multiple caches including a first cache and a second cache, and the first cache and the second cache may collectively include at least a portion of the multiple cache sets. Such a cache system may also include connections to a command bus coupled between the cache system and the processor, connections to an address bus coupled between the cache system and the processor, connections to a data bus coupled between the cache system and the processor, and connections to an execution type signal line from the processor identifying the execution type, as well as logic circuitry coupled to control the multiple cache sets according to the execution type.

[0057] In such embodiments, the cache system may be configured to be coupled between the processor and the memory system. Furthermore, when the execution type is a first type instructing the processor to perform non-speculated execution of instructions and the first cache set is configured to serve commands from the command bus for accessing the memory system, the logic circuitry is configured to copy a portion of the contents cached in the first cache set to a second cache set. The logic circuitry may also be configured to copy a portion of the contents cached in the first cache set to the second cache set independently of the current command received on the command bus.

[0058] Furthermore, when the execution type is a first type instructing the processor to perform non-speculous execution of instructions and the first cache set is configured to serve commands from the command bus for accessing the memory system, the logic circuitry can be configured to use a second cache set to serve subsequent commands from the command bus in response to a change in the execution type from the first type to a second type instructing the processor to perform speculative execution of instructions. The logic circuitry can also be configured to complete the synchronization of the portion of content from the first cache set to the second cache set after the execution type changes from the first type to the second type but before serving subsequent commands. The logic circuitry can also be configured to continue the synchronization of the portion of content from the first cache set to the second cache set while serving subsequent commands. Furthermore, the logic circuitry can be further coupled to control multiple cache sets according to multiple registers.

[0059] In addition to using a shadow cache to ensure speculative execution and synchronizing the contents between the main cache and the shadow cache to preserve the contents cached in the main cache for acceptance in the shadow cache, a spare cache set can be used to accelerate speculative execution. Furthermore, a spare cache set can be used to accelerate speculative execution without using a shadow cache. The use of a spare cache set is suitable for shadow cache implementations because it is possible to verify that the data stored in the cache set used as the shadow cache is valid and therefore used for normal execution, and some cache sets used as the main cache may not be ready to be used as shadow caches. Therefore, one or more cache sets can be used as spare cache sets to avoid delays while waiting for cache set availability. In other words, once speculation is confirmed, the contents of the cache set used as the shadow cache are confirmed to be valid and up-to-date; and therefore, the previous cache set used as the shadow cache for speculative execution is used for normal execution. However, some of the cache sets initially used as normal caches may not be ready for subsequent speculative execution. Therefore, one or more cache sets can be used as spares to avoid delays while waiting for cache set availability and to accelerate speculative execution.

[0060] In some embodiments, if synchronization from the cache set in the normal cache to the corresponding cache set in the shadow cache has not yet been completed, the cache set in the normal cache cannot be immediately released for use by the next speculative execution. In this case, if no spare cache set exists, the next speculative execution must wait until synchronization is complete so that the corresponding cache set in the normal cache can be released. This is just one example when a spare cache set is beneficial and can be added to the embodiments. Furthermore, there are many other situations where the cache set in the normal cache cannot be immediately released, so a spare cache set can be useful.

[0061] Furthermore, in some embodiments, speculative execution may reference memory regions that do not overlap with memory regions cached in the cache set used in the normal cache. Because the result of speculative execution is accepted, the cache sets in both the shadow cache and the normal cache may all reside in the normal cache. This can also cause latency, as the cache system spends time freeing up cache sets to support the next speculative execution. To free up a cache set, the cache system may identify the cache set, such as the least used cache set, and synchronize the cache set with the memory system. If the cache has data newer than the memory system, then the data can be written to the memory system.

[0062] Additionally, systems using spare cache sets can also utilize background synchronization circuit systems, such as... Figure 11A and 11B The background synchronization circuitry system 1102 is depicted in the diagram. In some embodiments, the background synchronization circuitry system 1102 may be part of logic circuitry 606 or 1006. When the initial speculation is confirmed, the cache set used in the initial speculation can be switched to join the set of cache sets used for main execution. Instead of using the cache set from the previous main execution that was being used in the case of speculation failure, the standby cache set can be made available immediately for the next speculative execution. Furthermore, the standby cache set can be updated via the background synchronization circuitry system for the next speculative execution. And, due to background synchronization, the standby cache set is ready for use when the cache set currently used for speculative execution is ready to be accepted for normal execution. In this way, there is no delay while waiting for the next cache set to be used for the next speculative execution. To be ready for the next speculative execution, the standby cache set can be synchronized to the normal cache set that is likely to be used for the next speculative execution or the least used cache set in the system.

[0063] Besides using shadow caches, synchronizing contents between the main cache and shadow caches, and using spare cache sets, extension tags can also be used to improve the use of interchangeable caches and cache sets for different types of execution performed by the processor (e.g., speculative and non-speculative execution). There are many different ways to use extension tags to address cache sets and cache blocks within a cache system. Two example methods are shown in... Figure 16 and 17 middle.

[0064] Generally, cache sets and cache blocks can be selected via memory addresses. In some instances, selection is done via set associativity. Figure 16 and 17 The two instances in the example use set association. Figure 16 In this context, set associativity is implicitly defined (e.g., through algorithms that can be used to determine which tag should be in which cache set for a given execution type). Figure 17 In this context, set association is implemented via bits in the cache set index within the memory address. Furthermore, Figure 16 and 17 The functional parts described herein can be implemented without using set associations (but this is not in...). Figure 16 and 17 (Depicted in Chinese).

[0065] In some embodiments, including those shown in Figure 16 and 17 In the embodiments described, the block index can be used as an address within an individual cache set to identify a specific cache block within the cache set. Furthermore, the extended tag can be used as an address of the cache set. The block index of the memory address can be used for each cache set to obtain the cache block and the tag associated with the cache block. Additionally, as... Figure 16 and 17 As shown, the tag comparison circuit compares an extended tag generated by a cache set with an extended cache tag generated by a memory address and the current execution type. The comparison output can be a cache hit or a cache miss. The construction of the extended tag ensures that at most one hit exists in the cache set. If a hit exists, a cache block from the selected cache set provides the output. Otherwise, the data associated with the memory address is either cached in any cache set or output from any cache set. In short, Figure 16 and 17 The extended labels described are used to select a cache set, and the block index is used to select a cache block and its label within the cache set.

[0066] In addition, such as Figure 17As shown, the combination of tags and cache set indexes in the system can provide functionality comparable to using only tags (such as...). Figure 16 Slightly similar functionality (as shown in the example). However, in Figure 17 In this approach, by separating the tag and the cache set index, the cache set does not need to store a redundant copy of the cache set index, because the cache set can be associated with a cache set register to store the cache set index. However, in Figure 16 In this context, the cache set does indeed need to store redundant copies of the cache set indicator in each block of the cache set. However, due to... Figure 16 In the embodiments depicted, the tags have the same cache set indicator, so the indicator can be stored in a register for the cache set (e.g., see the illustration). Figure 17 The tag is stored in the cache set register (in the cache set register). The advantage of using the cache set register is that the tag length can be shorter compared to implementations that do not have a cache set register.

[0067] Shown Figure 16 and 17 Two embodiments in the example have a cache set register configured to store execution types, such that a corresponding cache set can be used to implement different execution types (e.g., speculative and non-speculative execution types). However, the example shown... Figure 17 The embodiments described herein have registers further configured to store the execution type and cache set index. When the execution type is combined with the cache set index to form an extended cache set index, the extended cache set index can be used to select one of the cache sets without depending on the addressing via the tag of the cache block. Furthermore, when a tag from the selected cache set is compared with a tag in the address to determine a hit or miss, the two-step selection can be similar to or used in combination with extended tags to support interchangeability of cache sets for different execution types.

[0068] In addition to using extended tags and other techniques disclosed herein to improve the use of interchangeable caches and cache sets for different types of execution performed by the processor, circuitry included in or connected to the cache system can be used to map the physical outputs of cache sets from the cache hardware system to logical main caches and logical shadow caches, respectively, for normal and speculative execution performed by the processor. The mapping may be based on at least one control register (e.g., a Physical-to-Logical Set Mapping (PLSM) register).

[0069] Furthermore, this document discloses circuits that utilize mapping circuits (e.g., shown in...). Figure 18 The mapping circuit (1830) in the cache system is a computing device that maps the outputs of the physical cache set to the outputs of the logical cache set in an interchangeable cache system. A processor coupled to the cache system can execute two types of threads, such as speculative and non-speculative execution threads. Speculative threads execute speculatively with conditions that have not yet been evaluated. The data for speculative threads can reside in the logical shadow cache. The data for non-speculative threads can reside in the logical main cache or the normal cache. Subsequently, when the result of the evaluated condition becomes available, the system can either retain the result of the speculative thread execution while the condition requires the thread's execution, or remove the result. Using the mapping circuit, hardware circuitry used for the shadow cache can be repurposed for the main cache by changing the contents of the control register. Therefore, for example, if speculative threads need to be executed, it is not necessary to synchronize the main cache with the shadow cache.

[0070] In a conventional cache, each cache set is statically associated with a specific value of “index S” / “block index L”. In the cache system disclosed herein, any cache set can be used for any index value S / L and for any purpose in the main cache or shadow cache. The cache set can be used in a cache set register associated with the cache set and can be defined by the data in said cache set register. Selection logic can then be used to select the appropriate result based on the index value of S / L and the manner in which the cache set is used.

[0071] For example, four cache sets (cache sets 0 through 3) can initially be used as the main cache for S / L = 00, 01, 10, and 11, respectively. Assuming speculative executions do not change the cache sets defined by 01, 10, and 11, then the fourth cache set can be used as the speculative cache for S / L = 00. If the result of a speculative execution is needed, the mapping data can be changed to indicate that the main caches for S / L = 00, 01, 10, and 11 are used for the fourth cache set, cache set 1, cache set 2, and cache set 3, respectively. Cache set 0 can then be freed or invalidated for subsequent use in speculative executions. If the next speculative execution requires changing cache set S / L to 01, then cache set 0 can be used as a shadow cache (e.g., copied from cache set 1 and used to look up the content at the address with an S / L equal to '01').

[0072] Furthermore, the cache system and processor not only switch back and forth between the pre-determined main thread and the pre-determined speculative thread. Consider the speculative execution of the following pseudoprogram.

[0073] Instruction A;

[0074] If the condition is true,

[0075] Then instruction B;

[0076] End the conditional loop;

[0077] Instruction C; and

[0078] Instruction D.

[0079] For pseudo-programs, the processor can run two threads.

[0080] Thread A:

[0081] Instruction A;

[0082] Instruction C; and

[0083] Instruction D.

[0084] Thread B:

[0085] Instruction A;

[0086] Instruction B;

[0087] Instruction C; and

[0088] Instruction D.

[0089] The execution of instruction B is speculative because it depends on the test result of "condition = true" rather than "condition = false". Instruction B is only required if the condition is true. When the result of the test "condition = true" becomes available, the execution of thread A reaches instruction D, and the execution of thread A can reach instruction C. If the test result requires the execution of instruction B, then the cache contents of thread B are correct, and the cache contents of thread A are incorrect. Then, all changes made according to the cache of thread B should be preserved, and the processor can continue the execution of instruction C using the cache with the result of executing instruction B; and thread A is terminated. Since the changes made according to thread B are in the shadow cache, the contents of the shadow cache should be accepted as the main cache. If the test result does not require the execution of instruction B, then the result of thread B is discarded (e.g., the contents of the shadow cache are discarded or invalidated).

[0090] The cache sets used for shadow and normal caches can be swapped or changed based on mapping circuitry and control registers (e.g., Physical-to-Logical Set Mapping (PLSM) registers). In some embodiments, the cache system may include multiple cache sets, the multiple cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system may also include a connection to a command bus coupled between the cache system and the processor, and a connection to an address bus coupled between the cache system and the processor. The cache system may also include a control register, and mapping circuitry coupled to the control register to map corresponding physical outputs of the multiple cache sets to a first logical cache and a second logical cache based on the state of the control register. The cache system may be configured to be coupled between the processor and the memory system.

[0091] When the connection to the address bus receives a memory address from the processor and the control register is in a first state, the mapping circuitry can be configured to: map a first physical output to a first logical cache for a first type of execution performed by the processor to implement commands received from the command bus for accessing the memory system via the first cache set during the first type of execution; and map a second physical output to a second logical cache for a second type of execution performed by the processor to implement commands received from the command bus for accessing the memory system via the second cache set during the second type of execution. Furthermore, when the connection to the address bus receives a memory address from the processor and the control register is in a second state, the mapping circuitry is configured to: map a first physical output to a second logical cache to implement commands received from the command bus for accessing the memory system via the first cache set during the second type of execution; and map a second physical output to a first logical cache to implement commands received from the command bus for accessing the memory system via the second cache set for the first type of execution.

[0092] In some embodiments, the first logical cache is a normal cache for non-speculative execution performed by the processor, and the second logical cache is a shadow cache for speculative execution performed by the processor.

[0093] Furthermore, in some embodiments, the cache system may further include multiple registers associated with multiple cache sets, including a first register associated with a first cache set and a second register associated with a second cache set. The cache system may also include logic coupled to the processor to control the multiple cache sets according to the multiple registers. When a memory address is received from the processor via a connection to the address bus, the logic may be configured to generate a set index from at least the memory address and determine whether the generated set index matches a content stored in a first register or a content stored in a second register. Furthermore, the logic may be configured to execute a command received in a connection to the command bus via the first cache set in response to a match between the generated set index and a content stored in the first register, and to execute the command via the second cache set in response to a match between the generated set index and a content stored in the second register.

[0094] In some embodiments, the mapping circuit may be part of or connected to the logic circuit, and the state of the control register may control the state of the cache sets in a plurality of cache sets. In some embodiments, the state of the control register may control the state of the cache sets in a plurality of cache sets by changing the valid bit of each block of the cache set.

[0095] Furthermore, in some instances, the cache system may further include a connection to a speculative status signal line from the processor that identifies the state of speculative execution of instructions. The connection to the speculative status signal line can be configured to receive the state of speculative execution, and the state of speculative execution can indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuitry can be configured to change the state of the first and second cache sets via a control register if the state of speculative execution indicates that the result of speculative execution will be accepted (e.g., when speculative execution becomes the main execution thread). And, when the execution type changes from speculative execution to non-speculative execution, the logic circuitry can be configured to maintain the state of the first and second cache sets without change via a control register if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0096] In some embodiments, the mapping circuitry is part of or connected to the logic circuitry, and the state of the control register can control the state of cache registers among a plurality of cache registers via the mapping circuitry. In such instances, the cache system may further include a connection to a speculative status signal line from the processor that identifies the state of speculative execution of instructions by the processor. The connection to the speculative status signal line can be configured to receive the state of speculative execution, and the state of speculative execution indicates whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuitry can be configured to change the state of the first and second registers via the control register if the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, when the execution type changes from speculative execution to non-speculative execution, the logic circuitry can be configured to maintain the state of the first and second registers without change via the control register if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0097] Furthermore, this disclosure includes techniques for ensuring speculative instruction execution by using multiple interchangeable caches, each interchangeable as a shadow cache or a main cache. Speculative instruction execution can occur within the processor of a computing device. The processor can execute instructions in two different types of threads. One thread can be speculatively executed (e.g., using a condition that has not yet been evaluated). The speculative thread's data can reside in a logical cache acting as a shadow cache. The main thread's data can reside in a logical cache acting as a main cache. Subsequently, when the result of evaluating the condition becomes available, the processor can either retain the result of executing the speculative thread if the condition requires the thread's execution, or remove the result. The hardware circuitry used for the shadow cache can be modified to function as the main cache by changing the contents of registers. Therefore, if speculative thread execution is required, synchronization between the main cache and the shadow cache is not necessary.

[0098] The techniques disclosed herein also relate to the use of a unified cache architecture for implementing main and shadow caches with improved performance. In a unified cache architecture, the results of cache sets can be dynamically remapped using register sets for exchange between the main cache and the shadow cache. When speculation succeeds, the cache set used with the shadow cache has the correct data and can be remapped to the corresponding cache set for the main cache. This eliminates the need to copy data from the shadow cache to the main cache, as is done by other techniques using shadow and main caches.

[0099] Generally, a cache can be configured as multiple block sets. Each block set can have multiple blocks, and each block can hold a number of bytes. Memory addresses can be divided into three segments for accessing the cache: a tag, a block index (which can be used to address sets within multiple sets), and a cache block (which can be used to address bytes within a byte block). For each block in a set, the cache not only stores data from memory but also a tag indicating the address from which the data was loaded, as well as a field indicating whether the contents of the block are valid. Data can be retrieved from the cache using the block index (e.g., set ID) and the cache block (e.g., byte ID). The tag in the retrieved data is compared to the tag portion of the address. A matching tag means that data is cached for that address. Otherwise, it means that data can be cached for another address mapped to the same location in the cache.

[0100] By employing a technique using multiple interchangeable caches, the physical cache set of interchangeable caches is not hardwired as either a primary cache or a shadow cache. The physical cache set can be used as either a primary cache set or a shadow cache set. Furthermore, a register set can be used to specify whether the physical cache set is currently being used as a primary cache set or a shadow cache set. Generally, mapping can be constructed to transform the output of a physical cache set into the logical output of the corresponding cache set, represented by a block index (e.g., set ID) and a primary or shadow state. Remapping allows any available physical cache to be used as a shadow cache.

[0101] In some embodiments, a unified cache architecture may remap shadow caches (e.g., speculative caches) to the main cache, and may remap the main cache to speculative caches. It should be understood that the design may include any number of caches or cache sets that are interchangeable between the main cache or cache set or speculative cache or cache set.

[0102] It should be understood that there is no physical difference in the hardwired connections between the main cache or cache set and the speculative cache or cache set. Furthermore, in some embodiments, there is no physical difference in the hardwired connections between the logical units described herein. It should be understood that interchangeable caches or cache sets do not have different cache capacities and structures. Otherwise, these caches or cache sets would not be interchangeable. Moreover, the physical cache set can be dynamically configured as main or speculative, for example, without prior determination.

[0103] Furthermore, it should be understood that interchangeability occurs at the cache level, not the cache block level. Interchangeability at the cache block level allows the main cache and shadow cache to have different capacities; and therefore, they are not interchangeable.

[0104] Furthermore, in some embodiments, when a processor-made guess succeeds and a cache is being used as the main cache while another cache is being used as a guess or shadow cache, all valid bits associated with the cache index block of the main cache are set to indicate invalid (e.g., by indicating invalidity via a "0" bit value). In such embodiments, the initial state of all valid bits in the guess cache indicates invalidity, but then changes to indicate validity due to a successful guess. In other words, the previous state of the main cache is invalidated, and the previous state of the guess cache is set from invalid to valid and accessible by the main thread.

[0105] In some embodiments, the PLSM register used for the main cache can be changed from indicating the main cache to indicating the speculative cache. Changing the indication from the main cache to the speculative cache by the PLSM register can be done by a PLSM register that receives a valid bit indicating an invalid main cache after a successful speculative attempt. For example, after a successful speculative attempt, and if the first cache is initially the main cache and the second cache is initially a speculative cache, an invalid indication of bit "0" can replace the least significant bit in the 3-bit PLSM register used for the first cache, which can change "011" to "010" (or change "3" to "2"). And, for the 3-bit PLSM register used for the second cache, a valid indication of bit "1" can replace the least significant bit in the PLSM register, which can change "010" to "011" (or change "2" to "3"). Thus, as the example shows, the PLSM register initially used for the first cache (e.g., the main cache) and initially selected the first cache is changed to select the second cache (e.g., the speculative cache) after a successful speculative attempt. Furthermore, as the example demonstrates, the PLSM register, initially designated as the second cache (e.g., the speculative cache) and initially selected as the second cache, changes to select the first cache (e.g., the main cache) after a successful speculative attempt. With this design, the processor's main thread can first access the cache initially designated as the main cache, and then access the cache initially designated as the speculative cache after a successful speculative attempt by the processor. Similarly, the processor's speculative thread can first access the cache initially designated as the speculative cache, and then access the cache initially designated as the main cache after a successful speculative attempt by the processor.

[0106] Figure 1AA memory address 102a is shown, divided into a tag portion 104a, a block index portion 106a, and a block offset portion 108a. According to some embodiments of this disclosure, execution type 110a can be combined with portions of the memory address to control cache operations. The total number of bits used for controlling addressing in the cache system according to some embodiments disclosed herein is A bits. Furthermore, the sum of the bits used for portions 104a, 106a, and 108a and execution type 110a is equal to A bits. The tag portion 104a has K bits, the block index portion 106a has L bits, the block offset portion 108a has M bits, and the execution type 110a has one or more T bits.

[0107] For example, for a given execution type, data with all memory addresses having the same block index portion 106a and block offset portion 108a can be stored in the same physical location in the cache. When data at memory address 102a is stored in the cache, a block storage tag portion 104a containing the memory address is also used to identify which of the addresses with the same block index portion 106a and block offset portion 108a is currently cached at that location in the cache.

[0108] Data at memory addresses can be cached in different locations within a unified cache structure for different types of execution. For example, data can be cached in the main cache during non-speculated execution and subsequently in a shadow cache during speculative execution. Execution type 110a can be combined with tag portion 104a to select from a cache that can be dynamically configured for use in both main and speculative execution without restriction. Many different ways can be used to implement the combination of execution type 110a and tag portion 104a for selection. For example, Figure 2 and 4 The logic circuit 206 depicted may use execution type 110a and / or tag section 104a.

[0109] In a relatively simple implementation, execution type 110a can be combined with tag portion 104a to form an extended tag when determining whether a cache location contains data for memory address 102a and data for the current execution type of the instruction. For example, a cache system can use tag portion 104a to select a cache location without distinguishing execution type; and when tag portion 104a is combined with execution type 110a to form an extended tag, the extended tag can be used similarly to select cache locations with different types of execution (e.g., speculative execution and non-speculative execution), enabling the implementation of shadow caching techniques to enhance security. Furthermore, since information about the execution type associated with cached data is shared across many cache locations (e.g., in a cache set, or in a cache with multiple cache sets), it is not necessary to store execution types for individual locations; and selection mechanisms (e.g., switches, filters, or multiplexers, such as data multiplexers) can be used to implement selection based on execution type. Alternatively, physical caches or sets of physical caches for different types of execution can be remapped to logical caches pre-associated with different types of execution. Therefore, the use of logical cache can be selected according to execution type 110a.

[0110] Figure 1B This demonstrates another way to control cache operations by partitioning memory address 102b into portions. Memory address 102b is partitioned into a tag portion 104b, a cache set index portion 112b, a block index portion 106b, and a block offset portion 108b. The total number of bits for memory address 102b is A bits. Furthermore, the sum of the bits used for the four portions equals the A bits of address 102b. The tag portion 104b has K bits, the block index portion 106b has L bits, the block offset portion 108b has M bits, and the cache set index portion 112b has S bits. Therefore, for address 102b, its A bits = K bits + L bits + M bits + S bits. According to... Figure 1B The partitioning of memory address 102b allows for implementations of set associativity when caching data.

[0111] For example, multiple cache sets can be configured in the cache, where each cache set can be addressed using cache set index 112b. Data sets associated with the same cache set index can be cached in the same cache set. The tag portion 104b of a data block cached in the cache set can be stored in the cache in association with the data block. When address 102b is used to retrieve data from the cache set identified using cache set index 112b, the tag portion of the data block stored in the cache set can be retrieved and compared with tag portion 104b to determine whether there is a match between the tag 104b of the access request address 102b and the tag 104b stored in the cache set identified by cache set index 112b and for a cache block identified by block index 106b. If a match exists (e.g., a cache hit), then the cache block stored in the cache set is for memory address 112b; otherwise, the cache block stored in the cache set is for another memory address with the same cache set index 112b and the same block index 106b as memory address 102b, which causes a cache miss. In response to a cache miss, the cache system accesses main memory to retrieve the data block based on address 102b. To implement shadow caching, cache set index 112b can be combined with execution type 110a to form an extended cache set index. Therefore, an extended cache set index that identifies both the cache set index and the execution type can be used to address cache sets for different types of executions with different cache set indices.

[0112] exist Figure 1B In this process, cache set index portion 112b is retrieved from a predetermined portion of address 102b. Data stored at memory addresses with different set indices can be cached in different cache sets to implement set associativity in cached data. The cache set of a cache can be selected using the cache set index (e.g., portion 112b of address 102b). Alternatively, it can be used... Figure 1C The partitioning scheme described herein implements cache set association via tag 104c, which contains a cache set indicator. Optionally, the cache set indicator is calculated from tag 104c and used as a cache set index to address the cache set. Alternatively, set association can be implemented directly via tag 104c, such that for a cache hit, the cache set storing tag 104c is selected; and when no cache set stores tag 104c, a cache miss is determined. Alternatively, address 102d can be as follows: Figure 1DThe method described herein is used for caching operations, wherein the tag portion 104d contains a cache set index 112d, wherein the cache set is not explicitly and separately addressed using a cache set index. For example, to implement shadow caching technology, the combination of execution type 110e and tag 104e with an embedded cache set indicator ( Figure 1E (As depicted in the text) can be used to select a cache set that has the correct execution type and stores the same tag 104e for a cache hit. When no cache set has a matching execution type and stores the same tag 104e, a cache miss is determined.

[0113] In addition, such as Figure 1C As shown in the image, Figure 1C Another method is described for controlling cache operations by dividing memory address 102c into parts. Memory address 102c is divided into a tag portion 104c with a cache set indicator, a block index portion 106c, and a block offset portion 108c. The total number of bits in memory address 102c is A bits. Furthermore, the sum of the bits used for the three portions equals the A bits of address 102c. The tag portion 104c has K bits, the block index portion 106c has L bits, and the block offset portion 108c has M bits. Therefore, for address 102c, its A bits = K bits + L bits + M bits. As mentioned, according to Figure 1C The partitioning of memory address 102c allows for the implementation of set associativity when caching data.

[0114] In addition, such as Figure 1D As shown in the image, Figure 1D Another method is described for dividing a memory address 102d into parts to control cache operations. The memory address 102d is divided into a tag portion 104d with a cache set index 112d, a block index portion 106d, and a block offset portion 108d. The total number of bits for the memory address 102d is A bits. Furthermore, the sum of the bits used for the three portions equals the A bits of address 102d. The tag portion 104d has K bits, the block index portion 106d has L bits, and the block offset portion 108d has M bits. Therefore, for address 102d, its A bits = K bits + L bits + M bits. As mentioned, according to Figure 1D The partitioning of memory address 102d allows for implementations of set associativity when caching data.

[0115] In addition, such as Figure 1E As shown in the image, Figure 1E Describing the segmented memory address 102e as another way to control cache operations. Figure 1EA memory address 102e is shown, divided into a tag portion 104e, a block index portion 106e, and a block offset portion 108e, each with a cache set indicator. According to some embodiments of this disclosure, execution type 110e can be combined with portions of the memory address to control cache operations. The total number of bits used for controlling addressing in the cache system according to some embodiments disclosed herein is A bits. Furthermore, the sum of the bits used for portions 104e, 106e, and 108e and execution type 110e is equal to A bits. The tag portion 104e has K bits, the block index portion 106e has L bits, the block offset portion 108e has M bits, and the execution type 110e has T bits.

[0116] Figure 2 , 3A Examples of computing devices according to some embodiments of the present disclosure are shown in 3B, each computing device including a caching system having a cache that can perform interchangeable operations for a first type and a second type (e.g., for implementing shadow caching techniques for enhanced security).

[0117] Figure 2 Specifically, an aspect of an instance computing device is shown that includes a cache system 200 with multiple caches (e.g., see caches 202a, 202b, and 202c). The instance computing device is also shown as having a processor 201 and a memory system 203. The cache system 200 is configured to be coupled between the processor 201 and the memory system 203.

[0118] The cache system 200 is shown as including a connection 204a to the command bus 205a coupled between the cache system and the processor 201. The cache system 200 is also shown as including a connection 204b to the address bus 205b coupled between the cache system and the processor 201. Figure 1A , 1B Addresses 102a, 102b, 102c, 102d, and 102e, respectively, depicted in 1C, 1D, and 1E, may be communicated via address bus 205b, depending on the implementation of cache system 200. Cache system 200 is also shown to include connection 204c to data bus 205c coupled between cache system and processor 201. Cache system 200 is also shown to include connection 204d to execution type signal line 205d from processor 201 that identifies the execution type.

[0119] Figure 2 Not shown in the diagram, the cache system 200 may include configurable data bits. Configurable data bits may be included in the diagram shown in the diagram. Figure 3A The data 312 in the first state may be the data mentioned above, and may be included in the data displayed. Figure 3BThe data in the second state 314 may be the data mentioned above. Memory access requests from the processor and memory usage performed by the processor can be controlled via the command bus 205a, address bus 205b, and data bus 205c.

[0120] In some embodiments, the cache system 200 may include a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b). In such embodiments, as Figure 2 As shown, cache system 200 may include logic circuitry 206 coupled to processor 201. Furthermore, in such embodiments, logic circuitry 206 may be configured to control a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b) based on configurable data bits.

[0121] When the configurable data bits are in the first state (for example, see...) Figure 3A As depicted in data 312), when the execution type is the first type, logic circuit 206 can be configured to implement commands received from command bus 205a for accessing memory system 203 via first cache. Furthermore, when the configurable data bit is in a first state (e.g., see...), Figure 3A The data 312 depicted in the figure, when the execution type is the second type, the logic circuit 206 can be configured to implement the commands received from the command bus 205a for accessing the memory system 203 via the second cache.

[0122] When the configurable data bits are in the second state (for example, see...) Figure 3B As depicted in data 314), when the execution type is the first type, logic circuit 206 can be configured to implement commands received from command bus 205a for accessing memory system 203 via second cache. Furthermore, when the configurable data bit is in the second state (e.g., see...), Figure 3B The data 314 depicted in the figure, when the execution type is the second type, the logic circuit 206 can be configured to implement the command received from the command bus 205a for accessing the memory system 203 via the first cache.

[0123] In some embodiments, when the execution type changes from the second type to the first type, the logic circuit 206 is configured to switch configurable data bits.

[0124] In addition, such as Figure 2As shown, cache system 200 further includes a connection 208a to a second command bus 209a coupled between cache system and memory system 203. Cache system 200 also includes a connection 208b to a second address bus 209b coupled between cache system and memory system 203. Cache system 200 also includes a connection 208c to a second data bus 209c coupled between cache system and memory system 203. When the configurable data bit is in a first state, and the execution type is a first type (e.g., non-speculated type), logic circuitry 206 is configured to provide commands for accessing memory system 203 via the first cache to the second command bus 209a. When the configurable data bit is in the first state, and the execution type is a second type (e.g., speculative type), logic circuitry 206 is also configured to provide commands for accessing memory system via the second cache to the second command bus 209a.

[0125] When the configurable data bit is in the second state, and the execution type is the first type, logic circuit 206 is configured to provide commands for use via the second cache access memory system 203 to the second command bus 209a. Furthermore, when the configurable data bit is in the second state, and the execution type is the second type, logic circuit 206 is configured to provide commands for use via the first cache access memory system 203 to the second command bus 209a.

[0126] In some embodiments, connection 204a to command bus 205a is configured to receive read or write commands from processor 201 for accessing memory system 203. Furthermore, connection 204b to address bus 205b is configured to receive memory addresses from processor 201 for accessing memory system 203 in response to read or write commands. Additionally, connection 204c to data bus 205c is configured to transmit data to processor 201 for the processor to read data in response to read commands. Furthermore, connection 204c to data bus 205c is also configured to receive data from processor 201 for writing to memory system 203 in response to write commands. Additionally, connection 204d to execution type signal line 205d is configured to receive an identification of the execution type from processor 201 (e.g., identification of non-speculated or speculative execution types performed by the processor).

[0127] In some embodiments, logic circuitry 206 may be configured to select a first cache for a memory access request from processor 201 (e.g., one of the commands received from the command bus for accessing the memory system) when the configurable data bit is in a first state and the connection 204d with execution type signal line 205d receives an indication of a first type (e.g., a non-predicted type). Furthermore, logic circuitry 206 may be configured to select a second cache for a memory access request from processor 201 when the configurable data bit is in a first state and the connection 204d with execution type signal line 205d receives an indication of a second type (e.g., a predicted type). Additionally, logic circuitry 206 may be configured to select a second cache for a memory access request from processor 201 when the configurable data bit is in a second state and the connection 204d with execution type signal line 205d receives an indication of a first type. Furthermore, the logic circuit 206 can be configured to select a first cache for a memory access request from the processor 201 when the configurable data bit is in the second state and the connection 204d with the execution type signal line 205d receives an indication of the second type.

[0128] Figure 3A Specifically, an aspect of an instance computing device is shown that includes a cache system (e.g., cache system 200) having multiple caches (e.g., see caches 302 and 304). The instance computing device is also shown as having a register 306 storing data 312 that may contain configurable bits. Register 306 may be connected to or be part of logic circuitry 206. Figure 3A In the example shown, during a first time instance (“Time Instance X”), register 306 stores data 312 of configurable bits that can be in a first state. Content 308a received from a first cache (e.g., cache 302) during the first time instance contains content for a first type of execution. Furthermore, content 310a received from a second cache (e.g., cache 304) during the first time instance contains content for a second type of execution.

[0129] Figure 3B Specifically, an aspect of an instance computing device is shown that includes a cache system (e.g., cache system 200) having multiple caches (e.g., see caches 302 and 304). The instance computing device is also shown as having a register 306 storing data 314 that may contain configurable bits. Figure 3BIn the diagram, during the second time instance (“Time Instance Y”), register 306 stores data 314 of configurable bits that can be in a second state. Content 308b received from the first cache (e.g., cache 302) during the second time instance contains content for the second type of execution. Furthermore, content 310b received from the second cache (e.g., cache 304) during the second time instance contains content for the first type of execution.

[0130] The described line 320, which connects register 306 to caches 302 and 304, can be part of logic circuit 206.

[0131] In some embodiments, instead of using configurable bits to control the use of the cache in cache system 200, another form of data can be used to control the use of the cache in cache system 200. For example, logic circuitry 206 can be configured to control a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b) based on different data stored in register 306 that are not configurable bits. In this example, when register 306 stores first data or is in a first state, the logic circuitry can be configured to: implement commands received from the command bus for accessing the memory system via the first cache when the execution type is a first type; and implement commands received from the command bus for accessing the memory system via the second cache when the execution type is a second type. Furthermore, when register 306 stores second data or is in a second state, the logic circuitry can be configured to: implement commands received from the command bus for accessing the memory system via the second cache when the execution type is a first type; and implement commands received from the command bus for accessing the memory system via the first cache when the execution type is a second type.

[0132] Figure 4 , 5A 5B illustrates an example aspect of an example computing device according to some embodiments of the present disclosure, each computing device including a cache system having interchangeable caches for main-type execution or normal-type execution (e.g., non-speculated execution) and speculative execution.

[0133] Figure 4 Specifically, it displays content that includes multiple caches (for example, see...). Figure 4 The cache system 400 (including caches 202a, 202b, and 202c) described herein is an example of a computing device. Figure 4 In the example, the computing device is also shown as having a processor 401 and a memory system 203. For example... Figure 4As shown, cache system 400 is similar to cache system 200, but cache system 400 also includes a connection 402 to a speculative status signal line 404 from processor 401 that identifies the speculative execution status of instructions by processor 401.

[0134] Similarly, cache system 400 is shown as including connection 204a to command bus 205a coupled between cache system and processor 401. System 400 also includes connection 204b to address bus 205b coupled between cache system and processor 401. Figure 1A , 1B Addresses 102a, 102b, 102c, 102d, and 102e, respectively, depicted in 1C, 1D, and 1E, may be communicated via address bus 205b, depending on the implementation of cache system 400. System 400 also includes a connection 204c to data bus 205c coupled between cache system and processor 401. It also includes a connection 204d to execution type signal line 205d from processor 401 that identifies non-speculated execution type or speculative execution type. Figure 4 Not shown in the diagram, the cache system 400 may also include configurable data bits. Configurable data bits may be included in the diagram shown in the diagram. Figure 5A The data 312 in the first state may be the data mentioned above, and may be included in the data displayed. Figure 5B The data in the second state 314 may be the data mentioned above.

[0135] In some embodiments, the cache system 400 may include a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b). In such embodiments, as Figure 4 As shown, cache system 400 may include logic circuitry 406 coupled to processor 401. Furthermore, in such embodiments, logic circuitry 406 may be configured to control a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b) based on configurable data bits. When the configurable data bits are in a first state (e.g., see...), Figure 5A The logic circuit 406 can be configured to: execute commands received from the command bus 205a for accessing the memory system 203 via the first cache when the execution type is non-speculated; and execute commands received from the command bus 205a for accessing the memory system 203 via the second cache when the execution type is speculative. When the configurable data bit is in the second state (e.g., see...), Figure 5BAs depicted in data 314), logic circuit 406 can be configured to execute commands received from command bus 205a for accessing memory system 203 via second cache when the execution type is non-speculated. Furthermore, when the configurable data bits are in a second state (e.g., see...), Figure 5B The data 314 depicted in the figure, the logic circuit 406 can be configured to execute commands received from the command bus 205a for accessing the memory system 203 via the first cache when the execution type is speculative.

[0136] In some embodiments, for example Figure 4 As shown, the first type can be configured to instruct the processor to perform non-speculatory execution of instructions. In this type of instance, the second type can be configured to instruct the processor to perform speculative execution of instructions. In this type of embodiment, the cache system 400 may further include a connection 402 to a speculative status signal line 404 from the processor 401 that identifies the state of speculative execution of instructions by the processor. The connection 402 to the speculative status signal line 404 may be configured to receive the state of speculative execution, and the state of speculative execution may indicate whether the result of speculative execution will be accepted or rejected.

[0137] Furthermore, when the execution type changes from the second type or speculative type to the first type or non-speculative type, the logic circuit 406 of the system 400 can be configured to switch the configurable data bits if the status indication of speculative execution will accept the result of speculative execution. Conversely, when the execution type changes from the second type or speculative type to the first type or non-speculative type, the logic circuit 406 of the system 400 can be configured to maintain the configurable data bits without changing if the status indication of speculative execution will reject the result of speculative execution.

[0138] Figure 5A Specifically, an aspect of an instance computing device is shown that includes a cache system (e.g., cache system 400) having multiple caches (e.g., see caches 302 and 304). The instance computing device is also shown as having a register 306 storing data 312 that may contain configurable bits. Figure 5A In the example shown, during the first time instance (“Time Instance X”), register 306 stores data 312 that can be configured to be in the first state. This is consistent with... Figure 3A Similarly, the difference is that the content 502a received from the first cache (e.g., cache 302) during the first instance includes content for non-speculated execution. And, the content 504a received from the second cache (e.g., cache 304) during the first instance includes content for speculative execution.

[0139] Figure 5BSpecifically, an aspect of an instance computing device is shown that includes a cache system (e.g., cache system 400) having multiple caches (e.g., see caches 302 and 304). The instance computing device is also shown as having a register 306 storing data 314 that may contain configurable bits. Figure 5B In the example shown, during the second time instance (“Time Instance Y”), register 306 stores data 314 that can be configured as a second state. This is consistent with... Figure 3B Similarly, the difference is that the content 502b received from the first cache (e.g., cache 302) during the second time instance contains content for speculative execution. And, the content 504b received from the second cache (e.g., cache 304) during the second time instance contains content for non-speculative execution.

[0140] Furthermore, similarly, in Figure 5A and 5B In the diagram, the line 320 that connects register 306 to caches 302 and 304 can be part of the logic circuit 406 of cache system 400.

[0141] In some embodiments, instead of using configurable bits to control the use of the cache in cache system 400, another form of data can be used to control the use of the cache in cache system 400. For example, logic circuitry 406 in system 400 can be configured to control a first cache (e.g., see cache 202a) and a second cache (e.g., see cache 202b) based on different data stored in register 306 that is not configurable bits. In such an example, when register 306 stores first data or is in a first state, the logic circuitry can be configured to: implement commands received from the command bus for accessing the memory system via the first cache when the execution type is non-speculated; and implement commands received from the command bus for accessing the memory system via the second cache when the execution type is speculative. Furthermore, when register 306 stores the second data or is in the second state, the logic circuit can be configured to: when the execution type is non-speculated, execute the command received from the command bus for accessing the memory system via the second cache; and when the execution type is speculative, execute the command received from the command bus for accessing the memory system via the first cache.

[0142] Some embodiments may include a cache system, and the cache system may include multiple caches, including a first cache and a second cache. The system may also include a connection to a command bus configured to receive read or write commands from a processor connected to the cache system for reading from or writing to a memory system. The system may also include a connection to an address bus configured to receive memory addresses from the processor for accessing the memory system in response to read or write commands. The system may also include a connection to a data bus configured to: transmit data to the processor for the processor to read data in response to read commands; and receive data from the processor for writing to the memory system in response to write commands. In such instances, memory access requests from the processor and memory used by the processor may be defined by the command bus, address bus, and data bus. The system may also include an execution type signal line configured to receive an identification of the execution type from the processor. The execution type is a first execution type or a second execution type (e.g., normal or non-speculated execution or speculative execution).

[0143] The system may also include configurable data bits, which are configured to be set to a first state (e.g., "0") or a second state (e.g., "1") to control the selection of a first cache and a second cache for use by the processor.

[0144] The system may further include logic circuitry configured to select a first cache for processor use when the configurable data bit is in a first state and the execution type signal line receives an indication of a first type of execution. The logic circuitry may also be configured to select a second cache for processor use when the configurable data bit is in a first state and the execution type signal line receives an indication of a second type of execution. The logic circuitry may also be configured to select a second cache for processor use when the configurable data bit is in a second state and the execution type signal line receives an indication of a first type of execution. The logic circuitry may also be configured to select a first cache for processor use when the configurable data bit is in a second state and the execution type signal line receives an indication of a second type of execution.

[0145] In some embodiments, the first type of execution is speculative execution of instructions by the processor, and the second type of execution is non-speculative execution of instructions by the processor (e.g., normal or main execution). In such instances, the system may further include a connection to a speculative state signal line configured to receive speculative states from the processor. The speculative state may be an acceptance or rejection of a condition with nested instructions, which are initially executed by speculative execution of the processor and subsequently by normal execution of the processor when the speculative state is acceptance of the condition.

[0146] In some embodiments, the logic circuitry is configured to switch the configurable data bits from a first state to a second state upon acceptance conditionally received from the speculative state signal line. The logic circuitry may also be configured to maintain the state of the configurable data bits upon rejection conditionally received from the speculative state signal line.

[0147] In some embodiments, the logic circuitry is configured to select a second cache for use, as identified by a first state of the configurable data bits, and restrict the use of a first cache, as identified by the first state of the configurable data bits, when the signal received by the execution type signal line changes from an indication of normal execution to an indication of speculative execution. Under this change, the logic circuitry can ignore / bypass the speculative state because the processor in speculative execution is unaware of whether the main execution should execute instructions pre-formed under speculative execution.

[0148] The logic circuit can also be configured to maintain a first state of the configurable data bits when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of normal execution and when the speculative state received by the speculative state signal line is a conditional rejection, and to select a first cache for a memory access request when the execution type signal line receives an indication of normal execution.

[0149] In some embodiments, the logic circuitry is configured to invalidate and discard the contents of the second cache when the signal received by the execution type signal line changes from an indication of speculative execution to an indication of normal execution and when the speculative state received by the speculative state signal line is a conditional rejection.

[0150] In some embodiments, the system further includes a connection to a second command bus configured to transmit read or write commands to a memory system (e.g., including main memory). Read or write commands may be received from the processor by a cache system. The system may also include a connection to a second address bus configured to transmit memory addresses to the memory system. Memory addresses may be received from the processor by the cache system. The system may also include a connection to a second data bus configured to: transmit data to the memory system for writing into the memory system; and receive data from the memory system for transmission to the processor for reading by the processor. For example, a memory access request to the memory system from the cache system may be defined by the second command bus, the second address bus, and the second data bus.

[0151] In some embodiments, when the configurable data bit is in a first state, the logic circuitry is configured to: provide commands for use via the first cache access memory system to the second command bus when the execution type is a first type; and provide commands for use via the second cache access memory system to the second command bus when the execution type is a second type. Furthermore, when the configurable data bit is in a second state, the logic circuitry can be configured to: provide commands for use via the second cache access memory system to the second command bus when the execution type is a first type; and provide commands for use via the first cache access memory system to the second command bus when the execution type is a second type.

[0152] Some embodiments may include a system comprising a processor, a memory system, and a cache system coupled between the processor and the memory system. The system's cache system may include multiple caches, including a first cache and a second cache. The system's cache system may also include connections to a command bus coupled between the cache system and the processor, connections to an address bus coupled between the cache system and the processor, connections to a data bus coupled between the cache system and the processor, and connections to an execution type signal line from the processor that identifies the execution type.

[0153] The system's cache system may further include configurable data bits and logic circuitry coupled to the processor to control the first and second caches based on the configurable data bits. When the configurable data bits are in a first state, the logic circuitry may be configured to: execute commands received from the command bus for accessing the memory system via the first cache when the execution type is a first type; and execute commands received from the command bus for accessing the memory system via the second cache when the execution type is a second type. Furthermore, when the configurable data bits are in a second state, the logic circuitry may be configured to: execute commands received from the command bus for accessing the memory system via the second cache when the execution type is a first type; and execute commands received from the command bus for accessing the memory system via the first cache when the execution type is a second type.

[0154] In this system, a first type can be configured to instruct the processor to perform non-speculated execution of instructions, and a second type can be configured to instruct the processor to perform speculative execution of instructions. Furthermore, the system's cache system may further include a connection to a speculative status signal line from the processor that identifies the state of speculative execution of instructions. The connection to the speculative status signal line can be configured to receive the state of speculative execution, and the state of speculative execution can indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from the second type (speculative type) to the first type (non-speculative type), the logic circuitry can be configured to switch configurable data bits if the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, when the execution type changes from the second type (speculative type) to the first type (non-speculative type), the logic circuitry can also be configured to maintain the configurable data bits unchanged if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0155] Figure 6 , 7A Examples 7B, 8A, 8B, 9A, and 9B illustrate example aspects of example computing devices according to some embodiments of the present disclosure, each computing device including a caching system having an interchangeable set of caches for first-type and second-type execution (e.g., for implementing shadow caching technology and / or for primary-type and speculative-type execution with enhanced security).

[0156] Figure 6 Specifically, an aspect of an instance computing device is shown comprising a cache system 600 having multiple caches (e.g., see caches 602a, 602b, and 602c), wherein at least one of the caches is implemented in a cache set affinity manner. The instance computing device is also shown as having a processor 601 and a memory system 603. The cache system 600 is configured to be coupled between the processor 601 and the memory system 603.

[0157] The cache system 600 is shown as including a connection 604a to the command bus 605a coupled between the cache system and the processor 601. The cache system 600 is also shown as including a connection 604b to the address bus 605b coupled between the cache system and the processor 601. Figure 1A , 1BAddresses 102a, 102b, 102c, 102d, and 102e, respectively, depicted in 1C, 1D, and 1E, may be communicated via address bus 605b, depending on the implementation of cache system 600. Cache system 600 is shown as including connection 604c to data bus 605c coupled between cache system and processor 601. Cache system 600 is also shown as including connection 604d to execution type signal line 605d from processor 601 that identifies the execution type. Connections 604a, 604b, 604c, and 604d provide communication coupling between buses 605a, 605b, 605c, and 605d and logic circuitry 606 of cache system 600.

[0158] In addition, such as Figure 6 As shown, the cache system 600 further includes a connection 608a to a second command bus 609a coupled between the cache system and the memory system 603. The cache system 600 also includes a connection 608b to a second address bus 609b coupled between the cache system and the memory system 603. The cache system 600 also includes a connection 608c to a second data bus 609c coupled between the cache system and the memory system 603.

[0159] The cache system 600 also includes multiple cache sets (e.g., see cache sets 610a, 610b, and 610c). A cache set may include a first cache set (e.g., see cache set 610a) and a second cache set (e.g., see cache set 610b).

[0160] In addition, such as Figure 6 As shown, cache system 600 further includes multiple registers (e.g., see registers 612a, 612b, and 612c) associated with multiple cache sets respectively. A register (or cache set register) may include a first register (e.g., see register 612a) associated with a first cache set (e.g., see cache set 610a) and a second register (e.g., see register 612a) associated with a second cache set (e.g., see cache set 610b). Each of the multiple registers (e.g., see registers 612a, 612b, and 612c) may be configured to store a set index.

[0161] like Figure 6 as well as Figure 10As shown, caches 602a and 602b through 602c (caches 1 through N) are not a fixed structure. However, it should be understood that in some embodiments, the caches may be a fixed structure. Each of the depicted caches can be considered as a logical grouping of cache sets, and such logical grouping is shown by dashed lines representing each logical cache. Cache sets 610a through 610c (cache sets 1 through N) may be based on the contents of registers 612a through 612c (registers 1 through N). Cache sets 1 through N may be a set of cache sets within a cache system shared by cache 1 and caches 2 through N. Cache 1 may be a subset of said set; cache 2 may be another non-overlapping subset. The member cache sets in each of the caches may change based on the contents of registers 1 through N.

[0162] Depending on the implementation, cache set 1 (in a conventional sense) may or may not communicate with its register 1. The dashed line also shows... Figure 7A , 7B 8A, 8B, 9A and 9B are indicated Figure 7A , 7B The logical relationship between cache sets and their corresponding registers in 8A, 8B, 9A, and 9B. The contents of register 1 determine how cache set 1 is addressed (e.g., which cache set index will cause cache set 1 to be selected for output data). In some embodiments, there is no direct interaction between cache set 1 and its corresponding register 1. Depending on the embodiment, logic circuitry 606 or 1006 interacts with both the cache set and the corresponding register.

[0163] In some embodiments, logic circuitry 606 may be coupled to processor 601 to control multiple cache sets (e.g., cache sets 610a, 610b, and 610c) based on multiple registers (e.g., registers 612a, 612b, and 612c). In such embodiments, cache system 600 may be configured to be coupled between processor 601 and memory system 603. Furthermore, when connection 604b to address bus 605b receives a memory address from processor 601, logic circuitry 606 may be configured to generate a set index from at least the memory address and determine whether the generated set index matches the content stored in a first register (e.g., register 612a) or the content stored in a second register (e.g., register 612b). The logic circuit 606 can also be configured to execute a command received in the connection 604a with the command bus 605a via a first cache set (e.g., cache set 610a) in response to a generated set index matching the contents stored in a first register (e.g., register 612a), and to execute the command via a second cache set (e.g., cache set 610b) in response to a generated set index matching the contents stored in a second register (e.g., register 612b).

[0164] In some embodiments, the cache system 600 may include a first cache (e.g., see cache 602a) and a second cache (e.g., see cache 602b). In such embodiments, as Figure 2 As shown, cache system 600 may include logic circuitry 606 coupled to processor 601. Furthermore, in such embodiments, logic circuitry 606 may be configured to control a first cache (e.g., see cache 602a) and a second cache (e.g., see cache 602b) based on configurable data bits and / or corresponding registers (e.g., see registers 612a, 612b, and 612c).

[0165] In some embodiments, in response to determining that the dataset of memory system 603 associated with a memory address is not currently cached in cache system 600 (e.g., not cached in system cache 602a), logic circuitry 606 is configured to allocate a first cache set (e.g., cache set 610a) for caching the dataset and store the resulting set index in a first register (e.g., register 612a). In such embodiments and other embodiments, the cache system may include a connection to an execution type signal line from a processor (e.g., processor 601) that identifies the execution type (e.g., connection 604d to execution type signal line 605). Furthermore, in such embodiments and other embodiments, the resulting set index is further generated based on the type identified by the execution type signal line. Additionally, the resulting set index may include a pre-defined bit segment in the memory address and bits representing the type identified by execution type signal line 605d.

[0166] Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in a first state, logic circuitry 606 can be configured to execute commands received from command bus 605a for accessing memory system 603 via a first cache set (e.g., cache set 610a) when the execution type is a first type. Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in a first state, logic circuitry 606 can be configured to execute commands received from command bus 605a for accessing memory system 603 via a second cache set (e.g., cache set 610b) when the execution type is a second type.

[0167] Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in the second state, logic circuitry 606 can be configured to, when the execution type is the first type, execute commands received from command bus 605a for accessing memory system 603 via another cache set (e.g., cache set 610b or 610c) among the plurality of cache sets other than the first cache set. Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in the second state, logic circuitry 606 can be configured to, when the execution type is the second type, execute commands received from command bus 605a for accessing memory system 603 via another cache set (e.g., cache set 610a or 610c) among the plurality of cache sets other than the second cache set. Figure 6 (Another cache set not described in the text) commands to access memory system 603.

[0168] In some embodiments, each of the plurality of registers (e.g., see registers 612a, 612b, and 612c) may be configured to store a set index, and when the execution type changes from a second type to a first type (e.g., from a non-speculated type of execution to a speculated type), logic circuit 606 may be configured to change the contents stored in the first register (e.g., register 612a) and the contents stored in the second register (e.g., register 612b). Figure 7A and 7B , Figure 8A and 8B as well as Figure 9A and 9B The example illustrates an instance of changes to the contents stored in a first register (e.g., register 612a) and the contents stored in a second register (e.g., register 612b).

[0169] Figure 7A , 7B Each of Figures 8A, 8B, 9A, and 9B specifically illustrates an aspect of an instance computing device comprising a cache system having multiple cache sets (e.g., see caches 702, 704, and 706), wherein the cache sets are implemented via cache set association. The corresponding cache system in each of these figures is also shown having multiple registers, each associated with a cache set. The multiple registers include at least registers 712, 714, and 716. The multiple registers include at least one additional register not shown in the figures. Register 712 is shown as associated with or connected to cache set 702, register 714 is shown as associated with or connected to cache set 704, and register 716 is shown as associated with or connected to cache set 706.

[0170] Figure 7A , 7B Not shown in 8A, 8B, 9A, and 9B, each of the corresponding cache systems may further include connections to a command bus coupled between the cache system and the processor, connections to an address bus coupled between the cache system and the processor, and connections to a data bus coupled between the cache system and the processor. Each cache system may also include logic circuitry coupled to the processor to control multiple cache sets (e.g., cache sets 702, 704, and 706) according to multiple registers (e.g., registers 712, 714, and 716).

[0171] As by Figure 7A , 7BAs illustrated in 8A, 8B, 9A, and 9B, when the connection to the address bus of the cache system receives a memory address from the processor (e.g., see memory address 102b, 102c, or 102d), the logic circuitry of the cache system can be configured to generate set indices from the memory address (e.g., see set indices 722, 724, 726, or 728) (e.g., see set indexes generating 730, 732, 830, 832, 930, or 932).

[0172] Specifically, such as Figure 7A As shown, at least registers 712, 714, and 716 are configured in a first state. When the address bus connection to the cache system receives memory address 102b from the processor, the cache system's logic circuitry generates set indices 722, 724, or 726 based on at least set index generation 730a, 730b, or 730c and an entry in cache set index 112b for address 102b. Set index generation 730a, 730b, or 730c can be used to store set indices 722, 724, or 726 in registers 712, 714, or 716, respectively. Set index generation 730a, 730b, or 730c can also be used in comparisons of recently generated set indices with contents already stored in registers 712, 714, or 716. Set index generation 730a, 730b, and 730c occur when the registers are configured in the first state. The configuration of the first state is achieved through set index generation and storage.

[0173] Specifically, such as Figure 7B As shown, at least registers 712, 714, and 716 are configured in the second state. When the connection to the address bus of the cache system receives memory address 102b from the processor, the cache system's logic circuitry generates set indices 726, 722, or 728 based on at least set index generation 732a, 732b, or 732c and an entry of cache set index 112b for address 102b. Set index generation 732a, 732b, or 732c can be used to store set indices 726, 722, or 728 in registers 712, 714, or 716, respectively. Set index generation 732a, 732b, or 732c can also be used in comparisons of recently generated set indices with contents already stored in registers 712, 714, or 716. Set index generation 732a, 732b, and 732c occur when the registers are configured in the second state. The configuration of the second state is achieved through set index generation and storage.

[0174] Specifically, such as Figure 8AAs shown, at least registers 712, 714, and 716 are configured in a first state. When the connection to the address bus of the cache system receives memory address 102c from the processor, the logic circuitry of the cache system generates set indices 722, 724, or 726 based on at least set index generation 830a, 830b, or 830c and an entry of tag 104c with a cache set indicator for address 102c. Set index generation 830a, 830b, or 830c can be used to store set indices 722, 724, or 726 in registers 712, 714, or 716, respectively. Set index generation 830a, 830b, or 830c can also be used in comparisons of recently generated set indices with contents already stored in registers 712, 714, or 716, respectively. Set index generation 830a, 830b, and 830c occur when the registers are configured in the first state.

[0175] Specifically, such as Figure 8B As shown, at least registers 712, 714, and 716 are configured in the second state. When the connection to the address bus of the cache system receives memory address 102c from the processor, the logic circuitry of the cache system generates set indices 726, 722, or 728 based on at least set index generation 832a, 832b, or 832c and the entry of tag 104c with a cache set indicator for address 102c. Set index generation 832a, 832b, or 832c can be used to store set indices 726, 722, or 728 in registers 712, 714, or 716, respectively. Set index generation 832a, 832b, or 832c can also be used in comparisons of recently generated set indices with contents already stored in registers 712, 714, or 716, respectively. Set index generation 832a, 832b, and 832c occur when the registers are configured in the second state.

[0176] Specifically, such as Figure 9AAs shown, at least registers 712, 714, and 716 are configured in a first state. When the connection to the address bus of the cache system receives memory address 102d from the processor, the logic circuitry of the cache system generates set indices 722, 724, or 726 based on at least set index generation 930a, 930b, or 930c and the entry of cache set index 112d in tag 104d of address 102d. Set index generation 930a, 930b, or 930c can be used to store set indices 722, 724, or 726 in registers 712, 714, or 716, respectively. Set index generation 930a, 930b, or 930c can also be used in comparisons of recently generated set indices with contents already stored in registers 712, 714, or 716, respectively. Set index generation 930a, 930b, and 930c occur when the registers are configured in the first state.

[0177] Specifically, such as Figure 9B As shown, at least registers 712, 714, and 716 are configured in the second state. When the connection to the address bus of the cache system receives memory address 102d from the processor, the cache system's logic circuitry generates set indices 726, 722, or 728 based on at least set index generation 932a, 932b, or 932c and the entry of cache set index 112d in tag 104d of address 102d. Set index generation 932a, 932b, or 932c can be used to store set indices 726, 722, or 728 in registers 712, 714, or 716, respectively. Set index generation 932a, 932b, or 932c can also be used in comparisons of recently generated set indices with contents already stored in registers 712, 714, or 716. Set index generation 932a, 932b, and 932c occur when the registers are configured in the second state.

[0178] In passing Figure 7A and 7B In some embodiments of the cache system implementations described in 8A and 8B or 9A and 9B, when a memory address is received from the processor via a connection to the address bus, logic circuitry may be configured to determine whether the generated set index matches the contents stored in one of the registers (e.g., registers 712, 714, and 716). The contents stored in the register may be derived from a previous generation of the set index in the register and the storage of the set index.

[0179] In addition, through Figure 7A and 7BIn some embodiments of the cache system implementations described in 8A and 8B or 9A and 9B, the logic circuitry may be configured to execute a command received in a connection to a command bus via a first cache set in response to a generated set index matching the contents stored in an associated first register, and to execute the command via a second cache set in response to a generated set index matching the contents stored in an associated second register. Furthermore, in response to determining that a dataset of the memory system associated with a memory address is not currently cached in the cache system, the logic circuitry may be configured to allocate a first cache set for caching the dataset and store the generated set index in a first register. The generated set index may contain a pre-defined segment of the memory address.

[0180] Furthermore, in this type of embodiment, when the first and second registers are in a first state, the logic circuitry can be configured to: when the processor's execution type is a first type, implement commands received from the command bus for accessing the memory system via a first cache set; and when the execution type is a second type, implement commands received from the command bus for accessing the memory system via a second cache set. Furthermore, when the first and second registers are in a second state, the logic circuitry can be configured to: when the execution type is a first type, implement commands received from the command bus for accessing the memory system via another cache set among the plurality of cache sets besides the first cache set; and when the execution type is a second type, implement commands received from the command bus for accessing the memory system via yet another cache set among the plurality of cache sets besides the second cache set. In this example, each of the plurality of registers can be configured to store a set index, and when the execution type changes from the second type to the first type, the logic circuitry can be configured to change the contents stored in the first register and the contents stored in the second register.

[0181] Figure 10 Specifically, it displays content that includes multiple caches (for example, see...). Figure 10 This relates to an instance computing device aspect of the cache system 1000 (caches 602a, 602b, and 602c) depicted in the text, wherein at least one of the caches is implemented with cache set associativity (e.g., see cache sets 610a, 610b, and 610c). Figure 10 In the example, the computing device is also shown as having a processor 1001 and a memory system 603. For example... Figure 10 As shown, cache system 1000 is similar to cache system 600, but cache system 1000 also includes a connection 1002 to a speculative status signal line 1004 from processor 1001 that identifies the speculative execution status of instructions by processor 1001.

[0182] Similarly, cache system 1000 is shown as including connection 604a to command bus 605a coupled between cache system and processor 1001. System 1000 also includes connection 604b to address bus 605b coupled between cache system and processor 1001. Figure 1A , 1B Addresses 102a, 102b, 102c, 102d, and 102e, respectively, depicted in 1C, 1D, and 1E, may be communicated via address bus 605b, depending on the implementation of cache system 1000. System 1000 also includes a connection 604c to data bus 605c coupled between cache system and processor 1001. It also includes a connection 604d to execution type signal line 605d from processor 1001 that identifies non-speculated execution type or speculative execution type.

[0183] Similarly, the cache system 1000 is also shown to include a logic circuit 1006 that is similar to the logic circuit 606, but its circuitry is coupled to a connection 1002 that is coupled to the speculative state signal line 1004.

[0184] In some embodiments, logic circuitry 1006 may be coupled to processor 1001 to control multiple cache sets (e.g., cache sets 610a, 610b, and 610c) based on multiple registers (e.g., registers 612a, 612b, and 612c). Each of the multiple registers (e.g., see registers 612a, 612b, and 612c) may be configured to store a set index.

[0185] In such embodiments, cache system 1000 may be configured to couple between processor 1001 and memory system 603. Furthermore, when connection 604b to address bus 605b receives a memory address from processor 1001, logic circuitry 1006 may be configured to generate a set index from at least the memory address and determine whether the generated set index matches content stored in a first register (e.g., register 612a) or content stored in a second register (e.g., register 612b). Logic circuitry 1006 may also be configured to execute a command received in connection 604a to command bus 605a via a first cache set (e.g., cache set 610a) in response to a match between the generated set index and content stored in the first register (e.g., register 612a), and to execute the command via a second cache set (e.g., cache set 610b) in response to a match between the generated set index and content stored in the second register (e.g., register 612b).

[0186] In addition, the Cache System 1000 is shown to include and Figure 6 The corresponding connections shown are similar to those in 608a, 608b, and 608c. Relative to... Figure 6 and 10 The connections 608a, 608b, and 608c depicted herein, when the first and second registers (e.g., registers 612a and 612b) are in a first state, logic circuitry 606 or 1006 may be configured to provide commands for accessing memory system 603 via a first cache set (e.g., cache set 610a) to a second command bus 609a when the execution type is a first type (e.g., non-speculated type). Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in the first state, logic circuitry 606 or 1006 may be configured to provide commands for accessing memory system 603 via a second cache set (e.g., cache set 610b) to a second command bus 609a when the execution type is a second type (e.g., speculated type).

[0187] Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in the second state, logic circuitry 606 or 1006 may be configured to, when the execution type is the first type, use a cache set other than the first cache set (e.g., cache set 610b or 610c, or...). Figure 6 Commands to access memory system 603 via a cache set (or another cache set not depicted in 10) are provided to the second command bus 609a. Furthermore, when the first and second registers (e.g., registers 612a and 612b) are in a second state, logic circuitry 606 or 1006 may be configured to, when the execution type is second, be used to access memory system 603 via a cache set other than the second cache set (e.g., cache sets 610a or 610c, or...). Figure 6 Commands for accessing the memory system 603 (or another cache set not depicted in 10) are provided to the second command bus 609a.

[0188] In some embodiments, such as those shown in Figure 10 In this configuration, the first type can be configured to instruct processor 1001 to perform non-speculated execution of instructions; and the second type can be configured to instruct processor to perform speculative execution of instructions. (Example shown) Figure 10 In the cache system 1000, a connection 1002 is further included with respect to a speculative status signal line 1004 from the processor 1001 that identifies the speculative execution status of the processor on an instruction. The connection 1002 with the speculative status signal line 1004 is configured to receive the speculative execution status, and the speculative execution status can indicate whether the result of the speculative execution will be accepted or rejected.

[0189] In such embodiments, each of the plurality of registers (e.g., registers 612a, 612b, and 612c) can be configured to store a set index, and when the execution type changes from a speculative execution type to a non-speculative execution type, the logic circuit 1006 can be configured to modify the contents stored in the first register (e.g., register 612a) and the contents stored in the second register (e.g., register 612b) if the status indication of the speculative execution type is to accept the result of speculative execution. Furthermore, when the execution type changes from a speculative type to a non-speculative type, the logic circuit 1006 can be configured to maintain the contents stored in the first register and the contents stored in the second register without modification if the status indication of the speculative execution type is to reject the result of speculative execution.

[0190] Some embodiments may include a cache system comprising multiple cache sets, the multiple cache sets having at least a first cache set and a second cache set. The cache system may also include multiple registers respectively associated with the multiple cache sets. The multiple registers may include at least a first register associated with the first cache set configured to store a set index, and a second register associated with the second cache set configured to store a set index. The cache system may also include connections to a command bus coupled between the cache system and the processor, connections to an address bus coupled between the cache system and the processor, connections to a data bus coupled between the cache system and the processor, and connections to an execution type signal line from the processor that identifies the execution type.

[0191] The cache system may also include logic coupled to the processor to control multiple cache sets according to multiple registers. Furthermore, the cache system may be configured to be coupled between the processor and the memory system. When the first and second registers are in a first state, the logic may be configured to: implement commands received from the command bus for accessing the memory system via the first cache set when the execution type is a first type; and implement commands received from the command bus for accessing the memory system via the second cache set when the execution type is a second type. Additionally, when the first and second registers are in a second state, the logic may be configured to: implement commands received from the command bus for accessing the memory system via another cache set other than the first cache set when the execution type is a first type; and implement commands received from the command bus for accessing the memory system via yet another cache set other than the second cache set when the execution type is a second type.

[0192] The connection to the address bus can be configured to receive memory addresses from the processor, and the memory addresses can contain set indices.

[0193] In some embodiments, when the first and second registers are in a first state, a first set index associated with a first cache set is stored in the first register, and a second set index associated with a second cache set is stored in the second register. When the first and second registers are in a second state, the first set index may be stored in another register among a plurality of registers besides the first register, and the second set index may be stored in another register among a plurality of registers besides the second register. In such instances, when a connection to the address bus receives a memory address from the processor, the logic circuitry may be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches the content stored in the first register or the content stored in the second register. Furthermore, the logic circuitry may be further configured to execute a command received in the connection to the command bus via the first cache set in response to the generated set index matching the content stored in the first register, and to execute the command via the second cache set in response to the generated set index matching the content stored in the second register.

[0194] In response to determining that the dataset of the memory system associated with the memory address is not currently cached in the cache system, the logic circuitry can be configured to allocate a first cache set for caching the dataset and store the resulting set index in a first register.

[0195] In some embodiments, the generated set index is further generated based on the execution type identified by the execution type signal line. In such instances, the generated set index may include a pre-defined bit segment in a memory address and bits representing the execution type identified by the execution type signal line.

[0196] Some embodiments may include a system comprising a processor, a memory system, and a cache system. The cache system may include: multiple cache sets, including a first cache set and a second cache set; and multiple registers associated with the multiple cache sets, including a first register associated with the first cache set and a second register associated with the second cache set. The cache system may also include connections to a command bus coupled between the cache system and the processor, connections to an address bus coupled between the cache system and the processor, and connections to a data bus coupled between the cache system and the processor.

[0197] The cache system may also include logic coupled to the processor to control multiple cache sets based on multiple registers. When a memory address is received from the processor via a connection to the address bus, the logic may be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches a content stored in a first register or a content stored in a second register. Furthermore, the logic may be configured to execute a command received in a connection to the command bus via a first cache set in response to a match between the generated set index and a content stored in the first register, and to execute the command via a second cache set in response to a match between the generated set index and a content stored in the second register.

[0198] The cache system may further include a connection to an execution type signal line from the processor that identifies the execution type. A generated set index may be generated based on the type identified by the execution type signal line. The generated set index may include a pre-defined bit segment in the memory address and bits representing the type identified by the execution type signal line.

[0199] Figure 11A and 11B This description describes a background synchronization circuitry system according to some embodiments of the present disclosure for synchronizing content between a main cache and a shadow cache to store content cached in the main cache for receiving content in the shadow cache. Figure 11A and 11B The cache system includes a background synchronization circuit system 1102. For example, caches 1124 and 1126 may be... Figure 2 Or caches 202a and 202b in 4, or Figure 6 Alternatively, caches 602a and 602b in 10. The background synchronization circuit system 1102 may be part of logic circuits 206, 406, 606, or 1006.

[0200] Figure 11AThis describes a scenario where cache 1124 is used as the main cache during non-speculated execution and cache 1126 is used as a shadow cache during speculative execution. The background synchronization circuitry 1102 is configured to synchronize cache contents from cache 1124 to cache 1130, such that if conditional speculative execution is deemed necessary, cache 1126 can be used as the main cache in subsequent non-speculated executions; and cache 1124 can be used as a shadow cache in another instance of speculative execution. Synchronizing cache contents from cache 1124 to cache 1130 copies the previous execution result to cache 1126, ensuring no loss of execution result when cache 1124 is subsequently repurposed as a shadow cache. Cache contents from cache 1124 can be cached in cache 1124 but have not yet been flushed to memory (e.g., memory 203 or 603). Furthermore, some of the memory contents cached in cache 1124 with identical copies can also be copied from cache 1124 to cache 1126, so that when cache 1126 is subsequently used as the main cache, the contents previously cached in cache 1124 are also available in cache 1126. This speeds up access to previously cached contents. Copying contents between cache 1124 and cache 1126 is faster than retrieving data from memory into the cache system.

[0201] In some embodiments, if a variable is referenced during normal program execution, then the variable can be cached. In such instances, if the variable is referenced during a write-back to the cache during speculation, then the value in main memory is valid and correct. If the variable is referenced during a write-back to the cache during speculation, then a cache-specific cache can be used. Figure 11A The aforementioned instance features are described; and the valid values ​​of the variables can be found in cache 1124.

[0202] exist Figure 11A In the scenario described herein, the processor (e.g., processor 201, 401, 601, or 1001) may execute the first instruction set in a non-specular execution mode. During the execution of the first instruction set, the processor may access memory addresses to load data (e.g., instructions and operands) from memory and store computation results. Since cache 1124 is used as a main cache, the contents of the data and / or computation results may be cached in cache 1124. For example, cache 1124 may store computation results that have not yet been written back to memory; and cache 1124 may store loaded data (e.g., instructions and operands) that can be used in subsequent execution of instructions.

[0203] When preparing cache B 1226 for use as a shadow cache in speculative execution of the second instruction set, background synchronization circuitry 1102 copies the contents of the cache from cache 1124 to cache 1126 in synchronization 1130. At least part of the copy operation can be performed in the background, independently of the processor accessing memory via the cache system. For example, while the processor is accessing a first memory address in non-speculative execution of the first instruction set, background synchronization circuitry 1102 can copy the contents cached in cache 1124 for the second memory address to cache 1126. In some cases, the copy operation can be performed in the background concurrently with memory access via the cache system. For example, while the processor is accessing a first memory address in non-speculative execution of the first instruction set to store a computation result, background synchronization circuitry can copy the computation result to cache 1126 as cache contents for the first memory address.

[0204] In one implementation, the background synchronization circuitry 1102 is configured to complete the synchronization operation before allowing cache 1126 to be used for speculative execution of the second instruction set. Therefore, when cache 1126 is enabled for speculative execution of the second instruction set, valid content in cache 1124 can also be found in cache 1126. However, the synchronization operation may delay the use of cache 1126 as a shadow cache. Alternatively, the background synchronization circuitry 1102 is configured to prioritize the synchronization of dirty content from cache 1124 to cache 1126. Dirty content can be data in the cache that has been modified but data in main memory has not yet been modified.

[0205] Dirty content cached in cache 1124 may be newer than the content stored in memory at one or more corresponding addresses. For example, when the processor stores a computation result at address 1124, cache 1124 may cache the computation result at that address instead of immediately writing the computation result to memory at that address. When the computation result is written back to memory at that address, the cached content is no longer considered dirty. Cache 1124 stores data to track dirty content cached in cache 1124. Background synchronization circuitry 1102 may automatically copy dirty content from cache 1124 to cache 1126 when cache 1126 is ready to act as a shadow cache.

[0206] Optionally, prior to completing the synchronization operation, the background synchronization circuitry 1102 may allow cache 1126 to act as a shadow cache during conditional speculative execution of the second instruction set. During the period when cache 1126 is used as a shadow cache in speculative execution, the background synchronization circuitry 1102 may continue the synchronization operation 1130 of copying cache contents from cache 1124 to cache 1126. The background synchronization circuitry 1102 is configured to complete at least the synchronization of dirty contents from cache 1124 to cache 1126 before allowing cache 1126 to be accepted as the primary cache. For example, after an instruction requiring execution of the second instruction set, the background synchronization circuitry 1102 determines whether dirty contents in cache 1124 have been synchronized to cache 1126; and if not, then postpones the use of cache 1126 as the primary cache until synchronization is complete.

[0207] In some implementations, the background synchronization circuitry 1102 may continue its synchronization operation even after accepting cache 1126 as the main cache but before cache 1124 is used as a shadow cache in conditional speculative execution of the third instruction set.

[0208] Before completing synchronization operation 1130, the cache system may configure cache 1124 as an auxiliary cache between cache 1126 and memory during speculative execution. This allows the cache system to check cache 1124 to determine if the content at the memory address is not found in cache 1126 if it is; and if so, to copy the content from cache 1124 to cache 1126 (instead of loading it directly from memory). When the processor stores data at the memory address and the data is cached in cache 1126, the cache system checks to invalidate the content cached in cache 1124, which serves as an auxiliary cache.

[0209] After receiving the speculative execution result of the second instruction set, cache 1126 is reconfigured as the main cache, and the background synchronization circuit system 1102 can begin synchronizing the contents of the cache from cache 1126 to cache 1124, as follows: Figure 11B As explained in the text.

[0210] After speculative execution of the second instruction set, if the speculative status from the processor indicates that the result of the second instruction set execution should be rejected, then cache 1124 remains as the main cache; and the contents of cache 1126 may be invalid. Invalidation may involve cache 1126 marking all its entries as empty; therefore, any subsequent speculative execution begins with an empty speculative cache.

[0211] The background synchronization circuit system 1102 can synchronize the contents of the cache from cache 1124 to cache 1130 again for speculative execution of the third instruction set.

[0212] In some embodiments, each of caches 1124 and 1126 has a dedicated and fixed set of cache collections; and configurable bits are used to control the use of caches 1124 and 1126 as primary cache and shadow cache, respectively. Figure 3A , 3B As explained in 5A and 5B.

[0213] In other embodiments, cache 1124 and cache 1126 may share a pool of cache sets, some of which may be dynamically allocated to cache 1124 and cache 1126, such as... Figures 6 to 10 As explained in [the document]. When cache 1124 is used as the main cache and cache 1126 is used as a shadow cache, cache 1126 may have a smaller number of cache sets than cache 1124. Some of the cache sets in cache 1126 may be shadows of a portion of the cache sets in cache 1124, such that when it is determined that the result of speculative execution is accepted, a portion of the cache sets in cache 1124 can be reconfigured for use as a shadow cache in the next speculative execution; and the remaining portion of the cache sets unaffected by speculative execution can be reallocated from cache 1124 to cache 1126, so that the contents of the caches in the unaffected portion can be further used in subsequent non-speculative executions.

[0214] Figure 12 Demonstrating some embodiments according to this disclosure Figure 11A and 11B Example operation of background synchronization circuit system 1102.

[0215] like Figure 12 As shown, at operation 1202, the cache system configures the first cache as the primary cache and the second cache as a shadow cache. For example, when a dedicated cache with a fixed hardware architecture is used as both the first and second caches, the configurable bits can be used to configure the first cache as the primary cache and the second cache as a shadow cache, such as... Figures 2 to 5B As explained in [the document]. Alternatively, it can be as follows: Figures 6 to 10 The method described herein uses registers to allocate cache sets from the pool of cache sets to the first cache and the second cache, and to allocate from the first cache and the second cache.

[0216] At operation 1204, the cache system determines whether the current execution type has changed from non-speculated to speculative. For example, when the processor accesses memory via cache system 200, the processor further provides an indication of whether the current memory access is associated with conditional speculative execution. For example, this indication can be provided in signal line 205d configured to specify the execution type.

[0217] If the current execution type does not change from non-speculated to speculative, then at operation 1206, the cache system uses the first cache as the primary cache to service memory access requests from the processor. When memory access changes the contents of the cache in the first cache, the background synchronization circuitry 1102 can copy the contents cached in the first cache to the second cache in operation 1208. For example, the background synchronization circuitry 1102 can... Figure 2 Logic circuit 206 in Figure 4 406 in Figure 6 606 and / or Figure 10 Part 1006. The background synchronization circuit system 1102 can prioritize copies of dirty content cached in the first cache.

[0218] exist Figure 12 In the process, repeat operations 1204 to 1208 until the cache system 200 determines that the current execution type has changed to the speculative type.

[0219] Optionally, the background synchronization circuitry 1102 is configured to continue copying the contents cached in the first cache to the second cache in operation 1210 to complete the synchronization of at least dirty contents from the first cache to the second cache, and then in operation 1212 to allow the cache system to service memory requests from the processor using the second cache during speculative execution.

[0220] Optionally, the background synchronization circuit system 1102 can continue to operate synchronously, while the cache system uses a second cache to serve memory requests from the processor during speculative execution in operation 1212.

[0221] At operation 1214, the cache system determines whether the current execution type has changed to non-speculated. If the current execution type remains speculative, then operations 1210 and 1212 can be repeated.

[0222] In response to determining at operation 1214 that the current execution type has changed to non-speculated, the cache system determines whether to accept the result of speculative execution. The result of speculative execution corresponds to a change in the contents of the cache in the second cache. For example, processor 401 can, via... Figure 4The speculative state signal line 404 described herein or Figure 10 The speculative status signal line 1004 provides an indication of whether the result of speculative execution should be accepted.

[0223] If, in operation 1216, the cache system determines that it will reject the result of speculative execution, then in operation 1222, the cache system may discard the contents of the cache currently cached in the second cache (e.g., by setting the invalidation bit of the cache block in the second cache). Subsequently, in operation 1244, the cache system may maintain the first cache as the primary cache and maintain the second cache as a shadow cache; and in operation 1208, the background synchronization circuit system 1102 may copy the contents of the cache from the first cache to the second cache. When execution remains non-speculative, operations 1204 to 1208 may be repeated.

[0224] If, in operation 1216, the caching system determines that it will accept the result of speculative execution, then the background synchronization circuitry 1102 is configured, in operation 1218, to further copy the contents cached in the first cache to the second cache to complete the synchronization of at least dirty content from the first cache to the second cache before allowing the caching system to reconfigure the first cache as a shadow cache. In operation 1220, the caching system configures the first cache as a shadow cache and the second cache as the primary cache in a manner slightly similar to operation 1202. When the first cache is configured as a shadow cache, the caching system may invalidate its contents and then synchronize the contents cached in the second cache to the first cache in a manner slightly similar to operations 1222, 1224, 1208, and 1204.

[0225] For example, when a dedicated cache with a fixed hardware architecture is used as both the first and second caches, the configurable bits can be changed to configure the first cache as a shadow cache and the second cache as the main cache in operation 1220. Alternatively, when it is possible to... Figures 6 to 10 When the cache set is allocated from the cache set pool to the first cache and the second cache using the method described herein, the cache set initially in the first cache but not affected by speculative execution can be allocated via its associated register (e.g., ...). Figure 6 and 10Registers 612a and 612b described herein are reconfigured to be added to the second cache. The cache set initially in the first cache (but now, given that the contents of the second cache are empty) can be reconfigured as in the new first cache. Optionally, an additional cache set can be allocated from a pool of available cache sets and added to the new first cache. Optionally, some of the cache sets with invalid cache contents can be returned to the pool of available cache sets for future allocation (e.g., for addition to the second cache as a main cache or the first cache as a shadow cache).

[0226] This disclosure has been described in this specification with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications may be made thereto without departing from the broader spirit and scope set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative rather than restrictive sense.

[0227] For example, an embodiment may include a cache system comprising: a first cache; a second cache; a connection to a command bus coupled between the cache system and a processor; a connection to an address bus coupled between the cache system and the processor; a connection to a data bus coupled between the cache system and the processor; a connection to an execution type signal line from the processor identifying the execution type; and logic circuitry coupled to control the first and second caches according to the execution type. In such embodiments, the cache system is configured to be coupled between the processor and a memory system. Furthermore, when the execution type is a first type instructing the processor to perform non-speculated execution of instructions and the first cache is configured to serve commands from the command bus for accessing the memory system, the logic circuitry is configured to copy a portion of the contents cached in the first cache to the second cache.

[0228] In such embodiments, the logic circuitry may be configured to copy portions of the contents cached in the first cache to the second cache independently of the current command received in the command bus.

[0229] Furthermore, when the execution type is a first type instructing the processor to perform non-speculous execution of instructions and the first cache is configured to serve commands from the command bus for accessing the memory system, the logic circuitry can be configured to use a second cache to serve subsequent commands from the command bus in response to a change in the execution type from the first type to a second type instructing the processor to perform speculative execution of instructions. The logic circuitry can also be configured to complete the synchronization of the portion of content from the first cache to the second cache after the execution type changes from the first type to the second type but before serving subsequent commands. The logic circuitry can also be configured to continue the synchronization of the portion of content from the first cache to the second cache while serving subsequent commands.

[0230] In such embodiments, the cache system may further include configurable data bits, and logic circuitry may be further coupled to control a first cache and a second cache based on the configurable data bits. When the configurable data bits are in a first state, the logic circuitry may be configured to: implement commands received from the command bus for accessing the memory system via the first cache when the execution type is a first type; and implement commands received from the command bus for accessing the memory system via the second cache when the execution type is a second type. Furthermore, when the configurable data bits are in a second state, the logic circuitry may be configured to: implement commands received from the command bus for accessing the memory system via the second cache when the execution type is a first type; and implement commands received from the command bus for accessing the memory system via the first cache when the execution type is a second type. When the execution type changes from the second type to the first type, the logic circuitry may also be configured to switch the configurable data bits.

[0231] In such embodiments, the cache system may further include a connection to a speculative status signal line from the processor that identifies the speculative execution status of the processor on instructions. The connection to the speculative status signal line is configured to receive the speculative execution status. The speculative execution status indicates whether the result of the speculative execution will be accepted or rejected. When the execution type changes from a second type to a first type, the logic circuitry may be configured to: switch configurable data bits if the speculative execution status indicates that the result of the speculative execution will be accepted; and maintain the configurable data bits unchanged if the speculative execution status indicates that the result of the speculative execution will be rejected.

[0232] Furthermore, in such embodiments, the first cache and the second cache together comprise: a plurality of cache sets, which include the first cache set and the second cache set; and a plurality of registers respectively associated with the plurality of cache sets, the plurality of registers including a first register associated with the first cache set and a second register associated with the second cache set. In such instances, the logic circuitry may be further coupled to control the plurality of cache sets according to the plurality of registers. Furthermore, when a connection to the address bus receives a memory address from the processor, the logic circuitry may be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches a content stored in a first register or a content stored in a second register. The logic circuitry may also be configured to execute a command received in a connection to the command bus via the first cache set in response to the generated set index matching a content stored in the first register, and to execute the command via the second cache set in response to the generated set index matching a content stored in the second register. Furthermore, in response to determining that the dataset of the memory system associated with the memory address is not currently cached in the cache system, the logic circuitry may be configured to allocate the first cache set for caching the dataset and store the generated set index in the first register.

[0233] Additionally, in embodiments with cache sets, the cache system may further include a connection to an execution type signal line from the processor that identifies the execution type, and further generate a generated set index based on the type identified by the execution type signal line. The generated set index may include a pre-defined bit segment in the memory address and bits representing the type identified by the execution type signal line. Furthermore, when the first and second registers are in a first state, the logic circuitry may be configured to: implement a command received from the command bus for accessing the memory system via the first cache set when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via the second cache set when the execution type is the second type. And, when the first and second registers are in a second state, the logic circuitry is configured to: implement a command received from the command bus for accessing the memory system via another cache set other than the first cache set when the execution type is the first type; and implement a command received from the command bus for accessing the memory system via yet another cache set other than the second cache set when the execution type is the second type.

[0234] In such embodiments with a cache set, each of the plurality of registers can be configured to store a set index. Furthermore, when the execution type changes from a second type to a first type, the logic circuitry can be configured to modify the contents stored in the first register and the contents stored in the second register. Additionally, the first type can be configured to instruct the processor to perform non-speculated execution of instructions, and the second type can be configured to instruct the processor to perform speculative execution of instructions. In such instances, the cache system may further include a connection to a speculative status signal line from the processor that identifies the state of speculative execution of instructions. The connection to the speculative status signal line is configured to receive the state of speculative execution, and the state of speculative execution indicates whether the result of speculative execution will be accepted or rejected. When the execution type changes from the second type to the first type, the logic circuitry can be configured to: modify the contents stored in the first register and the contents stored in the second register if the state of speculative execution indicates that the result of speculative execution will be accepted; and maintain the contents stored in the first register and the contents stored in the second register without modification if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0235] Furthermore, for example, embodiments may include a cache system that typically includes multiple cache sets and multiple registers associated with each of the multiple cache sets. The multiple cache sets include a first cache set and a second cache set, and the multiple registers include a first register associated with the first cache set and a second register associated with the second cache set. Similarly, in such embodiments, the cache system may include connections to a command bus coupled between the cache system and the processor, connections to an address bus coupled between the cache system and the processor, connections to a data bus coupled between the cache system and the processor, connections to an execution type signal line from the processor identifying the execution type, and logic circuitry coupled to control the multiple cache sets according to the execution type. The cache system may also be configured to be coupled between the processor and a memory system. Furthermore, when the execution type is a first type instructing the processor to perform non-speculated execution of instructions and the first cache set is configured to serve commands from the command bus for accessing the memory system, the logic circuitry may be configured to copy a portion of the contents cached in the first cache set to the second cache set.

[0236] In such embodiments with cache sets, the logic circuitry can be configured to copy portions of the contents cached in a first cache set to a second cache set independently of the current command received on the command bus. When the execution type is a first type instructing the processor to perform non-speculative execution of an instruction and the first cache set is configured to serve commands from the command bus for accessing the memory system, the logic circuitry can be configured to use the second cache set to serve subsequent commands from the command bus in response to a change in the execution type from the first type to a second type instructing the processor to perform speculative execution of an instruction. The logic circuitry can also be configured to complete the synchronization of portions of the contents from the first cache set to the second cache set after the execution type changes from the first type to the second type but before serving subsequent commands. The logic circuitry can also be configured to continue the synchronization of portions of the contents from the first cache set to the second cache set while serving subsequent commands.

[0237] Furthermore, in such embodiments with cache sets, the logic circuitry can be further coupled to control multiple cache sets based on multiple registers. When a connection to the address bus receives a memory address from the processor, the logic circuitry can be configured to: generate a set index from at least the memory address; and determine whether the generated set index matches the content stored in a first register or the content stored in a second register. The logic circuitry can also be configured to execute a command received in the connection to the command bus via a first cache set in response to the generated set index matching the content stored in the first register, and to execute the command via a second cache set in response to the generated set index matching the content stored in the second register. Furthermore, in response to determining that the dataset of the memory system associated with the memory address is not currently cached in the cache system, the logic circuitry can be configured to allocate a first cache set for caching the dataset and store the generated set index in a first register.

[0238] Furthermore, in such embodiments with cache sets, the cache system may further include a connection to an execution type signal line from the processor that identifies the execution type, and may further generate a generated set index based on the type identified by the execution type signal line. The generated set index may include a pre-bit segment in the memory address and bits representing the type identified by the execution type signal line. When the first and second registers are in a first state, the logic circuitry may be configured to: when the execution type is the first type, implement a command received from the command bus for accessing the memory system via the first cache set; and when the execution type is the second type, implement a command received from the command bus for accessing the memory system via the second cache set. And, when the first and second registers are in a second state, the logic circuitry may be configured to: when the execution type is the first type, implement a command received from the command bus for accessing the memory system via another cache set among the plurality of cache sets other than the first cache set; and when the execution type is the second type, implement a command received from the command bus for accessing the memory system via yet another cache set among the plurality of cache sets other than the second cache set.

[0239] In such embodiments with a cache set, each of the plurality of registers is configured to store a set index, and when the execution type changes from a second type to a first type, the logic circuitry can be configured to modify the contents stored in the first register and the contents stored in the second register. Furthermore, the first type can be configured to instruct the processor to perform non-speculative execution of instructions, and the second type is configured to instruct the processor to perform speculative execution of instructions.

[0240] In such embodiments with a cache set, the cache system may further include a connection to a speculative status signal line from the processor that identifies the state of speculative execution of instructions by the processor. The connection to the speculative status signal line is configured to receive the state of speculative execution, and the state of speculative execution indicates whether the result of speculative execution will be accepted or rejected. When the execution type changes from a second type to a first type, the logic circuitry may be configured to: modify the contents of a first register and a second register if the state of speculative execution indicates that the result of speculative execution will be accepted; and maintain the contents of the first register and the second register without modification if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0241] Furthermore, in such embodiments with a cache set, the cache set can be partitioned among multiple caches within the caching system. For example, the cache set can be partitioned among first and second caches among multiple caches.

[0242] Figure 13 , 14A 14B, 14C, 15A, 15B, 15C and 15D illustrate embodiments of the present disclosure having a set of spare caches (e.g., see illustrations). Figure 14A and 15A A caching system that uses a spare cache set 1310d in the cache to accelerate speculative execution, and interchangeable cache sets (e.g., see cache sets 1310a, 1310b, 1310c, and 1310d) (e.g., see the caching system shown in the diagram). Figure 13 The instance aspect of the instance computing device of the cache system 1000 in the middle.

[0243] In addition to using a shadow cache to ensure speculative execution and to synchronize content between the main cache and the shadow cache to preserve content cached in the main cache for acceptance in the shadow cache, a spare cache set can also be used to accelerate speculative execution (e.g., see...). Figure 14A and 15A The spare cache set 1310d described in the document, and such as Figure 15B and 15C The cache set 1310b described in the document and such Figure 15D The cache set described in [reference 1310c] can also be used to accelerate speculative execution without using a shadow cache. Data stored in the cache set used as a shadow cache is verifiable and therefore used for normal execution (see, for example, [reference 1310c]). Figure 14A and 15A The cache set 1310c described in the document, and such as Figure 15B and 15C The cache set 1310d described in the document and such Figure 15D The cache set 1310b described herein, each of which is a cache set available for speculative execution and is a shadow cache, and subsequently available for normal execution after content verification. Furthermore, some cache sets are used as the main cache for normal or non-speculative execution (e.g., see...). Figure 14A and 15A The cache set 1310b described in the document, and such as Figure 15B and 15C The cache set 1310c described in the document and such Figure 15D The cache set (1310d) described in the document may not be ready to be used as a shadow cache for speculative execution. Therefore, one or more cache sets may be used as backup cache sets to avoid the latency of waiting for the availability of cache sets (e.g., see see below). Figure 14A and 15AThe spare cache set 1310d described in the document, and such as Figure 15B and 15C The cache set 1310b described in the document and such Figure 15D The cache set described in the document is 1310c.

[0244] Once the speculation is confirmed, the contents of the cache set used as the shadow cache are confirmed to be valid and up-to-date; and therefore, the previous cache set used as the shadow cache for speculative execution is used for normal execution. For example, see... Figure 14A and 15A The cache set 1310c described in the document, and such as Figure 15B and 15C The cache set 1310d described in the document and such Figure 15D The cache set 1310b described herein, each of which is a set of caches available for speculative execution and serving as a shadow cache, and subsequently available for normal execution after content verification. However, some of the cache sets initially used as normal caches may not be ready for subsequent speculative execution. For example, see, Figure 14A and 15A The cache set 1310b described in the document, and such as Figure 15B and 15C The cache set 1310c described in the document and such Figure 15D The cache set 1310d described in the document, each of which serves as a portion of the normal cache but may not be ready for subsequent speculative execution. Therefore, one or more cache sets can be used as backup cache sets to avoid delays while waiting for cache set availability and to accelerate speculative execution. For example, see, Figure 14A and 15A The spare cache set 1310d described in the document, and such as Figure 15B and 15C The cache set 1310b described in the document and such Figure 15D The cache set 1310c described in the document, each of which is used as a spare cache set.

[0245] In some embodiments, when the cache system has a background synchronization circuitry (e.g., see background synchronization circuitry 1102), if synchronization from the cache set in the normal cache to the corresponding cache set in the shadow cache has not yet been completed (e.g., see illustrated in...), Figure 11AIf synchronization (1130) fails, the cache set in the normal cache cannot be immediately released for use in the next speculative execution. In this case, if no spare cache set exists, the next speculative execution must wait until synchronization is complete so that the corresponding cache set in the normal cache can be released. This is just one example of a situation where a spare cache set is beneficial. There are many other situations where the cache set in the normal cache cannot be released immediately.

[0246] Furthermore, for example, speculative execution reference memory systems (e.g., see...) Figure 6 , 10 The memory regions in the memory system 603 (in 13) that do not overlap with the memory regions in the cache set used in the normal cache. Because of the result of speculative execution, the cache sets in both the shadow cache and the normal cache are now entirely in the normal cache. This can also cause latency, as the cache system spends time freeing up cache sets to support the next speculative execution. To free up a cache set, the cache system needs to identify the cache set, such as the least used cache set, and synchronize the cache set with the memory system. If the cache has data newer than the memory system, then the data needs to be written to the memory system.

[0247] Additionally, use a spare cache set (e.g., see...) Figure 14A and 15A The spare cache set 1310d described in the document, and such as Figure 15B and 15C The cache set 1310b described in the document and such Figure 15D The system of cache set 1310c described herein can also use a background synchronization circuit system (e.g., background synchronization circuit system 1102). When the initial prediction is confirmed, the cache set used in the initial prediction can be swapped (e.g., see see below). Figure 14A and 15A The cache set 1310c described in the document is added to the cache set used for main execution (for example, see...). Figure 14A As shown in B and C, and as Figure 15A The cache set 1310a described in B, C, and D is a cache set of sets in the cache set used for main execution or non-speculated execution. Instead, a cache set from the previous main execution that was being used in the case of speculative failure is used (e.g., see see...). Figure 14A and 15A The cache set 1310b described in the document, and such as Figure 15B and 15CThe cache set 1310c described in the document and such Figure 15D The cache set described in document 1310d can immediately make the spare cache set available for the next speculative execution (e.g., see see below). Figure 14A and 15A The spare cache set 1310d described in the document, and such as Figure 15B and 15C The cache set 1310b described in the document and such Figure 15D The cache set 1310c described herein can be updated, for example, via a background synchronization circuit system 1102 for the next speculative execution. Furthermore, due to background synchronization, the cache set currently used for speculative execution (e.g., as described above) is updated. Figure 14A and 15A The cache set 1310c shown in the document is ready to be accepted for use during normal execution, as is the alternative cache set (e.g., such as...). Figure 14A and 15A The spare cache set 1310d shown in the diagram is ready for use. In this way, there is no delay while waiting for the next cache set to be used for the next speculative execution. To prepare for the next speculative execution, the spare cache set (e.g., such as...) can be... Figure 14A and 15A The cache set 1310c shown in the document is synchronized to the normal cache set that is likely to be used for the next speculative execution (e.g., such as...). Figure 14A and 15A The cache set shown in the document (1310b) or the least used cache set in the system.

[0248] Figure 13 Example aspects of an instance computing device having an instance computing device according to some embodiments of the present disclosure, having a cache system 1000 with interchangeable cache sets (e.g., see cache sets 1310a, 1310b, 1310c and 1310d) including a spare cache set to accelerate speculative execution. Figure 13 The computing device in it is similar to Figure 10 The computing device depicted in [the document]. For example, shown in [the document]. Figure 13 The device includes a processor 1001, a memory system 603, a cache system 1000, and connections 604a to 604d and 608a to 608c, as well as connection 1002.

[0249] exist Figure 13In the diagram, cache system 1000 is shown having cache sets (e.g., cache sets 1310a, 1310b, 1310c, and 1310d). Cache system 1000 is also shown having a connection 604d to an execution type signal line 605d from processor 1001 that identifies the execution type, and a connection 1002 to a signal line 1004 from processor 1001 that identifies the state of speculative execution.

[0250] The cache system 1000 is also shown to include logic circuitry 1006, which is configurable to allocate a first subset of the cache set when the execution type is a first type, instructing the processor 1001 to perform non-specular execution of instructions (e.g., see see below). Figure 13 The cache 602a shown is used for caching during cache operations. The logic circuit 1006 can also be configured to allocate a second subset of the cache set when the execution type changes from a first type to a second type instructing the processor to perform speculative execution of instructions (e.g., see see below). Figure 13 The cache 602b shown is used for caching in cache operations. The logic circuit 1006 can also be configured to retain at least one cache set or a third subset of the cache set when the execution type is second (e.g., see see below). Figure 13 The cache 602c shown in the document.

[0251] Logic circuit 1006 can also be configured to reconfigure the second subset when the execution type is the first type and when the execution type changes from the second type to the first type and the state indication of speculative execution will accept the result of speculative execution (for example, see...). Figure 13 The cache 602b shown is used for caching in cache operations. Furthermore, the logic circuit 1006 can also be configured to allocate at least one cache set or a third subset (e.g., see see below) when the execution type changes from a first type to a second type and when the execution type changes from a second type to a first type and the state indication of the speculative execution will accept the result of the speculative execution. Figure 13 The cache 602c shown is used for caching during cache operations. The logic circuit 1006 can also be configured to retain at least one cache set or a third subset (e.g., see [reference needed]) when the execution type is the second type and when at least one cache set is the least used cache set among multiple cache sets. Figure 13 The cache 602c shown in the document.

[0252] In some embodiments, the cache system may include one or more mapping tables that can map the cache sets mentioned herein. Furthermore, in such embodiments, logic circuitry, such as the logic circuitry mentioned herein, may be configured to allocate and reconfigure subsets of the cache sets, such as caches in the cache system, according to one or more mapping tables. The mapping may be an alternative to or other than the cache set registers described herein.

[0253] In some embodiments, such as at least Figure 13 , 14A As shown in 14C and 15A to 15D, cache system 1000 may include cache set registers (e.g., see cache set registers 1312a, 1312b, 1312c, and 1312d) respectively associated with cache sets (e.g., see cache set registers 1310a, 1310b, 1310c, and 1310d). In such embodiments, logic circuitry 1006 may be configured to allocate and reconfigure subsets of the cache sets according to the cache set registers (e.g., see see...). Figure 13 The caches shown are 602a, 602b, and 602c.

[0254] Furthermore, in some embodiments, such as Figures 15A to 15D As shown, a first subset of the cache set may contain a first cache set, a second subset of the cache set may contain a second cache set, and a third subset may contain a third cache set. In such embodiments, a cache set register may include a first cache set register associated with the first cache set, the first cache set register being configured to initially store an index of the first cache set such that the first cache set is used for non-speculated execution (e.g., see see below). Figure 15A The cache set index 1504b shown is stored in cache set register 1312b. The cache set register may also include a second cache set register associated with the second cache set, the second cache set register being configured to initially store the second cache set index so that the second cache set is used for speculative execution (e.g., see see below). Figure 15A The cache set index 1504c shown is stored in the cache set register 1312c. The cache set register may also include a third cache set register associated with a third cache set, which is configured to initially store the third cache set index such that the third cache set is used as a backup cache set (e.g., see see below). Figure 15A The cache set index 1504d shown is stored in cache set register 1312d.

[0255] Furthermore, in such embodiments, logic circuitry 1006 may be configured to generate set indexes (e.g., see set indexes 1504a, 1504b, 1504c, and 1504d) based on a memory address received from the address bus 605b of processor 1001 and an identification of speculative or non-speculative execution received from the execution type signal line 605d of the processor. Additionally, logic circuitry 1006 may be configured to determine whether the set indexes match the contents stored in a first cache set register, a second cache set register, or a third cache set register.

[0256] Furthermore, in such embodiments, logic circuitry 1006 may be configured to store a first cache set index in a second cache set register or another cache set register associated with another cache set in a second subset of a plurality of cache sets, such that when the execution type changes from a second type to a first type and the state indication of speculative execution indicates that the result of speculative execution will be accepted, the second cache set or another cache set in the second subset is used for non-speculative execution. For example, see the description of cache set index 1504b stored in the second cache set register 1312c. Figure 15B This allows the second cache set 1310c to be used for non-speculsive execution. Furthermore, the logic circuit 1006 can be configured to store the second cache set index in a third cache set register or another cache set register associated with another cache set in at least one cache set, such that when the execution type changes from the second type to the first type and the state indication of speculative execution indicates that the result of speculative execution will be accepted, the third cache set or another cache set in at least one cache set is used for speculative execution. For example, see the description of cache set index 1504c stored in the third cache set register 1312d. Figure 15B This makes the third cache set 1310d available and usable for speculative execution. The logic circuit 1006 can also be configured to store the third cache set index in a first cache set register or another cache set register associated with another cache set in a first subset of the plurality of cache sets, such that when the execution type changes from the second type to the first type and the status indication of speculative execution indicates that the result of speculative execution will be accepted, the first cache set or the other cache set in the first subset serves as a backup cache set. For example, see the description of cache set index 1504d stored in the first cache set register 1312b. Figure 15B This allows the first cache set 1310b to be used as a backup cache set.

[0257] Figure 14A , 14B 14C illustrates some embodiments of this disclosure having a set of spare caches (e.g., see as...). Figure 14A and 14B The alternative cache set 1310d shown in the document and such Figure 14C The instance aspect of the caching system 1000, which uses the spare cache set 1310b shown in the diagram to accelerate the execution of speculative execution, is an instance aspect of the computing device. Specifically, Figure 14A The cache sets in the first state are shown. In the first state, cache sets 1310a and 1310b can be used for non-speculated execution, cache set 1310c can be used for speculative execution, and cache set 1310d is used as a spare cache set. Figure 14B The cache sets in the second state are shown, in which cache sets 1310a, 1310b and 1310c are available for non-speculated execution, and cache set 1310c is available for and can be used for speculative execution. Figure 14C The cache sets in the third state are shown, in which cache sets 1310a and 1310c can be used for non-speculated execution, cache set 1310d can be used for speculative execution, and cache set 1310b is used as a spare cache set.

[0258] Figure 15A , 15B 15C and 15D each illustrate an instance aspect of an instance computing device having an instance computing device according to some embodiments of the present disclosure having an interchangeable cache set (e.g., see cache sets 1310a, 1310b, 1310c and 1310d) that includes a spare cache set to accelerate speculative execution.

[0259] Specifically, Figure 15A The cache sets in the first state are shown. In this first state, cache sets 1310a and 1310b can be used for non-speculated execution (or execution of the first type), cache set 1310c can be used for speculative execution (or execution of the second type), and cache set 1310d is used as a spare cache set. Figure 15AAs shown, in this first state, logic circuit 1006 can be configured to store cache set index 1504b in cache set register 1312b, such that the content 1502b in cache set 1310b is used for non-speculsive execution. Additionally, in this first state, logic circuit 1006 can be configured to store cache set index 1504c in cache set register 1312c, such that cache set 1310c is available and can be used for speculative execution. Logic circuit 1006 can also be configured to store cache set index 1504d in cache set register 1312d, such that cache set 1310d is used as a spare cache set in this first state.

[0260] Figure 15B The cache sets in the second state are shown. In the second state, cache sets 1310a and 1310c can be used for non-speculated execution, cache set 1310d can be used for speculative execution, and cache set 1310b is used as a spare cache set. Figure 15B The second state described occurs when the execution type changes from type two to type one and the state indication of speculative execution is that it will accept the result of speculative execution. For example... Figure 15B As shown, in this second state, logic circuit 1006 can be configured to store cache set index 1504b in cache set register 1312c, such that the content 1502b in cache set 1310c is used for non-speculsive execution. Additionally, in this second state, logic circuit 1006 can be configured to store cache set index 1504c in cache set register 1312d, such that cache set 1310d is available for speculative execution. Logic circuit 1006 can also be configured to store cache set index 1504d in cache set register 1312b, such that cache set 1310b is used as a spare cache set in this second state.

[0261] Figure 15C The primary focus is on the cache sets in the second state, where cache sets 1310a and 1310c are available for non-speculated execution, and cache set 1310b is used as a backup cache set. However... Figure 15C The example shows that cache set 1310d is being used for speculative execution rather than just for what is available. Figure 15C As shown, in this second state, logic circuit 1006 can be configured to store cache set index 1504c in cache set register 1312d, so that the contents 1502c stored in cache set 1310d can also be used for speculative execution.

[0262] Figure 15DThe cache sets in the third state are shown, in which cache sets 1310a and 1310d are available for non-speculated execution, cache set 1310b is available for speculative execution, and cache set 1310c is used as a spare cache set. In subsequent loops following the second state, Figure 15D The third state described occurs when the execution type changes back from the second type to the first type and the state indication of speculative execution will accept the result of speculative execution. For example... Figure 15D As shown, in this third state, logic circuit 1006 can be configured to store cache set index 1504b in cache set register 1312d, such that the content 1502b in cache set 1310d is used for non-speculsive execution. Additionally, in this third state, logic circuit 1006 can be configured to store cache set index 1504c in cache set register 1312b, such that cache set 1310b is available for speculative execution. Logic circuit 1006 can also be configured to store cache set index 1504d in cache set register 1312c, such that cache set 1310c is used as a spare cache set in this third state.

[0263] As by Figures 15A to 15D As shown, the cache sets are interchangeable and the cache sets used as backup cache sets are also interchangeable.

[0264] In such embodiments, when connection 604b to address bus 605b receives a memory address from processor 1001, logic circuitry 1006 may be configured to generate a set index from at least memory address 102b based on this cache set index 112b of the address (e.g., see set indexes generating set indices 1504a, 1504b, 1504c, and 1504d, respectively, resulting in set indices 1506a, 1506b, 1506c, and 1506d). Furthermore, when connection 604b to address bus 605b receives a memory address from processor 1001, logic circuitry 1006 may be configured to determine whether the generated set index matches the contents stored in one of the registers (which may be the stored set indexes 1504a, 1504b, 1504c, or 1504d). Furthermore, logic circuit 1006 can be configured to execute commands received in connection 604a with command bus 605a via cache set in response to a match between the generated set index and the content stored in the corresponding register. Additionally, in response to determining that the dataset of the memory system associated with the memory address is not currently cached in the cache system, logic circuit 1006 can be configured to allocate a cache set for caching the dataset and store the generated set index in the corresponding register. The generated set index may contain pre-defined segments from the memory address, such as... Figures 15A to 15B As shown in the image.

[0265] Furthermore, in such embodiments, logic circuitry 1006 may be configured to generate set indexes (e.g., see set indexes 1504a, 1504b, 1504c, and 1504d) based on a memory address (e.g., memory address 102b) received from the address bus 605b of processor 1001 and an identification of speculative or non-speculative execution received from the execution type signal line 605d of the processor. Additionally, logic circuitry 1006 may be configured to determine whether the set indexes match the contents stored in cache set registers 1312b, 1312c, or 1312d.

[0266] In some embodiments, the cache system may include multiple cache sets, a connection to an execution type signal line from the processor indicating the execution type, a connection to a signal line from the processor indicating the state of speculative execution, and logic circuitry. The logic circuitry may be configured to: allocate a first subset of the multiple cache sets for caching in cache operations when the execution type is a first type indicating non-speculative execution of instructions by the processor; and allocate a second subset of the multiple cache sets for caching in cache operations when the execution type changes from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuitry may also be configured to retain at least one cache set (or a third subset of the multiple cache sets) when the execution type is the second type. The logic circuitry may also be configured to, when the execution type is the first type, reconfigure the second subset for caching in cache operations when the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, the logic circuit can also be configured to allocate at least one cache set (or a third subset of multiple cache sets) for caching during cache operations when the execution type changes from the first type to the second type, or when the execution type changes from the second type to the first type and the state indication of the speculative execution will accept the result of the speculative execution.

[0267] In such embodiments, the logic circuitry may be configured to retain at least one cache set (or a third subset of multiple cache sets) when the execution type is second and at least one cache set (or a third subset of multiple cache sets) contains the least used cache set among multiple cache sets.

[0268] Furthermore, in such embodiments, the caching system may include one or more mapping tables that map multiple cache sets. In this instance, logic circuitry is configured to allocate and reconfigure subsets of the multiple cache sets according to one or more mapping tables.

[0269] Furthermore, in such embodiments, the caching system may include multiple cache set registers, each associated with a plurality of cache sets. In this example, logic circuitry is configured to allocate and reconfigure subsets of the plurality of cache sets based on the multiple cache set registers. In this example, a first subset of the plurality of cache sets may include a first cache set, a second subset of the plurality of cache sets may include a second cache set, and at least one cache set (or a third subset of the plurality of cache sets) may include a third cache set. Additionally, the multiple cache set registers may include a first cache set register associated with a first cache set, configured to initially store a first cache set index such that the first cache set is used for non-speculated execution. The multiple cache set registers may also include a second cache set register associated with a second cache set, configured to initially store a second cache set index such that the second cache set is used for speculative execution. The multiple cache set registers may also include a third cache set register associated with a third cache set, configured to initially store a third cache set index such that the third cache set is used as a spare cache set.

[0270] In such embodiments, the logic circuitry can be configured to generate a set index based on a memory address received from the processor's address bus and an identification of speculative or non-speculative execution received from the processor's execution type signal line that identifies the execution type. Furthermore, the logic circuitry can be configured to determine whether the set index matches the contents stored in a first cache set register, a second cache set register, or a third cache set register. When the execution type changes from a second type to a first type and the speculative execution status indicates that the result of speculative execution will be accepted, the logic circuitry can also be configured to store the first cache set index in a second cache set register or another cache set register associated with another cache set in a second subset of multiple cache sets, such that the second cache set or another cache set in the second subset is used for non-speculative execution. When the execution type changes from the second type to the first type and the status indication of speculative execution indicates that it will accept the result of speculative execution, the logic circuit can also be configured to store the second cache set index in a third cache set register or another cache set register associated with another cache set (or a third subset of multiple cache sets) in at least one cache set, such that the third cache set or another cache set (or a third subset of multiple cache sets) is used for speculative execution. When the execution type changes from the second type to the first type and the status indication of speculative execution indicates that it will accept the result of speculative execution, the logic circuit can also be configured to store the third cache set index in a first cache set register or another cache set register associated with another cache set in a first subset of multiple cache sets, such that the first cache set or another cache set in a first subset is used as a spare cache set.

[0271] In some embodiments, the cache system may include multiple cache sets having a first subset of cache sets, a second subset of cache sets, and a third subset of cache sets. The cache system may also include connections to an execution type signal line from the processor identifying the execution type, connections to a signal line from the processor identifying the state of speculative execution, and logic circuitry. The logic circuitry may be configured to: allocate the first subset of the multiple cache sets for caching in cache operations when the execution type is a first type indicating non-speculative execution of instructions by the processor; and allocate the second subset of the multiple cache sets for caching in cache operations when the execution type changes from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuitry may also be configured to retain the third subset of the multiple cache sets when the execution type is the second type. The logic circuitry may also be configured to reconfigure the second subset for caching in cache operations when the execution type is the first type, and when the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted. The logic circuit can also be configured to allocate a third subset for caching in cache operations when the execution type changes from the first type to the second type, or when the execution type changes from the second type to the first type and the state indication of speculative execution will accept the result of speculative execution.

[0272] In some embodiments, the cache system may include multiple caches, including a first cache, a second cache, and a third cache. The cache system may also include connections to an execution type signal line from the processor indicating the execution type, connections to a signal line from the processor indicating the state of speculative execution, and logic circuitry. The logic circuitry may be configured to: allocate the first cache for caching in cache operations when the execution type is a first type indicating non-speculative execution of instructions by the processor; and allocate the second cache for caching in cache operations when the execution type changes from the first type to a second type indicating speculative execution of instructions by the processor. The logic circuitry may also be configured to retain the third cache when the execution type is the second type. The logic circuitry may also be configured to reconfigure the second cache for caching in cache operations when the execution type is the first type, and when the execution type changes from the second type to the first type and the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, the logic circuitry may also be configured to allocate the third cache for caching in cache operations when the execution type changes from the first type to the second type.

[0273] Figure 16 and 17Example aspects of an instance computing device are shown, according to some embodiments of the present disclosure, having interchangeable cache sets (e.g., see cache sets 1610a, 1610b, 1710a, and 1710b) with extended tags (e.g., see extended tags 1640a, 1640b, 1740a, and 1740b) that utilize different types of execution (e.g., speculative and non-speculative execution) performed by the processor. Furthermore, Figure 16 and 17 Explain the addressing cache system (e.g.) Figure 6 , 10 Different ways of selecting cache sets and cache blocks within cache systems 600 and 1000 (described in Figures 1 and 13, respectively) are shown. Furthermore, ways of selecting cache sets and cache blocks via memory addresses such as (shown in Figure 1) memory addresses 102e or 102b and memory addresses 102a, 102c, or 102d are also shown.

[0274] Figure 16 and 17 The two instances in the example use set association, and set association can be used to implement caching systems, such as caching systems 600 and 1000. Figure 16 In this context, set associativity is implicitly defined (e.g., through algorithms that can be used to determine which tag should be in which cache set for a given execution type). Figure 17 In this context, set association is implemented via bits in the cache set index within the memory address. Furthermore, Figure 16 and 17 The functionality described herein can be implemented without using set associations (although this is not depicted), for example, by showing them separately in Figure 2 and 4 The cache system is implemented in 200 and 400.

[0275] exist Figure 16 and 17In this context, block indices (e.g., see block indices 106e and 106b) can be used as addresses within individual cache sets (e.g., see cache sets 1610a, 1610b, 1710a, and 1710b) to identify specific cache blocks within the cache set (e.g., see cache blocks 1624a, 1624b, 1628a, 1628b, 1724a, 1724b, 1728a, and 1728b). Furthermore, extension tags (e.g., extension tags 1640a, 1640b, 1740a, 1740b, 1650, and 1750) can be used as addresses for the cache sets. The block indexes of memory addresses (e.g., see memory addresses 102e and 102b) (e.g., see block indices 106e and 106b) can be used for each cache set (e.g., see cache sets 1610a, 1610b, 1710a and 1710b) to obtain cache blocks (e.g., see cache blocks 1624a, 1624b, 1628a, 1628b, 1724a, 1724b, 1728a and 1728b) and the tags associated with the cache blocks (e.g., see corresponding tags 1622a, 1622b, 1626a, 1626b, 1722a, 1722b, 1726a and 1726b).

[0276] In addition, such as Figure 16 and 17 As shown, tag comparison circuitry (e.g., tag comparison circuitry 1660a, 1660b, 1760a, and 1760b) can compare extended tags generated by the cache sets (e.g., extended tags 1640a, 1640b, 1740a, and 1740b) with extended cache tags (e.g., extended tag 1650) from memory addresses (e.g., see memory addresses 102e and 102b) and the current execution type (e.g., see execution types 110e and 110b) to determine a cache hit or miss. The construction of the extended tags ensures that at most one hit exists within the cache sets (e.g., see cache sets 1610a, 1610b, 1710a, and 1710b). If a cache hit occurs, the output is provided from the selected cache set (e.g., see cache blocks 1624a, 1624b, 1628a, 1628b, 1724a, 1724b, 1728a, and 1728b). Otherwise, the data associated with the memory address (e.g., memory address 102e or 102b) is neither cached in nor output from any of the cache sets. In short, Figure 16 and 17 The extended labels described are used to select a cache set, and the block index is used to select a cache block and its label within the cache set.

[0277] In addition, such as Figure 16 and 17 As shown, memory addresses are segmented in different ways (e.g., see addresses 102e and 102b); and therefore, the control of cache operations differs depending on the address. However, some similarities exist. For example, as shown in Figure 16 and 17 The system uses cache sets via set-associative control. Control of cache operations may include controlling whether the cache set is used for a first or second type of execution performed by the processor (e.g., non-speculating and speculative execution), and this control may be partially or entirely via set-associative control.

[0278] exist Figure 16 In the example, the extended tag 1650 for memory address 102e has execution type 110e and tag 104e, wherein tag 104e has a cache set indicator that implements set association. Figure 17 In this example, the extended tag 1750 for memory address 102b has an execution type 110e, a cache set index 112b, and a tag 104b. In this instance, the cache set index 112b implements set associativity instead of the cache set indicator in the tag. Different partitions of the memory address slightly alter how the extended tags (e.g., extended tags 1640a, 1640b, 1650, 1740a, 1740b, and 1750) control cache operations via set associativity.

[0279] Using memory address segmentation, in this example, extended tags from memory addresses and execution types (e.g., see extended tags 1650 and 1750) are compared with extended tags for cache sets (e.g., see extended tags 1640a, 1640b, 1740a, and 1740b) to control cache operations implemented via the cache sets. Depending on whether the extended tags input to the comparison circuit match or do not match, the tag comparison circuit (e.g., tag comparison circuits 1660a, 1660b, 1760a, and 1760b) can output a hit or miss. The extension tags used for cache sets (e.g., see extension tags 1640a, 1640b, 1740a, and 1740b) may originate from execution types (e.g., see execution types 1632a, 1632b, 1732a, and 1732b) stored in registers (e.g., see registers 1612a, 1612b, 1712a, and 1712b) and block tags (e.g., see tags 1622a, 1622b, 1626a, 1626b, 1722a, 1722b, 1726a, and 1726b) from the first cache set (e.g., see cache sets 1610a, 1610b, 1710a, and 1710b). Furthermore, as... Figure 16 and 17 As shown, the execution type differs in each register of the cache set. For the example shown, a first cache set (e.g., cache set 1610a or 1710a) can be used for the first type of execution (e.g., non-speculated execution), and a second cache set (e.g., cache set 1610b or 1710b) can be used for the second type of execution (e.g., speculative execution).

[0280] exist Figure 17 In the middle, the combination of tag 104b and cache set index 112b is provided and displayed. Figure 16 Similar functionality to label 104e. However, in Figure 17 In this context, by separating tag 104b from cache set index 112b, the cache set does not need to store a redundant copy of cache set index 112b. This is because the cache set (e.g., see cache sets 1710a and 1710b) can be associated with cache set registers (e.g., see registers 1712a and 1712b) to store cache set indices (e.g., see cache set indices 1732a and 1732b). However, in Figure 16In this context, cache sets (e.g., see cache sets 1610a and 1610b) do require redundant copies of cache set indicators to be stored in each of their blocks (e.g., see blocks 1624a, 1624b, 1628a, and 1628b) because the associated registers of the cache sets are not configured to store cache set indices.

[0281] In other words, since tags 1622a, 1622b, etc., have the same cache set indicator, the indicator can be stored only once in the registers used for the cache set (e.g., see cache set registers 1712a and 1712b). This is Figure 17 The arrangement described in the text is superior. Figure 16 One of the benefits of the arrangement described herein. Furthermore, Figure 17 The lengths of labels 1722a, 1722b, 1726a, and 1726b in the text are related to the display. Figure 16 The implementations of the labels in the document (e.g., see 1622a, 1622b, 1626a, and 1626b) are shorter because... Figure 17 The cache set registers (e.g., registers 1712a and 1712b) depicted in the document store both the cache set index and the execution type.

[0282] When the execution type is combined with a cache set index to form an extended cache set index, the extended cache set index can be used to select one of the cache sets. The tag from the selected cache set is then compared with the tag in the address to determine a hit or miss. This two-step selection can be similar to a regular two-step selection using a cache set index, or it can be combined with extended tags to support more efficient interchangeability of cache sets for different execution types (e.g., speculative and non-speculative execution types).

[0283] In some embodiments, a cache system (e.g., cache system 600 or 1000) may include multiple cache sets (e.g., cache sets 610a to 610c, 1010a to 1010c, 1310a to 1310d, 1610a to 1610b, or 1710a to 1710b). The multiple cache sets may include a first cache set and a second cache set (e.g., see cache sets 1610a to 1610b and set 1710a to 1710b). The cache system may also include multiple registers (e.g., registers 612a to 612c, 1012a to 1012c, 1312a to 1312d, 1612a to 1612b, or 1712a to 1712b) respectively associated with the multiple cache sets. Multiple registers may include a first register associated with a first cache set and a second register associated with a second cache set (e.g., see registers 1612a to 1612b and registers 1712a to 1712b).

[0284] The cache system may also include a connection (e.g., see connection 604a) to a command bus (e.g., see command bus 605a) coupled between the cache system and the processor (e.g., see processors 601 and 1001). The cache system may also include a connection (e.g., see address bus 605b) coupled between the cache system and the processor.

[0285] The cache system may also include logic circuitry coupled to the processor to control multiple cache sets according to multiple registers (e.g., see logic circuitry 606 and 1006). When the connection to the address bus receives memory addresses from the processor (e.g., see memory addresses 102a to 102e shown in Figure 1 and respectively shown in…),… Figure 16 and 17 When addresses 102e and 102b in the memory address are received, the logic circuitry can be configured to generate extended tags (e.g., see extended tags 1650 and 1750) from at least the memory address. Furthermore, when the connection to the address bus receives a memory address from the processor, the logic circuitry can be configured to determine whether the generated extended tag (e.g., see extended tags 1650 and 1750) matches a first extended tag (e.g., see extended tags 1640a and 1740a) for a first cache set (e.g., see cache sets 1610a and 1710a) or a second extended tag (e.g., see extended tags 1640b and 1740b) for a second cache set (e.g., see cache sets 1610b and 1710b).

[0286] The logic circuitry (e.g., see logic circuitry 606 and 1006) may also be configured to implement, via a first cache set (e.g., see cache sets 1610a and 1710a), a command received in a connection (e.g., see connection 604a) to a command bus (e.g., see command bus 605a) in response to a generated extended tag (e.g., see command bus 605a) matching a first extended tag (e.g., see command bus 605a), and via a second cache set (e.g., see command bus 604a) in response to a generated extended tag matching a second extended tag (e.g., see command bus 605a) matching a second extended tag (e.g., see command bus 605a and 1710b).

[0287] The logic circuits (e.g., see logic circuits 606 and 1006) may also be configured to generate a first extended tag (e.g., see extended tags 1640a and 1740a) from cache addresses of a first cache set (e.g., see cache sets 1610a and 1710a) (e.g., see blocks marked 'tag' in extended tags 1640a and 1740a, and tags 1622a, 1622b, 1722a, 1722b, etc.) and contents stored in a first register (e.g., see registers 1612a and 1712a) (e.g., see blocks marked 'execution type' in extended tags 1640a and 1740a and blocks marked 'cache set index' in extended tag 1740a, and execution type 1632a and cache set index 1732a). The logic circuit can also be configured to generate a second extended tag (e.g., see extended tags 1610b and 1710b) from cache addresses of a second cache set (e.g., see blocks marked 'tag' in extended tags 1640b and 1740b, and tags 1626a, 1626b, 1726a, 1726b, etc.) and contents stored in a second register (e.g., see registers 1612b and 1712b) (e.g., see blocks marked 'execution type' in extended tags 1640b and 1740b and blocks marked 'cache set index' in extended tag 1740b, and execution type 1632b and cache set index 1732b).

[0288] In some embodiments, a cache system (e.g., cache system 600 or 1000) may further include a connection (e.g., see connection 604d) to an execution type signal line (e.g., see execution type signal line 605d) from a processor (e.g., see processors 601 and 1001) that identifies the execution type. In such embodiments, logic circuitry (e.g., see logic circuitry 606 and 1006) may be configured to access memory addresses (e.g., see the addresses shown respectively in the diagrams). Figure 16 and 17 The memory addresses 102e and 102b in the diagram) and the execution type identified by the execution type signal line (see, for example, the diagram shown in the diagram). Figure 16 and 17 The execution type 110e generates an extended label (e.g., see extended labels 1650 and 1750). Furthermore, in such embodiments, the contents stored in each of the first and second registers (e.g., see registers 1612a, 1612b, 1712a, and 1712b) may contain an execution type (e.g., see first execution type 1632a and second execution type 1632b).

[0289] In some embodiments, to determine whether a generated extended tag (e.g., see extended tags 1650 and 1750) matches a first extended tag (e.g., see extended tags 1640a and 1740a) for a first cache set or a second extended tag (e.g., see extended tags 1640b and 1740b) for a second cache set, logic circuitry (e.g., see logic circuitry 606 and 1006) may be configured to compare the first extended tag (e.g., see extended tags 1640a and 1740a) with the generated extended tag (e.g., see extended tags 1650 and 1750) to determine a cache hit or miss for the first cache set (e.g., see cache sets 1610a and 1710a). Specifically, as Figure 16 and 17 As shown, a first tag comparison circuit (e.g., see tag comparison circuits 1660a and 1760a) is configured to receive a first extended tag (e.g., see extended tags 1640a and 1740a) and a generated extended tag (e.g., see extended tags 1650 and 1750) as inputs. The first tag comparison circuit (e.g., see tag comparison circuits 1660a and 1760a) is also configured to compare the first extended tag with the generated extended tag to determine a cache hit or miss for a first cache set. The first tag comparison circuit (e.g., see tag comparison circuits 1660a and 1760a) is also configured to output the determined cache hit or miss for the first cache set (e.g., see outputs 1662a and 1762a).

[0290] Furthermore, to determine whether the generated extension tag matches a first extension tag for a first cache set or a second extension tag for a second cache set, logic circuitry may be configured to compare the second extension tag (e.g., see extension tags 1640b and 1740b) with the generated extension tag (e.g., see extension tags 1650 and 1750) to determine a cache hit or miss for the second cache set (e.g., see cache sets 1610b and 1710b). Specifically, as Figure 16 and 17 As shown, the second tag comparison circuit (e.g., see tag comparison circuits 1660b and 1760b) is configured to receive a second extended tag (e.g., see extended tags 1640b and 1740b) and a generated extended tag (e.g., see extended tags 1650 and 1750) as inputs. The second tag comparison circuit (e.g., see tag comparison circuits 1660b and 1760b) is also configured to compare the second extended tag with the generated extended tag to determine a cache hit or miss for the second cache set. The second tag comparison circuit (e.g., see tag comparison circuits 1660b and 1760b) is also configured to output the determined cache hit or miss for the second cache set (e.g., see outputs 1662b and 1762b).

[0291] In some embodiments, the logic circuitry (e.g., see logic circuitry 606 and 1006) may be further configured to receive output from a first cache set (e.g., see cache sets 1610a and 1710a) when the logic circuitry determines that the generated extended tag (e.g., see extended tags 1640a and 1740a) matches a first extended tag (e.g., see extended tags 1640a and 1740a) for a first cache set. The logic circuitry may also be further configured to receive output from a second cache set (e.g., see cache sets 1610b and 1710b) when the logic circuitry determines that the generated extended tag (e.g., see cache sets 1610a and 1710a) matches a second extended tag (e.g., see extended tags 1640a and 1740a) for a second cache set.

[0292] In some embodiments, the cache address of the first cache set includes a first tag (e.g., see tags 1622a, 1622b, 1722a, and 1722b) of cache blocks (e.g., see cache blocks 1624a, 1624b, 1724a, and 1724b) in the first cache set (e.g., see cache sets 1610a and 1710a). In such embodiments, the cache address of the second cache set includes a second tag (e.g., see tags 1626a, 1626b, 1726a, and 1726b) of cache blocks (e.g., see cache blocks 1628a, 1628b, 1728a, and 1728b) in the second cache set (e.g., see cache sets 1610b and 1710b). Furthermore, in such embodiments, block indexes are generally used as addresses within individual cache sets. For example, in such embodiments, the logic circuitry (e.g., see logic circuitry 606 and 1006) may be configured to use a first block index from the memory address (e.g., see the examples shown respectively). Figure 16 and 17 The block indices 106e and 106b from memory addresses 102e and 102b are used to obtain the first cache block in the first cache set and the tag associated with the first cache block (e.g., see cache blocks 1624a, 1624b, 1724a and 1724b and their corresponding associated tags 1622a, 1622b, 1722a and 1722b). Furthermore, logic circuits (e.g., see logic circuits 606 and 1006) can be configured to use a second block index from the memory address (e.g., see the examples shown in [references to be inserted here]). Figure 16 and 17 The block indices 106e and 106b from memory addresses 102e and 102b are used to obtain the second cache block in the second cache set and the tag associated with the second cache block (e.g., see cache blocks 1628a, 1628b, 1728a and 1728b and their corresponding associated tags 1626a, 1626b, 1726a and 1726b).

[0293] In some embodiments (e.g.) Figure 16In the embodiments described herein, when the first and second cache sets (e.g., see cache sets 1610a and 1610b) are in a first state, the cache address of the first cache set (e.g., see labels 1622a, 1622b, etc.) contains a first cache set indicator associated with the first cache set. The first cache set indicator may be a first cache set index. In such embodiments, when the first and second cache sets are in the first state, the cache address of the second cache set (e.g., see labels 1626a, 1626b, etc.) contains a second cache set indicator associated with the second cache set. The second cache set indicator may be a second cache set index.

[0294] In addition, in the exhibition Figure 16 In the embodiments described, when the first and second cache sets (e.g., see cache sets 1610a and 1610b) are in the second state (this is not in Figure 16 (As depicted in the image), the cache address of the first cache set contains a second cache set indicator associated with the second cache set. Furthermore, when the first and second cache sets are in a second state, the cache address of the second cache set contains a first cache set indicator associated with the first cache set. This change in the contents within the cache address enables interchangeability between cache sets.

[0295] In display Figure 16 In the embodiments described above, the cache set indicator is repeated in the tag of each cache block in the cache set, and therefore, the tags are more numerous than those in the cache set. Figure 17 The label for each cache block in the cache set depicted is longer. Figure 17 Instead of repeating the cache set index in the label of each cache block, the set index is stored in the cache set register associated with the cache set (see, for example, registers 1712a and 1712b).

[0296] In some embodiments (e.g.) Figure 17In the embodiments described herein, when the first and second cache sets (e.g., see cache sets 1710a and 1710b) are in a first state, the cache addresses of the first cache set (e.g., see tags 1722a, 1722b, etc.) may not include a first cache set indicator associated with the first cache set. Instead, the first cache set indicator is shown as being stored in a first cache set register 1712a (e.g., see first cache set index 1732a stored in cache set register 1712a). This reduces the size of the tags used for cache blocks in the first cache set, since the cache set indicator is stored in a register associated with the first cache set. Furthermore, when the first and second cache sets are in the first state, the cache addresses of the second cache set (e.g., see tags 1726a, 1726b, etc.) may not include a second cache set indicator associated with the second cache set. Alternatively, the second cache set indicator is displayed as stored in the second cache set register 1712b (see, for example, the second cache set index 1732b stored in the cache set register 1712b). This reduces the size of the tags used for cache blocks in the second cache set, since the cache set indicator is stored in a register associated with the second cache set.

[0297] In addition, in the exhibition Figure 17 In the embodiments described, when the first and second cache sets (e.g., see cache sets 1710a and 1710b) are in the second state (this is not in Figure 17 As depicted in the diagram, the cache addresses of the first cache set (e.g., see labels 1722a, 1722b, etc.) may not contain a second cache set indicator associated with the second cache set. Instead, the second cache set indicator is stored in the first cache set register 1712a. Furthermore, when the first and second cache sets are in a second state, the cache addresses of the second cache set (e.g., see labels 1726a, 1726b, etc.) may not contain a first cache set indicator associated with the first cache set. Instead, the first cache set indicator is stored in the second cache set register 1712b. This change in the contents of the cache set registers enables interchangeability between cache sets.

[0298] In some embodiments, such as Figure 17As shown, when the first and second registers (e.g., see registers 1712a and 1712b) are in a first state, the contents stored in the first register (e.g., see register 1712a) may include a first cache set index (e.g., see cache set index 1732a) associated with a first cache set (e.g., see cache set index 1710a). And, the contents stored in the second register (e.g., see register 1712b) may include a second cache set index (e.g., see cache set index 1732b) associated with a second cache set (e.g., see cache set index 1710a). In such embodiments, although not in Figure 17 As described in the text, when the first and second registers are in the second state, the contents stored in the first register may include a second cache set index associated with the second cache set, and the contents stored in the second register may include a first cache set index associated with the first cache set.

[0299] In some embodiments (e.g.) Figure 16 In the embodiments shown, and for example, embodiments having a connection to an execution type signal line that identifies the execution type, the cache system (e.g., see cache system 1000) may further include a connection (e.g., see connection 1002) to a speculative state signal line (e.g., see speculative state signal line 1004) that identifies the state of speculative execution of instructions from a processor (e.g., see processor 1001). In such embodiments, the connection to the speculative state signal line may be configured to receive the state of speculative execution. The state of speculative execution may indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to change the state of the first and second cache sets (e.g., see cache sets 1610a and 1610b) if the state of speculative execution indicates that the result of speculative execution will be accepted. And, when the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to maintain the state of the first and second cache sets (e.g., see cache sets 1610a and 1610b) without changing if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0300] Similarly, in some embodiments (e.g.) Figure 17In the embodiments shown, and for example, embodiments having a connection to an execution type signal line that identifies the execution type, the cache system may further include a connection to a speculative state signal line that identifies the state of speculative execution of instructions from the processor. In such embodiments, the connection to the speculative state signal line may be configured to receive the state of speculative execution. The state of speculative execution may indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to change the state of the first and second cache sets (e.g., see cache sets 1610a and 1610b) if the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, when the execution type changes from speculative execution to non-speculative execution, the logic circuitry may be configured to change the state of the first and second registers (e.g., see registers 1712a and 1712b) if the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, when the execution type changes from speculative execution to non-speculative execution, the logic circuit can be configured to maintain the state of the first and second registers (e.g., see registers 1712a and 1712b) without changing if the state indication of speculative execution will reject the result of speculative execution.

[0301] In some embodiments, the cache system may include multiple cache sets, including a first cache set and a second cache set. The cache system may also include multiple registers associated with the multiple cache sets, including a first register associated with the first cache set and a second register associated with the second cache set. The cache system may further include a connection to a command bus coupled between the cache system and the processor, a connection to an address bus coupled between the cache system and the processor, and logic coupled to the processor to control the multiple cache sets according to the multiple registers. The logic may be configured to generate a first extension tag from a cache address of the first cache set and the contents stored in the first register, and to generate a second extension tag from a cache address of the second cache set and the contents stored in the second register. The logic may also be configured to determine whether the first extension tag for the first cache set or the second extension tag for the second cache set matches a generated extension tag generated based on a memory address received from the processor. Furthermore, the logic circuit can be configured to implement a command received in connection with the command bus via a first cache set in response to a generated extended tag matching a first extended tag, and to implement the command via a second cache set in response to a generated extended tag matching a second extended tag.

[0302] In such embodiments, the cache system may further include a connection to an address bus coupled between the cache system and the processor. When the connection to the address bus receives a memory address from the processor, the logic circuitry may be configured to generate an extended tag from at least the memory address. Furthermore, the cache system may include a connection to an execution type signal line from the processor that identifies the execution type. In such instances, the logic circuitry may be configured to generate an extended tag from the memory address and the execution type identified by the execution type signal line. Additionally, the contents stored in each of the first and second registers may contain the execution type.

[0303] Furthermore, to determine whether the generated extended tag matches a first extended tag for a first cache set or a second extended tag for a second cache set, the logic circuitry may be configured to: compare the first extended tag with the generated extended tag to determine a cache hit or miss for the first cache set; and compare the second extended tag with the generated extended tag to determine a cache hit or miss for the second cache set. Additionally, the logic circuitry may be configured to: receive an output from the first cache set when the logic circuitry determines that the generated extended tag matches a first extended tag for the first cache set; and receive an output from the second cache set when the logic circuitry determines that the generated extended tag matches a second extended tag for the second cache set. In such embodiments and other embodiments, the cache address of the first cache set may include a first tag of a cache block in the first cache set, and the cache address of the second cache set may include a second tag of a cache block in the second cache set.

[0304] In some embodiments, the cache system may include multiple cache sets, including a first cache set and a second cache set. The cache system may also include multiple registers associated with the multiple cache sets, including a first register associated with the first cache set and a second register associated with the second cache set. Furthermore, the cache system may include a connection to a command bus coupled between the cache system and the processor, a connection to an execution type signal line from the processor identifying the execution type, a connection to an address bus coupled between the cache system and the processor, and logic coupled to the processor to control the multiple cache sets according to the multiple registers. When the connection to the address bus receives a memory address from the processor, the logic circuit may be configured to: generate an extended tag from the memory address and the execution type identified by the execution type signal line; and determine whether the generated extended tag matches a first extended tag for the first cache set or a second extended tag for the second cache set. Furthermore, the logic circuitry can be configured to implement a command received in connection with the command bus via a first cache set in response to a generated extended tag matching a first extended tag, and to implement the command via a second cache set in response to a generated extended tag matching a second extended tag.

[0305] Figure 18 This section illustrates a cache system according to some embodiments of the present disclosure, having interchangeable cache sets (e.g., see cache sets 1810a, 1810b, and 1810c) with mapping circuitry 1830 to logical cache set outputs (e.g., see logical outputs 1840a, 1840b, and 1840c) (e.g., see cache sets 1810a, 1810b, and 1810c). Figure 6 and 10 The instance aspect of the instance computing device (the cache system 600 and 1000 in the middle).

[0306] As shown, the cache system may include multiple cache sets (e.g., see cache sets 1810a, 1810b, and 1810c). The multiple cache sets include a first cache set (e.g., see cache set 1810a) configured to provide a first physical output (e.g., see physical output 1820a) upon a cache hit, and a second cache set (e.g., see cache set 1810b) configured to provide a second physical output (e.g., see physical output 1820b) upon a cache hit. The cache system may also include a connection to a command bus (e.g., see command bus 605a) coupled between the cache system and a processor (e.g., see processors 601 and 1001). Figure 6 and 10 (See connection 604a as depicted). The cache system may also include a connection (see connection 604b) to an address bus (see address bus 605b) coupled between the cache system and the processor.

[0307] Shown Figure 18 In this system, the cache system includes a control register 1832 (e.g., a Physical-to-Logical Set Mapping (PLSM) register 1832) and a mapping circuit 1830 coupled to the control register to map the corresponding physical outputs (e.g., physical outputs 1820a, 1820b, and 1820c) of multiple cache sets (e.g., see cache sets 1810a, 1810b, and 1810c) to a first logical cache (e.g., a normal cache) and a second logical cache (e.g., a shadow cache) as corresponding logical cache set outputs (e.g., see logical outputs 1840a, 1840b, and 1840c). The mapping of physical outputs (e.g., see physical outputs 1820a, 1820b, and 1820c) to logical cache set outputs (e.g., see logical outputs 1840a, 1840b, and 1840c) by the mapping circuit 1830 is based on the state of the control register 1832. like Figure 18 As shown, at least logical outputs 1840a and 1840b are mapped to a first logical cache for a first type of execution, and at least logical output 1840c is mapped to a second logical cache for a second type of execution. Not shown, the cache system may be configured to be coupled between the processor and a memory system (e.g., see memory system 603).

[0308] When a connection to the address bus (e.g., see address bus 605b) (e.g., see connection 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when the control register 1832 is in the first state (shown in... Figure 18 In the case of a first physical output (e.g., see physical output 1820a), the mapping circuit 1830 may be configured to map the first physical output (e.g., see logical output 1840a) to a first logical cache (e.g., see logical output 1840a) for a first type of execution performed by the processor, in order to implement commands received from the command bus (e.g., see command bus 605a) for accessing the memory system (e.g., see memory system 603) via the first cache set (e.g., cache set 1820a) during the first type of execution (e.g., non-speculated execution).

[0309] Furthermore, when a connection to the address bus (e.g., see address bus 605b) (e.g., see connection 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when the control register 1832 is in the first state (shown in... Figure 18 In the case of a second physical output (e.g., see physical output 1820b), the mapping circuit 1830 may be configured to map the second physical output (e.g., see logical output 1840b) to a second logical cache (e.g., see logical output 1840b) for a second type of execution performed by the processor, in order to implement commands received from the command bus (e.g., see command bus 605a) for accessing the memory system (e.g., see memory system 603) via the second cache set (e.g., cache set 1820b) during the second type of execution (e.g., speculative execution).

[0310] When a connection to the address bus (e.g., see address bus 605b) (e.g., see connection 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when control register 1832 is in a second state (not shown) Figure 18 In the middle, the mapping circuit 1830 is configured to map a first physical output (e.g., see physical output 1820a) to a second logic cache (e.g., see logic output 1840b) to implement commands received from the command bus (e.g., see command bus 605a) for accessing the memory system (e.g., see memory system 603) via the first cache set (e.g., cache set 1820a) during a second type of execution (e.g., speculative execution).

[0311] Furthermore, when a connection to the address bus (e.g., see address bus 605b) (e.g., see connection 605b) receives a memory address (e.g., see memory address 102b) from a processor (e.g., see processors 601 and 1001) and when the control register 1832 is in the second state (not shown in... Figure 18 In the middle, the mapping circuit 1830 is configured to map the second physical output (e.g., see physical output 1820b) to the first logic cache (e.g., see logic output 1840a) to implement commands received from the command bus (e.g., see command bus 605a) for accessing the memory system (e.g., see memory system 603) via the second cache set (e.g., cache set 1820b) during the first type of execution (e.g., non-speculated execution).

[0312] In some embodiments, the first logical cache is a normal cache for non-speculative execution performed by the processor, and the second logical cache is a shadow cache for speculative execution performed by the processor.

[0313] Mapping circuit 1830 addresses issues related to execution type. It provides a solution regarding how execution type involves mapping physical cache sets to logical cache sets. Using mapping circuit 1830, memory addresses (e.g., see address 102b) can be applied in each cache set (e.g., see physical outputs 1820a, 1820b, and 1820c) to produce physical outputs (e.g., see physical outputs 1820a, 1820b, and 1820c). The physical outputs (e.g., see physical outputs 1820a, 1820b, and 1820c) contain tags and cache blocks located using block indices (e.g., see block index 106b) derived from memory addresses. Mapping circuit 1830 can reroute physical outputs (e.g., see physical outputs 1820a, 1820b, and 1820c) to one of logical outputs (e.g., see logical outputs 1840a, 1840b, and 1840c). The cache system can perform tag comparisons at either the physical or logical output. If the tag comparison is performed at the physical output, then the tag hit or miss of the physical output is routed through mapping circuit 1830 to produce a hit or miss result for the logical output. Otherwise, the tag itself is routed through mapping circuit 1830; and a tag comparison is performed at the logical output to produce the corresponding tag hit or miss result.

[0314] like Figure 18As explained, logical outputs are predefined for both speculative and non-speculative execution. Therefore, the current execution type (e.g., see execution type 110e) can be used to select which part of the logical output will be used. For example, since logical output 1840c is predefined for... Figure 18 The execution is speculative, so if the current execution type is normal execution, then its result can be discarded. Otherwise, if the current execution type is speculative, then the result from... Figure 18 The result of the first part of the logic output (e.g., outputs 1840a and 1840b) may be blocked.

[0315] exist Figure 18 In the embodiments shown, if the current execution type is speculative, then the hit or miss result from the logical output used for non-speculative execution can be ANDed with '0' to cause a cache "miss"; and the hit or miss result from the logical output used for non-speculative execution can be ANDed with '1' to keep the result unchanged. Execution type 110e can be configured such that speculative execution = 0 and non-speculative execution = 1, and the tag hit or miss result from non-speculative outputs 1840a to 1840b can be ANDed with the execution type (e.g., execution type 110e) to produce a hit or miss that takes into account both the matching tag and the execution type. Furthermore, the tag hit or miss result from 1840c can be ANDed with the reciprocal of execution type 110e to produce a hit or miss.

[0316] Figure 19 and 20 The present disclosure illustrates some embodiments of the present disclosure that have the advantages of being shown in Figure 18 The circuit in (mapping circuit 1830) outputs the physical cache set (for example, see...). Figure 18 The physical outputs 1820a, 1820b, and 1820c depicted in the figure and shown in Figure 19 The physical output 1820a) in the cache maps to the logical cache set outputs (e.g., see logical outputs 1840a, 1840b, and 1840c) in an interchangeable cache set (e.g., see [link to cache set]). Figures 18 to 21 The cache systems of the cache sets 1810a, 1810b and 1810c depicted in the document (see, for example, those shown in the document) Figure 6 and 10 The instance aspect of the instance computing device (the cache system 600 and 1000 in the middle).

[0317] To be precise, Figure 19The diagram shows a first cache set 1810a, a first cache set register 1812a, a tag 1815a for the first cache set (containing the current tag and cache set index), a tag and set index 1850 from address 102b (containing the current tag 104b from memory address 102b and the current cache set index 112b), and a tag comparison circuit 1860a for the first cache set 1810a. Furthermore, Figure 19 A first cache set 1810a is shown, having cache blocks and associated tags (e.g., see cache blocks 1818a and 1818b and tags 1816a and 1816b), and a first cache set register 1812a storing a cache set index 1813a for the first cache set. Furthermore, Figure 19 The diagram illustrates a tag comparison circuit 1860b for the second cache set 1810b. The figure shows the physical output 1820a from the first cache set 1810a being output to the mapping circuit 1830. The second cache set 1810b and other cache sets in the system can also provide their respective physical outputs to the mapping circuit 1830 (although this is not shown in the diagram). Figure 19 (Depicted in Chinese).

[0318] Figure 20 The demonstration shows the physical outputs provided to the mapping circuit 1830 (for example, see the physical outputs 1820a, 1820b, and 1820c provided by cache sets 1810a, 1810b, and 1810c, respectively). Figure 20 (As shown in the image) are instances of multiple cache collections of the system. Figure 20 Also depicted are portions of the mapping circuit 1830 (see, for example, multiplexers 2004a, 2004b and 2004c, and PLSM registers 2006a, 2006b and 2006c). Figure 20 A first cache 1810a is also shown, having at least cache blocks 1818a and 1818b and associated tags 1816a and 1816b. Furthermore, a second cache 1810b is also shown, having at least cache blocks 1818c and 1818d and associated tags 1816c and 1816d.

[0319] Figure 19Multiplexers 1904a and 1904b and PLSM registers 1906a and 1906b are also shown, which may be part of logic circuitry (e.g., see logic circuitry 606 and 1006) and / or mapping circuitry (e.g., see mapping circuitry 1830). Each of multiplexers 1904a and 1904b receives at least hit or miss results 1862a and 1862b from tag comparison circuits 1860a and 1860b, which each compare a corresponding tag for a cache set (e.g., see the tag for a first cache set 1815a) with a tag and set index from a memory address (e.g., see tag and set index 1850). In some instances, an equivalent multiplexer may exist for each tag comparison for each cache set of the system. Each of the multiplexers (e.g., see multiplexers 1904a and 1904b) can output a selected hit or miss result based on the state of the corresponding PLSM register of the multiplexer (e.g., see PLSM registers 1906a and 1906b). The PLSM register controlling the selection of the multiplexer for outputting cache hit or miss results from cache set comparisons can be controlled by such registers when the main PLSM register (e.g., control register 1832) is part of the mapping circuit 1830.

[0320] In some embodiments, the PLSM registers (e.g., see PLSM registers 1906a and 1906b, and...) Figure 21 Each of the PLSM registers 2108a, 2108b, and 2108c depicted may be a one-, two-, or three-bit register, or a register of any bit length, depending on the specific implementation. Such PLSM registers can be used (e.g., by multiplexers) to select the appropriate physical tag comparison result or to output the correct result for one of the hit or miss logic units.

[0321] exist Figure 20 In the cases of PLSM registers 2006a, 2006b, and 2006c as depicted, such registers (e.g., used by a multiplexer) can be used to select the cache set (e.g., see see below). Figure 20 The appropriate physical output of the cache sets 1810a, 1810b, and 1810c shown in the figure (for example, see the figure shown in the figure). Figure 20 The physical outputs 1820a, 1820b, and 1820c are shown in the diagram. These PLSM registers can also be, depending on the specific implementation, one-, two-, or three-bit registers, or registers of any bit length. Furthermore, the control register 1832 can be, depending on the specific implementation, a one-, two-, or three-bit register, or registers of any bit length.

[0322] In some embodiments, the selection of physical outputs from a cache set or the selection of cache hits or misses is determined by a multiplexer (e.g., see illustrated in...). Figure 19 The multiplexers 1904a and 1904b in the example are shown. Figure 20 The multiplexers 2004a, 2004b, and 2004c shown in [the document / reference] Figure 21 The multiplexers 2110a, 2110b, and 2110c in the system are used for this purpose. These multiplexers can be arranged in the system such that there is at least one multiplexer per output type and per logic unit or per cache set. As shown in the figure, in some embodiments, there are n n-to-1 multiplexers in the presence of n cache sets or logic comparison units.

[0323] like Figure 19 As shown, the computing device may include a first multiplexer (e.g., multiplexer 1904a) configured to output a first hit or miss result or a second hit or miss result (e.g., see PLSM register 1906a) based on the content received from a first PLSM register (e.g., see PLSM register 1906a). Figure 19 The hit or miss outputs 1862a and 1862b shown in the diagram are output to the processor. The computing device may also include a second multiplexer (e.g., multiplexer 1904b) configured to output the second hit or miss result or the first hit or miss result (e.g., see PLSM register 1906b) to the processor based on the content received from the second PLSM register (e.g., see PLSM register 1906b). Figure 19 The hit or miss outputs 1862b and 1862a shown in the figure are output to the processor.

[0324] In some embodiments, the control register (e.g., shown in...) can be accessed from... Figure 18 The control register 1832 receives the contents of the PLSM register. For example, in some embodiments, when the contents received from the first PLSM register indicate a first state, the first multiplexer outputs a first hit or miss result, and when the contents received from the first PLSM register indicate a second state, the first multiplexer outputs a second hit or miss result. Furthermore, when the contents received from the second PLSM register indicate a first state, the second multiplexer can output a second hit or miss result. And, when the contents received from the second PLSM register indicate a second state, the second multiplexer can output a first hit or miss result.

[0325] like Figure 20As shown, the computing device may include a first multiplexer (e.g., multiplexer 2004a) configured to output a first physical output 1820a of a first cache set or a second physical output 1820b of a second cache set to the processor based on content received from a first PLSM register (e.g., PLSM register 2006a). The computing device may also include a second multiplexer (e.g., multiplexer 2004b) configured to output the first physical output 1820a of the first cache set or the second physical output 1820b of the second cache set to the processor based on content received from a second PLSM register (e.g., PLSM register 2006b).

[0326] In some embodiments, the control register (e.g., shown in...) can be accessed from... Figure 18 The control register 1832 receives the contents of the PLSM register. For example, in some embodiments, when the contents received from the first PLSM register indicate a first state, the first multiplexer outputs a first physical output 1820a, and when the contents received from the first PLSM register indicate a second state, the first multiplexer outputs a second physical output 1820b. Furthermore, when the contents received from the second PLSM register indicate a first state, the second multiplexer can output the second physical output 1820b. And, when the contents received from the second PLSM register indicate a second state, the second multiplexer can output the first physical output 1820a.

[0327] In some embodiments, block selection may be based on a combination of block index and master or shadow settings. These parameters control the PLSM register.

[0328] In some embodiments (e.g., shown in) Figure 19 and 20 In the example (e.g., tag and index), only one address is fed into the interchangeable cache sets (e.g., cache sets 1810a, 1810b, and 1810c). In this type of embodiment, if a cache set experiences a miss, there is a signal indicating which cache set to update based on memory control.

[0329] When the cache set is in the first state, multiplexer 1904a is controlled by PLSM register 1906a to provide a hit or miss output for cache set 1810a, and thus provides a hit or miss status for the cache set for main execution or normal execution. When the cache set is in the first state, multiplexer 1904b is controlled by PLSM register 1906b to provide a hit or miss output for cache set 1810b, and thus provides a hit or miss status for the cache set for speculative execution. Conversely, when the cache set is in the second state, multiplexer 1904a is controlled by PLSM register 1906a to provide a hit or miss output for cache set 1810b, and thus provides a hit or miss status for the cache set for main execution or normal execution. When the cache set is in the second state, the multiplexer 1904b is controlled by the PLSM register 1906b to provide a hit or miss output for the cache set 1810a, and thus provides a hit or miss status for the cache set used for speculative execution.

[0330] Similar to the selection of a hit or miss signal, data retrieved from the interchangeable cache can be chosen to produce a result for the processor (e.g., in the case of a hit), as illustrated in [example diagram]. Figure 20 The physical outputs are 1820a, 1820b, and 1820c.

[0331] For example, in the first state of the cache set, when cache set 1810a is used as the main cache set and cache set 1810b is used as the shadow cache set, multiplexer 2004a is controlled by PLSM register 2006a to select the physical output 1820a of cache set 1810a for either the main logic cache or the normal logic cache used for non-speculating execution. Furthermore, for example, in the second state of the cache set, when cache set 1810b is used as the main cache set and cache set 1810a is used as the shadow cache set, then multiplexer 2004a is controlled by PLSM register 2006a to select the physical output 1820b of cache set 1810b for either the main logic cache or the normal logic cache used for non-speculating execution. In this type of instance, in the first state of the cache set, when cache set 1810a is used as the main cache set and cache set 1810b is used as the shadow cache set, then the multiplexer 2004b is controlled by the PLSM register 2006b to select the physical output 1820b of cache set 1810b for speculative execution of the shadow logical cache. Furthermore, for example, in the second state of the cache set, when cache set 1810a is used as the main cache set and cache set 1810b is used as the shadow cache set, then the multiplexer 2004b is controlled by the PLSM register 2006b to select the physical output 1820a of cache set 1810a for speculative execution of the shadow logical cache.

[0332] In some embodiments, the caching system may further include multiple cache sets (e.g., see...). Figures 18 to 21 The cache sets 1810a, 1810b, and 1810c shown in the figure are associated with multiple registers (for example, see...). Figure 19 The register 1812a is shown in the diagram. The register may include a first register (see register 1812a) associated with a first cache set (e.g., see cache set 1810a) and a second register (not shown in the diagram) associated with a second cache set (e.g., see cache set 1810b). Figures 18 to 21 In the description but Figure 6 and 10(As depicted in the diagram). The cache system may also include logic circuitry (e.g., see processors 601 and 1001) coupled to the processor (e.g., see processors 601 and 1001) to control multiple cache sets according to multiple registers. When a memory address is received from the processor via a connection to an address bus (e.g., see address bus 605b) (e.g., see connection 604b), the logic circuitry may be configured to generate a set index from at least the memory address and determine whether the generated set index matches the contents stored in a first register or the contents stored in a second register. Furthermore, the logic circuitry may be configured to implement a command received in a connection to a command bus (e.g., see command bus 605a) (e.g., see connection 604a) via the first cache set in response to the generated set index matching the contents stored in the first register, and to implement the command via a second cache set in response to the generated set index matching the contents stored in the second register.

[0333] In some embodiments, the mapping circuitry (e.g., see mapping circuitry 1830) may be part of or connected to the logic circuitry, and the state of the control register (e.g., see control register 1832) may control the state of cache sets among a plurality of cache sets. In some embodiments, the state of the control register may control the state of cache sets among a plurality of cache sets by changing the valid bit of each block of the cache set (e.g., see...). Figures 21 to 23 ).

[0334] Furthermore, in some instances, the cache system may further include a connection (e.g., see connection 1002) to a speculative status signal line (e.g., see speculative status signal line 1004) that identifies the state of speculative execution of instructions by the processor. The connection to the speculative status signal line may be configured to receive the state of speculative execution, and the state of speculative execution may indicate whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, logic circuitry (e.g., see logic circuitry 606 and 1006) may be configured to change the state of the first and second cache sets via a control register (e.g., see control register 1832) if the state of speculative execution indicates that the result of speculative execution will be accepted. And, when the execution type changes from speculative execution to non-speculative execution, logic circuitry may be configured to maintain the state of the first and second cache sets without change via the control register if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0335] In some embodiments, the mapping circuitry (e.g., see mapping circuitry 1830) is part of or connected to logic circuitry (e.g., see logic circuitry 606 and 1006), and the state of a control register (e.g., see control register 1832) can control multiple cache registers (e.g., see...) via the mapping circuitry. Figure 19 The cache registers in register 1812a) shown in the diagram represent the state of the cache registers. In such instances, the cache system may further include a connection (e.g., see connection 1002) to a speculative status signal line (e.g., see speculative status signal line 1004) that identifies the state of speculative execution of instructions from the processor. The connection to the speculative status signal line can be configured to receive the state of speculative execution, and the state of speculative execution indicates whether the result of speculative execution will be accepted or rejected. When the execution type changes from speculative execution to non-speculative execution, the logic circuitry can be configured to change the state of the first and second registers via a control register if the state of speculative execution indicates that the result of speculative execution will be accepted. Furthermore, when the execution type changes from speculative execution to non-speculative execution, the logic circuitry can be configured to maintain the state of the first and second registers without change via a control register if the state of speculative execution indicates that the result of speculative execution will be rejected.

[0336] Figure 21 This illustration demonstrates some embodiments of the present disclosure having interchangeable cache sets (e.g., shown in...). Figure 18 The cache sets in the image, including cache sets 1810a, 1810b, and 1810c, are instances of a caching system computing device. The cache sets (e.g., cache sets 1810a, 1810b, and 1810c) are shown as utilized in the image. Figure 18 The circuit (mapping circuit 1830) maps the outputs of the physical cache set to the outputs of the logical cache set.

[0337] Figure 21 The portion depicted is a portion of a computing device that includes memory (e.g., main memory), a processor (e.g., see processor 1001), and at least three interchangeable cache sets (e.g., see interchangeable cache sets 1810a, 1810b, and 1810c). The processor is configured to execute a main thread and a speculative thread.

[0338] like Figure 21 As shown, a first cache set (e.g., cache set 1810a) may be coupled between memory and processor, and may include a first plurality of blocks for the main thread in a first state of the cache set (e.g., see shown in...). Figure 21(Blocks 2101a, 2101b, and 2101c in the cache). Each of the first plurality of blocks may contain cached data, a first valid bit, and a block address containing an index and a tag. Furthermore, the processor (alone or in conjunction with the cache controller) may be configured to change each first valid bit from indicating valid to indicating invalid when the speculation thread's speculation is successful, such that in the second state of the cache set, the first plurality of blocks become accessible to the speculation thread but blocked from the main thread.

[0339] like Figure 21 As shown, a second cache set (e.g., cache set 1810b) may be coupled between main memory and the processor, and may include a second plurality of blocks for speculating on threads in a first state of the cache set (e.g., see shown in...). Figure 21 (Blocks 2101d, 2101e, and 2101f in the cache). Each of the second plurality of blocks may contain cached data, a second valid bit, and a block address containing an index and a tag. Furthermore, the processor (alone or in conjunction with the cache controller) may be configured to change each second valid bit from indicating invalid to indicating valid when the speculation thread's speculation is successful, such that in the second state of the cache set, the second plurality of blocks become accessible to the main thread but blocked from speculation.

[0340] In some embodiments, such as Figure 21 As shown, a block in the first plurality of blocks can correspond to a corresponding block in the second plurality of blocks. Furthermore, a block in the first plurality of blocks can correspond to a corresponding block in the second plurality of blocks by having the same block address as the corresponding block in the second plurality of blocks.

[0341] In addition, such as Figure 21 As shown, the computing device may include a first physical-to-logical set mapping (PLSM) register (e.g., PLSM register 1 2108a) configured to receive a first valid bit of a block from the first plurality of blocks. The first valid bit may indicate the validity of cached data for the block from the first plurality of blocks. It may also indicate whether the block from the first plurality of blocks or the corresponding block from the second plurality of blocks is used in the main thread.

[0342] In addition, such as Figure 21 As shown, the computing device may include a second PLSM register (e.g., PLSM register 22108b) configured to receive a second valid bit of a block from the second plurality of blocks. The second valid bit indicates the validity of cached data for the block from the second plurality of blocks. It may also indicate whether a block from the second plurality of blocks or a corresponding block from the first plurality of blocks is used in the main thread.

[0343] In addition, such as Figure 21As shown, the computing device may include a logic unit 2104a for a first cache set, the logic unit 2104a being configured to determine whether a block among a first plurality of blocks is a hit or a miss. The logic unit 2104a is shown to include a comparator 2106a and an AND gate 2107a. The comparator 2106a determines whether there is a match between the tag of the block and the corresponding tag of an address in memory. And, if the tags match and the valid bits of the block are valid, then the AND gate 2107a outputs an indication of a block hit. Otherwise, the AND gate 2107a outputs an indication of a block miss. In other words, the logic unit 2104a for the first cache is configured to output a first hit or miss result based on the determination at the logic unit.

[0344] In addition, such as Figure 21 As shown, the computing device may include a logic unit 2104b for a second cache set, the logic unit 2104b being configured to determine whether a block in a second plurality of blocks is a hit or a miss. The logic unit 2104b is shown to include a comparator 2106b and an AND gate 2107b. The comparator 2106b determines whether there is a match between the tag of the block and the corresponding tag of an address in memory. And, if the tags match and the valid bits of the block are valid, then the AND gate 2107b outputs an indication of a block hit. Otherwise, the AND gate 2107b outputs an indication of a block miss. In other words, the logic unit 2104b for the second cache is configured to output a second hit or miss result based on the determination at the logic unit.

[0345] In addition, such as Figure 21 As shown, the computing device may include a first multiplexer (e.g., multiplexer 2110a) configured to output a first hit or miss result or a second hit or miss result to the processor based on a first valid bit received from a first PLSM register. The computing device may also include a second multiplexer (e.g., multiplexer 2110b) configured to output a second hit or miss result or a first hit or miss result to the processor based on a second valid bit received from a second PLSM register. In some embodiments, the first multiplexer outputs a first hit or miss result when the first valid bit received from the first PLSM register indicates a valid result, and outputs a second hit or miss result when the first valid bit received from the first PLSM register indicates an invalid result. Furthermore, the second multiplexer outputs a second hit or miss result when the second valid bit received from the second PLSM register indicates a valid result. Furthermore, when the second valid bit indication received from the second PLSM register is invalid, the second multiplexer outputs the first hit or miss result.

[0346] In some embodiments, block selection may be based on a combination of block index and master setting or shadow setting.

[0347] In some embodiments, only one address (e.g., tag and index) is fed into interchangeable cache sets (e.g., cache sets 1810a, 1810b, and 1810c). In such embodiments, if a cache set produces a miss, there is a signal indicating which cache set to update based on memory control. Similar to the selection of a hit or miss signal, data retrieved from the interchangeable cache can be selected to produce a result for the processor (e.g., in the case of a hit). For example, in a first state of the cache sets, if cache set 1810a is used as the main cache set and cache set 1810b is used as the shadow cache set, then multiplexer 2110a is controlled by PLSM register 2108a to select the hit or miss output of cache set 1804a and the hit or miss state of the main cache set. Furthermore, the multiplexer 2110b is controlled by the PLSM register 2108b to provide hit / miss outputs for the cache set 1810b, and thus provides the hit or miss status of the shadow cache set.

[0348] In this type of embodiment, when the cache set is in the second state, and when cache set 1810a is used as a shadow cache and cache set 1810b is used as a main cache, multiplexer 2110a can be controlled by PLSM register 2108b to select the hit or miss output of cache set 1810b and the hit or miss state of the main cache. Furthermore, multiplexer 2110b can be controlled by PLSM register 2108b to provide the hit or miss output of cache set 1810a, and thus provide the hit or miss state of the shadow cache.

[0349] Therefore, multiplexer 2110a can output whether the main cache has a cache hit or miss in the cache with the address used; and multiplexer 2110b can output whether the shadow cache has a cache hit or miss in the cache with the same address. Then, depending on whether the address is speculative, one of the outputs can be selected. When a cache miss exists, the address is used in memory to load data into the corresponding cache. The PLSM register can similarly implement updates to the corresponding cache set 1810a or set 1810b.

[0350] In some embodiments, in a first state of the cache set, during speculative execution of the first instruction by the speculative thread, the effects of speculative execution are stored in a second cache set (e.g., cache set 1810b). During speculative execution of the first instruction, the processor may be configured to assert a signal indicating speculative execution configured to prevent changes to the first cache set (e.g., cache set 1810a). When the signal is asserted by the processor, the processor may be further configured to prevent the second cache set (e.g., cache set 1810b) from updating memory.

[0351] When the state of the cache set changes to the second state, in response to determining that the execution of the first instruction will be performed using the main thread, the second cache set (instead of the first cache set) is used with the first instruction. In response to determining that the execution of the first instruction will not be performed using the main thread, the first cache set is used with the first instruction.

[0352] In some embodiments, in the first state, during the speculative execution of the first instruction, the processor accesses memory via a second cache set (e.g., cache set 1810b). Furthermore, during the speculative execution of one or more instructions, access to the contents of the second cache is restricted to the processor's speculative execution of the first instruction. During the speculative execution of the first instruction, the processor may be prohibited from modifying the first cache set (e.g., cache set 1810a).

[0353] In some embodiments, the contents of the first cache set (e.g., cache set 1810a) and / or the second cache set (e.g., cache set 1810b) may be accessible via a cache coherence protocol.

[0354] Figure 22 and 23 Methods 2200 and 2300, respectively, according to some embodiments of the present disclosure, utilize interchangeable cache sets for speculative and non-speculative execution performed by a processor. Specifically, methods 2200 and 2300 can be derived from... Figure 21 The computing device described herein performs this operation. Furthermore, it can be performed by... Figures 18 to 20 The computing devices described herein and any of the computing devices disclosed herein perform slightly similar methods; however, such computing devices control the cache state, cache set state, or cache set register state via a parameter other than the valid bits of the block address. For example, in Figure 16 In this context, the state of the cache set is controlled by the cache set indicator within the tag of the cache set block. Furthermore, for example, in... Figure 17In this context, the state of the cache set is controlled via the state of the cache set register associated with the cache set. In this instance, the state is controlled via the cache set index stored in the cache set register. On the other hand, for cache sets accessed via… Figures 21 to 23 The disclosed embodiments control the state of the cache set via the valid bits of the block addresses within the cache set.

[0355] Method 2200 includes, at block 2202, a main thread and a speculative thread executed by a processor (e.g., processor 1001). Method 2200 includes, at block 2204, a first cache set (e.g., such as...) of a cache system coupled between the memory system and the processor. Figure 21 The cache set 1810a shown in the document provides the first plurality of blocks for the main thread (e.g., Figure 21 The blocks 2101a, 2101b, and 2101c depicted in the diagram. Each of the first plurality of blocks may contain cached data, a first valid bit, and a block address with an index and a tag. Method 2200 includes, at block 2206, a second plurality of blocks (e.g., blocks 2101d, 2101e, and 2101f) in a second cache set (e.g., cache set 1810b) coupled between the memory system and the processor for speculating on threads. Each of the second plurality of blocks may contain cached data, a second valid bit, and a block address with an index and a tag.

[0356] At box 2207, method 2200, for example, determines whether the speculation of the speculation thread has successfully continued, by having the processor identify such that a first plurality of blocks become accessible to the speculation thread but blocked from the main thread, and a second plurality of blocks become accessible to the main thread but blocked from the speculation thread. Figure 22 As shown, if the speculation thread fails, the validity bits of the first and second plurality of blocks are not changed by the processor and remain the same validity values ​​as before determining whether the speculation thread succeeded at box 2207. Therefore, the state of the cache set does not change from the first state to the second state.

[0357] At block 2208, method 200 continues by having the processor (alone or in conjunction with the cache controller) change each first valid bit from indicating valid to indicating invalid when the speculative thread's speculation is successful, making the first plurality of blocks accessible to the speculative thread but blocked from the main thread. Furthermore, at block 2210, method 200 continues by having the processor (alone or in conjunction with the cache controller) change each second valid bit from indicating invalid to indicating valid when the speculative thread's speculation is successful, making the second plurality of blocks accessible to the main thread but blocked from the speculative thread. Therefore, the state of the cache set changes from the first state to the second state.

[0358] In some embodiments, during the speculative execution of the first instruction by the speculative thread, the effects of the speculative execution are stored in a second cache set. In such embodiments, during the speculative execution of the first instruction, the processor may assert a signal indicating speculative execution that can prevent changes to the first cache. Furthermore, when the signal is asserted by the processor, the processor may prevent the second cache from updating memory. This occurs when the cache set is in a first state.

[0359] Furthermore, in this type of embodiment, in response to determining that the execution of the first instruction will be performed using the main thread, a second cache set (instead of the first cache set) is used with the first instruction. In response to determining that the execution of the first instruction will not be performed using the main thread, the first cache is used with the first instruction. This occurs when the cache set is in the second state.

[0360] In some embodiments, during the speculative execution of the first instruction, the processor accesses memory via a second cache. Furthermore, during the speculative execution of one or more instructions, access to the contents of the second cache is restricted to the processor's speculative execution of the first instruction. In such embodiments, the processor is prohibited from modifying the first cache during the speculative execution of the first instruction.

[0361] In some embodiments, the contents of the first cache can be accessed via a cache coherence protocol.

[0362] exist Figure 23 In this context, method 2300 includes the operations at blocks 2202, 2204, 2206, 2207, 2208, and 2210 of method 2200.

[0363] Method 2300 includes a first physical-to-logical mapping set (PLSM) register at block 2302 (e.g., shown in...). Figure 21 The PLSM register 2108a) in the first plurality of blocks receives a first valid bit of a block. The first valid bit can indicate the validity of cached data in the block of the first plurality of blocks. Furthermore, method 2300 includes, at block 2304, receiving a second valid bit of a block of a second plurality of blocks by a second PLSM register (e.g., PLSM register 2108b). The second valid bit can indicate the validity of cached data in the block of the second plurality of blocks.

[0364] At box 2306, method 2300 includes a first logical unit for a first cache set (e.g., Figure 21The logic unit 2104a) depicted in the diagram determines whether a block in the first plurality of blocks is a hit or a miss. At block 2307, method 2300 continues with the first logic unit outputting a first hit or miss result based on the determination. Furthermore, at block 2308, method 2300 includes a second logic unit (e.g., logic unit 2104b) for the second cache set determining whether a block in the second plurality of blocks is a hit or a miss. At block 2309, method 2300 continues with the second logic unit outputting a second hit or miss result based on the determination.

[0365] At box 2310, method 2300 is performed by a first multiplexer (e.g., Figure 21 The multiplexer 2110a depicted outputs a first hit or miss result or a second hit or miss result to the processor for continuation based on a first valid bit received from the first PLSM register. In some embodiments, the first multiplexer outputs a first hit or miss result when the first valid bit received from the first PLSM register is valid, and outputs a second hit or miss result when the first valid bit received from the first PLSM register is invalid.

[0366] Furthermore, at block 2312, a second multiplexer (e.g., multiplexer 2110b) outputs either a second hit or miss result or a first hit or miss result to the processor based on the second valid bit received from the second PLSM register. In some embodiments, the second multiplexer outputs a second hit or miss result when the second valid bit received from the second PLSM register indicates a valid result. And, when the second valid bit received from the second PLSM register indicates an invalid result, the second multiplexer outputs a first hit or miss result.

[0367] Some embodiments may include a central processing unit (CPU) having a processing circuitry system configured to execute a main thread and a speculative thread. The CPU may also include or be connected to a first cache set configured to couple a cache system between main memory and the processing circuitry system, the first cache set having a first plurality of blocks for the main thread. Each of the first plurality of blocks may contain cached data, a first valid bit, and a block address including an index and a tag. The processing circuitry system (alone or in conjunction with a cache controller) may be configured to change each of the first valid bits from indicating valid to indicating invalid when a speculative thread's speculation is successful, such that the first plurality of blocks become accessible for the speculative thread but blocked for the main thread. The CPU may also include or be connected to a second cache set configured to couple a cache system between main memory and the processing circuitry system, the second cache set containing a second plurality of blocks for the speculative thread. Each of the second plurality of blocks may contain cached data, a second valid bit, and a block address with an index and a tag. The processing circuitry (alone or in conjunction with the cache controller) can be configured to change each second valid bit from indicating invalid to indicating valid when the speculation thread's speculation is successful, making the second plurality of blocks accessible to the main thread and blocked from the speculation thread. Furthermore, the blocks in the first plurality of blocks correspond to the corresponding blocks in the second plurality of blocks by having the same block address as the corresponding blocks in the second plurality of blocks.

[0368] The techniques disclosed herein are applicable at least to computer systems where the processor and memory are separate, and the processor communicates with the memory and storage devices via a communication bus and / or computer network. Furthermore, the techniques disclosed herein are applicable to computer systems where processing power is integrated within the memory / storage device. For example, processing circuitry including the execution unit and / or registers of a typical processor can be implemented within an integrated circuit and / or integrated circuit package of the memory media to perform processing within the memory device. Therefore, the processors discussed above and illustrated in the figures (e.g., see processors 201, 401, 601, and 1001) are not necessarily central processing units in a von Neumann architecture. The processor can be a unit integrated within memory to overcome the von Neumann bottleneck, which limits computational performance due to the latency of data movement between the central processing unit and memory, which are separately configured according to the von Neumann architecture.

[0369] The descriptions and figures in this disclosure are illustrative and should not be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in some cases, well-known or conventional details are omitted to avoid obscuring the description. References to one or more embodiments in this disclosure do not necessarily refer to the same embodiment; and such references imply at least one.

[0370] In the foregoing description, this disclosure has been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A cache system comprising: a plurality of cache sets comprising: a first cache set configured to provide a first physical output upon a cache hit; and a second cache set configured to provide a second physical output upon a cache hit; a connection to a command bus, the command bus coupled between the cache system and a processor; a connection to an address bus, the address bus coupled between the cache system and the processor; a control register, wherein a state of the control register is capable of controlling a state of a cache set of the plurality of cache sets; and a mapping circuit coupled to the control register to map respective physical outputs of the plurality of cache sets to a first logical cache and a second logical cache according to the state of the control register; wherein the cache system is configured to be coupled between the processor and a memory system; wherein when the connection to the address bus receives a memory address from the processor and when the control register is in a first state, the mapping circuit is configured to: map the first physical output to the first logical cache for non-speculative execution by the processor to implement commands received from the command bus for accessing the memory system via the first cache set during the non-speculative execution; and map the second physical output to the second logical cache for speculative execution by the processor to implement commands received from the command bus for accessing the memory system via the second cache set during the speculative execution; and wherein when the connection to the address bus receives a memory address from the processor and when the control register is in a second state, the mapping circuit is configured to: map the first physical output to the second logical cache to implement commands received from the command bus for accessing the memory system via the first cache set during the speculative execution; and map the second physical output to the first logical cache to implement commands received from the command bus for accessing the memory system via the second cache set for the non-speculative execution.

2. The cache system of claim 1, wherein the first logical cache is a normal cache for non-speculative execution by the processor, and wherein the second logical cache is a shadow cache for speculative execution by the processor.

3. The cache system of claim 1, further comprising: a plurality of registers respectively associated with the plurality of cache sets, the plurality of registers comprising: a first register associated with the first cache set; and a second register associated with the second cache set; and a logic circuit coupled to the processor to control the plurality of cache sets according to the plurality of registers. wherein when the connection to the address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the memory address; and determine whether the generated set index matches contents stored in the first register or contents stored in the second register; and wherein the logic circuit is configured to implement a command received in the connection to the command bus via the first cache set in response to the generated set index matching the contents stored in the first register, and to implement the command via the second cache set in response to the generated set index matching the contents stored in the second register.

4. The cache system of claim 3, wherein the mapping circuit is part of or connected to the logic circuit.

5. The cache system of claim 4, wherein the state of the control register can control the state of a cache set of the plurality of cache sets by changing a valid bit of each block of the cache set.

6. The cache system of claim 4, further comprising: a connection to a speculation status signal line from the processor, the speculation status signal line identifying a state of speculative execution of instructions by the processor, wherein the connection to the speculation status signal line is configured to receive the state of speculative execution, and wherein the state of speculative execution indicates whether results of speculative execution are to be accepted or rejected; and wherein when the type of execution changes from the speculative execution to a non-speculative execution, the logic circuit is configured to: change the state of the first cache set and the second cache set via the control register if the state of speculative execution indicates that results of speculative execution are to be accepted; and maintain the state of the first cache set and the second cache set without change via the control register if the state of speculative execution indicates that results of speculative execution are to be rejected.

7. The cache system of claim 3, wherein the mapping circuit is part of or connected to the logic circuit, and wherein the state of the control register can control a state of a cache register of the plurality of registers via the mapping circuit.

8. The cache system of claim 7, further comprising: a connection to a speculation status signal line from the processor, the speculation status signal line identifying a state of speculative execution of instructions by the processor, wherein the connection to the speculation status signal line is configured to receive the state of speculative execution, and wherein the state of speculative execution indicates whether results of speculative execution are to be accepted or rejected; and wherein when the type of execution changes from the speculative execution to a non-speculative execution, the logic circuit is configured to: change the state of the first register and the second register via the control register if the state of speculative execution indicates that results of speculative execution are to be accepted; and maintain the state of the first register and the second register without change via the control register if the state of speculative execution indicates that results of speculative execution are to be rejected. and wherein said status indication of the speculative execution indicates that a result of the speculative execution is to be rejected, said status of said first register and said second register is maintained via said control register without change.

9. A cache system comprising: a plurality of cache sets including: a first cache set configured to provide a first physical output upon a cache hit; and a second cache set configured to provide a second physical output upon a cache hit; a connection to a command bus, said command bus coupled between said cache system and a processor; a control register, wherein a status of said control register is capable of controlling a status of a cache set of said plurality of cache sets; and a mapping circuit coupled to said control register to map respective physical outputs of said plurality of cache sets to a first logical cache and a second logical cache according to said status of said control register; wherein said first logical cache is a normal cache for non-speculative execution by said processor, and wherein said second logical cache is a shadow cache for speculative execution by said processor; wherein when said control register is in a first state, said mapping circuit is configured to: map said first physical output to said normal cache to implement commands received from said command bus for accessing a memory system via said first cache set during said non-speculative execution; and map said second physical output to said shadow cache to implement commands received from said command bus for accessing said memory system via said second cache set during said speculative execution; and wherein when said control register is in a second state, said mapping circuit is configured to: map said first physical output to said shadow cache to implement commands received from said command bus for accessing said memory system via said first cache set during said speculative execution; and map said second physical output to said normal cache to implement commands received from said command bus for accessing said memory system via said second cache set for said non-speculative execution.

10. The cache system of claim 9, further comprising: a connection to an address bus, said address bus coupled between said cache system and said processor; a plurality of registers respectively associated with said plurality of cache sets, said plurality of registers including: a first register associated with said first cache set; and a second register associated with said second cache set; and a logic circuit coupled to said processor to control said plurality of cache sets according to said plurality of registers; wherein when said connection to said address bus receives a memory address from said processor, said logic circuit is configured to: generate a set index from at least said memory address; and generate a tag from at least said memory address. determining whether the generated set index matches contents stored in the first register or contents stored in the second register; and wherein the logic circuit is configured to implement commands received in the connection with the command bus via the first cache set in response to the generated set index matching the contents stored in the first register, and to implement the commands via the second cache set in response to the generated set index matching the contents stored in the second register.

11. The cache system of claim 10, wherein the mapping circuit is part of or connected to the logic circuit.

12. The cache system of claim 11, further comprising: a connection to a speculation status signal line from the processor that identifies a status of speculative execution of instructions by the processor, wherein the connection to the speculation status signal line is configured to receive the status of speculative execution, and wherein the status of speculative execution indicates whether results of speculative execution are to be accepted or rejected; and wherein when a type of execution changes from the speculative execution to a non-speculative execution, the logic circuit is configured to: change the status of the first cache set and the second cache set via the control register if the status of speculative execution indicates that results of speculative execution are to be accepted; and maintain the status of the first cache set and the second cache set via the control register without change if the status of speculative execution indicates that results of speculative execution are to be rejected.

13. The cache system of claim 10, wherein the mapping circuit is part of or connected to the logic circuit, and wherein the status of the control register is capable of controlling a status of a cache register in the plurality of registers via the mapping circuit.

14. The cache system of claim 13, further comprising: a connection to a speculation status signal line from the processor that identifies a status of speculative execution of instructions by the processor, wherein the connection to the speculation status signal line is configured to receive the status of speculative execution, and wherein the status of speculative execution indicates whether results of speculative execution are to be accepted or rejected; and wherein when a type of execution changes from the speculative execution to a non-speculative execution, the logic circuit is configured to: change the status of the first register and the second register via the control register if the status of speculative execution indicates that results of speculative execution are to be accepted; and maintain the status of the first register and the second register via the control register without change if the status of speculative execution indicates that results of speculative execution are to be rejected.

15. A cache system, comprising: a plurality of cache sets, including: a first cache set configured to provide a first physical output upon a cache hit; and a second cache set configured to provide a second physical output upon a cache hit; and a mapping circuit configured to: determine whether a generated set index matches contents stored in the first register or contents stored in the second register; and implement commands received in the connection with the command bus via the first cache set in response to the generated set index matching the contents stored in the first register, and to implement the commands via the second cache set in response to the generated set index matching the contents stored in the second register. a second cache set configured to provide a second physical output upon a cache hit; a connection to a command bus, the command bus coupled between the cache system and a processor; a connection to an address bus, the address bus coupled between the cache system and the processor; a control register, wherein a state of the control register is capable of controlling a state of a cache set of the plurality of cache sets; and a mapping circuit coupled to the control register to map respective physical outputs of the plurality of cache sets to a first logical cache and a second logical cache according to the state of the control register; wherein the first logical cache is a normal cache for non-speculative execution by the processor, and wherein the second logical cache is a shadow cache for speculative execution by the processor; wherein when the connection to the address bus receives a memory address from the processor and when the control register is in a first state, the mapping circuit is configured to: map the first physical output to the normal cache to implement commands received from the command bus for accessing a memory system via the first cache set during the non-speculative execution; and map the second physical output to the shadow cache to implement commands received from the command bus for accessing the memory system via the second cache set during the speculative execution; and wherein when the connection to the address bus receives a memory address from the processor and when the control register is in a second state, the mapping circuit is configured to: map the first physical output to the shadow cache to implement commands received from the command bus for accessing the memory system via the first cache set during the speculative execution; and map the second physical output to the normal cache to implement commands received from the command bus for accessing the memory system via the second cache set for the non-speculative execution.

16. The cache system of claim 15, further comprising: a plurality of registers respectively associated with the plurality of cache sets, the plurality of registers comprising: a first register associated with the first cache set; and a second register associated with the second cache set; and a logic circuit coupled to the processor to control the plurality of cache sets according to the plurality of registers; wherein when the connection to the address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the memory address; and determine whether the generated set index matches contents stored in the first register or contents stored in the second register; and wherein the logic circuit is configured to implement a command received in the connection with the command bus via the first cache set in response to the generated set index matching the contents stored in the first register, and to implement the command via the second cache set in response to the generated set index matching the contents stored in the second register.

17. The cache system of claim 16, wherein the mapping circuit is part of or connected to the logic circuit.

18. The cache system of claim 17, further comprising: a connection from a speculation status signal line from the processor that identifies a status of speculative execution of instructions by the processor, wherein the connection with the speculation status signal line is configured to receive the status of speculative execution, and wherein the status of speculative execution indicates whether results of speculative execution are to be accepted or rejected; and wherein when the type of execution changes from the speculative execution to a non-speculative execution, the logic circuit is configured to: change the status of the first cache set and the second cache set via the control register if the status of speculative execution indicates that speculative execution is to be accepted; and maintain the status of the first cache set and the second cache set without change via the control register if the status of speculative execution indicates that speculative execution is to be rejected.

19. The cache system of claim 16, wherein the mapping circuit is part of or connected to the logic circuit, and wherein the status of the control register is capable of controlling the status of cache registers in the plurality of registers via the mapping circuit.

20. The cache system of claim 19, further comprising: a connection from a speculation status signal line from the processor that identifies a status of speculative execution of instructions by the processor, wherein the connection with the speculation status signal line is configured to receive the status of speculative execution, and wherein the status of speculative execution indicates whether results of speculative execution are to be accepted or rejected; and wherein when the type of execution changes from the speculative execution to a non-speculative execution, the logic circuit is configured to: change the status of the first register and the second register via the control register if the status of speculative execution indicates that speculative execution is to be accepted; and maintain the status of the first register and the second register without change via the control register if the status of speculative execution indicates that speculative execution is to be rejected.

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