Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

A semiconductor device is provided that suppresses characteristic fluctuations, component degradation, and shape anomalies. The semiconductor device includes a first region containing multiple components and a second region containing multiple dummy components. The second region is disposed at the edge of the first region, and both the components and dummy components comprise oxide semiconductors. The components and dummy components have the same structure, and the structures contained in the components and the structures contained in the dummy components are made of the same material and disposed in the same layer. Furthermore, the oxide semiconductor comprises In, element M (M is Al, Ga, Y, or Sn), and Zn.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor material and a semiconductor device.

[0002] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, or storage devices are also types of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices sometimes include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the aforementioned technical fields. One aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Furthermore, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Background Technology

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be applied to transistors. In addition, oxide semiconductors have attracted attention as other materials. Among oxide semiconductors, in addition to single-metal oxides such as indium oxide and zinc oxide, multi-metal oxides are also known. Among multi-metal oxides, research on In-Ga-Zn oxides (hereinafter also referred to as IGZO) is particularly active.

[0005] Through research on IGZO, CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single-crystal nor amorphous, were discovered in oxide semiconductors (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 disclose techniques for manufacturing transistors using oxide semiconductors with CAAC structures. Non-Patent Documents 4 and 5 disclose oxide semiconductors with even lower crystallinity than CAAC and nc structures, which also exhibit minute crystals.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic have been reported (see Non-Patent Documents 7 and 8).

[0007] [Preliminary Technology Documents]

[0008] [Non-patent literature]

[0009] [Non-Patent Literature 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186

[0010] [Non-Patent Literature 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, p. 04ED18-1-04ED18-10

[0011] [Non-Patent Literature 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, pp. 151-154

[0012] [Non-Patent Literature 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, pp. Q3012-Q3022

[0013] [Non-Patent Literature 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, pp. 155-164

[0014] [Non-Patent Literature 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7

[0015] [Non-Patent Literature 7] S. Matsuda et al., “2015 Symposium on VLSI Technology: Digest of Technical Papers”, 2015, pp. T216-T217

[0016] [Non-Patent Literature 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629 Summary of the Invention

[0017] The technical problem that the invention aims to solve

[0018] One objective of this invention is to suppress deviations in electrical characteristics and shape among the multiple elements included in a semiconductor device. Furthermore, one objective of this invention is to suppress characteristic fluctuations and element degradation in a semiconductor device.

[0019] One objective of this invention is to provide a semiconductor device capable of retaining data over a long period. Another objective of this invention is to provide a semiconductor device with stable electrical characteristics and reliability of transistors in a semiconductor device using oxide semiconductor transistors.

[0020] One objective of this invention is to provide a semiconductor device with good electrical characteristics. Another objective of this invention is to provide a semiconductor device capable of miniaturization or high integration. Another objective of this invention is to provide a semiconductor device with high productivity. Another objective of this invention is to provide a semiconductor device with high design freedom.

[0021] One objective of this invention is to provide a semiconductor device capable of suppressing power consumption. Another objective of this invention is to provide a semiconductor device with a fast information write speed. Finally, another objective of this invention is to provide a novel semiconductor device.

[0022] Note that the description of the above objectives does not preclude the existence of other objectives. Furthermore, one embodiment of the invention does not necessarily need to achieve all of the above objectives. In addition, objectives beyond those described above can be naturally understood and derived from the description in the specification, drawings, claims, etc.

[0023] means of solving technical problems

[0024] One aspect of the present invention is a semiconductor device comprising a first region containing a plurality of elements and a second region containing a plurality of dummy elements, the second region being disposed at the edge of the first region, and both the elements and the dummy elements comprising oxide semiconductors.

[0025] One aspect of the present invention is a semiconductor device comprising a first region containing a plurality of elements, a second region containing a plurality of dummy elements, and a third region containing a plurality of elements and dummy elements, wherein the second region is disposed at the edges of the first region and the third region, and both the elements and dummy elements comprise oxide semiconductors.

[0026] In the aforementioned semiconductor device, the element and the dummy element have the same structure, and the structures contained in the element and the structures contained in the dummy element are made of the same material and disposed in the same layer.

[0027] The aforementioned semiconductor device is a chip with the second region configured at the end.

[0028] One aspect of the present invention includes a first region containing a plurality of first elements, a second region containing a plurality of second elements, and a third region between the first region and the second region containing a plurality of dummy elements, wherein the first elements, the second elements, and the dummy elements contain oxide semiconductors, and after the first elements, the second elements, and the dummy elements are formed in the same step, the substrate is truncated along the third region to form a first chip having the first region and a second chip having the second region.

[0029] In the aforementioned semiconductor device, the oxide semiconductor comprises In, element M (M is Al, Ga, Y or Sn), and Zn.

[0030] Invention Effects

[0031] According to one aspect of the present invention, a semiconductor device can be provided that suppresses deviations in electrical characteristics and shape among a plurality of elements in a semiconductor device.

[0032] According to one aspect of the present invention, a semiconductor device having transistors using oxide semiconductors can be provided, exhibiting stable electrical characteristics and reliability of the transistors. According to another aspect of the present invention, a semiconductor device capable of retaining data for extended periods can be provided.

[0033] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. According to one aspect of the present invention, a semiconductor device with high productivity can be provided. According to one aspect of the present invention, a semiconductor device with high design freedom can be provided.

[0034] According to one aspect of the present invention, a semiconductor device with fast information writing speed can be provided. According to one aspect of the present invention, a semiconductor device capable of suppressing power consumption can be provided. According to one aspect of the present invention, a novel semiconductor device can be provided.

[0035] Note that the description of the above effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily require achieving all of the above effects. In addition, effects other than those described above can be naturally understood and derived from the description in the specification, drawings, claims, etc.

[0036] Brief description of the attached figures

[0037] [Figure 1] is a top view and cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0038] [Figure 2] is a top view and cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0039] [Figure 3] is a cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0040] [Figure 4] is a top view and cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0041] [Figure 5] is a top view of a semiconductor device according to one aspect of the present invention.

[0042] [Figure 6] is a diagram illustrating a structural example of a transistor according to one aspect of the present invention.

[0043] [Figure 7] is a diagram illustrating a structural example of a transistor according to one aspect of the present invention.

[0044] [Figure 8] is a diagram illustrating a structural example of a transistor according to one aspect of the present invention.

[0045] [Figure 9] is a diagram illustrating a structural example of a transistor according to one aspect of the present invention.

[0046] [Figure 10] is a diagram illustrating a structural example of a transistor according to one aspect of the present invention.

[0047] [Figure 11] is a block diagram illustrating a structural example of a storage device according to one aspect of the present invention.

[0048] [Figure 12] is a circuit diagram showing a structural example of a storage device according to one aspect of the present invention.

[0049] [Figure 13] is a schematic diagram of a semiconductor device according to one aspect of the present invention.

[0050] [Figure 14] is a schematic diagram of a storage device according to one aspect of the present invention.

[0051] [Figure 15] is a diagram illustrating an example of a display device and an example of the circuit structure of a pixel.

[0052] [Figure 16] is a diagram illustrating an example of the circuit structure of a pixel.

[0053] [Figure 17] is a diagram illustrating an example of the structure of a drive circuit.

[0054] [Figure 18] is a diagram illustrating an example of a display device.

[0055] [Figure 19] is a diagram illustrating an example of a display device.

[0056] [ Figure 20 [ ] is a diagram illustrating an example of a display module.

[0057] [Figure 21] shows a diagram of an electronic device according to one aspect of the present invention.

[0058] [Figure 22] is a top view and cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0059] [ Figure 23 [ ] is a cross-sectional view illustrating the semiconductor device according to this embodiment.

[0060] [ Figure 24 [ ] is a diagram illustrating the etching amount of the channel portion of the semiconductor device according to this embodiment.

[0061] Methods of implementing the invention

[0062] The embodiments will now be described with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the following embodiments.

[0063] Furthermore, in the accompanying drawings, exaggerated descriptions of sizes, layer thicknesses, and / or areas are sometimes used for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Additionally, the drawings schematically illustrate ideal examples and are not limited to the shapes or values ​​shown. Furthermore, the same symbols are used across different drawings to denote the same parts or parts with the same function, omitting repeated descriptions. Moreover, the same shading lines are sometimes used when representing parts with the same function, without additional symbols.

[0064] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate the arrangement of the constituent elements in conjunction with the accompanying drawings. Furthermore, the positional relationships of the constituent elements may be appropriately altered depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in this specification may be substituted as appropriate.

[0065] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel formed between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel-forming region, and the source. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0066] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0067] Furthermore, in this specification, "electrical connection" includes connections made through a "material having a certain electrical effect." Here, there are no particular limitations on the "element having a certain electrical effect," as long as it can transmit and receive electrical signals between the connected objects. For example, "element having a certain electrical effect" includes not only electrodes and wiring, but also switching elements such as transistors, resistive elements, inductors, capacitors, and other elements with various functions.

[0068] Note that in this specification, nitrogen oxides refer to compounds in which the nitrogen content is greater than the oxygen content. Furthermore, oxynitrides refer to compounds in which the oxygen content is greater than the nitrogen content. Additionally, the content of each element can be determined, for example, using Rutherford backscattering spectrometry (RBS).

[0069] In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and less than 10°. Therefore, it also includes a state where the angle is -5° or more and less than 5°. Furthermore, "approximately parallel" refers to a state where the angle formed by two straight lines is -30° or more and less than 30°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is 80° or more and less than 100°. Therefore, it also includes a state where the angle is 85° or more and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is 60° or more and less than 120°.

[0070] Note that in this specification, a barrier film refers to a film that has the function of inhibiting the permeation of impurities such as hydrogen or oxygen. When the barrier film is conductive, it is sometimes also called a conductive barrier film.

[0071] Furthermore, in this specification and the like, the normally-on characteristic of a transistor refers to its characteristic of being in a conducting state when no potential (0V) is applied to the power supply. For example, the normally-on characteristic of a transistor sometimes refers to the electrical characteristic of current (Id) flowing between the drain and source when the voltage (Vg) applied to the gate of the transistor is 0V.

[0072] In this specification, etc., an oxide semiconductor is a type of metal oxide. A metal oxide is an oxide containing a metallic element. Metal oxides sometimes exhibit insulating, semiconducting, or conductive properties depending on their composition and formation method. Metal oxides exhibiting semiconducting properties are called metal oxide semiconductors or oxide semiconductors (also abbreviated as OS). Metal oxides exhibiting insulating properties are called metal oxide insulators or oxide insulators. Metal oxides exhibiting conductive properties are called metal oxide conductors or oxide conductors. In other words, the metal oxide used in the channel formation region of a transistor can be called an oxide semiconductor.

[0073] (Implementation Method 1)

[0074] In this embodiment, a semiconductor device comprising elements using oxide semiconductors is described with reference to FIGS. 1 to 5.

[0075] Among the aforementioned components using oxide semiconductors are switching elements (transistors, etc.), capacitors, inductors, storage elements, and display elements (light-emitting elements, etc.).

[0076] Furthermore, oxide semiconductors can use metal oxides containing indium. For example, In-M-Zn oxides (where element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, hafnium, tantalum, tungsten, or magnesium) can be used. In addition, In-Ga oxides and In-Zn oxides can also be used as oxide semiconductors.

[0077] For example, transistors using oxide semiconductors in the region forming the channel have extremely low leakage current in the non-conducting state, thus enabling the provision of low-power semiconductor devices.

[0078] Furthermore, by using oxide semiconductors, various components can be stacked to achieve three-dimensional integration. In other words, oxide semiconductors can be formed by methods such as sputtering, thereby creating three-dimensional integrated circuits (3D integrated circuits) where circuits are not only arranged on the plane of the substrate but also in the vertical direction.

[0079] On the other hand, with the increasing integration of semiconductor devices, the etching speed and etching shape sometimes change depending on the proportion of the area of ​​the mask opening (the area of ​​the etched part) to the whole and the pattern density of a part of the mask opening, which is known as the loading effect.

[0080] In this specification, pattern density refers to the area ratio of the structures formed in any region. For example, when a conductive film is formed on the entire surface of any region, the pattern density is 100%. On the other hand, when a portion of the conductive film is removed and multiple conductors are formed, the pattern density of the conductors can be obtained by dividing the area of ​​the remaining conductors by the area of ​​the arbitrary region.

[0081] The following description refers to Figures 2 and 3. Figure 2(A) is a top view of the semiconductor device. Furthermore, Figure 2(B) is a cross-sectional view along the dashed line A1-A2 in Figure 2(A). In Figures 2 and 3, some components have been omitted for clarity.

[0082] As shown in FIG2, a high pattern density region 12 including a structure 28 serving as an interlayer film and a plurality of elements 22 and a low pattern density region 13 including only the structure 28 serving as an interlayer film and without any elements are formed on the substrate 10.

[0083] Furthermore, element 22 in the accompanying drawings is simplified to show an element comprising an oxide semiconductor. Additionally, structures 28 comprising oxides having an oxygen content exceeding the stoichiometric composition are disposed near multiple elements 22.

[0084] Figures 3(A), 3(B), and 3(C) schematically illustrate the following process: films 23 and 27, which form structures or interlayer films constituting element 22, are formed on substrate 10, and then film 27 is processed by dry etching using mask 29 to expose film 23. Figure 3(D) schematically illustrates the formation process of film 26A, which forms a structure constituting element 22. Furthermore, Figure 3(E) schematically illustrates the state in which structure 26 is formed at the openings in films 27 and 23 after processing film 26A.

[0085] Before etching begins, free radicals (shown as white dots in the figure) that facilitate etching diffuse uniformly above the substrate 10. Here, after the etching process begins, as shown in Figure 3(A), the area 12 with the larger etched area consumes more free radicals, while the area 13 with the smaller etched area consumes fewer. That is, the amount of free radicals above region 12 is less than the amount above region 13, resulting in a slower etching rate in the region near the center of region 12. On the other hand, in the region adjacent to region 13 of region 12, the free radicals above region 13 are consumed, resulting in a faster etching rate.

[0086] Furthermore, as shown in Figure 3(B), as the etching process progresses, products are released from film 27 (shown as black dots in the figure), thereby further reducing the amount of free radicals above region 12. On the other hand, no products are released from film 27 above region 13, resulting in less variation in the amount of free radicals. Therefore, the etching rate in the region near the center of region 12 may become slower. On the other hand, in the region adjacent to region 13 of region 12, the free radicals above region 13 are consumed, thereby increasing the etching rate.

[0087] Therefore, as shown in Figure 3(C), when the membrane 27 is processed in the region near the center of region 12 to expose the membrane 23, a portion of the membrane 23 located below the membrane 27 in the region adjacent to region 13 of region 12 is sometimes removed to an unintentional extent (hereinafter referred to as etching amount or membrane thinning amount).

[0088] Furthermore, as shown in FIG3(D), a film 26A is formed to form the structure constituting element 22. Then, as shown in FIG3(E), when structure 26 is formed in a state where the region adjacent to region 13 of region 12 is over-etched, the shape of structure 26 becomes abnormal. That is, due to the abnormal shape of structure 26, the possibility of characteristic fluctuations occurring among multiple elements 22 increases.

[0089] Furthermore, when the membrane 23 is used as the structure of the element 22, sometimes the element 22 exhibits poor characteristics due to excessive thinning of the membrane in the region of region 12 adjacent to region 13. That is, the region of region 12 adjacent to region 13 exposes the membrane 23 more quickly than the region near the center of region 12. Therefore, the region of region 12 adjacent to region 13 exposes the membrane 23 to plasma for a longer period than the region near the center of region 12, resulting in cumulative damage to the membrane 23. In other words, the characteristics of the element 22 formed in the region of region 12 adjacent to region 13 may be worse than those of the element 22 formed in the region near the center of region 12.

[0090] Furthermore, the electrical characteristics of transistors using oxide semiconductors fluctuate due to impurities (typically hydrogen, water, etc.) and oxygen vacancies in the oxide semiconductor, thus making the transistor prone to always-on characteristics (meaning that current flows in the channel transistor even when no voltage is applied to the gate electrode). Moreover, when the transistor is driven in an oxide semiconductor containing more than an appropriate amount of excess oxygen, the electrical characteristics of the transistor sometimes change due to variations in the valence of the excess oxygen atoms, leading to a decrease in reliability.

[0091] Therefore, oxide semiconductors used in transistors are preferably oxide semiconductors with high purity intrinsics that do not have impurities, oxygen vacancies, or oxygen exceeding stoichiometric composition (hereinafter also referred to as excess oxygen).

[0092] However, in transistors using oxide semiconductors, oxygen vacancies are sometimes created in the oxide semiconductor because oxygen in the oxide semiconductor is absorbed by the conductors that make up the transistor or by the conductors used for connecting to the transistor in plugs or wiring. For example, when a heat treatment is performed during transistor formation, oxygen in the oxide semiconductor is sometimes absorbed by the conductors that make up the transistor due to this heat treatment.

[0093] Furthermore, oxygen vacancies can sometimes form in oxide semiconductors due to process damage during transistor formation. Additionally, oxygen in the oxide semiconductor can sometimes be absorbed by conductors that make up the transistor or by connectors or wiring used to connect to the transistor due to heating processes during transistor formation, resulting in oxygen vacancies in the oxide semiconductor.

[0094] Therefore, it is preferable to provide a structure containing an oxide with an oxygen content exceeding the stoichiometric composition near the oxide semiconductor of the transistor. For example, the oxide is preferably formed with a region containing oxygen in excess compared to the stoichiometric composition (hereinafter also referred to as an excess oxygen region). Specifically, the excess oxygen region may be provided in the interlayer film or the like surrounding the transistor.

[0095] When the above structure is adopted, excess oxygen in the structure including the excess oxygen region diffuses into the oxygen vacancies generated in the oxide semiconductor, thereby compensating for the oxygen vacancies. On the other hand, when excess oxygen in the structure including the excess oxygen region diffuses beyond an appropriate value, the excess oxygen supplied may sometimes alter the structure of the oxide semiconductor.

[0096] In view of this, in one aspect of the present invention, characteristic fluctuations between multiple elements formed in a denser circuit region are suppressed by providing dummy elements (hereinafter also referred to as sacrificial elements) between a sparser circuit region and a denser circuit region.

[0097] The aforementioned dummy element and the element with circuit function are manufactured through the same process. Therefore, the dummy element and the element with circuit function are formed in the same layer. At least one of the structures constituting the dummy element and the structure constituting the element with circuit function are made of the same material. Furthermore, the dummy element and the element with circuit function preferably have the same structure.

[0098] The following description refers to Figure 1. Figure 1(A) is a top view of the semiconductor device. Furthermore, Figure 1(B) is a cross-sectional view along the dashed line A1-A2 of Figure 1(A). In Figure 1, some components have been omitted for clarity.

[0099] As shown in FIG1, a high pattern density region 12 including a structure 28 serving as an interlayer film and a plurality of elements 22 is formed on the substrate 10, a low pattern density region 13 including only the structure 28 serving as an interlayer film and no elements are formed thereon, and a region 11 located between the region 13 and the region 12 including the structure 28 serving as an interlayer film and a plurality of dummy elements 21.

[0100] Furthermore, for ease of understanding, although multiple structures serving as dummy elements 21 are shown in shaded lines, dummy elements 21 preferably have the same structure as element 22. Additionally, structures 28 containing oxides whose oxygen content exceeds the stoichiometric composition are disposed near the multiple elements 22 and dummy elements 21.

[0101] By setting a region 11 including a dummy element 21 at the edge of region 12, the shape defects and characteristic fluctuations of the multiple elements 22 formed in region 12 can be reduced.

[0102] In other words, by using the component arranged in the high-speed processing region 11 as a pseudo-component 21 and the component 22 arranged in the region 12 as the standard design process, the shape and characteristic fluctuations of the component 22 that is used to start the semiconductor device can be suppressed.

[0103] Furthermore, for example, in the case where the structure 28 without region 11 in FIG2 uniformly includes an excess oxygen region, there is a high probability that the oxygen diffusion amount of the element 22 disposed in the region near the center of region 12 and the element 22 disposed in the region adjacent to region 13 of region 12 is different.

[0104] For example, in a standard design process where the characteristics of element 22 located in a region near the center of region 12 are taken as the standard design process, excess oxygen contained in region 13 diffuses into the region of region 12 adjacent to region 13 during a heat treatment process to promote the diffusion of excess oxygen, thereby potentially filling the excess oxygen in the element 22 located in the region of region 12 adjacent to region 13.

[0105] In other words, excess oxygen exceeding a suitable value may diffuse into element 22 located in region 12 adjacent to region 13.

[0106] Here, as shown in FIG1, since a region 11 including a plurality of dummy elements 21 is formed at the edge of a high pattern density region 12 including a plurality of elements 22, characteristic fluctuations between the plurality of elements 22 disposed in the region 12 can be suppressed.

[0107] In other words, when a structure 28 containing an oxide with an oxygen content exceeding the stoichiometric composition is arranged across regions 12, 11 and regions with low element density, excess oxygen diffusing from the structure 28 arranged in the region with low element density is absorbed by the pseudo-element 21 by arranging region 11 between region 12 and the region with low element density, thereby suppressing the diffusion of excess oxygen to region 12.

[0108] Furthermore, by configuring a region 11 comprising multiple dummy elements 21 at the edge of region 12, it is possible for the structure including the dummy elements 21 to absorb impurities (typically hydrogen, water, etc.) diffusing from the outside of the semiconductor device even after the semiconductor device has been manufactured. In other words, the diffusion of impurities to element 22 can be suppressed by the dummy elements 21 capturing the impurities. Therefore, the reliability of element 22 can be improved.

[0109] This allows for the suppression of deviations in the electrical characteristics of transistors. Furthermore, it enables the provision of highly reliable transistors. Additionally, it suppresses transistor shape abnormalities and electrostatic discharge (ESD) damage. Consequently, yield is improved, and thus the productivity of semiconductor devices can also be increased.

[0110] <Structure Example of a Semiconductor Device 2>

[0111] Hereinafter, another example of a semiconductor device comprising elements using oxide semiconductors, one aspect of the present invention, will be described with reference to FIG4.

[0112] Furthermore, in the semiconductor device shown in Figure 4, the same symbols represent structures that have the same functions as the constituent elements of the semiconductor device shown in the above structural examples.

[0113] Specifically, Figure 4(A) is a top view of the semiconductor device formed on the substrate 15 before it is diced. Figure 4(B) is a cross-sectional view of the portion indicated by the dashed lines A1-A2 in Figure 4(A).

[0114] The substrate 15 may be, for example, a semiconductor substrate (also referred to as a "semiconductor wafer"). A plurality of circuit regions 16 are provided on the substrate 15. Furthermore, a plurality of separate regions 18, indicated by double-dotted lines, are also provided on the substrate 15. The circuit regions include a high-pattern-density region 12 containing elements 22 and a region 11 containing dummy elements 21.

[0115] A separation region 18 is disposed between region 12 of one circuit region 16 and region 12 of another circuit region 16. Furthermore, a separation line (also referred to as a "cutting line") is located at a position overlapping with the separation region 18. A chip including region 12 can be cut from the substrate 15 by cutting along the separation line.

[0116] Here, the separation region 18 preferably includes region 11 containing the dummy element 21. By using region 11 as a separation region, the designed region 12 can be expanded, thereby achieving high integration.

[0117] Furthermore, since the separation region 18 includes region 11, the conductive layer and semiconductor layer contained in the dummy element 21 can mitigate ESD that may be generated during the cutting process, thereby preventing a decrease in yield caused by the cutting process.

[0118] Furthermore, generally, in order to cool the substrate, remove shavings, and prevent charging, carbonated water with a lower resistivity than pure water is supplied to the cutting section during the cutting process. By providing a conductive layer or semiconductor layer on the separation region 18, the amount of pure water used can be reduced. Therefore, the production cost of semiconductor devices can be reduced. In addition, the productivity of semiconductor devices can be improved.

[0119] Furthermore, impurities such as water that intrude from the separation region 18 are captured by the dummy element 21, thereby suppressing the reduction in reliability.

[0120] <Structure Example of a Semiconductor Device 3>

[0121] Hereinafter, another example of a semiconductor device comprising elements using oxide semiconductors, according to one aspect of the present invention, will be described with reference to FIG5. FIG5(A) and FIG5(B) are top views of a semiconductor device formed on substrate 10.

[0122] Furthermore, in the semiconductor device shown in Figure 5, the same symbols represent structures that have the same functions as the constituent elements of the semiconductor device shown in the above structural examples.

[0123] In semiconductor devices, multiple circuits with different functions are sometimes arranged on the same substrate. The density of components or wiring required to form the circuit varies depending on the desired circuit structure. Specifically, as shown in FIG5(B), the density of component and wiring arrangement (hereinafter also referred to as the layout in the circuit area) differs between a circuit area (corresponding to area 12 in the figure) that is regularly arranged and highly integrated, such as memory cells or pixel areas, and a circuit area (corresponding to area 14 in the figure) where the layout is determined as needed, such as driving circuits or correction circuits. Furthermore, area 13, which is the outer periphery of the circuit area, has no components, resulting in a significant difference in pattern density between it and area 12.

[0124] Therefore, as shown in Figure 5(A), by setting dummy elements 21 in sparse region 14 such that the density of the elements is equal to that in region 12, the difference in pattern density of the layout in the circuit region is reduced. In this specification, the statement that a value is equal to other values ​​does not necessarily indicate strict consistency, but rather indicates a degree of similarity, equality, or approximation within the scope of common technical knowledge.

[0125] In other words, by reducing the difference in pattern density in the circuit area to a degree that makes it less likely to cause processing abnormalities or electrostatic damage, or by making the pattern density in the circuit area equal, it is possible to suppress the non-uniformity of characteristics and abnormal shape between components.

[0126] Furthermore, the difference in pattern density of the layout in the circuit region can be reduced or made equal in the degree to which the excess oxygen diffused to each element disposed in each region is less likely to cause differences. By adopting this structure, the excess oxygen diffused to each element included in each region can be suppressed.

[0127] For example, in a certain structure, although the average pattern density of the entire substrate is 40%, sometimes the pattern density of a certain area of ​​the substrate is 70%, while the pattern density of other areas is 10%. Therefore, the area with a pattern density of 10% is a sparse area, so dummy elements 21 can be formed with a pattern density of approximately 70%. That is, without configuring dummy elements 21, the average pattern density of the entire substrate is d. ave %, compared to d ave The pattern density of the dense region is d high %, compared to d ave The pattern density of the sparse region is d low %. Furthermore, this can be achieved by using a pattern density of d. low The area is set with pseudo-element 21 to make the pattern density d. ave % or more, preferably d high %.

[0128] Furthermore, by employing this structure, when the structure 28 uniformly includes an excess oxygen region, the amount of oxygen diffused into a single element 22 is equal in the element 22 disposed in region 12 and in the plurality of elements 22 disposed in region 14. Therefore, deviations in element characteristics are suppressed in regions 12 and 14, thereby allowing for the placement of elements 22 with high reliability.

[0129] Furthermore, by configuring the dummy element 21, impurities (typically hydrogen, water, etc.) in the oxide semiconductor are sometimes absorbed by the conductor included in the dummy element 21 due to the various thermal conditions of some heating processes in the transistor formation process (the history of these thermal conditions is also called thermal history). In other words, the dummy element 21 captures impurities, thus suppressing the diffusion of impurities to the element 22. As a result, the reliability of the element 22 can be improved.

[0130] This allows for the suppression of deviations in the electrical characteristics of transistors. Furthermore, it enables the provision of highly reliable transistors. Additionally, it suppresses transistor shape abnormalities and electrostatic discharge (ESD) damage. Consequently, yield is improved, and thus the productivity of semiconductor devices can also be increased.

[0131] Furthermore, highly integrated semiconductor devices can be easily used. Furthermore, a semiconductor device with a transistor having a large off-state current can be provided. Furthermore, a semiconductor device with a transistor having a small off-state current can be provided. Furthermore, a semiconductor device that improves reliability while suppressing fluctuations in electrical characteristics and achieving stable electrical characteristics can be provided.

[0132] The configurations, structures, and methods shown in this embodiment can be appropriately combined with the configurations, structures, and methods shown in other embodiments.

[0133] (Implementation Method 2)

[0134] This embodiment describes a structural example of the transistor shown in the above embodiment.

[0135] <Example 1 of a transistor structure>

[0136] Reference Figures 6(A) to 6(C) This section describes a structural example of transistor 200A. Figure 6(A) is a top view of transistor 200A. Figure 6(B) is a cross-sectional view of the portion indicated by dashed lines L1-L2 in Figure 6(A). Figure 6(C) is a cross-sectional view of the portion indicated by dashed lines W1-W2 in Figure 6(A). In the top view of Figure 6(A), constituent elements are omitted for clarity.

[0137] exist Figures 6(A) to 6(C) The diagram shows transistor 200A, insulators 210, 212, 214, 216, 280, 282, and 284, which serve as interlayer films. It also shows plug 246 (conductors 246s and 246d) electrically connected to transistor 200A and used as contact plugs, and conductor 203 used as wiring.

[0138] Transistor 200A includes a conductor 260 (conductors 260a and 260b) used as a first gate (also called top gate) electrode, a conductor 205 (conductors 205a and 205b) used as a second gate (also called bottom gate) electrode, an insulator 250 used as a first gate insulator, an insulator 220, an insulator 222 and an insulator 224 used as a second gate insulator, an oxide 230 (oxides 230a, 230b and 230c) including a region forming a channel, a conductor 240s used as one of the source and drain, a conductor 240d used as the other of the source and drain, and an insulator 274.

[0139] Insulators 210 and 212 are used as interlayer membranes.

[0140] As the interlayer film, single layers or stacks of insulators such as silicon oxide, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST) can be used. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide can be added to these insulators. Furthermore, these insulators can be nitrided. Additionally, silicon oxide, silicon oxynitride, or silicon nitride can be laminated onto the aforementioned insulators.

[0141] For example, insulator 210 is preferably used as a barrier film to prevent impurities such as water and hydrogen from entering transistor 200A from the substrate side. Therefore, insulating material with the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (making it difficult for such impurities to permeate) is preferably used as insulator 210. In addition, insulating material with the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (making it difficult for such oxygen to permeate) is preferably used. Furthermore, for example, aluminum oxide or silicon nitride is preferably used as insulator 210. By adopting this structure, impurities such as water and hydrogen can be inhibited from diffusing to the transistor 200A from the side closer to the substrate than to the insulator 210.

[0142] For example, the dielectric constant of insulator 212 is preferably lower than that of insulator 210. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0143] The conductor 203 is formed by embedding it within the insulator 212. Here, the height of the top surface of the conductor 203 can be approximately the same as the height of the top surface of the insulator 212. The conductor 203 has a single-layer structure, but the invention is not limited thereto. For example, the conductor 203 can also have a multilayer film structure with two or more layers. As the conductor 203, a conductive material with high conductivity, primarily composed of tungsten, copper, or aluminum, is preferably used.

[0144] In transistor 200A, conductor 260 is sometimes used as the first gate electrode, and conductor 205 is sometimes used as the second gate electrode. In this case, the threshold voltage of transistor 200A can be controlled by independently changing the potential applied to conductor 205 without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, the threshold voltage of transistor 200A can be made greater than 0V, and the off-state current can be reduced. Therefore, compared with not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential applied to conductor 260 is 0V.

[0145] Furthermore, for example, by overlapping conductor 205 onto conductor 260, when a potential is applied to conductor 260 and conductor 205, the electric field generated from conductor 260 and the electric field generated from conductor 205 are connected, and the channel formation region formed in oxide 230 can be covered.

[0146] In other words, a region can be formed around the channel by the electric field of the conductor 260 used as the first gate electrode and the electric field of the conductor 205 used as the second gate electrode. In this specification, the structure of the transistor in which the electric field of the first gate electrode and the electric field of the second gate electrode form a region around the channel is referred to as a surround channel (S-channel) structure.

[0147] Similar to insulators 210 and 212, insulators 214 and 216 are used as interlayer films. For example, insulator 214 is preferably used as a barrier film to prevent impurities such as water and hydrogen from entering transistor 200A from the substrate side. By employing this structure, impurities such as water and hydrogen can be prevented from diffusing from the side closer to the substrate than from insulator 214 to the transistor 200A side. For example, the dielectric constant of insulator 216 is preferably lower than that of insulator 214. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0148] In the conductor 205 used as the second gate electrode, conductor 205a is formed in contact with the inner walls of the openings of insulators 214 and 216, and conductor 205b is formed on its inner side. Here, the height of the top surface of conductor 205a and conductor 205b can be approximately the same as the height of the top surface of insulator 216. Furthermore, in transistor 200A, conductors 205a and conductor 205b are stacked, but the present invention is not limited thereto. For example, conductor 205 can have a single-layer structure or a stacked structure of three or more layers.

[0149] Here, the conductive material 205a is preferably a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (making it difficult for such impurities to permeate). Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (making it difficult for such oxygen to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurity or oxygen.

[0150] For example, by giving conductor 205a the function of inhibiting oxygen diffusion, the decrease in conductivity caused by oxidation of conductor 205b can be suppressed.

[0151] Furthermore, when conductor 205 also functions as wiring, it is preferable to use a highly conductive material with tungsten, copper, or aluminum as the main components of conductor 205b. In this case, conductor 203 is not necessarily required. In the accompanying drawings, conductor 205b has a single-layer structure, but it can also have a multilayer structure, for example, a multilayer structure of titanium, titanium nitride, and the aforementioned conductive materials can be used.

[0152] Insulators 220, 222 and 224 are used as the second gate insulator.

[0153] Here, in the insulator 224 that is in contact with the oxide 230, it is preferable to remove the oxygen by heating. In this specification, the oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulator 224. By providing an insulator containing oxygen in a manner that allows it to contact the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200A.

[0154] As the insulator 224, specifically, an oxide material that undergoes partial oxygen removal upon heating is preferably used. An oxide that undergoes oxygen removal upon heating is defined as one in which the amount of oxygen removed, converted to oxygen molecules in TDS (Thermal Desorption Spectroscopy) analysis, is 1.0 × 10⁻⁶. 18molecules / cm 3 The preferred value is 1.0 × 10⁴. 19 molecules / cm 3 The above is further preferred to be 2.0×10 19 molecules / cm 3 Above, or 3.0 × 10 20 molecules / cm 3 The above-mentioned oxide film. Furthermore, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0155] The insulator 222 preferably has a barrier property. When the insulator 222 has a barrier property, the insulator 222 is used as a layer to suppress impurities such as hydrogen from entering the transistor 200A from the periphery of the transistor 200A.

[0156] As the insulator 222, a single layer or stack of insulators comprising so-called high-k materials such as aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST) are preferably used. When miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0157] For example, insulator 220 preferably has thermal stability. For example, silicon oxide and silicon oxynitride have thermal stability. Therefore, when silicon oxide and silicon oxynitride are used for insulator 220 and a high-k material is used for insulator 222, a multilayer structure with thermal stability and a high relative permittivity can be achieved by using the combination of insulator 220 and insulator 222.

[0158] Note that in Figure 6, the second gate insulator has a three-layer stacked structure, but it can also have a single-layer structure or a stacked structure with two or more layers. In this case, it is not limited to a stacked structure made of the same material, but can also be a stacked structure made of different materials.

[0159] The oxide 230, which includes the region used as the channel formation region, comprises oxide 230a, oxide 230b on oxide 230a, and oxide 230c on oxide 230b. When oxide 230a is disposed under oxide 230b, impurities can be prevented from diffusing from the structure formed under oxide 230a to oxide 230b. When oxide 230c is disposed on oxide 230b, impurities can be prevented from diffusing from the structure formed above oxide 230c to oxide 230b. As oxide 230, an oxide semiconductor of one of the following metal oxides can be used.

[0160] Furthermore, the transistor 200A shown in Figure 6 includes a region where conductor 240 (conductors 240s and 240d) overlaps with oxide 230c, insulator 250, and conductor 260. By employing this structure, a transistor with a large on-state current can be provided. Furthermore, a transistor with high controllability can be provided.

[0161] One of the conductors 240 is used as the source electrode, and the other is used as the drain electrode.

[0162] The conductor 240 can be made of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or alloys with such metals as the main component. In particular, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen and high oxidation resistance.

[0163] Furthermore, although a single-layer structure is shown as conductor 240 in Figure 6, a stacked structure of two or more layers can also be used. For example, a tantalum nitride film and a tungsten film are preferably stacked. In addition, a titanium film and an aluminum film can also be stacked. Furthermore, a two-layer structure with an aluminum film stacked on a tungsten film, a two-layer structure with a copper film stacked on a copper-magnesium-aluminum alloy film, a two-layer structure with a copper film stacked on a titanium film, and a two-layer structure with a copper film stacked on a tungsten film can also be used.

[0164] In addition, a three-layer structure can also be used, in which an aluminum film or a copper film is laminated on a titanium film or a titanium nitride film and a titanium film or titanium nitride film is formed thereon; or a three-layer structure can be used, in which an aluminum film or a copper film is laminated on a molybdenum film or a molybdenum nitride film and a molybdenum film or molybdenum nitride film is formed thereon. Furthermore, transparent conductive materials containing indium oxide, tin oxide, or zinc oxide can also be used.

[0165] Alternatively, a barrier layer may be provided on the conductor 240. The barrier layer is preferably made of a material that blocks oxygen or hydrogen. By employing this structure, oxidation of the conductor 240 can be suppressed during the formation of the insulator 274.

[0166] The barrier layer can be, for example, a metal oxide. In particular, insulating films that have the ability to block oxygen or hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide, are preferred. Alternatively, silicon nitride formed by CVD can also be used.

[0167] By including a barrier layer, the range of materials that can be selected for the conductor 240 can be expanded. For example, the conductor 240 can be made of materials with low oxidation resistance and high conductivity, such as tungsten or aluminum. Furthermore, conductors that are easy to deposit or process can be used, for example.

[0168] Insulator 250 is used as the first gate insulator.

[0169] When miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. In this case, similar to the second gate insulator, the insulator 250 can also have a stacked structure. By using a stacked structure of a high-k material and a thermally stable material as the insulator used as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness. Furthermore, a stacked structure with thermal stability and a high relative permittivity can be achieved.

[0170] The conductor 260 used as the first gate electrode includes a conductor 260a and a conductor 260b on the conductor 260a. Similar to the conductor 205a, the conductor 260a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0171] When conductor 260a has the function of inhibiting oxygen diffusion, the material selectivity of conductor 260b can be improved. That is, by including conductor 260a, the oxidation of conductor 260b can be inhibited, thereby preventing a decrease in conductivity.

[0172] As a conductive material that suppresses oxygen diffusion, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc., are preferably used, for example. Furthermore, as the conductor 260a, an oxide semiconductor suitable for oxide 230 can be used. In this case, by forming the conductor 260b using a sputtering method, the resistivity of the conductor 260a can be reduced, making it a conductor. This conductor can be referred to as an OC (Oxide Conductor) electrode.

[0173] Furthermore, since conductor 260 is used for wiring, a conductor with high conductivity is preferred. For example, conductor 260b can be a conductive material with tungsten, copper, or aluminum as its main components. Additionally, conductor 260b can also employ a multilayer structure; for example, a multilayer of titanium, titanium nitride, and the aforementioned conductive material can be used.

[0174] Furthermore, it is preferable that the insulator 274 is provided in a manner that covers the top and side surfaces of the conductor 260, the side surfaces of the insulator 250, and the side surfaces of the oxide 230c. The insulator 274 is preferably made of an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide and hafnium oxide are preferred. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, as well as silicon oxynitride and silicon nitride, can be used.

[0175] By insulator 274, oxidation of conductor 260 can be suppressed. Furthermore, by including insulator 274, the diffusion of impurities such as water and hydrogen contained in insulator 280 into transistor 200A can be suppressed.

[0176] Insulators 280, 282 and 284 are used as interlayer membranes.

[0177] Similar to insulator 214, insulator 282 is preferably used as a barrier insulating film to prevent impurities such as water or hydrogen from entering transistor 200A from the outside.

[0178] Furthermore, similar to insulator 216, the dielectric constants of insulators 280 and 284 are preferably lower than that of insulator 282. By using a material with a lower dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0179] In addition, transistor 200A can also be electrically connected to other structures via plugs or wiring such as plug 246 embedded in insulators 280, 282 and 284.

[0180] Furthermore, similar to conductor 205, the plug 246 can be made of a single layer or a stack of conductive materials such as metals, alloys, metal nitrides, or metal oxides. For example, high-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. By using low-resistance conductive materials, wiring resistance can be reduced.

[0181] For example, by using a stacked structure of tantalum nitride, a conductor that blocks hydrogen and oxygen, and tungsten, which has high conductivity, as the plug 246, the diffusion of impurities from the outside can be suppressed while maintaining the conductivity of the wiring.

[0182] Alternatively, a barrier insulator 276 (insulator 276a and insulator 276b) can be provided between the plug 246 and the insulator 280. By providing the insulator 276, the reaction between the oxygen in the insulator 280 and the plug 246, which would otherwise lead to the oxidation of the plug 246, can be suppressed.

[0183] Furthermore, by providing an insulator 276 with barrier properties, the range of materials that can be selected for the conductors used in the plug or wiring can be expanded. For example, by using a metal material with oxygen-absorbing properties and high conductivity as the plug 246, a low-power semiconductor device can be provided. Specifically, materials with low oxidation resistance and high conductivity, such as tungsten and aluminum, can be used. In addition, conductors that are easy to form films or process can be used, for example.

[0184] By having the above structure, a semiconductor device with a transistor having a large on-state current can be provided. Alternatively, a semiconductor device with a transistor having a small off-state current can be provided. Alternatively, a semiconductor device with improved reliability while suppressing electrical characteristic fluctuations and achieving stable electrical characteristics can be provided.

[0185] <Constructing Materials>

[0186] [Substrate]

[0187] While there are no major restrictions on the materials that can be used as substrates, the substrate must possess sufficiently high heat resistance to withstand subsequent heat treatments. For example, single-crystal or polycrystalline semiconductor substrates made of silicon or silicon carbide, or compound semiconductor substrates made of silicon-germanium, can be used. Additionally, SOI substrates or substrates on which semiconductor elements such as strain gauge transistors or FIN-type transistors are mounted can also be used. Furthermore, materials suitable for high electron mobility transistors (HEMTs), such as gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, and silicon-germanium, can also be used. In other words, the substrate can not only be a supporting substrate but also a substrate on which transistors or other devices are formed.

[0188] Furthermore, glass substrates such as barium borosilicate glass and aluminum borosilicate glass, ceramic substrates, quartz substrates, and sapphire substrates can be used as substrates. Flexible substrates can also be used. When using a flexible substrate, transistors or capacitors can be fabricated directly on the flexible substrate, or they can be fabricated on another fabrication substrate and then the transistor can be peeled off and transferred to the flexible substrate. Furthermore, to peel the transistor and capacitor from the fabrication substrate and transfer them to the flexible substrate, a release layer is preferably provided between the fabrication substrate and the transistor and capacitor.

[0189] Flexible substrates can be made of materials such as metals, alloys, resins, glass, or their fibers. A lower coefficient of linear expansion of the flexible substrate is preferred, as it suppresses deformation caused by environmental factors. For example, a flexible substrate with a coefficient of linear expansion of 1 × 10⁻⁶ can be used. -3 / K or less, 5×10 -5 / K or less or 1×10 -5 Materials for / K. Examples of resins include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. In particular, aramids have a low coefficient of linear expansion, making them suitable for flexible substrates.

[0190] [Insulator]

[0191] As an insulator, a single layer or stack of materials selected from the following can be used: aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminosilicates, etc. In addition, materials in which multiple oxides, nitrides, oxynitrides, and oxides are mixed can also be used.

[0192] Note that in this specification, nitrogen oxides refer to compounds in which the nitrogen content is greater than the oxygen content. Furthermore, oxynitrides refer to compounds in which the oxygen content is greater than the nitrogen content. Additionally, the content of each element can be determined, for example, using Rutherford backscattering spectrometry (RBS).

[0193] Furthermore, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, it is preferable to reduce the hydrogen concentration in the insulator to prevent an increase in the hydrogen concentration in the semiconductor layer. Specifically, the hydrogen concentration in the insulator, measured by secondary ion mass spectrometry (SIMS), is 2 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is a further preferred option: 5×10 18 atoms / cm 3 The following. In particular, it is preferable to reduce the hydrogen concentration in the insulator that is in contact with the semiconductor layer.

[0194] Furthermore, to prevent an increase in nitrogen concentration in the semiconductor layer, it is preferable to reduce the nitrogen concentration in the insulator. Specifically, the nitrogen concentration in the insulator, as measured by SIMS, is 5 × 10⁻⁶. 19 atoms / cm 3 The following is preferred: 5×10 18 atoms / cm 3Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0195] Furthermore, the defects in the region of the insulator that is at least in contact with the semiconductor layer are preferably few, typically indicating a low level of signal observed by electron spin resonance (ESR). For example, the E' center observed at a g value of 2.001 can be cited as an example of such a signal. The E' center originates from dangling bonds in silicon. For example, when using a silicon oxide layer or a silicon oxynitride layer as the insulator, a spin density of 3 × 10⁻⁶ originating from the E' center can be used. 17 spins / cm 3 The following, preferably 5×10 16 spins / cm 3 The following silicon oxide layer or silicon oxynitride layer.

[0196] Sometimes, in addition to the signals mentioned above, signals originating from nitrogen dioxide (NO2) are observed. This signal splits into three signals due to the nuclear spin of nitrogen: a g value of 2.037 or higher and 2.039 or lower (first signal), a g value of 2.001 or higher and 2.003 or lower (second signal), and a g value of 1.964 or higher and 1.966 or lower (third signal).

[0197] For example, as an insulator, it is preferable to use a signal originating from nitrogen dioxide (NO2) with a spin density of 1 × 10⁻⁶. 17 spins / cm 3 Above and less than 1×10 18 spins / cm 3 Insulators.

[0198] Nitrogen dioxide (NO2) and nitrogen oxides (NO) x An energy level is formed in the insulator. This energy level is located in the bandgap of the oxide semiconductor layer. Therefore, when nitrogen oxides (NO...)... x When electrons diffuse to the interface between the insulator and the oxide semiconductor layer, the energy level sometimes traps electrons on the insulator side. As a result, the trapped electrons remain near the interface between the insulator and the oxide semiconductor layer, thereby causing the threshold voltage of the transistor to drift in the positive direction. Therefore, when a film with a low content of nitrogen oxides is used as the insulator, the drift of the transistor's threshold voltage can be reduced.

[0199] As nitrogen oxides (NO) xInsulators that release less ammonia can be used, for example, a silicon oxynitride layer. This silicon oxynitride layer is characterized by a lower ammonia release compared to nitrogen oxides (NOx) as measured by thermal desorption spectroscopy (TDS). x Membranes that release a large amount of ammonia, typically 1×10⁻⁶. 18 pcs / cm 3 Above and 5×10 19 pcs / cm 3 The following is a summary. Furthermore, the ammonia release mentioned above refers to the total amount released in TDS within a temperature range of 50°C to 650°C or 50°C to 550°C during heat treatment.

[0200] Because when heat treatment is performed, nitrogen oxides (NOx) x It reacts with ammonia and oxygen, so using insulators that release a lot of ammonia can reduce nitrogen oxides (NOx). x ).

[0201] At least one of the insulators in contact with the oxide semiconductor layer is preferably formed using an insulator that releases oxygen upon heating. Specifically, an insulator is preferably used whose oxygen removal amount, converted to oxygen atoms, is 1.0 × 10⁻⁶ when performing TDS analysis (wherein a heat treatment is performed at a film surface temperature of 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower). 18 atoms / cm 3 The preferred value is 1.0 × 10⁴. 19 atoms / cm 3 or above 1.0×10 20 atoms / cm 3 That's all. Furthermore, in this specification and other materials, the oxygen released by heating is referred to as "excess oxygen".

[0202] Furthermore, insulators containing excess oxygen can be formed by adding oxygen to the insulator. As an oxygen addition treatment, heat treatment under an oxidizing atmosphere, plasma treatment, etc., can be used. Alternatively, oxygen addition can be performed using ion implantation, ion doping, plasma immersion ion implantation, etc. Examples of gases used in the oxygen addition treatment include... 16 O2 or 18 Oxygen gases such as O2, nitrous oxide, or ozone are also oxygen-containing gases. Note that in this specification, the process of adding oxygen is sometimes referred to as "oxygen doping." Oxygen doping can also be performed while the substrate is heated.

[0203] As insulators, heat-resistant organic materials such as polyimide, acrylic resins, benzocyclobutene resins, polyamides, and epoxy resins can be used. In addition to the aforementioned organic materials, low-dielectric-constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass) can also be used. Furthermore, a planarized insulator can be formed by stacking multiple insulating films made of these materials.

[0204] Siloxane resins are resins containing Si-O-Si bonds formed from siloxane materials as starting materials. Siloxane-based resins may include organic groups (e.g., alkyl or aryl) or fluorine groups as alternatives. Furthermore, the organic groups may also have fluorine groups.

[0205] There are no particular restrictions on the method of forming the insulator. Note that sometimes a calcination process is required depending on the material used in the insulator. In this case, transistors can be manufactured efficiently by combining the calcination process of the insulator with other heat treatment processes.

[0206] [electrode]

[0207] As the conductive material used to form the electrode, materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium can also be used. Alternatively, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used.

[0208] In addition, conductive materials containing the aforementioned metallic elements and oxygen can also be used. Furthermore, conductive materials containing the aforementioned metallic elements and nitrogen can also be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, can also be used. Additionally, indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium gallium zinc oxide, and indium tin oxide with added silicon can also be used. Furthermore, indium gallium zinc oxide containing nitrogen can also be used.

[0209] Furthermore, multiple conductors formed from the above-described materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used. Furthermore, a stacked structure combining conductive materials containing nitrogen and conductive materials containing oxygen can also be used.

[0210] Furthermore, when an oxide semiconductor is used as the semiconductor layer and a stacked structure combining a material containing the aforementioned metal elements and an oxygen-containing conductive material is used as the gate electrode, it is preferable to provide an oxygen-containing conductive material on one side of the semiconductor layer. By providing an oxygen-containing conductive material on one side of the semiconductor layer, oxygen detached from the conductive material can be easily supplied to the semiconductor layer.

[0211] Furthermore, highly embedded conductive materials such as tungsten or polycrystalline silicon can be used as electrodes. Alternatively, a combination of highly embedded conductive materials with barrier layers (diffusion prevention layers) such as titanium layers, titanium nitride layers, or tantalum nitride layers can be used. Electrodes are sometimes referred to as "contact plugs."

[0212] In particular, the electrode that contacts the gate insulator is preferably made of a conductive material that does not easily allow impurities to pass through. Examples of conductive materials that do not easily allow impurities to pass through include tantalum nitride.

[0213] By using insulating materials that do not easily allow impurities to pass through as insulators and conductive materials that do not easily allow impurities to pass through as electrodes, the diffusion of impurities into the transistor can be further suppressed. Therefore, the reliability of the transistor can be further improved. In other words, the reliability of the semiconductor device can be further improved.

[0214] [Semiconductor layer]

[0215] As the semiconductor layer, one or more of the following can be used: single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor. As the semiconductor material, silicon or germanium can be used, for example. Furthermore, compound semiconductors or organic semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0216] Furthermore, when using organic semiconductors as semiconductor layers, low-molecular-weight organic materials with aromatic rings or π-electron conjugated conductive polymers can be used. For example, red fluorene, tetraphenylene, pentaphenylene, perylene diimide, tetracyanoquinone dimethyl ether, polythiophene, polyacetylene, and poly(p-phenylene vinylidene) can be used.

[0217] Semiconductor layers can also be stacked. When semiconductor layers are stacked, semiconductors with different crystal states can be used, as can different semiconductor materials.

[0218] Furthermore, since oxide semiconductors, as a type of metal oxide, have a band gap of 2 eV or more, transistors with extremely low off-state currents can be realized when oxide semiconductors are used as the semiconductor layer. Specifically, the off-state current can be set to less than 1 × 10⁻⁶ eV for a source-drain voltage of 3.5 V and a channel width of 1 μm at room temperature (typically 25 °C). -20 A. Less than 1×10-22 A or less than 1×10 -24 A. That is to say, the switching ratio can be 20 digits or more. Furthermore, in transistors using oxide semiconductors (OS transistors) as the semiconductor layer, the insulation withstand voltage between the source and drain is high. Therefore, transistors with high reliability can be provided. Furthermore, transistors with high output voltage and high withstand voltage can be provided. Furthermore, semiconductor devices with high reliability can be provided, etc. Furthermore, semiconductor devices with high output voltage and high withstand voltage can be provided.

[0219] Furthermore, in this specification and the like, a transistor using crystalline silicon in the semiconductor layer forming the channel is referred to as a "Si transistor".

[0220] Compared to OS transistors, crystalline Si transistors readily achieve higher mobility. However, crystalline Si transistors struggle to achieve the extremely low off-state currents of OS transistors. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer based on its purpose and application. For example, depending on the purpose or application, a combination of OS transistors and crystalline Si transistors may be used.

[0221] When using an oxide semiconductor layer as the semiconductor layer, it is preferable to form the oxide semiconductor layer by sputtering. Oxide semiconductor layers formed by sputtering have a higher density, making it preferred. When forming the oxide semiconductor layer by sputtering, a rare gas (typically argon), oxygen, or a mixture of a rare gas and oxygen can be used as the sputtering gas. Furthermore, it is necessary to ensure the high purity of the sputtering gas. For example, a high-purity gas with a dew point of -60°C or below, preferably -100°C or below, is used as the oxygen or rare gas used as the sputtering gas. By using a high-purity sputtering gas to form a thin film, the incorporation of moisture and other contaminants into the oxide semiconductor layer can be minimized.

[0222] When forming an oxide semiconductor layer by sputtering, it is preferable to remove as much moisture as possible from the film-forming chamber of the sputtering apparatus. For example, it is preferable to use an adsorption vacuum pump, such as a cryogenic pump, to perform high-vacuum evacuation (evacuating to 5 × 10⁻⁶ m³ / s) of the film-forming chamber. -7 Pa to 1×10 -4 (Approximately Pa). In particular, during the standby period of the sputtering apparatus, the partial pressure of gas molecules equivalent to H2O (equivalent to gas molecules with m / z = 18) in the film formation chamber is preferably 1 × 10⁻⁶ Pa. -4 Pa or less, more preferably 5×10 Pa -5 Below Pa.

[0223] [Metal Oxides]

[0224] Oxide semiconductors, as one type of metal oxide, preferably contain at least indium or zinc. Indium and zinc are particularly preferred. Furthermore, aluminum, gallium, yttrium, or tin are also preferred. Alternatively, one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium may be included.

[0225] Here, we consider the case where the oxide semiconductor contains indium, element M, and zinc. Note that element M can be aluminum, gallium, yttrium, or tin, etc. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of the above elements can sometimes be combined as element M.

[0226] Furthermore, in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Additionally, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0227] [Structure of metal oxides]

[0228] Oxide semiconductors, a type of metal oxide, are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0229] CAAC-OS exhibits c-axis orientation, with multiple nanocrystals linked along the ab-plane direction, resulting in a distorted crystal structure. Distortion refers to the change in the orientation of the lattice arrangement between regions with consistent lattice alignment and other regions with consistent lattice alignment within the linked nanocrystal region.

[0230] Nanocrystals are primarily hexagonal, but not limited to regular hexagons; sometimes they are non-regular hexagonal. Furthermore, nanocrystals sometimes exhibit pentagonal or heptagonal lattice arrangements during distortion. Moreover, in CAAC-OS, clear grain boundaries are difficult to observe even near the distortion. That is, it is known that lattice distortion can suppress grain boundary formation. This is because CAAC-OS can contain distortion due to the low density of oxygen atoms along the ab-plane or changes in interatomic bonding distance caused by the substitution of metal elements.

[0231] CAAC-OS tends to have a layered crystalline structure (also called a layered structure), in which layers containing indium and oxygen (hereinafter referred to as In layers) and layers containing elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. Furthermore, indium and element M can substitute for each other; when element M in a (M, Zn) layer is replaced by indium, the layer can also be represented as an (In, M, Zn) layer. Similarly, when indium in an In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0232] CAAC-OS is a highly crystalline metal oxide. Furthermore, distinct grain boundaries are not readily observed in CAAC-OS, thus reducing the likelihood of decreased electron mobility due to grain boundaries. Additionally, the crystallinity of metal oxides can sometimes decrease due to the incorporation of impurities or the formation of defects; therefore, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Consequently, metal oxides containing CAAC-OS exhibit stable physical properties. Therefore, metal oxides containing CAAC-OS possess excellent heat resistance and high reliability.

[0233] In nc-OS, the atomic arrangement in tiny regions (e.g., regions above 1 nm and below 10 nm, particularly above 1 nm and below 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed throughout the film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0234] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0235] Oxide semiconductors (metal oxides) have various structures and properties. One embodiment of the present invention may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0236] [Transistors containing metal oxides]

[0237] Next, the use of the aforementioned metal oxide in the channel formation region of a transistor will be explained.

[0238] By using the aforementioned metal oxides in the channel formation region of a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a transistor with high reliability can be achieved.

[0239] Furthermore, it is preferable to use metal oxides with low carrier density in transistors. Reducing the carrier density of the metal oxide film lowers the impurity concentration and thus the defect state density. In this specification, the state of low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". For example, the carrier density in the metal oxide can be lower than 8 × 10⁻⁶. 11 / cm 3 Preferably less than 1×10 11 / cm 3 More preferably, less than 1×10 10 / cm 3 And it is 1×10 -9 / cm 3 above.

[0240] Because high-purity intrinsic or substantially high-purity intrinsic metal oxide films have a low defect state density, they may have a low trap state density.

[0241] Furthermore, the charge trapped in the trap levels of metal oxides takes a long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical characteristics of transistors with channel formation regions in metal oxides with high trap state densities are sometimes unstable.

[0242] Therefore, reducing the impurity concentration in the metal oxide is effective in stabilizing the electrical characteristics of the transistor. To further reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0243] [Impurities]

[0244] Here, we will explain the effects of various impurities in metal oxides.

[0245] When a metal oxide contains silicon or carbon, one of Group 14 elements, defect energy levels are formed in the metal oxide. Therefore, the concentration of silicon or carbon in the metal oxide or near the metal oxide interface (the concentration measured by secondary ion mass spectrometry (SIMS)) is set to 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 17 atoms / cm 3 the following.

[0246] Furthermore, when the metal oxide contains alkali metals or alkaline earth metals, defect energy levels can sometimes be formed, leading to the formation of charge carriers. Therefore, transistors using metal oxides containing alkali metals or alkaline earth metals as the channel formation region tend to exhibit always-on characteristics. Consequently, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of alkali metals or alkaline earth metals in the metal oxide, as measured by SIMS, should be 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0247] When a metal oxide contains nitrogen, electrons are generated as charge carriers, increasing the carrier density, and the metal oxide is readily n-type. As a result, transistors using nitrogen-containing metal oxides in the channel formation region tend to exhibit always-on characteristics. Therefore, it is preferable to minimize the amount of nitrogen in the channel formation region of this metal oxide. For example, the nitrogen concentration in the metal oxide, as measured by SIMS, is less than 5 × 10⁻⁶. 19 atoms / cm 3 Preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0248] Hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Furthermore, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using hydrogen-containing metal oxides as the channel formation region tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the metal oxide. Specifically, the hydrogen concentration in the metal oxide, as measured by SIMS analysis, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 .

[0249] By using metal oxides with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0250] As a semiconductor used in transistors, a metal oxide film with high crystallinity is preferred. Using this film can improve the stability or reliability of the transistor. Examples of such films include, for instance, single-crystal metal oxide films or polycrystalline metal oxide films. However, forming single-crystal or polycrystalline metal oxide films on a substrate requires high-temperature or laser heating processes. Therefore, the manufacturing process becomes more expensive and throughput decreases.

[0251] Non-patent documents 1 and 2 report the discovery of In-Ga-Zn oxides (also known as CAAC-IGZO) with a CAAC structure in 2009. These documents report that CAAC-IGZO exhibits c-axis orientation, indistinct grain boundaries, and can be formed on substrates at low temperatures. Furthermore, transistors using CAAC-IGZO are reported to possess excellent electrical characteristics and reliability.

[0252] Furthermore, in 2013, an In-Ga-Zn oxide with an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Literature 3). It is reported here that the atomic arrangement of nc-IGZO in small regions (e.g., regions above 1 nm and below 3 nm) is periodic, and no regularity of crystal orientation is observed between different regions.

[0253] Non-Patent Documents 4 and 5 show the shift in average crystal size when the aforementioned CAAC-IGZO, nc-IGZO, and low-crystallinity IGZO films are irradiated with an electron beam, respectively. In the low-crystallinity IGZO film, approximately 1 nm of crystalline IGZO can be observed before electron beam irradiation. Therefore, Non-Patent Documents 4 and 5 report that the presence of a completely amorphous structure could not be confirmed in the IGZO. Furthermore, it is disclosed that CAAC-IGZO and nc-IGZO films exhibit higher stability relative to electron beam irradiation compared to the low-crystallinity IGZO film. Therefore, CAAC-IGZO or nc-IGZO films are preferably used as semiconductors for transistors.

[0254] Non-Patent Document 6 discloses a transistor using metal oxides with extremely low leakage current in the non-conducting state; specifically, the off-state current of the transistor is yA / μm per channel width of 1μm (10). -24 (A / μm) level (order). For example, a low-power CPU that utilizes the characteristic of low leakage current of transistors using metal oxides has been disclosed (see Non-Patent Document 7).

[0255] Furthermore, there are reports of applying transistors using metal oxide transistors to display devices, taking advantage of their low leakage current (see Non-Patent Document 8). In display devices, the displayed image is switched dozens of times per second. The number of image switches per second is called the "refresh rate." The refresh rate is sometimes referred to as the "drive frequency." Such high-speed image switching, which is difficult for the human eye to perceive, is considered a cause of eye fatigue. Therefore, a technique has been proposed to reduce the refresh rate of the display device to decrease the number of image rewrites. A drive with a lower refresh rate can reduce the power consumption of the display device. This drive method is called "idle stop (IDS) drive."

[0256] The discovery of CAAC and nc structures has contributed to improving the electrical characteristics and reliability of metal-oxide transistors using CAAC or nc structures, reducing manufacturing costs, and increasing throughput. Furthermore, research has been conducted on utilizing the low leakage current of these transistors for application in display devices and LSIs.

[0257] <Film Formation Methods>

[0258] Insulating materials used to form insulators, conductive materials used to form electrodes, and semiconductor materials used to form semiconductor layers can be obtained through sputtering, spin coating, CVD (Chemical Vapor Deposition) methods (including thermal CVD, MOCVD (Metal Organic Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), High Density Plasma CVD, LPCVD (Low Pressure CVD), APCVD (Atmospheric Pressure CVD), ALD (Atomic Layer Deposition), MBE (Molecular Beam Epitaxy), and PLD (Pulsed Laser Deposition). Deposition can be achieved through methods such as pulsed laser deposition, dip coating, spraying, droplet jetting (inkjet printing, etc.), and printing (screen printing, offset printing, etc.).

[0259] High-quality films can be obtained at lower temperatures using plasma CVD. In film deposition methods that do not use plasma, such as MOCVD, ALD, or thermal CVD, damage is less likely to occur on the formed surface. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes accumulate charge due to receiving charge from the plasma. This accumulated charge can sometimes damage these components. On the other hand, in plasma-free film deposition methods, since this plasma damage does not occur, the yield of semiconductor devices can be improved. Furthermore, without plasma damage during film deposition, films with fewer defects can be obtained.

[0260] Unlike film deposition methods that use particles released from a target material, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed by ALD have excellent step coverage and thickness uniformity, making ALD suitable for forming films covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other film deposition methods, such as CVD, which has a faster deposition rate.

[0261] The composition of the resulting film can be controlled by adjusting the flow rate ratio of the source gas in CVD or ALD methods. For example, when using CVD or ALD, films with arbitrary compositions can be formed by adjusting the flow rate ratio of the source gas. Furthermore, for example, when using CVD or ALD, films with continuously varying compositions can be formed by changing the flow rate ratio of the source gas while forming the film. When forming a film while changing the flow rate ratio of the source gas, the time required for conveying and adjusting the pressure can be eliminated, thus reducing the time required for film formation compared to using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0262] Note that when using the ALD method for film formation, it is preferable to use a chlorine-free gas as the material gas.

[0263] <Example 2 of transistor structure>

[0264] Reference Figures 7(A) to 7(C) A structural example of transistor 200B will be described. Figure 7(A) is a top view of transistor 200B. Figure 7(B) is a cross-sectional view along the dotted line L1-L2 in Figure 7(A). Figure 7(C) is a cross-sectional view along the dotted line W1-W2 in Figure 7(A). Furthermore, for clarity, some components are omitted in the top view of Figure 7(A).

[0265] Transistor 200B is a variation of transistor 200A. Therefore, to avoid repetition, we will mainly describe its differences from transistor 200A.

[0266] Furthermore, in the transistor 200B shown in FIG7, oxide 230c, insulator 250 and conductor 260 are disposed within the opening of insulator 280, separated by insulator 274. Additionally, oxide 230c, insulator 250 and conductor 260 are disposed between conductor 240s and conductor 240d.

[0267] Furthermore, oxide 230c is preferably formed within the opening of insulator 280, with insulator 274 in between. When insulator 274 is barrier, it can suppress the diffusion of impurities from insulator 280 into oxide 230.

[0268] Insulator 250 is used as the first gate insulator. Insulator 250 is preferably disposed in the opening of insulator 280, with oxide 230c and insulator 274 separated.

[0269] In this structure, an insulator 274 is provided between the insulator 280 and the transistor 200B. The insulator 274 is preferably made of an insulating material that has the function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen. For example, aluminum oxide and hafnium oxide are preferred. Furthermore, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, as well as silicon oxynitride and silicon nitride, can also be used.

[0270] By including insulator 274, impurities such as water and hydrogen in insulator 280 can be suppressed from diffusing into oxide 230b through oxide 230c and insulator 250. Furthermore, excess oxygen contained in insulator 280 can be suppressed from oxidizing conductor 260.

[0271] <Example 3 of transistor structure>

[0272] Figure 8 shows an example of a semiconductor device including transistor 200C. Figure 8(A) shows the top surface of the semiconductor device. Note that for clarity, some parts of the film are omitted in Figure 8(A). Furthermore, Figure 8(B) is a cross-sectional view corresponding to the dashed lines L1-L2 shown in Figure 8(A), and Figure 8(C) is a cross-sectional view corresponding to the dashed lines W1-W2.

[0273] Note that in the semiconductor device shown in FIG8, the same symbols are added to the constituent elements that have the same function as the constituent elements constituting the semiconductor devices shown in FIG2 to FIG4.

[0274] exist Figures 8(A) to 8(C)In this structure, a portion of the exposed surface of oxide 230b includes regions 231s and 231d without a conductor 240. One of regions 231s and 231d is used as a source region, and the other as a drain region. Furthermore, an insulator 273 is included between oxide 230b and insulator 274.

[0275] Region 231 (regions 231s and 231d) shown in Figure 8 is a region formed by adding elements described later to oxide 230b. Region 231 can be formed, for example, using a dummy gate.

[0276] Specifically, a dummy gate is formed on oxide 230b, which is then used as a mask to add an element that reduces the resistance of oxide 230b. In other words, the element is added to a region of oxide 230b that does not overlap with the dummy gate, thereby forming region 231. Methods for adding this element include: ion implantation by mass separation of the ionized source gas; ion doping by adding the element without mass separation of the ionized source gas; and plasma immersion ion implantation, etc.

[0277] In addition, boron or phosphorus are typical elements that contribute to the low resistivity of oxide 230. Other elements that can be used include hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. The concentration of this element can be measured using methods such as secondary ion mass spectrometry (SIMS).

[0278] In particular, boron and phosphorus are preferred as they can be used in production lines for amorphous silicon or low-temperature polycrystalline silicon. Existing setups can be used, thereby reducing equipment investment.

[0279] Next, insulating films serving as insulator 273 and insulator 274 can be formed on oxide 230b and the dummy gate. By providing a stack of insulating films serving as insulator 273 and insulator 274, a region overlapping region 231 with oxide 230c and insulator 250 can be provided.

[0280] Specifically, an insulating film becoming insulator 280 is formed on an insulating film becoming insulator 274. Then, CMP (Chemical Mechanical Polishing) is performed on the insulating film becoming insulator 280 to remove a portion of the insulating film becoming insulator 280, exposing the dummy gate. Next, when removing the dummy gate, it is preferable to also remove a portion of the insulator 273 that is in contact with the dummy gate. As a result, insulator 274 and insulator 273 are exposed on the side of the opening provided in insulator 280, and a portion of region 231 provided in oxide 230b is exposed on the bottom surface of the opening. Next, an oxide film becoming oxide 230c, an insulating film becoming insulator 220, and a conductive film becoming conductor 260 are sequentially formed in the opening. Then, CMP or the like is used to remove the oxide film becoming oxide 230c, the insulating film becoming insulator 220, and a portion of the conductive film becoming conductor 260 until insulator 280 is exposed, thereby forming the transistor shown in FIG8.

[0281] Note that insulators 273 and 274 are not necessarily required. They can be designed appropriately based on the required transistor characteristics.

[0282] The transistor shown in Figure 8 can utilize existing devices and does not require conductor 240, thereby reducing costs.

[0283] <Example 4 of a transistor structure>

[0284] Reference Figures 9(A) to 9(C) This section illustrates a structural example of transistor 200D. Figure 9(A) is a top view of transistor 200D. Figure 9(B) is a cross-sectional view of the portion indicated by dashed lines L1-L2 in Figure 9(A). Figure 9(C) is a cross-sectional view of the portion indicated by dashed lines W1-W2 in Figure 9(A). For clarity, some components are omitted in the top view of Figure 9(A).

[0285] Transistor 200D is a variation of transistor 200B described above. Therefore, to avoid repetition, the differences between transistor 200D and transistor 200B will be explained primarily.

[0286] The transistor 200D shown in Figure 9 has a conductor 242s disposed between a conductor 240s and an oxide 230b, and a conductor 242d disposed between a conductor 240d and an oxide 230b. Here, the conductor 240s (conductor 240d) has a region extending beyond the top surface of the conductor 242s (conductor 242d) and the side surface of the conductor 260, and contacts the top surface of the oxide 230b. Here, the conductor 242 can be any conductor that can be used for the conductor 240. Furthermore, the thickness of the conductor 242 is preferably at least thicker than that of the conductor 240. Additionally, in the transistor 200D shown in Figure 9, the conductor 205, which serves as the second gate electrode, is also used for wiring, and the conductor 203 is not provided.

[0287] Because transistor 200D shown in Figure 9 has the above-described structure, compared to transistor 200B, conductor 240 can be positioned closer to conductor 260. Alternatively, the ends of conductor 240s and conductor 240d can overlap conductor 260. This reduces the substantially longer channel of transistor 200D, thereby improving its on-state current and frequency characteristics.

[0288] Furthermore, conductors 242s (conductors 242d) preferably overlap with conductors 240s (conductors 240d). By employing this structure, when etching to form the opening of the buried plug 246s (plug 246d), conductors 242s (conductors 242d) are used as an etch stop layer to prevent over-etching of oxide 230b.

[0289] Furthermore, in the transistor 200D shown in FIG. 9, the insulator 245 may also be configured in contact with the insulator 244. The insulator 244 is preferably used as a barrier insulating film to prevent impurities such as water or hydrogen or excess oxygen from entering the transistor 200D from the insulator 280 side. As the insulator 245, an insulator that can be used for the insulator 244 can be used. In addition, as the insulator 245, nitride insulators such as aluminum nitride, titanium nitride, silicon nitride, or silicon oxynitride can also be used, for example.

[0290] Furthermore, in the transistor 200D shown in FIG. 9, unlike the transistor 200B shown in FIG. 7, the conductor 205 can also have a single-layer structure. In this case, an insulating film as an insulator 216 can be formed on the patterned conductor 205, and the top of the insulating film can be removed by chemical mechanical polishing (CMP) or the like until the top surface of the conductor 205 is exposed. Here, it is preferable to improve the flatness of the top surface of the conductor 205. For example, the average surface roughness (Ra) of the top surface of the conductor 205 can be 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. As a result, the flatness of the insulator formed on the conductor 205 can be improved, and the crystallinity of oxides 230b and 230c can be improved.

[0291] <Example 5 of transistor structure>

[0292] Reference Figures 10(A) to 10(C) This section illustrates a structural example of transistor 200E. Figure 10(A) is a top view of transistor 200E. Figure 10(B) is a cross-sectional view of the portion indicated by dashed lines L1-L2 in Figure 10(A). Figure 10(C) is a cross-sectional view of the portion indicated by dashed lines W1-W2 in Figure 10(A). For clarity, constituent elements are omitted in the top view of Figure 10(A).

[0293] Transistor 200E is a variation of the transistor described above. Therefore, to avoid repetition, the differences from the transistor described above will be explained primarily.

[0294] exist Figures 10(A) to 10(C) In this configuration, the conductor 205, which will be used as the second gate, is also used for wiring without conductor 203. Furthermore, an insulator 250 is included on oxide 230c, and a metal oxide 252 is included on insulator 250. Furthermore, a conductor 260 is included on metal oxide 252, and an insulator 270 is included on conductor 260. Furthermore, an insulator 271 is included on insulator 270.

[0295] The metal oxide 252 preferably has the function of suppressing oxygen diffusion. By providing the oxygen-suppressing metal oxide 252 between the insulator 250 and the conductor 260, oxygen diffusion to the conductor 260 is suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen can be suppressed.

[0296] Furthermore, the metal oxide 252 can be used as part of the first gate electrode. For example, an oxide semiconductor that can be used as oxide 230 can be used as the metal oxide 252. In this case, by forming the conductor 260 using a sputtering method, the resistance value of the metal oxide 252 can be reduced, making it a conductive layer.

[0297] Furthermore, metal oxide 252 is sometimes used as part of the first gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, a metal oxide that is a high-k material with a high relative permittivity is preferably used as the metal oxide 252. By employing this stacked structure, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0298] Although the metal oxide 252 in transistor 200E is shown as a single-layer structure, a stacked structure of two or more layers can also be used. For example, a metal oxide used as part of the first gate electrode and a metal oxide used as part of the first gate insulator can be stacked.

[0299] When metal oxide 252 is used as the first gate electrode, the on-state current of transistor 200E can be increased without weakening the effect of the electric field from conductor 260. Furthermore, when metal oxide 252 is used as the first gate insulator, leakage current between conductor 260 and oxide 230 can be suppressed by maintaining the distance between conductor 260 and oxide 230 using the physical thickness of insulator 250 and metal oxide 252. Thus, by providing a stacked structure of insulator 250 and metal oxide 252, the physical distance between conductor 260 and oxide 230 and the electric field strength applied from conductor 260 to oxide 230 can be easily adjusted.

[0300] Specifically, the oxide semiconductor that can be used as oxide 230 can be used as metal oxide 252 by making it low-resistive. Alternatively, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium and magnesium can be used.

[0301] In particular, alumina, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as insulators. Hafnium aluminate, in particular, has higher heat resistance than hafnium oxide films. Therefore, it is less prone to crystallization during the thermal runaway processes in subsequent steps, making it preferred. Note that metal oxide 252 is not an essential component and can be appropriately designed according to the desired transistor characteristics.

[0302] The insulator 270 preferably uses an insulating material that inhibits the permeation of impurities such as water or hydrogen, as well as oxygen. For example, alumina or hafnium oxide is preferred. This prevents the conductor 260 from oxidizing due to oxygen from above the insulator 270. Furthermore, it inhibits impurities such as water or hydrogen from above the insulator 270 from entering the oxide 230 through the conductor 260 and the insulator 250.

[0303] Insulator 271 is used as a hard mask. By providing insulator 271, conductor 260 can be processed in such a way that the side of conductor 260 is substantially perpendicular to the substrate surface. Specifically, the angle formed between the side of conductor 260 and the substrate surface can be 75° or more and 100° or less, preferably 80° or more and 95° or less.

[0304] Alternatively, the insulator 271 can also function as a barrier layer by using an insulating material that inhibits the permeation of impurities such as water, hydrogen, and oxygen. In this case, the insulator 270 may not be required.

[0305] By using insulator 271 as a hard mask, selectively removing a portion of insulator 270, conductor 260, metal oxide 252, insulator 250, and oxide 230c can make their sides roughly the same and expose a portion of the surface of oxide 230b.

[0306] Furthermore, transistor 200E has regions 231s and 231d on a portion of the exposed oxide 230b surface. One of regions 231s and 231d is used as a source region, and the other is used as a drain region.

[0307] For example, by using ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment, impurity elements such as phosphorus or boron can be introduced onto the surface of the exposed oxide 230b, thereby forming regions 231s and 231d. Note that in this embodiment, "impurity element" refers to an element other than the main component element.

[0308] Alternatively, a metal film can be formed after a portion of the surface of oxide 230b is exposed, followed by a heat treatment to diffuse the elements contained in the metal film into oxide 230b, thereby forming regions 231s and 231d.

[0309] The resistivity decreases in the region of oxide 230b where impurity elements are introduced. Therefore, regions 231s and 231d are sometimes referred to as "impurity regions" or "low-resistance regions".

[0310] By using insulator 271 or conductor 260 as a mask, regions 231s and 231d can be formed in a self-aligned manner. Therefore, regions 231s and 231d do not overlap with conductor 260, reducing parasitic capacitance. Furthermore, the bias region is not formed between the channel formation region and the source / drain regions (regions 231s and 231d). By forming regions 231s and 231d in a self-aligned manner, it is possible to achieve increased on-state current, decreased threshold voltage, and increased operating frequency.

[0311] Furthermore, to further reduce the off-state current, a bias region can be provided between the channel formation region and the source / drain region. The bias region is a region with high resistivity and is a region where the aforementioned impurity elements are not introduced. This bias region can be formed by introducing the aforementioned impurity elements after forming the insulator 275. In this case, the insulator 275 is also used as a mask, similar to the insulator 271. Therefore, the region of oxide 230b overlapping with the insulator 275 is not introduced with impurity elements, thereby maintaining a high resistivity in this region.

[0312] Transistor 200E includes an insulator 275 on the sides of insulator 270, conductor 260, metal oxide 252, insulator 250, and oxide 230c. The insulator 275 is preferably an insulator with a low relative permittivity. For example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, porous silicon oxide, and resin are preferred. In particular, when silicon oxide, silicon oxynitride, silicon oxynitride, or porous silicon oxide is used for the insulator 275, excess oxygen regions can easily form in the insulator 275 in subsequent processes, which is preferred. Furthermore, silicon oxide and silicon oxynitride have thermal stability, so they are preferred. In addition, the insulator 275 preferably has oxygen-diffusing properties.

[0313] Furthermore, transistor 200E includes insulator 274 on insulator 275 and oxide 230. Insulator 274 is preferably formed by sputtering. By using sputtering, an insulator with few impurities such as water or hydrogen can be formed. For example, aluminum oxide is preferably used as insulator 274.

[0314] Sometimes, hydrogen is extracted from the structure formed by sputtering to create an oxide film. Therefore, insulator 274 extracts hydrogen and water from oxide 230 and insulator 275, thereby reducing the hydrogen concentration in oxide 230 and insulator 275.

[0315] This embodiment can be implemented by appropriately combining the structures described in other embodiments, examples, etc.

[0316] (Implementation Method 3)

[0317] In this embodiment, referring to FIGS. 11 and 12, a storage device (hereinafter sometimes referred to as an OS storage device) using an oxide-based semiconductor transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor according to one aspect of the present invention will be described. An OS storage device is a storage device that includes at least a capacitor and an OS transistor for controlling the charging and discharging of the capacitor. Because the off-state current of an OS transistor is extremely small, an OS storage device has excellent retention characteristics and can therefore be used as a non-volatile memory.

[0318] <Structure Examples of Storage Devices>

[0319] Figure 11(A) shows an example of the structure of an OS storage device. The storage device 1400 includes peripheral circuitry 1411 and a storage cell array 1470. The peripheral circuitry 1411 includes row circuitry 1420, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460.

[0320] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is the wiring connected to the memory cells included in the memory cell array 1470, and its details are described below. The amplified data signal, as the data signal RDATA, is output to the outside of the memory device 1400 via the output circuit 1440. Furthermore, the row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and can select the row to be accessed.

[0321] The storage device 1400 is supplied with a low power supply voltage (VSS), the peripheral circuit 1411 is supplied with a high power supply voltage (VDD), and the memory cell array 1470 is supplied with a high power supply voltage (VIL). In addition, the storage device 1400 receives external control signals (CE, WE, RE), address signals ADDR, and data signals WDATA. The address signal ADDR is input to the row decoder and column decoder, and WDATA is input to the write circuit.

[0322] The control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row and column decoders. CE is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals can be input as needed.

[0323] The memory cell array 1470 includes a plurality of memory cells MCs configured in a row and column configuration and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a column, etc. Furthermore, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a row, etc.

[0324] Furthermore, although an example showing the peripheral circuit 1411 and the memory cell array 1470 forming on the same plane is illustrated in FIG11(A), this embodiment is not limited thereto. For example, as shown in FIG11(B), the memory cell array 1470 may also be arranged in a manner overlapping a portion of the peripheral circuit 1411. For example, a structure in which the readout amplifier is arranged overlapping the memory cell array 1470 may also be adopted.

[0325] Figure 12 illustrates a structural example of a storage cell that can be applied to the aforementioned storage cell MC.

[0326] [DOSRAM]

[0327] Figures 12(A) to 12(C) An example of the circuit structure of a DRAM memory cell is shown. In this specification and other materials, DRAM using a 1OS transistor 1 capacitor type memory cell is sometimes referred to as DOSRAM. The memory cell 1471 shown in FIG12(A) includes a transistor M1 and a capacitor CA. Furthermore, the transistor M1 includes a gate (sometimes called the top gate) and a back gate.

[0328] The first terminal of transistor M1 is connected to the first terminal of capacitor CA. The second terminal of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor CA is connected to wiring CAL.

[0329] Wiring BIL is used as the bit line, and wiring WOL is used as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CA. During data writing and reading, it is preferable to apply a low-level potential to wiring CAL. Wiring BGL is used to apply a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0330] Furthermore, the memory cell MC is not limited to memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also adopt a structure like memory cell 1472 shown in FIG12(B), where the back gate of transistor M1 is not connected to wiring BGL, but connected to wiring WOL. Furthermore, for example, the memory cell MC can also be a memory cell composed of a single-gate transistor, i.e., a transistor M1 without a back gate, as shown in memory cell 1473 in FIG12(C).

[0331] When the semiconductor device shown in the above embodiment is used in memory cell 1471, the transistor shown in the previous embodiment can be used as transistor M1. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made extremely low. In other words, since the written data can be held by transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, the memory cell refresh operation can be eliminated. In addition, since the leakage current is extremely low, multi-valued data or analog data can be stored in memory cells 1471, 1472, and 1473.

[0332] Furthermore, in DOSRAM, when the read amplifier is arranged in a manner overlapping the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance, thereby reducing the storage capacitance of the memory cells.

[0333] [NOSRAM]

[0334] Figures 12(D) to 12(H) An example circuit structure of a gain-cell type memory cell with two transistors and one capacitor is shown. The memory cell 1474 shown in Figure 12(D) includes transistor M2, transistor M3, and capacitor CB. Furthermore, transistor M2 includes a top gate (sometimes simply referred to as the gate) and a back gate. In this specification and the like, a memory device including a gain-cell type memory cell that uses an OS transistor for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0335] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; transistor M2's gate is connected to wiring WOL; and transistor M2's back gate is connected to wiring BGL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0336] Wiring WBL is used as the write bit line, wiring RBL is used as the read bit line, and wiring WOL is used as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CB. It is preferable to apply a low-level potential to wiring CAL during data writing, holding, and reading. Wiring BGL is used to apply a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0337] Furthermore, the memory cell MC is not limited to memory cell 1474, and its circuit structure can be appropriately modified. For example, the memory cell MC can also adopt a structure where the back gate of transistor M2 is not connected to wiring BGL, but connected to wiring WOL, as shown in memory cell 1475 in FIG12(E). Furthermore, for example, the memory cell MC can also be a memory cell composed of a single-gate transistor, i.e., a transistor M2 without a back gate, as shown in memory cell 1476 in FIG12(F). Furthermore, for example, the memory cell MC can also have a structure where wiring WBL and wiring RBL are combined into a single wiring BIL, as shown in memory cell 1477 in FIG12(G).

[0338] When the semiconductor device shown in the above embodiment is used in memory cell 1474, the transistor M2 can be the transistor shown in the previous embodiment. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be made extremely low. Therefore, since the written data can be held by transistor M2 for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, memory cell refresh operations can be eliminated. Moreover, due to the extremely low leakage current, multi-valued data or analog data can be held in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0339] Furthermore, transistor M3 can also be a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of a Si transistor can be n-channel or p-channel. The field-effect mobility of a Si transistor is sometimes higher than that of an OS transistor. Therefore, a Si transistor can also be used as the readout transistor M3. Furthermore, by using a Si transistor in transistor M3, transistor M2 can be stacked on top of transistor M3, thereby reducing the footprint of the memory cell and enabling high integration of the memory device.

[0340] Furthermore, transistor M3 can also be an OS transistor. When OS transistors are used for transistors M2 and M3, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0341] Furthermore, Figure 12(H) shows an example of a gain-cell type memory cell with 3 transistors and 1 capacitor. The memory cell 1478 shown in Figure 12(H) includes transistors M4 to M6 and capacitor CC. Capacitor CC can be appropriately configured. Memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that supplies a low-level potential. Alternatively, memory cell 1478 can be electrically connected to wiring RBL and wiring WBL without being electrically connected to wiring BIL.

[0342] Transistor M4 is an OS transistor that includes a back gate, which is electrically connected to wiring BGL. Alternatively, the back gate and gate of transistor M4 can be electrically connected to each other. Or, transistor M4 may not include a back gate.

[0343] Furthermore, transistors M5 and M6 can each be either n-channel or p-channel Si transistors. Alternatively, transistors M4 through M6 can all be OS transistors. In this case, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0344] When the semiconductor device shown in the above embodiment is used in the memory cell 1478, the transistor shown in the previous embodiment can be used as transistor M4. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be made extremely low.

[0345] Note that the structure of the peripheral circuit 1411, the memory cell array 1470, etc. shown in this embodiment is not limited to the structure described above. Furthermore, the configuration or function of these circuits and the wiring, circuit elements, etc., connected to them can be changed, removed, or added as needed.

[0346] This embodiment can be implemented by appropriately combining the structures described in other embodiments, examples, etc.

[0347] (Implementation Method 4)

[0348] In this embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted will be described with reference to FIG13. Multiple circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating multiple circuits (systems) on a single chip is sometimes referred to as a System on Chip (SoC).

[0349] As shown in Figure 13(A), the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0350] A bump (not shown) is provided on the chip 1200, which is connected to the first side of the printed circuit board (PCB) 1201 as shown in FIG13(B). In addition, a plurality of bumps 1202 are provided on the back side of the first side of the PCB 1201, which are connected to the motherboard 1203.

[0351] Alternatively, storage devices such as DRAM 1221 and flash memory 1222 can be provided on the motherboard 1203. For example, the DOSRAM shown in the above embodiment can be applied to the DRAM 1221. Furthermore, for example, the NOSRAM shown in the above embodiment can be applied to the flash memory 1222.

[0352] CPU 1211 preferably has multiple CPU cores. Furthermore, GPU 1212 preferably has multiple GPU cores. Additionally, CPU 1211 and GPU 1212 may each have a memory for temporary data storage. Alternatively, a memory shared by both CPU 1211 and GPU 1212 may be provided on chip 1200. The aforementioned NOSRAM or DOSRAM can be used in this memory. Furthermore, GPU 1212 is suitable for parallel computation of multiple data sets, and can be used for image processing or product operations. By incorporating an image processing circuit or product operation circuit using the oxide semiconductor of the present invention as GPU 1212, image processing and product operations can be performed with low power consumption.

[0353] Furthermore, since the CPU1211 and GPU1212 are located on the same chip, the wiring between the CPU1211 and GPU1212 can be shortened, and data transfer from the CPU1211 to the GPU1212, data transfer between the memory of the CPU1211 and GPU1212, and transfer of the operation result from the GPU1212 to the CPU1211 after the operation in the GPU1212 is completed can be performed at high speed.

[0354] The analog arithmetic unit 1213 includes one or both of an analog-to-data (A / D) conversion circuit and a data-to-analog (D / A) conversion circuit. Alternatively, the aforementioned product summation circuit may also be provided in the analog arithmetic unit 1213.

[0355] The storage controller 1214 has circuitry that serves as a controller for the DRAM 1221 and circuitry that serves as an interface for the flash memory 1222.

[0356] Interface 1215 has interface circuitry for connecting to external devices such as display devices, speakers, microphones, imaging devices, and controllers. Controllers include mice, keyboards, and game console controllers. As the aforementioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc., can be used.

[0357] Network circuit 1216 includes network circuits such as LAN (Local Area Network). Additionally, it may include network security circuits.

[0358] The aforementioned circuit (system) can be formed on chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, no additional manufacturing process is required, and chip 1200 can be manufactured at low cost.

[0359] The motherboard 1203, which includes a PCB 1201 with a chip 1200 having a GPU 1212, a DRAM 1221, and a flash memory 1222, can be referred to as a GPU module 1204.

[0360] The GPU module 1204 can reduce its size due to the presence of the chip 1200 using SoC technology. Furthermore, the GPU module 1204, with its high image processing capabilities, is suitable for use in portable electronic devices such as smartphones, tablets, laptops, and portable game consoles. Moreover, by utilizing the product-summing circuitry of the GPU 1212, methods such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN) can be executed, thereby enabling the chip 1200 to be used as an AI chip, or the GPU module to be used as an AI system module.

[0361] The structure shown in this embodiment can be appropriately combined with the structures shown in other embodiments, examples, etc.

[0362] (Implementation Method 5)

[0363] In this embodiment, an application example of a storage device using the semiconductor device described in the above embodiments is explained. The semiconductor device described in the above embodiments can be applied, for example, to storage devices in various electronic devices (e.g., information terminals, computers, smartphones, e-book reader terminals, digital cameras (including camcorders), video recording devices, navigation systems, etc.). Note that here, "computer" includes tablet computers, notebook computers, desktop computers, and mainframe computers such as server systems. Alternatively, the semiconductor device described in the above embodiments can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB storage devices, and SSDs (solid-state drives). Figure 14 schematically illustrates several structural examples of removable storage devices. For example, the semiconductor device described in the above embodiments is fabricated into a packaged memory chip and used in various storage devices or removable memories.

[0364] Figure 14(A) is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed within the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device shown in the above embodiment can be assembled on the substrate 1104, such as the memory chip 1105.

[0365] Figure 14(B) is a schematic diagram of the external appearance of the SD card, and Figure 14(C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed within the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 1113. Thus, through wireless communication between the host device and the SD card 1110, data can be read from and written to the memory chip 1114. The semiconductor devices shown in the above embodiments can be assembled on the substrate 1113, such as the memory chip 1114.

[0366] Figure 14(D) is a schematic diagram of the external appearance of the SSD, and Figure 14(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled onto the memory chip 1154 on the substrate 1153.

[0367] This embodiment can be implemented by appropriately combining the structures described in other embodiments, examples, etc.

[0368] (Implementation Method 6)

[0369] In this embodiment, a display device and a display module are described as an example of a semiconductor device using transistors disclosed in this specification.

[0370] Furthermore, transistors using oxide semiconductors, as described below with reference to transistor 200, are sometimes referred to as OS transistors.

[0371] <Display Device>

[0372] Next, an example of a display device that can use the above-described transistors and / or semiconductor devices will be described. Figure 15(A) is a block diagram illustrating a structural example of the display device 500.

[0373] The display device 500 shown in Figure 15(A) includes a driving circuit 511, a driving circuit 521a, a driving circuit 521b, and a display area 531. In addition, the driving circuits 511, 521a, and 521b are sometimes collectively referred to as "driving circuits" or "peripheral driving circuits".

[0374] The driving circuits 521a and 521b can be used as, for example, scan line driving circuits. Furthermore, the driving circuit 511 can be used as, for example, a signal line driving circuit. Alternatively, only one of the driving circuits 521a and 521b may be provided. Furthermore, a certain circuit may be provided at a position opposite to the driving circuit 511 across the display area 531.

[0375] Furthermore, the display device 500 shown in FIG15(A) includes p wirings 535 arranged substantially parallel to each other and controlled by driving circuits 521a and / or 521b, and q wirings 536 arranged substantially parallel to each other and controlled by driving circuit 511 (p and q are natural numbers greater than 1). The display area 531 includes a plurality of pixels 532 arranged in a matrix. Each pixel 532 includes pixel circuitry 534 and a display element.

[0376] Furthermore, full-color display can be achieved by using three pixels 532 as one pixel. The three pixels 532 control the transmittance, reflectance, or luminous intensity of red, green, or blue light, respectively. Moreover, the color of the light controlled by the three pixels 532 is not limited to a combination of red, green, and blue; it can also be yellow, cyan, or magenta.

[0377] In addition to the pixels controlling red, green, and blue light, a pixel 532 can be added to control white light, and four pixels 532 can be used as one pixel. By adding a pixel 532 to control white light, the brightness of the display area can be increased. Furthermore, by increasing the number of pixels 532 used as one pixel, red, green, blue, yellow, cyan, and magenta can be appropriately combined and used, thereby expanding the color gamut that can be reproduced.

[0378] When the pixels are configured in a matrix of 1920×1080, a display device 500 capable of displaying at a resolution known as Full HD (also called "2K resolution," "2K1K," or "2K," etc.) can be achieved. Furthermore, for example, when the pixels are configured in a matrix of 3840×2160, a display device 500 capable of displaying at a resolution known as Ultra HD (also called "4K resolution," "4K2K," or "4K," etc.) can be achieved. Furthermore, for example, when the pixels are configured in a matrix of 7680×4320, a display device 500 capable of displaying at a resolution known as Ultra HD (also called "8K resolution," "8K4K," or "8K," etc.) can be achieved. By increasing the number of pixels, a display device 500 capable of displaying at a resolution of 16K or 32K can also be achieved.

[0379] The wiring 535_g in row g (where g is a natural number greater than 1 and less than p) is electrically connected to q pixels 532 in row g among the plurality of pixels 532 arranged in row p and column q in the display area 531. Furthermore, the wiring 536_h in column h (where h is a natural number greater than 1 and less than q) is electrically connected to p pixels 532 in column h among the pixels 532 arranged in row p and column q.

[0380] [Display Components]

[0381] The display device 500 can take various forms or incorporate various display elements. Examples of display elements include display media whose contrast, brightness, reflectivity, and transmittance vary due to electrical or magnetic effects, such as EL (electroluminescent) elements (organic EL elements, inorganic EL elements, or EL elements containing both organic and inorganic materials), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron emission elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLV), display elements using MEMS (microelectromechanical systems), digital micromirror devices (DMD), DMS (digital micro-shutter), MIRASOL (registered trademark), IMOD (interferometric modulation) elements, shutter-type MEMS display elements, optical interference-type MEMS display elements, electrowetting elements, piezoelectric ceramic displays, and display elements using carbon nanotubes. Furthermore, quantum dots can be used as display elements.

[0382] Examples of display devices using EL elements include EL displays. Examples of display devices using electron emission elements include field emission displays (FEDs) or surface-conduction electron-emitter displays (SEDs). Examples of display devices using quantum dots include quantum dot displays. Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, intuitive liquid crystal displays, and projective liquid crystal displays). Examples of display devices using electronic ink, electronic powder fluid (registered trademark), or electrophoretic elements include electronic paper. Furthermore, display devices can also be plasma display panels (PDPs). Additionally, display devices can also be retinal scanning imaging devices.

[0383] Note that when implementing a transflective or reflective liquid crystal display, it is sufficient to make part or all of the pixel electrodes function as reflective electrodes. For example, part or all of the pixel electrodes can be made of aluminum, silver, etc. Furthermore, storage circuits such as SRAM can be placed below the reflective electrodes. This further reduces power consumption.

[0384] Note that when using LEDs, graphene or graphite can also be disposed under the electrodes or nitride semiconductors of the LED. Graphene or graphite can also be a multilayer film with multiple layers stacked. Thus, by providing graphene or graphite, it is easier to form nitride semiconductors, such as crystalline n-type GaN semiconductor layers, on it. Furthermore, by providing crystalline p-type GaN semiconductor layers, LEDs can be constructed. Additionally, an AlN layer can be disposed between the graphene or graphite and the crystalline n-type GaN semiconductor layer. Furthermore, the GaN semiconductor layer included in the LED can also be formed by MOCVD. Note that the GaN semiconductor layer included in the LED can also be formed by sputtering graphene.

[0385] Figures 15(B), 15(C), 16(A), and 16(B) show examples of circuit structures that can be used for pixel 532.

[0386] [An example of a pixel circuit used in a light-emitting display device]

[0387] The pixel circuit 534 shown in Figure 15(B) includes transistor 461, capacitor 463, transistor 468, and transistor 464. Furthermore, the pixel circuit 534 shown in Figure 15(B) is electrically connected to a light-emitting element 469 that can be used as a display element.

[0388] The OS transistor can be used as transistor 461, transistor 468, and transistor 464. In particular, it is preferred to use the OS transistor as transistor 461.

[0389] One of the source and drain of transistor 461 is electrically connected to wiring 536_h. Furthermore, the gate of transistor 461 is electrically connected to wiring 535_g. Video signals are supplied from wiring 536_h.

[0390] Transistor 461 has the function of controlling the writing of video signals to node 465.

[0391] One of the two electrodes of capacitor 463 is electrically connected to node 465, and the other is electrically connected to node 467. Additionally, the other of the source and drain electrodes of transistor 461 is electrically connected to node 465.

[0392] Capacitor 463 functions as a storage capacitor to hold data written to node 465.

[0393] One of the source and drain of transistor 468 is electrically connected to the potential supply line VL_a, and the other is electrically connected to node 467. Furthermore, the gate of transistor 468 is electrically connected to node 465.

[0394] One of the source and drain of transistor 464 is electrically connected to the potential supply line V0, and the other is electrically connected to node 467. Furthermore, the gate of transistor 464 is electrically connected to wiring 535_g.

[0395] One of the anode and cathode of the light-emitting element 469 is electrically connected to the potential supply line VL_b, and the other is electrically connected to node 467.

[0396] As the light-emitting element 469, for example, an organic electroluminescent element (also known as an organic EL element) can be used. However, the light-emitting element 469 is not limited to this, and for example, an inorganic EL element made of inorganic materials can also be used.

[0397] For example, a high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other.

[0398] In the display device 500 having the pixel circuit 534 of FIG15(B), the pixels 532 of each row are selected sequentially by the driving circuit 521a and / or the driving circuit 521b, so that the transistors 461 and 464 are turned on to write the video signal to the node 465.

[0399] When transistors 461 and 464 are in the off state, pixel 532, where data is written to node 465, is held in a holding state. Furthermore, the amount of current flowing between the source and drain electrodes of transistor 468 is controlled according to the potential of the data written to node 465, and the light-emitting element 469 emits light with a brightness corresponding to the amount of current flowing through it. By performing the above steps line by line, an image can be displayed.

[0400] Alternatively, transistors with a back gate can be used as transistors 461, 464, and 468, as shown in Figure 16(A). In transistors 461 and 464 shown in Figure 16(A), the gate and the back gate are electrically connected. Therefore, the gate and the back gate are always at the same potential. Furthermore, in transistor 468, the back gate is electrically connected to node 467. Therefore, the back gate and node 467 are always at the same potential.

[0401] The above-mentioned OS transistor can be used as at least one of transistor 461, transistor 468 and transistor 464.

[0402] [An example of a pixel circuit for a liquid crystal display device]

[0403] The pixel circuit 534 shown in Figure 15(C) includes a transistor 461 and a capacitor 463. Furthermore, the pixel circuit 534 shown in Figure 15(C) is electrically connected to a liquid crystal element 462 that can be used as a display element. Preferably, an OS transistor is used as transistor 461.

[0404] The potential of one of the pairs of electrodes of liquid crystal element 462 is appropriately set according to the specifications of pixel circuit 534. For example, a common potential (common potential) or the same potential as the capacitor line CL described below can be applied to one of the pairs of electrodes of liquid crystal element 462. Alternatively, different potentials can be applied to one of the pairs of electrodes of liquid crystal element 462 in each pixel 532. The other of the pairs of electrodes of liquid crystal element 462 is electrically connected to node 466. The orientation state of liquid crystal element 462 depends on the data written to node 466.

[0405] As a driving method for a display device having liquid crystal element 462, for example, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, VA mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. In addition to the methods mentioned above, other driving methods for display devices include ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, and guest-host mode. However, it is not limited to these; various liquid crystal elements and their driving methods can be used as driving methods for display devices.

[0406] When liquid crystal elements are used as display components, thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, high-molecular-weight dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals can be used. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, etc., depending on the conditions.

[0407] Alternatively, a liquid crystal exhibiting a blue phase can be used without an alignment film. The blue phase is a type of liquid crystal phase that appears just before the cholesteric liquid crystal transitions to an isotropic phase when the temperature is raised. Since the blue phase only appears within a narrow temperature range, a liquid crystal composition containing 5 wt.% or more of a chiral reagent is used in the liquid crystal layer to improve the temperature range. Because the liquid crystal composition, including the blue phase liquid crystal and the chiral reagent, has a short response speed (less than 1 msec) and is optically isotropic, alignment processing is not required, and viewing angle dependence is low. Furthermore, since an alignment film is not required and rubbing is unnecessary, electrostatic damage caused by rubbing can be prevented, thereby reducing defects and breakage of the liquid crystal display device during manufacturing. Therefore, the productivity of the liquid crystal display device can be improved.

[0408] Alternatively, a method called multidomaining or multidomain design can be used, which divides a pixel into several regions (sub-pixels) and causes the molecules to tilt in different directions.

[0409] Furthermore, the inherent resistance of liquid crystal materials is 1×10⁻⁶. 9 Ω·cm or higher, preferably 1×10 11 Ω·cm or more, more preferably 1×10 12 Ω·cm or higher. Furthermore, the inherent resistance values ​​in this specification are measured at 20°C.

[0410] In the pixel circuit 534 at row g and column h, one of the source and drain of transistor 461 is electrically connected to wiring 536_h, and the other is electrically connected to node 466. The gate of transistor 461 is electrically connected to wiring 535_g. Wiring 536_h supplies video signals. Transistor 461 has the function of controlling the writing of video signals to node 466.

[0411] One of the pair of electrodes of capacitor 463 is electrically connected to a wiring supplied with a specific potential (hereinafter referred to as capacitor line CL), and the other is electrically connected to node 466. Furthermore, the potential value of capacitor line CL is appropriately set according to the specifications of pixel circuit 534. Capacitor 463 functions as a storage capacitor to hold data written to node 466.

[0412] For example, in a display device 500 including the pixel circuit 534 of FIG15(C), the pixel circuits 534 of each row are selected sequentially by the driving circuit 521a and / or the driving circuit 521b, so that the transistor 461 is turned on to write video signals to the node 466.

[0413] Node 466 is written into the pixel circuit 534 of the video signal, which then becomes a hold-up state when transistor 461 is in the off state. By performing the above steps row by row, an image can be displayed on the display area 531.

[0414] Alternatively, a transistor with a back gate can be used as transistor 461, as shown in Figure 16(B). The gate of transistor 461 shown in Figure 16(B) is electrically connected to the back gate. Therefore, the gate and the back gate are always at the same potential.

[0415] [Example of peripheral circuit structure]

[0416] Figure 17(A) shows a structural example of drive circuit 511. Drive circuit 511 includes shift register 512, latch circuit 513, and buffer 514. Furthermore, Figure 17(B) shows a structural example of drive circuit 521a. Drive circuit 521a includes shift register 522 and buffer 523. Drive circuit 521b may also have the same structure as drive circuit 521a.

[0417] Shift registers 512 and 522 are input with start pulse SP, clock signal CLK, etc.

[0418] [Structure Example of a Display Device]

[0419] By utilizing the OS transistors shown in the above embodiments, a part or all of the driving circuit including the shift register can be formed on the same substrate as the pixel portion to form a system-on-panel.

[0420] In this embodiment, structural examples of a display device using a liquid crystal element and a display device using an EL element will be described. In FIG18(A), a sealant 4005 is provided around a pixel portion 4002 disposed on a first substrate 4001, and the pixel portion 4002 is sealed using the sealant 4005 and a second substrate 4006. In FIG18(A), a signal line driving circuit 4003 and a scan line driving circuit 4004 formed on a separately prepared substrate using single-crystal semiconductors or polycrystalline semiconductors are mounted in a region on the first substrate 4001 that is different from the region surrounded by the sealant 4005. Furthermore, various signals and potentials supplied to the separately formed signal line driving circuit 4003, scan line driving circuit 4004, or pixel portion 4002 are supplied from FPC 4018a (FPC: Flexible Printed Circuit) and FPC 4018b.

[0421] In Figures 18(B) and 18(C), a sealant 4005 is provided around the pixel portion 4002 and the scan line drive circuit 4004 disposed on the first substrate 4001. Furthermore, a second substrate 4006 is disposed on the pixel portion 4002 and the scan line drive circuit 4004. Therefore, the pixel portion 4002 and the scan line drive circuit 4004, together with the display element, are sealed by the first substrate 4001, the sealant 4005, and the second substrate 4006. In Figures 18(B) and 18(C), a signal line drive circuit 4003 formed on a separately prepared substrate using a single-crystal semiconductor or a polycrystalline semiconductor is mounted in a region on the first substrate 4001 that is different from the region surrounded by the sealant 4005. In Figures 18(B) and 18(C), various signals and potentials supplied to the signal line drive circuit 4003, the scan line drive circuit 4004, or the pixel portion 4002 are supplied from the FPC 4018.

[0422] Although Figures 18(B) and 18(C) show examples of separately forming a signal line drive circuit 4003 and mounting it to the first substrate 4001, the structure is not limited to this. A separate scan line drive circuit can be formed and mounted, or only a portion of the signal line drive circuit or a portion of the scan line drive circuit can be separately formed and mounted.

[0423] Furthermore, there are no particular restrictions on the connection method for the separately formed drive circuit, and wire bonding, COG (Chip On Glass) packaging, TCP (Tape Carrier Package), COF (Chip On Film) packaging, etc. can be used. Figure 18(A) shows an example of mounting the signal line drive circuit 4003 and the scan line drive circuit 4004 using the COG method, Figure 18(B) shows an example of mounting the signal line drive circuit 4003 using the COG method, and Figure 18(C) shows an example of mounting the signal line drive circuit 4003 using the TCP method.

[0424] In addition, display devices sometimes include a panel in which the display element is sealed and a module, including an IC and a controller, which is installed in the panel.

[0425] Furthermore, the pixel portion and scan line driving circuit disposed on the first substrate include multiple transistors, and the OS transistors shown in the above embodiments can be applied.

[0426] Figures 19(A) and 19(B) are cross-sectional views showing the cross-sections formed by the portion indicated by the dashed lines N1-N2 in Figure 18(B). Figure 19(A) is an example of a liquid crystal display device that uses a liquid crystal element as a display element. Furthermore, Figure 19(B) is an example of a light-emitting display device (also known as an "EL display device") that uses a light-emitting element as a display element.

[0427] The display device shown in Figures 19(A) and 19(B) includes an electrode 4015, which is electrically connected to the terminals included in the FPC 4018 via an anisotropic conductor 4019. Furthermore, the electrode 4015 is electrically connected to wiring 4014 through openings formed in insulators 4112, 4111, and 4110.

[0428] Electrode 4015 is formed of the same conductor as the first electrode layer 4030, and wiring 4014 is formed of the same conductor as the source electrode and drain electrode of transistor 4010 and transistor 4011.

[0429] Furthermore, the pixel portion 4002 and the scan line driving circuit 4004 disposed on the first substrate 4001 include a plurality of transistors. Figures 19(A) and 19(B) illustrate the transistor 4010 included in the pixel portion 4002 and the transistor 4011 included in the scan line driving circuit 4004. In Figure 19(A), an insulator 4112 is disposed on the transistors 4010 and 4011, and in Figure 19(B), a partition wall 4510 is also disposed on the insulator 4112.

[0430] Furthermore, transistors 4010 and 4011 are disposed on insulator 4102. Additionally, transistors 4010 and 4011 include an electrode 4017 formed on insulator 4103, on which insulator 4112 is formed. Electrode 4017 can be used as a back gate electrode.

[0431] Transistors 4010 and 4011 can be the transistors shown in the above embodiments. OS transistors are preferably used as transistors 4010 and 4011. The electrical characteristic fluctuations of OS transistors are suppressed, thus they are electrically stable. Therefore, the display device of this embodiment shown in Figures 19(A) and 19(B) can be a highly reliable display device.

[0432] Furthermore, the OS transistor can reduce the current value in the off-state (off-state current value). Therefore, the hold time of electrical signals such as image signals can be extended, and the write interval in the power-on state can also be extended. Thus, the refresh frequency can be reduced, thereby suppressing power consumption.

[0433] Furthermore, since OS transistors also exhibit high field-effect mobility, high-speed driving is possible. Therefore, by using these OS transistors in the drive circuitry or pixel section of the display device, high-quality images can be provided. Moreover, since the drive circuitry and pixel section can be fabricated separately on the same substrate, the number of components in the display device can be reduced.

[0434] Furthermore, the display device shown in Figures 19(A) and 19(B) includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and an electrode formed in the same process as the source and drain electrodes. The electrodes overlap each other with an insulator 4103 in between.

[0435] Generally, the capacitance of the capacitor installed in the pixel section of the display device is set considering factors such as the leakage current of the transistors arranged in the pixel section, so that it can maintain its charge for a specified period. The capacitance can be set considering factors such as the off-state current of the transistors.

[0436] For example, by using OS transistors in the pixel section of a liquid crystal display device, the capacitance of the capacitor can be reduced to less than 1 / 3, and even less than 1 / 5, of the liquid crystal capacitance. When using OS transistors, capacitors can be omitted.

[0437] A transistor 4010 disposed in the pixel portion 4002 is electrically connected to the display element. In FIG19(A), the liquid crystal element 4013, which serves as the display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that insulators 4032 and 4033, which serve as alignment films, are disposed in a manner that holds the liquid crystal layer 4008. The second electrode layer 4031 is disposed on one side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 overlap with the liquid crystal layer 4008.

[0438] Furthermore, the spacer 4035 is a columnar spacer obtained by selectively etching the insulator, and it is provided to control the spacing (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that spherical spacers can also be used.

[0439] Furthermore, optical components (optical substrates) such as a black matrix (light-shielding layer), polarization components, phase difference components, and anti-reflection components can be appropriately provided in the display device. For example, circular polarization utilizing polarization substrates and phase difference substrates can also be used. In addition, backlighting, sidelighting, etc., can also be used as light sources.

[0440] Furthermore, the display device shown in Figures 19(A) and 19(B) includes an insulator 4111 and an insulator 4104. The insulators 4111 and 4104 are insulators that do not easily allow impurity elements to pass through. By sandwiching the semiconductor layer of the transistor by the insulators 4111 and 4104, the ingress of impurities from the outside can be prevented. Furthermore, when the insulators 4111 and 4104 are in contact with the outside of the pixel portion 4002, the effect of preventing impurities from entering from the outside can be improved.

[0441] For example, insulator 4104 can be formed using the same material and method as insulator 222. For example, insulator 4111 can be formed using the same material and method as insulator 274.

[0442] As a display element included in a display device, a light-emitting element (also known as an EL element) utilizing electroluminescence can be used. An EL element has a layer containing a light-emitting compound (also known as an EL layer) between a pair of electrodes. When a potential difference higher than the threshold voltage of the EL element is created between the pair of electrodes, holes are injected into the EL layer from the anode side, while electrons are injected into the EL layer from the cathode side. The injected electrons and holes recombine in the EL layer, thereby causing the light-emitting material contained in the EL layer to emit light.

[0443] EL elements are distinguished based on whether the light-emitting material is an organic compound or an inorganic compound. The former is usually called an organic EL element, while the latter is called an inorganic EL element.

[0444] In organic light-emitting diode (EL) devices, electrons are injected into the EL layer from one electrode by applying a voltage, while holes are injected into the EL layer from the other electrode. Through the recombination of these charge carriers (electrons and holes), the luminescent organic compound forms an excited state, and emits light when it returns to the ground state from this excited state. Due to this mechanism, such light-emitting devices are called current-excited light-emitting devices (LEDs).

[0445] In addition to light-emitting compounds, the EL layer can also include materials with high hole injection capacity, materials with high hole transport capacity, hole blocking materials, materials with high electron transport capacity, materials with high electron injection capacity, or bipolar materials (materials with high electron and hole transport capacity), etc.

[0446] EL layers can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet printing, and coating.

[0447] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices based on their device structure. Dispersed inorganic EL devices include a light-emitting layer in which luminescent material particles are dispersed in a binder, and their light emission mechanism utilizes donor-acceptor recombination luminescence. Thin-film inorganic EL devices have a structure in which the light-emitting layer is sandwiched between dielectric layers, and these dielectric layers are sandwiched between electrodes; their light emission mechanism utilizes localized luminescence from the inner-shell electron transitions of metal ions. Note that organic EL devices are used here as the light-emitting element for explanation.

[0448] To extract light, at least one of the pair of electrodes of the light-emitting element needs to be transparent. A transistor and a light-emitting element are formed on a substrate. The light-emitting element can be a top-emitting structure that extracts light from a surface opposite to the substrate; a bottom-emitting structure that extracts light from a surface on one side of the substrate; or a double-sided emitting structure that extracts light from both surfaces.

[0449] The light-emitting element 4513 is electrically connected to the transistor 4010 disposed in the pixel portion 4002. Although the light-emitting element 4513 has a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, it is not limited to this structure. The structure of the light-emitting element 4513 can be appropriately modified according to the direction of light extraction from the light-emitting element 4513, etc.

[0450] The partition wall 4510 is formed using organic or inorganic insulating materials. It is particularly preferred to use a photosensitive resin material to form an opening in the first electrode layer 4030, and the side of the opening is formed as an inclined surface with a continuous curvature.

[0451] The light-emitting layer 4511 can be composed of a single layer or a stack of multiple layers.

[0452] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc., from entering the light-emitting element 4513, a protective layer can be formed on the second electrode layer 4031 and the partition wall 4510. As a protective layer, silicon nitride film, silicon oxynitride film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film, aluminum oxynitride film, DLC (Diamond Like Carbon) film, etc., can be formed. Furthermore, a filler 4514 is provided and sealed within the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005. Thus, to prevent exposure to external gases, it is preferable to use a protective film (adhesive film, UV-curable resin film, etc.) with high hermeticity and low degassing for encapsulation (sealing).

[0453] As filler 4514, in addition to inert gases such as nitrogen or argon, ultraviolet-curing resins or thermosetting resins can also be used, such as PVC (polyvinyl chloride), acrylic resins, polyimide, epoxy resins, silicone resins, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate). Filler 4514 may also contain a desiccant.

[0454] As a sealant 4005, glass materials such as glass powder or two-component mixed resins that cure at room temperature, such as light-curing resins or thermosetting resins, can be used. Sealant 4005 may also contain a desiccant.

[0455] Furthermore, depending on the requirements, optical thin films such as polarizers or circular polarizers (including elliptical polarizers), retardation plates (λ / 4 plates, λ / 2 plates), and color filters can be appropriately disposed on the light-emitting surface of the light-emitting element. Additionally, anti-reflective films can be disposed on the polarizers or circular polarizers. For example, anti-glare treatment can be performed, which reduces reflected glare by utilizing the surface irregularities to diffuse reflected light.

[0456] By incorporating a microcavity structure into the light-emitting element, it is possible to extract light with high color purity. Furthermore, by combining the microcavity structure with color filters, reflected glare can be prevented, thereby improving image visibility.

[0457] Regarding the first electrode layer and the second electrode layer (also known as the pixel electrode layer, common electrode layer, counter electrode layer, etc.) that apply voltage to the display element, their light transmittance and reflectivity can be selected according to the direction of light extraction, the location of the electrode layer, and the pattern structure of the electrode layer.

[0458] As the first electrode layer 4030 and the second electrode layer 4031, transparent conductive materials such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon oxide can be used.

[0459] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 may be formed from one or more of the following metals, alloys, and nitrides: tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag).

[0460] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also known as a conductive polymer). As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. Examples include polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or derivatives thereof composed of two or more of aniline, pyrrole, and thiophene.

[0461] Furthermore, since transistors are easily damaged by static electricity, etc., it is preferable to provide a protection circuit to protect the drive circuit. The protection circuit is preferably constructed using non-linear components.

[0462] By employing the shift register described in the above embodiments, a highly reliable display device can be provided. Furthermore, by employing the transistor described in the above embodiments, the reliability of the display device can be further improved. Moreover, by employing the transistor described in the above embodiments, a display device with high resolution, large size, and high display quality can be provided. Furthermore, a display device with reduced power consumption can be provided.

[0463] <Display Module>

[0464] As an example of a semiconductor device employing the aforementioned OS transistor, a display module will be described. Figure 20 In the display module 6000 shown, a touch sensor 6004 connected to FPC 6003, a display panel 6006 connected to FPC 6005, a backlight unit 6007, a frame 6009, a printed circuit board 6010, and a battery 6011 are disposed between the upper cover 6001 and the lower cover 6002. Note that sometimes the backlight unit 6007, battery 6011, touch sensor 6004, etc., are not provided.

[0465] For example, the semiconductor device of one aspect of the present invention can be used in integrated circuits, etc., mounted on touch sensor 6004, display panel 6006, printed circuit board 6010. For example, the previously described display device can be used in display panel 6006.

[0466] The shape and size of the upper cover 6001 and the lower cover 6002 can be appropriately changed according to the size of the touch sensor 6004 and the display panel 6006, etc.

[0467] The touch sensor 6004 can be a resistive or capacitive type and can be used overlaid on the display panel 6006. Touch sensor functionality can be added to the display panel 6006. For example, by providing touch sensor electrodes within each pixel of the display panel 6006, the functionality of a capacitive touch panel can be added. Alternatively, by providing a light sensor within each pixel of the display panel 6006, the functionality of an optical touch sensor can be added. The touch sensor 6004 can be omitted if it is not required.

[0468] The backlight unit 6007 includes a light source 6008. The light source 6008 can be disposed at the end of the backlight unit 6007, and a light diffusion plate can be used. Furthermore, when a light-emitting display device or the like is used for the display panel 6006, the backlight unit 6007 can be omitted.

[0469] In addition to protecting the display panel 6006, the frame 6009 also functions as an electromagnetic shield, blocking electromagnetic waves generated from the printed circuit board 6010 side. The frame 6009 can also function as a heat sink.

[0470] Printed circuit board 6010 includes power supply circuitry and signal processing circuitry for outputting video and clock signals. A battery 6011 or a commercial power supply can be used to power the power supply circuitry. Note that when using a commercial power supply, battery 6011 can be omitted.

[0471] In addition, the display module 6000 may be further equipped with components such as polarizers, phase difference plates, and prism sheets.

[0472] This embodiment can be implemented by appropriately combining the structures described in other embodiments and examples.

[0473] (Implementation Method 7)

[0474] A semiconductor device according to one aspect of the present invention can be applied to processors or chips such as CPUs and GPUs. Figure 21 shows a specific example of an electronic device having a processor or chip such as a CPU or GPU according to one aspect of the present invention.

[0475] <Electronic Devices and Systems>

[0476] The GPU or chip according to one aspect of the present invention can be installed in a wide variety of electronic devices. Examples of electronic devices include, in addition to television sets, desktop or laptop personal computers, monitors for computers, digital signage, and large game consoles such as pinball machines, which have large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices. Furthermore, by incorporating an integrated circuit or chip according to one aspect of the present invention into an electronic device, the electronic device can possess artificial intelligence.

[0477] An electronic device according to one aspect of the present invention may also include an antenna. By receiving signals through the antenna, images or information can be displayed on a display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0478] An electronic device according to one aspect of the present invention may also include a sensor (the sensor having the function of measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0479] An electronic device according to one aspect of the present invention can have various functions. For example, it can have the following functions: displaying various information (static images, moving images, text images, etc.) on a display unit; a touch panel; displaying a calendar, date, or time; executing various software (programs); performing wireless communication; reading programs or data stored in a storage medium; etc. Figure 21 shows an example of an electronic device.

[0480] [Mobile phone]

[0481] Figure 21(A) shows a mobile phone (smartphone), one of the information terminals. The information terminal 5500 includes a housing 5510 and a display unit 5511. The display unit 5511 has a touch panel as an input interface, and buttons are provided on the housing 5510.

[0482] By applying a chip according to one aspect of the present invention to an information terminal 5500, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include applications that identify a session and display the content of that session on a display unit 5511, applications that identify text or graphics input by a user to a touch panel provided with the display unit 5511 and display that text or graphics on the display unit 5511, and applications that perform biometric identification such as fingerprints or voiceprints.

[0483] [Information Terminal]

[0484] Figure 21(B) shows a desktop information terminal 5300. The desktop information terminal 5300 includes an information terminal body 5301, a display 5302, and a keyboard 5303.

[0485] Similar to the aforementioned information terminal 5500, by applying a chip according to one aspect of the present invention to the desktop information terminal 5300, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include design support software, document proofreading software, and automatic menu generation software. Furthermore, by using the desktop information terminal 5300, novel artificial intelligence technologies can be developed.

[0486] Note that in the examples above, Figures 21(A) and 21(B) show smartphones and desktop information terminals as examples of electronic devices, but information terminals other than smartphones and desktop information terminals can also be applied. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), laptop information terminals, workstations, etc.

[0487] [Electrical Products]

[0488] Figure 21(C) shows an example of an electric refrigerator / freezer 5800. The electric refrigerator / freezer 5800 includes an outer casing 5801, a refrigerator door 5802, and a freezer door 5803, etc.

[0489] By applying a chip according to one aspect of the present invention to an electric refrigerator / freezer 5800, an electric refrigerator / freezer 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator / freezer 5800 can have the function of automatically generating a menu based on the food stored in the electric refrigerator / freezer 5800 or the consumption period of the food, and automatically adjusting the temperature of the electric refrigerator / freezer 5800 according to the stored food.

[0490] In the above example, the electric refrigerator / freezer is described as an electrical appliance. However, other electrical appliances could include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners (including air conditioners with heating and cooling), washing machines, dryers, and audio-visual equipment.

[0491] [Game console]

[0492] Figure 21(D) shows an example of a portable game console 5200. The portable game console includes a casing 5201, a display unit 5202, and buttons 5203, etc.

[0493] By applying a GPU or chip according to one aspect of the present invention to a portable game console 5200, a low-power portable game console 5200 can be realized. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat generation on the circuitry itself, peripheral circuitry, and modules.

[0494] Furthermore, by applying a GPU or chip according to one aspect of the present invention to a portable game console 5200, a portable game console 5200 with artificial intelligence can be realized.

[0495] The progress of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are normally governed by the game's programming. However, by applying artificial intelligence to the portable game console 5200, it is possible to achieve performances that are not limited to the game's programming. For example, it is possible to display the content of the player's questions, the progress of the game, the time elapsed, and changes in the behavior of characters appearing in the game.

[0496] Furthermore, when playing games that require multiple players using the portable game console 5200, artificial intelligence can be used to create human-like game players. This allows one person to play a game that requires multiple players, and thus, one person can also play a game that requires multiple players.

[0497] Although Figure 21(D) shows a portable game console as an example of a game console, game consoles using GPUs or chips according to one aspect of the present invention are not limited to this. Examples of game consoles using GPUs or chips according to one aspect of the present invention include home-based stationary game consoles, arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.), and ball-throwing machines installed in sports facilities.

[0498] [Moving Object]

[0499] One embodiment of the present invention, the GPU or chip, can be applied to a car as a moving body and the area around the driver's seat of the car.

[0500] Figure 21(E1) is a diagram of an example of a moving body, a car 5700, and Figure 21(E2) is a diagram of the perimeter of the windshield inside the car interior. Figure 21(E2) shows display panels 5701, 5702, and 5703 mounted on the dashboard and display panel 5704 mounted on the pillar.

[0501] Display panels 5701 to 5703 can provide various information by displaying speedometer, tachometer, driving distance, fuel level, gear position, and air conditioning settings. Furthermore, users can appropriately change the displayed content and layout of the display panels according to their preferences, enhancing design flexibility. Display panels 5701 to 5703 can also be used as lighting devices.

[0502] By displaying images captured by a camera (not shown) installed on the vehicle 5700 on the display panel 5704, blind spots (obstructions to the view) can be filled. In other words, by displaying images captured by a camera installed on the exterior of the vehicle 5700, blind spots can be filled, thereby improving safety. Furthermore, by displaying images that fill in unseen areas, safety can be confirmed more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

[0503] Because the GPU or chip of one aspect of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in the autonomous driving system of a car 5700. The chip can also be used in systems for navigation, hazard prediction, etc. Furthermore, navigation, hazard prediction, and other information can be displayed on display panels 5701 to 5704.

[0504] While the automobile was used as an example of a mobile body in the above example, mobile bodies are not limited to automobiles. For example, trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets) can also be cited as mobile bodies, and the chip of one aspect of the present invention can be applied to these mobile bodies to provide a system utilizing artificial intelligence.

[0505] [Broadcasting and Television System]

[0506] One embodiment of the present invention, the GPU or chip, can be applied to broadcast television systems.

[0507] Figure 21(F) schematically illustrates data transmission in a broadcast television system. Specifically, Figure 21(F) shows the path of radio waves (broadcast television signals) transmitted from broadcast television station 5680 to television receivers (TV) 5600 in each household. TV 5600 has a receiver (not shown) through which broadcast television signals received by antenna 5650 are input to TV 5600.

[0508] Although an Ultra High Frequency (UHF) antenna is shown as antenna 5650 in Figure 21(F), BS, 110-degree CS antenna, CS antenna, etc. can be used as antenna 5650.

[0509] Radio waves 5675A and 5675B are terrestrial broadcast television signals. Radio tower 5670 amplifies the received radio wave 5675A and transmits radio wave 5675B. Each household can receive radio wave 5675B using antenna 5650 and then watch terrestrial TV broadcasts on TV 5600. Furthermore, the broadcast television system can be for satellite broadcast television using artificial satellites, data broadcast television using optical routes, etc., and is not limited to the terrestrial broadcast television shown in Figure 21(F).

[0510] Furthermore, the chip according to one aspect of the present invention can also be applied to the aforementioned broadcast television system to form a broadcast television system utilizing artificial intelligence. When broadcast television data is transmitted from broadcast television station 5680 to TV 5600 in each household, the broadcast television data is compressed using an encoder; when the antenna 5650 receives the broadcast television data, the broadcast television data is recovered using a decoder included in the TV 5600. By utilizing artificial intelligence, for example, the display model contained in the displayed image can be identified in fluctuation compensation prediction, one of the compression methods of the encoder. In addition, intra-frame prediction using artificial intelligence can also be performed. For example, when TV 5600 receives low-resolution broadcast television data and performs high-resolution display, supplementary image processing such as upconversion can be performed during the recovery of the broadcast television data by the decoder.

[0511] The aforementioned broadcast television system utilizing artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting, which involves larger amounts of broadcast television data.

[0512] Furthermore, as an application of artificial intelligence on the TV5600 side, for example, an AI-enabled recording device can be installed within the TV5600. By adopting this structure, the AI-enabled recording device can learn the user's preferences and automatically record television programs that match those preferences.

[0513] The electronic device described in this embodiment, its functions, examples of artificial intelligence applications, and their effects can be implemented by appropriately combining them with descriptions of other electronic devices.

[0514] This embodiment can be implemented by appropriately combining the structures described in other embodiments, examples, etc.

[0515] [Example 1]

[0516] In this embodiment, a semiconductor device 990 with a plurality of transistors 200 is fabricated to allow cross-sectional observation of the transistors 200 located in any region.

[0517] As shown in Figure 22(A), the semiconductor device 990 includes 132 rows × 132 columns of transistors 200 manufactured in the same process. Furthermore, in the semiconductor device 990, the density of the transistors 200 is set to 0.88 transistors / μm. 2 .

[0518] Here, Figure 22(B) is a cross-sectional view along the L-length direction of transistor 200Ex, which is made as transistor 200. The channel length and channel width of transistor 200Ex are both designed to be 60 nm.

[0519] The materials used in the structure of transistor 200Ex are shown below. Note that in transistor 200Ex, components having the same function as the components of transistor 200 shown in the above embodiment are given the same symbols. Therefore, components not listed in the table below can be found in the above embodiment.

[0520] [Table 1]

[0521]

[0522] <Sample Manufacturing Method>

[0523] The following describes a method for manufacturing a semiconductor device 990 having transistors 200.

[0524] Silicon oxide is formed as an insulator 224 by CVD.

[0525] Next, as film 230a, In-Ga-Zn oxide is formed on insulator 224 by sputtering using a target with an In:Ga:Zn ratio of 1:3:4 [atomic number ratio]. Then, as film 230b, In-Ga-Zn oxide is formed on film 230a by sputtering using a target with an In:Ga:Zn ratio of 4:2:4.1 [atomic number ratio]. Furthermore, films 230a and 230b are formed continuously.

[0526] Next, as a film that becomes a conductor 240, a tantalum nitride film is formed on the film that becomes an oxide 230 by sputtering.

[0527] Next, the film that becomes oxide 230a, the film that becomes oxide 230b, and the film that becomes conductor 240 are processed to form oxide 230a, oxide 230b, and conductor 240.

[0528] Next, an insulator 273 is formed on oxides 230a and 230b and conductor 240. Furthermore, the insulator 273 has a laminated structure of an alumina film formed by sputtering and an alumina film formed by ALD.

[0529] Next, a silicon oxide film is formed on insulator 273 by CVD as the film that becomes insulator 280. Then, the film that becomes insulator 280 is planarized using CMP to form insulator 280.

[0530] Next, a portion of insulator 280, insulator 273, and conductor 240 is removed to form an opening that exposes oxide 230a and oxide 230b.

[0531] Here, the insulator 280 is processed using a dry etching method with gases containing carbon, hydrogen, and fluorine. The insulator 273 is processed using a wet etching method with tetramethylammonium hydroxide (TMAH). Furthermore, the conductor 240 is processed using a dry etching method with gases containing fluorine and chlorine.

[0532] Next, a film of oxide 230c is formed on the exposed insulator 224, the exposed oxide 230a, and the exposed oxide 230b. Furthermore, oxide 230c has a stacked structure. As the first oxide of oxide 230c, an In-Ga-Zn oxide is formed by sputtering using a target with an In:Ga:Zn ratio of 4:2:4.1. Next, as the second oxide of oxide 230c, an In-Ga-Zn oxide is formed on the first oxide of oxide 230c by sputtering using a target with an In:Ga:Zn ratio of 1:3:4. Furthermore, the first and second oxides are formed sequentially.

[0533] Next, silicon oxide is formed as the insulator 250 by CVD. Then, titanium nitride and tungsten films are continuously formed as the conductor 260 by CVD.

[0534] Next, CMP is used to remove a portion of the film that becomes conductor 260, film that becomes insulator 250, and film that becomes oxide 230c, to form conductor 260, insulator 250, and oxide 230c.

[0535] The semiconductor device 990 having multiple transistors 200 is manufactured through the above process.

[0536] <Cross-sectional observation of transistor 200>

[0537] Next, cross-sectional views were taken of the transistors 200 arranged in 132 rows × 132 columns in the semiconductor device 990, specifically the transistors 200 in the 1st row × 1st column (1,1), the transistors 200 in the 3rd row × 3rd column (3,3), the transistors 200 in the 6th row × 6th column (6,6), the transistors 200 in the 45th row × 35th column (45,35), and the transistors 200 in the 65th row × 65th column (65,65).

[0538] Furthermore, as a comparative example, a cross-sectional view was taken of a semiconductor device in which a transistor 200Ex is formed in the central part of a region having the same area as semiconductor device 990.

[0539] Furthermore, cross-sectional observations were performed using a scanning transmission electron microscope (STEM). The observation apparatus used was the HD-2700 manufactured by Hitachi High-Technologies Corporation. Figure 23 The cross-sectional STEM observation results of semiconductor device 990 and a comparative example are shown.

[0540] Figure 23 The lower section shows the region corresponding to region 991, indicated by the dashed line in the upper left section of the cross-sectional view of each transistor in the semiconductor device 990. Furthermore, the upper right section shows the region corresponding to region 991, in the cross-sectional view of the transistor in the comparative example.

[0541] Here, in region 991 of each transistor, the interface between conductor 240 and oxide 230b, and their continuous surface, are indicated by dashed lines. Furthermore, the interface between oxide 230c and oxide 230b is also indicated by dashed lines. It can be seen that in both the comparative example and the semiconductor device 990, the interface between oxide 230c and oxide 230b is located below the continuous surface of the interface between conductor 240 and oxide 230b. In other words, it can be seen that a portion of oxide 230 is removed during the process of removing a portion of conductor 240.

[0542] Therefore, the distance between the upper and lower dashed lines, as indicated by the arrow, corresponds to the amount of oxide 230 removed during the process of removing a portion of the conductor 240 (hereinafter referred to as the etching amount). Figure 24 The etching amount of the channel portion of each transistor 200 is shown.

[0543] Depend on Figure 24The results show that the etching depth of the transistors in the comparative examples and transistor 200(1,1) is 3.0 nm or more. On the other hand, the etching depth of transistor 200(3,3) is about 2.0 nm, and the etching depths of transistors 200(6,6), 200(45,35), and 200(65,65) are less than 2 nm.

[0544] It can be confirmed that processing fluctuations occur depending on the layout during the process of removing a portion of the conductor 240. In particular, the transistors 200 (1,1) located at the outermost end of the circuit region have the highest etching amount. On the other hand, it can also be seen that the etching amount of transistors 200 (65,65) closer to the center than transistors 200 (3,3) which are closer to the center than the outermost end is almost uniform.

[0545] Furthermore, in a comparative example without other surrounding transistors, an etching amount equal to that of transistor 200(1,1) can be confirmed. This result suggests that a loading effect occurred during the process of removing the conductor 240 from the semiconductor device 990.

[0546] It can be argued that transistor inhomogeneity can be suppressed by placing sacrificial elements in regions with large processing fluctuations. Specifically, when low-pattern-density regions are adjacent to high-pattern-density regions, processing fluctuations occur at the edges of the high-pattern-density regions depending on the layout. In other words, by placing sacrificial elements between regions with different pattern densities, the transistor inhomogeneity present in the high-pattern-density regions can be suppressed.

[0547] At least a portion of this embodiment can be implemented in combination with other embodiments shown in this specification.

[0548] [Symbol Explanation]

[0549] 10: Substrate, 11: Region, 12: Region, 13: Region, 14: Region, 15: Substrate, 16: Circuit Region, 18: Separation Region, 21: Pseudo-Component, 22: Component, 23: Film, 26: Structure, 26A: Film, 27: Film, 28: Structure, 29: Mask

Claims

1. A semiconductor device, comprising: A first region containing multiple components; as well as The second region contains multiple pseudo-elements. One of the plurality of components is a first transistor. One of the plurality of pseudo-elements is a second transistor. Both the first transistor and the second transistor include: Oxide semiconductor; The insulator on the oxide semiconductor; and Conductors on the insulator The height of the top surface of the insulator is the same as the height of the top surface of the conductor. Furthermore, the second region is located at the edge of the first region.

2. A semiconductor device, comprising: A first region containing multiple components; A second region containing multiple pseudo-elements; as well as The third region contains multiple components and multiple pseudo-components. The second region is located at the edge of the first region and the edge of the third region. The first region and the third region are surrounded by the second region. Furthermore, the plurality of elements in the first region, the plurality of pseudo-elements in the second region, and the plurality of elements and pseudo-elements in the third region all comprise oxide semiconductors.

3. The semiconductor device according to claim 1 or 2, The elements among the plurality of components and the pseudo-elements among the plurality of pseudo-elements have the same structure. Furthermore, the structures contained in the element and the structures contained in the pseudo-element use the same material and are disposed in the same layer.

4. The semiconductor device according to claim 1 or 2, The semiconductor device is a chip with the second region disposed at the end.

5. The semiconductor device according to claim 1 or 2, The oxide semiconductor contains In, element M, and Zn, wherein element M is Al, Ga, Y, or Sn.

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