Array substrate, light control panel and display device

Abstract

An array substrate, a light control panel and a display device. The array substrate comprises a plurality of gate lines extending respectively along a first direction, a plurality of data lines extending respectively along a second direction intersecting the first direction and a plurality of light control pixel units. Each of the gate lines comprises a plurality of grid parts arranged in parallel and connected in sequence along the first direction, and each grid part comprises a grid line and an opening area surrounded by the grid lines. The array substrate can improve the display effect of a display device comprising the array substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate, a light control panel and a display device. Background Art

[0002] The liquid crystal display device includes a backlight module and a liquid crystal panel. The backlight module is arranged on the non-display side of the liquid crystal panel to provide a light source for the display operation of the display panel. The liquid crystal panel includes a polarizer, an array substrate, an opposing substrate, and a liquid crystal molecule layer filled between the two substrates. The liquid crystal display device deflects the liquid crystal molecules in the liquid crystal molecule layer by forming an electric field between the array substrate and the opposing substrate. The deflected liquid crystal molecules cooperate with the polarizer to form a liquid crystal light valve. Since the liquid crystal molecule layer itself does not emit light, it needs to rely on a backlight module to realize the display function. With the continuous development of display technology, users have put forward higher and higher requirements on the contrast, brightness uniformity, etc. of the display device. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an array substrate. The array substrate includes a plurality of gate lines extending along a first direction, a plurality of data lines extending along a second direction intersecting the first direction, and a plurality of light-controlling pixel units. Each of the gate lines includes a plurality of grid portions arranged in parallel and connected in sequence along the first direction, and each grid portion includes a grid line and an opening area surrounded by the grid line.

[0004] For example, in at least one example of the array substrate, the grid lines of each of the grid portions include a first fold line route and a second fold line route; the starting point of the first fold line route is connected to the starting point of the second fold line route; the end point of the first fold line route is connected to the end point of the second fold line route; and the vertex of the first fold line route and the vertex of the second fold line route are spaced apart in the second direction.

[0005] For example, in at least one example of the array substrate, the first fold line route includes a first line segment and a second line segment connected in sequence, and the connection point between the first line segment and the second line segment is the vertex of the first fold line route; the second fold line route includes a third line segment and a fourth line segment connected in sequence, and the connection point between the third line segment and the fourth line segment is the vertex of the second fold line route; and the absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction, and the absolute value of the acute angle between the fourth line segment and the first direction are between 38 degrees and 55 degrees.

[0006] For example, in at least one example of the array substrate, the absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction, and the absolute value of the acute angle between the fourth line segment and the first direction are between 42 degrees and 48 degrees.

[0007] For example, in at least one example of the array substrate, the first fold line and the second fold line are symmetrical with respect to a line connecting a starting point of the first fold line and an end point of the first fold line.

[0008] For example, in at least one example of the array substrate, the first line segment and the second line segment are symmetrical with respect to the line connecting the vertices of the first zigzag line and the vertices of the second zigzag line; and the third line segment and the fourth line segment are symmetrical with respect to the line connecting the vertices of the first zigzag line and the vertices of the second zigzag line.

[0009] For example, in at least one example of the array substrate, each of the data lines has two overlapping positions with a grid line of a corresponding grid portion in a direction perpendicular to the array substrate, or overlaps with a connection between two adjacent grid portions in a direction perpendicular to the array substrate.

[0010] For example, in at least one example of the array substrate, the array substrate further includes a common electrode line extending along the second direction. The common electrode line overlaps with a connection point between two adjacent grid parts in a direction perpendicular to the array substrate, or has two overlapping positions with a grid line of a corresponding grid part in a direction perpendicular to the array substrate.

[0011] For example, in at least one example of the array substrate, an opening area surrounded by each of the grid portions and one or two of the light-control pixel units partially overlap in a direction perpendicular to the array substrate.

[0012] For example, in at least one example of the array substrate, the boundary routing of each of the light-control pixel units is formed by a first fold line routing of the corresponding data line and the corresponding grid portion of the gate line; and a second fold line routing of the grid portion of each gate line passes through the interior of the corresponding light-control pixel unit.

[0013] For example, in at least one example of the array substrate, the array substrate further includes a common electrode line extending along the second direction. The common electrode line overlaps with the connection between two adjacent grid parts in a direction perpendicular to the array substrate; the boundary line of each light-control pixel unit is formed by the corresponding common electrode line and the first fold line of the grid part of the corresponding gate line; and the second fold line of the grid part of each gate line passes through the interior of the corresponding light-control pixel unit.

[0014] For example, in at least one example of the array substrate, each of the light-control pixel units also includes a switching element and a pixel electrode; the switching element includes a gate, a source, and a drain, the gate of the switching element is electrically connected to the corresponding second zigzag routing, and one of the source and the drain of the switching element is electrically connected to the pixel electrode; and the number of the switching elements is equal to the number of the second zigzag routing.

[0015] For example, in at least one example of the array substrate, the width of the first fold line and the width of the second fold line are both between 9 micrometers and 11 micrometers.

[0016] For example, in at least one example of the array substrate, the grid lines of each of the grid parts include a first fold line and a second fold line; the starting point of the first fold line is connected to the starting point of the second fold line, and the end point of the first fold line is connected to the end point of the second fold line; the vertex of the first fold line and the vertex of the second fold line are arranged at intervals in the second direction; the first fold line includes a first line segment and a second line segment connected in sequence, and the connection point of the first line segment and the second line segment is the vertex of the first fold line; the second fold line includes a third line segment connected in sequence. a line segment and a fourth line segment, the connection point of the third line segment and the fourth line segment is the vertex of the second fold line; the absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction, and the absolute value of the acute angle between the fourth line segment and the first direction are between 42 degrees and 48 degrees; the first fold line and the second fold line are symmetrical with respect to the line connecting the starting point of the first fold line and the end point of the first fold line; the first line segment and the second line segment are symmetrical with respect to the line connecting the starting point of the first fold line and the end point of the first fold line; the first line segment and the second line segment are symmetrical with respect to the line connecting the starting point of the first fold line and the end point of the first fold line The vertices of the first fold line and the vertices of the second fold line are symmetrical; the third line segment and the fourth line segment are symmetrical relative to the vertices of the first fold line and the vertices of the second fold line; each of the data lines has two overlapping positions with a grid line of a corresponding grid part in a direction perpendicular to the array substrate; the array substrate also includes a common electrode line extending along the second direction, and the connection between the common electrode line and two adjacent grid parts overlaps in a direction perpendicular to the array substrate; each opening area surrounded by the grid part and the two light control pixel units overlap in a vertical direction. The light-controlling pixel units partially overlap in a direction perpendicular to the array substrate; the boundary routing of the light-controlling pixel unit is formed by the first folded-line routing of the grid portion of the corresponding data line and the corresponding gate line, and the second folded-line routing of the grid portion of each gate line passes through the interior of the corresponding light-controlling pixel unit; each of the light-controlling pixel units also includes a switching element and a pixel electrode; the switching element includes a gate, a source and a drain, the gate of the switching element is electrically connected to the corresponding second folded-line routing, one of the source and the drain of the switching element is electrically connected to the pixel electrode, and the number of the switching elements is equal to the number of the second folded-line routings.

[0017] At least one embodiment of the present disclosure further provides a light control panel, which includes an opposing substrate, a liquid crystal layer, and any array substrate provided by at least one embodiment of the present disclosure. The array substrate and the opposing substrate are arranged opposite to each other, and the liquid crystal layer is sandwiched between the array substrate and the opposing substrate.

[0018] At least one embodiment of the present disclosure further provides a display device, comprising: a display panel, a backlight unit, and any light control panel provided by at least one embodiment of the present disclosure. The display panel is located on the light emitting side of the light control panel, and the backlight unit is located on a side of the light control panel away from the display panel.

[0019] For example, in at least one example of the display device, the display panel includes a plurality of display pixel units arranged in an array; a size of each of the grid portions in the first direction is equal to twice a size of each of the display pixel units in the first direction; and a size of each of the grid portions in the second direction is less than or equal to twice a size of each of the display pixel units in the second direction.

[0020] For example, in at least one example of the display device, the size of each of the light-control pixel units in the first direction is equal to twice the size of each of the display pixel units in the first direction; and the size of each of the light-control pixel units in the second direction is equal to 2.5-3 times the size of each of the display pixel units in the first direction.

[0021] At least one embodiment of the present disclosure further provides a method for manufacturing an array substrate, comprising: forming a plurality of gate lines extending along a first direction respectively; forming a plurality of data lines extending along a second direction intersecting the first direction respectively. The plurality of gate lines and the plurality of data lines intersect to define a plurality of light-control pixel units, each of the gate lines comprising a plurality of grid portions arranged in parallel and connected in sequence along the first direction, each grid portion comprising a grid line and an opening area surrounded by the grid line. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0023] Figure 1A A cross-sectional schematic diagram of a liquid crystal display device is shown;

[0024] Figure 1B Shows Figure 1A A schematic plan view of a light control panel and a display panel of a liquid crystal display device shown;

[0025] Figure 1C Shows Figure 1A The light control pixel unit of the light control panel shown;

[0026] Figure 2A Shown in the first perspective Figure 1AA schematic diagram of a gate line blocking condition of a liquid crystal display device shown;

[0027] Figure 2B Shown in the second viewing angle Figure 1A A schematic diagram of a gate line blocking condition of a liquid crystal display device shown;

[0028] Figure 3 is a plan view of an array substrate provided by at least one embodiment of the present disclosure;

[0029] Figure 4 Shows Figure 3 A plan view of the gate lines of the array substrate shown;

[0030] Figure 5 Shows Figure 3 A plan view schematic diagram of a switch element and a pixel electrode of an array substrate shown;

[0031] Fig. 6A A schematic plan view of another array substrate provided by at least one embodiment of the present disclosure is shown;

[0032] Figure 6B A schematic plan view showing another gate line of an array substrate provided by at least one embodiment of the present disclosure;

[0033] Figure 7 is a cross-sectional schematic diagram of a light control panel provided by at least one embodiment of the present disclosure;

[0034] Figure 8 is a cross-sectional schematic diagram of a display device provided by at least one embodiment of the present disclosure;

[0035] Fig. 9A yes Figure 8 A schematic plan view of a display panel of the display device shown;

[0036] Fig. 9B yes Figure 8 A schematic plan view of the display device shown;

[0037] Fig.10 yes Fig. 9B A schematic plan view of a grid portion of a display device shown; and

[0038] Fig.11 yes Fig. 9B A schematic plan view of a pixel unit of a display device shown in FIG. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0040] Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0041] The inventors of the present disclosure have noticed in their research that ordinary liquid crystal display devices (e.g., liquid crystal display devices based on advanced super-dimensional field switching technology with a single liquid crystal cell) usually have a dark state light leakage problem, which makes the contrast of the display screen of the liquid crystal display device low. The inventors of the present disclosure have noticed in their research that a liquid crystal display device with dual liquid crystal cells can be used to improve the contrast of the display screen, which is exemplarily described below in conjunction with FIG. 1.

[0042] Figure 1A Schematic diagram of a cross section of a liquid crystal display device 500 is shown. Figure 1A As shown, the liquid crystal display device 500 includes a backlight unit 503, a light control panel 502 and a display panel 501 which are arranged in sequence. Figure 1B Shows Figure 1A Schematic diagram of a plan view of a light control panel 502 and a display panel 501 of a liquid crystal display device 500. For example, the light control panel 502 is configured to adjust the intensity of light emitted by a backlight unit 503 and incident on the display panel 501.

[0043] like Figure 1BAs shown, the display panel 501 includes a plurality of first signal lines 541 extending along a first direction D1 and a plurality of second signal lines 542 extending along a second direction D2; the plurality of first signal lines 541 and the plurality of second signal lines 542 intersect to define a plurality of display pixel units 530; each display pixel unit 530 includes a first display sub-pixel unit 531, a second display sub-pixel unit 532 and a third display sub-pixel unit 533; the first display sub-pixel unit 531, the second display sub-pixel unit 532 and the third display sub-pixel unit 533 are, for example, red display sub-pixel units, green display sub-pixel units and blue display sub-pixel units, respectively. For example, the first direction D1 is perpendicular to the second direction D2. For example, the first signal line 541 is a gate line of the display panel 501, and the second signal line 542 is a data line of the display panel 501.

[0044] like Figure 1B As shown, the light control panel 502 includes a plurality of gate lines 510 extending along a first direction D1 and a plurality of data lines 521 extending along a second direction D2 intersecting the first direction D1; the plurality of gate lines 510 and the plurality of data lines 521 intersect to define a plurality of light control pixel units 523. For example, the width of the first signal line 541 is greater than the width of the gate line 510. For example, the sizes of the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 in the first direction D1 are the same as each other, and for example, the sizes of the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 in the second direction D2 are the same as each other.

[0045] like Figure 1B As shown, each gate line 510 is implemented as a zigzag line; each gate line 510 includes a plurality of first line segments 511 and a plurality of second line segments 512, the plurality of first line segments 511 and the plurality of second line segments 512 are alternately arranged, and adjacent first line segments 511 and second line segments 512 are connected to each other. Figure 1B As shown, the angle (acute angle) between the first line segment 511 (or / the second line segment 512) and the first direction D1 is about 50-70 degrees to reduce the moiré problem of the liquid crystal display device 500. For example, the first line segment 511 and the second line segment 512 are both straight line segments.

[0046] Figure 1C Shows Figure 1A The light control pixel unit 523 of the light control panel 502 is shown. Figure 1C As shown, the size of the light-control pixel unit 523 in the first direction D1 is L1, and the size of the light-control pixel unit 523 in the second direction D2 is L2. Figure 1B and Figure 1CAs shown, the size L1 of the light control pixel unit 523 in the first direction D1 is equal to twice the size of the display pixel unit 530 in the first direction D1, and the size L2 of the light control pixel unit 523 in the second direction D2 is equal to four times the size of the display pixel unit 530 in the second direction D2.

[0047] The inventors of the present disclosure have noticed in their research that by implementing the gate line 510 as a zigzag line, the problem of uneven brightness of the liquid crystal display device 500 can be suppressed, for example, the problem of uneven brightness is a problem of bad black and white stripes or bad horizontal stripes (for example, bad black and white stripes at a side viewing angle). The specific analysis is as follows. In the case where the gate line 510 is implemented as a straight line, if an alignment error occurs when the light control panel 502 and the display panel 501 are attached, the positive projection of the gate line 510 (straight line) on the display panel 501 will overlap with a row of display pixels of the display panel 501, and the gate line 510 will block the light provided by the backlight unit 503, and make the brightness of the area corresponding to the gate line 510 of the liquid crystal display device 500 close to zero (that is, corresponding to the black stripes), and the area of ​​the liquid crystal display device 500 corresponding to the gate line 510 outside the gate line 510 corresponds to the white stripes; in this case, the liquid crystal display device 500 has black stripes and white stripes arranged alternately in the second direction D2, that is, the liquid crystal display device 500 may have a bad black and white stripe problem. When the gate line 510 is implemented as a zigzag line, the black and white stripe defect or horizontal stripe defect problem of the liquid crystal display device 500 can be suppressed.

[0048] The inventors of the present disclosure also noticed in their research that Figure 1A and Figure 1B The illustrated liquid crystal display device 500 may have at least one of a color unevenness problem (rainbow pattern) problem and a signal delay problem.

[0049] For example, Figure 1A and Figure 1B The liquid crystal display device 500 shown may have a rainbow problem; the rainbow problem is the problem of uneven color mixing in different areas of the display device. Specifically, when the predetermined display screen of the display device is a white screen, the actual screen observed by the user has color stripes. The rainbow problem is related to the difference in the shielding of the gate line 510 on the display sub-pixel units of different colors at different viewing angles. Figure 2A and Figure 2B The rainbow problem is illustrated below. Figure 2A The diagram shows the first viewing angle (eg, frontal viewing angle). Figure 1A Schematic diagram of the shielding condition of the gate line 510 of the liquid crystal display device 500 shown in FIG. Figure 2B The second perspective (eg, side perspective) is shown. Figure 1ASchematic diagram of the shielding of the gate line 510 of the liquid crystal display device 500 shown in FIG. For the convenience of explanation, it is assumed here that the sizes of the first display sub-pixel unit 531, the second display sub-pixel unit 532 and the third display sub-pixel unit 533 in the first direction D1 are the same as each other; the first line segment 511 and the second line segment 512 are both straight line segments. Figure 2A and Figure 2B As shown, since the sizes of the first display sub-pixel unit 531, the second display sub-pixel unit 532 and the third display sub-pixel unit 533 in the first direction D1 are the same, the length of the portion of the line segment (e.g., the first line segment 511) corresponding to the first display sub-pixel unit 531, the length of the portion of the line segment (e.g., the first line segment 511) corresponding to the second display sub-pixel unit 532, and the length of the portion of the line segment (e.g., the first line segment 511) corresponding to the third display sub-pixel unit 533 are the same. Figure 2A As shown, at the first viewing angle, since the portion of the line segment (e.g., the first line segment 511) corresponding to the second display sub-pixel unit 532 also overlaps with the first signal line 541, at the first viewing angle, the overlapping area of ​​the line segment (e.g., the first line segment 511) and the first display sub-pixel unit 531 and the overlapping area of ​​the line segment (e.g., the first line segment 511) and the third display sub-pixel unit 533 are both smaller than the overlapping area of ​​the line segment (e.g., the first line segment 511) and the second display sub-pixel unit 532; in this case, the display image at the first viewing angle is biased towards the color of the second display sub-pixel unit 532. For similar reasons, such as Figure 2B As shown, the display image under the second viewing angle is biased towards the color of the first display sub-pixel unit 532 (that is, the display sub-pixel unit corresponding to the overlapping area of ​​the line segment and the first signal line 541). Since the user observes the liquid crystal display device 500 within a certain viewing angle range, the actual image observed by the user has color stripes. It should be noted that the portion of the line segment corresponding to the display sub-pixel unit refers to the portion of the line segment between the two intersections of the line segment and the boundary of the display sub-pixel unit (for example, a column of display sub-pixel units where the display sub-pixel unit is located) in the first direction.

[0050] For example, Figure 1A and Figure 1B The liquid crystal display device 500 shown may have a signal delay problem. This is because the angle (acute angle) between the first line segment 511 (or / and the second line segment 512) and the first direction D1 is large, so the length of the first line segment 511 (or / and the second line segment 512) is long. Therefore, the time required for the signal to be transmitted from one end of the gate line 510 to the other end of the gate line 510 is long.

[0051] Embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, a light control panel, and a display device. The array substrate includes a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction intersecting the first direction, and a plurality of light control pixel units. Each gate line includes a plurality of grid portions arranged in parallel and connected in sequence along the first direction, and each grid portion includes grid lines and an opening area surrounded by the grid lines. The array substrate can enhance the display effect of a display device including the array substrate. For example, the array substrate can suppress the unevenness of a display screen of a display device including the array substrate (for example, uneven brightness and uneven color).

[0052] The array substrate provided according to the embodiment of the present disclosure is described below in a non-limiting manner through several examples and embodiments. As described below, different features in these specific examples and embodiments can be combined with each other without conflicting with each other to obtain new examples and embodiments, and these new examples and embodiments also fall within the scope of protection of the present disclosure.

[0053] Figure 3 FIG. 1 is a schematic plan view of an array substrate 100 provided by at least one embodiment of the present disclosure. Figure 3 As shown, the array substrate 100 includes a plurality of gate lines 101 extending along a first direction D1 and a plurality of data lines 102 extending along a second direction D2 intersecting the first direction D1. For example, the first direction D1 is perpendicular to the second direction D2.

[0054] like Figure 3 As shown, a plurality of gate lines 101 and a plurality of data lines 102 intersect to define a plurality of light-control pixel units 103, each gate line 101 includes a plurality of grid portions 110 arranged in parallel and connected in sequence along a first direction D1, and each grid portion 110 includes a grid line 111 and an opening area 112 surrounded by the grid lines 111. For example, the plurality of gate lines 101 are configured to provide scanning signals, and the plurality of data lines 102 are configured to provide data signals.

[0055] For example, Figure 3 As shown, the data line 102 may be a straight line parallel to the first direction D1, but the embodiments of the present disclosure are not limited thereto. According to actual application requirements, the data line 102 may also be implemented as a zigzag line, that is, the data line 102 has a zigzag structure.

[0056] For example, by making each gate line 101 include a plurality of grid portions 110 arranged in parallel and connected in sequence along the first direction D1, the display effect of the display device 01 including the array substrate 100 can be improved. For example, by making each gate line 101 include a plurality of grid portions 110 arranged in parallel and connected in sequence along the first direction D1, the light control panel 10 including the array substrate 100 (see Figure 7 ) of the grid size (compared to Figure 1B In this case, the difference between the size of the grid of the light control panel 10 of the array substrate 100 and the size of the grid of the display panel of the display device 01 including the array substrate 100 can be reduced, thereby suppressing the moiré of the display device 01 including the array substrate 100 and improving the display device 01 including the array substrate 100 (see Figure 8 ) display effect. For example, Figure 3 The grids of the light control panel 10 of the array substrate 100 shown refer to the grids formed by the adjacent grid portions 110 and the data lines 102 and the grids corresponding to the grid portions 110 .

[0057] Figure 4 Shows Figure 3 FIG. 1 is a plan view of a gate line 101 of an array substrate 100. Figure 3 and Figure 4 As shown, the grid lines 111 of each grid portion 110 include a first fold line 120 and a second fold line 130; the starting point of the first fold line 120 and the starting point of the second fold line 130 are connected; the end point of the first fold line 120 and the end point of the second fold line 130 are connected; the vertices of the first fold line 120 and the vertices of the second fold line 130 are spaced apart in the second direction D2.

[0058] like Figure 3 and Figure 4 As shown, the first fold line route 120 includes a first line segment 121 and a second line segment 122 connected in sequence, and the connection point of the first line segment 121 and the second line segment 122 is the vertex of the first fold line route 120 (in the same grid portion 110); the second fold line route 130 includes a third line segment 131 and a fourth line segment 134 connected in sequence, and the connection point of the third line segment 131 and the fourth line segment 134 is the vertex of the second fold line route 130 (in the same grid portion 110).

[0059] It should be noted that the extension of the plurality of gate lines 101 along the first direction D1 only defines the extension direction of the gate lines 101 , but does not mean that the lines (the first fold line 120 and the second fold line 130 ) included in the gate lines 101 are parallel to the first direction D1 .

[0060] For example, Figure 3 and Figure 4As shown, the absolute value of the acute angle between the first line segment 121 and the first direction D1, the absolute value of the acute angle between the second line segment 122 and the first direction D1, the absolute value of the acute angle between the third line segment 131 and the first direction D1, and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1 are between 38 degrees and 55 degrees (for example, 38 degrees and 50 degrees).

[0061] For example, by reducing the absolute value of the acute angle between the first line segment 121 and the first direction D1, the absolute value of the acute angle between the second line segment 122 and the first direction D1, the absolute value of the acute angle between the third line segment 131 and the first direction D1, and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1, the difference in the occlusion of sub-pixels of different colors in the display panel 20 of the display device 01 including the array substrate 100 by the gate line 101 of the array substrate 100 can be reduced, thereby suppressing rainbow patterns (for example, suppressing rainbow patterns in solid color images).

[0062] For example, by reducing the absolute value of the acute angle between the first line segment 121 and the first direction D1, the absolute value of the acute angle between the second line segment 122 and the first direction D1, the absolute value of the acute angle between the third line segment 131 and the first direction D1, and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1, the lengths of the first line segment 121, the second line segment 122, the third line segment 131 and the fourth line segment 134 can also be reduced, thereby reducing the time required for a signal to be transmitted from one end (for example, the left end) of the gate line 101 to the other end (for example, the right end) of the gate line 101, thereby reducing signal delay.

[0063] For example, Figure 3 and Figure 4 As shown, the absolute value of the acute angle between the first line segment 121 and the first direction D1, the absolute value of the acute angle between the second line segment 122 and the first direction D1, the absolute value of the acute angle between the third line segment 131 and the first direction D1, and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1 are between 42 degrees and 48 degrees (for example, 43 degrees and 44 degrees).

[0064] For example, by making the absolute value α1 of the acute angle between the first line segment 121 and the first direction D1, the absolute value of the acute angle between the second line segment 122 and the first direction D1, the absolute value of the acute angle between the third line segment 131 and the first direction D1, and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1 within the range of 42 degrees to 48 degrees (for example, 43 degrees to 44 degrees), rainbow lines can be suppressed and signal delay can be reduced without degrading (for example, not significantly degrading) the black and white line problem.

[0065] For example, by making each gate line 101 include a plurality of grid portions 110 arranged in parallel and connected sequentially along the first direction D1, it is possible to ensure that each row of display pixel units 204 in the display panel 20 of the display device 01 including the array substrate 100 is partially blocked by the gate line 101 while reducing the absolute value of the acute angle between the first line segment 121 and the first direction D1, the absolute value of the acute angle between the second line segment 122 and the first direction D1, the absolute value of the acute angle between the third line segment 131 and the first direction D1, and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1, thereby avoiding the degradation of the black and white stripes problem.

[0066] For example, by making each gate line 101 include a plurality of grid portions 110 arranged in parallel and sequentially connected along the first direction D1, it is possible to avoid doubling the number of light control pixel units 103 of the light control panel 10 while reducing the absolute value of the acute angle between the first line segment 121-the fourth line segment 134 and the first direction D1, thereby avoiding an increase in the load (for example, capacitive load) of the light control panel 10.

[0067] For example, Figure 3 and Figure 4 As shown, the first fold line 120 and the second fold line 130 are symmetrical with respect to the line connecting the starting point of the first fold line 120 and the end point of the first fold line 120; in this case, the display effect of the display device 01 including the array substrate 100 can be improved.

[0068] For example, Figure 3 and Figure 4 As shown, the first line segment 121 and the second line segment 122 are symmetrical with respect to the line connecting the vertices of the first fold line 120 and the vertices of the second fold line 130; the third line segment 131 and the fourth line segment 134 are symmetrical with respect to the line connecting the vertices of the first fold line 120 and the vertices of the second fold line 130; in this case, the display effect of the display device 01 including the array substrate 100 can be further improved.

[0069] For example, Figure 3 and Figure 4 As shown, the boundary line of the light control pixel unit 103 is formed by the first fold line 120 of the grid portion 110 of the corresponding data line 102 and the corresponding gate line 101; the second fold line 130 of the grid portion 110 of each gate line 101 passes through the interior of the corresponding light control pixel unit 103. Figure 3As shown, two adjacent data lines 102 intersect with the first fold line routing 120 of two adjacent gate lines, and the portion of the two adjacent data lines 102 located between the first fold line routing 120 of the two adjacent gate lines and the portion of the first fold line routing 120 of the two adjacent gate lines located between the two adjacent data lines 102 form a boundary routing of the light control pixel unit 103.

[0070] For example, each light-control pixel unit 103 further includes a switch element 141 and a pixel electrode 142; Figure 5 Shows Figure 3 FIG. 1 is a plan view of a switch element 141 and a pixel electrode 142 of an array substrate 100. Figure 5 As shown, the switch element 141 includes a gate, a source, and a drain. The gate of the switch element 141 is electrically connected to the corresponding second zigzag line 130 (that is, the second zigzag line 130 that passes through the light-control pixel unit 103 including the switch element 141), one of the source and the drain of the switch element 141 is electrically connected to the pixel electrode 142 (for example, electrically connected through a via hole), and the other of the source and the drain of the switch element 141 is electrically connected to the data line 102. For example, the number of switch elements 141 is equal to the number of second zigzag lines 130 (that is, the number of grid portions 110). For example, as Figure 5 As shown, the gate of the switch element 141 is electrically connected to the position of the second fold line 130 close to the vertex of the second fold line 130. For example, the gate line 101 and the data line 102 can be formed of a metal material (for example, copper, aluminum or aluminum alloy), and the pixel electrode 142 can be formed of a transparent conductive material. For example, the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO).

[0071] For example, the pixel electrode 142 has substantially the same shape as the light-controlling pixel unit 103. For example, the pixel electrode 142 has substantially the same shape as the light-controlling pixel unit 103 means that the pixel electrode 142 and the light-controlling pixel unit 103 have the same design shape, and in actual products, the shapes of the pixel electrode 142 and the light-controlling pixel unit 103 are allowed to have a certain deviation (for example, less than 5% or 10%).

[0072] For example, the pixel electrode 142 and the light-control pixel unit 103 have substantially the same size. For example, the pixel electrode 142 and the light-control pixel unit 103 have substantially the same size means that the ratio of the difference between the size of the pixel electrode 142 and the size of the light-control pixel unit 103 to the average value of the size of the pixel electrode 142 and the size of the light-control pixel unit 103 is less than 10% (for example, less than 5%).

[0073] For example, Figure 3 and Figure 4As shown, each data line 102 and a corresponding grid portion 110 (that is, the grid portion 110 that overlaps with the orthographic projection of each data line 102 on the gate line) have two overlapping positions in a direction perpendicular to the array substrate 100. For example, the overlapping positions correspond to the vertices of the first fold line 120 and the vertices of the second fold line 130, respectively. Figure 3 and Figure 4 As shown, the array substrate 100 further includes a common electrode line 104 extending along the second direction D2, and the common electrode line 104 overlaps with the connection between two adjacent grid portions 110 in a direction perpendicular to the array substrate 100. Figure 3 and Figure 4 As shown, the opening area 112 surrounded by each grid portion 110 and the two light-controlling pixel units 103 partially overlap in a direction perpendicular to the array substrate 100. Figure 3 As shown, a plurality of common electrode lines 104 and a plurality of data lines 102 are alternately arranged in a first direction D1. It should be noted that each data line 102 has two overlapping positions with a corresponding grid line of a grid portion 110 in a direction perpendicular to the array substrate 100, which means that each data line 102 overlaps with two positions on a grid line of a corresponding grid portion 110 in a direction perpendicular to the array substrate 100, or the orthographic projection of each data line 102 on the gate line has two overlapping positions with a corresponding grid line of the grid portion 110.

[0074] For example, the width of the first fold line 120 and the second fold line 130 are both between 9 micrometers and 11 micrometers (eg, 10 micrometers). Figure 1B The width of the gate line 101 shown is about 20 microns. Figure 3 The first fold line 120 and the second fold line 130 are approximately Figure 1B The half of the width of the gate line 510 shown can ensure that the aperture ratio of the display device 01 including the array substrate 100 does not decrease.

[0075] Fig. 6A FIG. 1 is a plan view of another array substrate 100 provided by at least one embodiment of the present disclosure. Fig. 6A The array substrate 100 shown in FIG. Figure 3 The array substrate 100 shown is similar; only the differences between the two are described here, and the similarities are not repeated.

[0076] Fig. 6AThe boundary routing of the light control pixel unit 103 of the array substrate 100 shown is formed by the corresponding common electrode line 104 and the first fold line 120 of the grid portion 110 of the corresponding gate line 101; the second fold line 130 of the grid portion 110 of each gate line 101 passes through the interior of the corresponding light control pixel unit 103. Fig. 6A In the illustrated array substrate 100 , an opening area 112 surrounded by each grid portion 110 and a light-control pixel unit 103 partially overlap in a direction perpendicular to the array substrate 100 .

[0077] like Fig. 6A As shown, two adjacent common electrode lines 104 intersect with the first fold line routing 120 of two adjacent gate lines, and the portion of the two adjacent common electrode lines 104 located between the first fold line routing 120 of the two adjacent gate lines and the portion of the first fold line routing 120 of the two adjacent gate lines located between the two adjacent common electrode lines 104 form a boundary routing of the light control pixel unit 103.

[0078] It should be noted that the first line segment 121, the second line segment 122, the third line segment 131 and the fourth line segment 134 are not limited to being implemented as Figure 3 The straight line segment shown (correspondingly, the grid portion 110 of the grid line 101 is not limited to being a diamond shape) can also be implemented as a curved line segment. Figure 6B FIG. 2 shows a plan view of another gate line 101 of an array substrate 100 provided by at least one embodiment of the present disclosure. Figure 6B As shown, the first line segment 121 , the second line segment 122 , the third line segment 131 , and the fourth line segment 134 are all implemented as curved line segments.

[0079] In some examples, the connection between each data line 102 and two adjacent grid portions 110 overlaps in a direction perpendicular to the array substrate 100, and the common electrode line 104 has two overlapping positions with the grid lines of a corresponding grid portion 110 (that is, the grid portion 110 that overlaps with the orthographic projection of the common electrode line 104 on the gate line) in a direction perpendicular to the array substrate 100. It should be noted that the common electrode line 104 has two overlapping positions with the grid lines of a corresponding grid portion 110 in a direction perpendicular to the array substrate 100, which means that the common electrode line 104 overlaps with two positions of the grid lines of a corresponding grid portion 110 in a direction perpendicular to the array substrate 100, or the orthographic projection of the common electrode line 104 on the gate line has two overlapping positions with the grid lines of a corresponding grid portion 110.

[0080] At least one embodiment of the present disclosure further provides a light control panel 10 . Figure 7 FIG. 1 is a cross-sectional schematic diagram of a light control panel 10 provided by at least one embodiment of the present disclosure. Figure 7 As shown, the light control panel 10 includes an opposing substrate 201, a liquid crystal layer 202, and any array substrate 100 provided by at least one embodiment of the present disclosure; the array substrate 100 and the opposing substrate 201 are arranged opposite to each other, and the liquid crystal layer 202 is sandwiched between the array substrate 100 and the opposing substrate 201. Figure 7 As shown, the counter substrate 201, the liquid crystal layer 202 and the array substrate 100 are sequentially arranged in the third direction D3. For example, the third direction D3, the first direction D1 and the second direction D2 intersect each other (for example, are perpendicular to each other).

[0081] For example, the light control panel 10 can adjust the transmittance of each light control pixel unit 103 of the light control panel 10 based on the data signal it receives, and the light control panel 10 can be used to provide the adjusted backlight to the display panel 20. For example, the light control pixel unit 103 of the light control panel is configured to control the intensity of light incident on the display sub-pixel unit corresponding to the light control pixel unit 103.

[0082] At least one embodiment of the present disclosure further provides a display device 01. For example, the display device 01 can be implemented as a display device based on ADS (Advanced Super Dimensional Field Switching Technology) or a display device based on IPS-ADS (i.e., i-ADS, In-Plane Switching-Advanced Super Dimensional Field Switching Technology) technology.

[0083] Figure 8 01 is a cross-sectional schematic diagram of a display device 01 provided by at least one embodiment of the present disclosure. Figure 8 As shown, the display device 01 includes a display panel 20, a backlight unit 30, and any light control panel 10 provided by at least one embodiment of the present disclosure. The display panel 20 is located on the light emitting side of the light control panel 10, and the backlight unit 30 is located on the side of the light control panel 10 away from the display panel 20. For example, Figure 8 As shown, the display panel 20, the light control panel 10 and the backlight unit 30 are sequentially arranged in the third direction D3. For example, compared with the opposing substrate 201 of the light control panel 10, the array substrate 100 of the light control panel 10 is closer to the backlight unit 30. For example, the resolution of the display panel 20 is twice that of the light control panel 10.

[0084] Fig. 9A yes Figure 8 FIG. 2 is a plan view of a display panel 20 of a display device 01. Fig. 9AAs shown, the display panel 20 includes a plurality of first signal lines 205 extending along a first direction D1 and a plurality of second signal lines 206 extending along a second direction D2; the plurality of first signal lines 205 and the plurality of second signal lines 206 intersect to define a plurality of display pixel units 204. For example, the first signal lines 205 are gate lines of the display panel 20, and the second signal lines 206 are data lines of the display panel 20.

[0085] like Fig. 9A As shown, each display pixel unit 204 includes a first display sub-pixel unit 2041, a second display sub-pixel unit 2042 and a third display sub-pixel unit 2043; the first display sub-pixel unit 2041, the second display sub-pixel unit 2042 and the third display sub-pixel unit 2043 are, for example, a red display sub-pixel unit, a green display sub-pixel unit and a blue display sub-pixel unit, respectively.

[0086] Fig. 9B yes Figure 8 Schematic diagram of a plan view of the display device 01 shown. Fig. 9B As shown, the size of each display pixel unit 204 in the first direction D1 is equal to the size of each display pixel unit 204 in the second direction D2. Fig. 9B As shown, the size of each display sub-pixel unit in the first direction D1 is equal to one third of the size of each display pixel unit 204 in the first direction D1. For example, the width of the first signal line 205 (the width of the first signal line 205 in the second direction) is greater than the width of the first fold line 120 (and the width of the second fold line 130). For example, the width of the first signal line 205 (the width of the first signal line 205 in the second direction) is greater than twice the width of the first fold line 120 (and the width of the second fold line 130).

[0087] Fig.10 yes Fig. 9B FIG. 1 is a plan view of the grid portion 110 of the display device 01. Fig. 9B and Fig.10 As shown, the size of the mesh portion 110 in the first direction D1 is W1, and the size of the mesh portion 110 in the second direction D2 is W2. Fig. 9BAs shown, the size W1 of the grid portion 110 in the first direction D1 is equal to twice the size of the display pixel unit 204 in the first direction D1; the size W2 of the grid portion 110 in the second direction D2 is less than (slightly less than) twice the size of the display pixel unit 204 in the second direction D2, and is greater than the size of the display pixel unit 204 in the second direction D2. In some examples, the size W2 of the grid portion 110 in the second direction D2 may also be equal to twice the size of the display pixel unit 204 in the second direction D2, in which case, the vertex of the first fold line 120 and the vertex of the second fold line 130 intersect with the second direction D2.

[0088] Fig.11 yes Fig. 9B FIG. 1 is a plan view of a pixel unit of the display device 01. Fig. 9B and Fig.11 As shown, the size of the light-control pixel unit 103 in the first direction D1 is P1, and the size of the light-control pixel unit 103 in the second direction D2 is P2. Figure 1B and Figure 1C As shown, the size P1 of the light control pixel unit 103 in the first direction D1 is equal to twice the size of the display pixel unit 204 in the first direction D1; the size (2) of the light control pixel unit 103 in the second direction D2 is equal to 2.5 times to 3 times the size of the display pixel unit 204 in the first direction D1.

[0089] It should be noted that the size of the pixel unit in the second direction D2 is equal to the spacing in the second direction D2 between two parallel lines connected to the vertices on both sides of the pixel unit in the second direction D2 and parallel to the first direction D1; for example, the size of the pixel unit in the second direction D2 is equal to the spacing in the second direction D2 between a line connected to the vertex on the upper side of the pixel unit in the second direction D2 and parallel to the first direction D1 and a line connected to the vertex on the lower side of the pixel unit in the second direction D2 and parallel to the first direction D1.

[0090] For example, the display device 01 further includes an isotropic diffusion film (not shown in the figure) disposed between the display panel 20 and the light control panel 10. The isotropic diffusion film can diffuse the light emitted by the light control panel 10 within a smaller angle range, thereby blurring the pattern of the data line 102 and further eliminating the moiré pattern, and at the same time, will not have a significant impact on the direction of the light emitted by the light control panel 10.

[0091] For example, the display device 01 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. It should be noted that other components of the display device (e.g., a control device, an image data encoding / decoding device, a row scanning driver, a column scanning driver, a clock circuit, etc.) can use applicable components, which are all understood by ordinary technicians in the field and are not described here, nor should they be used as limitations on the present disclosure. The display device can achieve an improved display effect.

[0092] For example, based on the same inventive concept, at least one embodiment of the present disclosure further provides a method for manufacturing an array substrate, which includes: forming a plurality of gate lines extending along a first direction, a plurality of data lines extending along a second direction intersecting the first direction, and a plurality of light-controlling pixel units.

[0093] For example, each gate line includes a plurality of grid portions arranged in parallel and connected in sequence along a first direction, and each grid portion includes a grid line and an opening area surrounded by the grid line. For example, the specific structure of the array substrate can refer to the array substrate provided by at least one embodiment of the present disclosure, and will not be repeated here. For example, a display device including an array substrate manufactured using the manufacturing method can improve the display effect.

[0094] Although the disclosure has been described in detail above with general descriptions and specific implementation methods, it is obvious to those skilled in the art that some modifications or improvements may be made to the embodiments of the disclosure. Therefore, these modifications or improvements made without departing from the spirit of the disclosure are within the scope of protection claimed by the disclosure.

[0095] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. An array substrate, comprising a plurality of gate lines extending along a first direction, a plurality of data lines extending along a second direction intersecting the first direction, and a plurality of light-controlling pixel units, wherein the plurality of gate lines are configured to provide scanning signals, and the plurality of data lines are configured to provide data signals. in, Each of the grid lines comprises a plurality of grid portions arranged in parallel and connected in sequence along the first direction, and each grid portion comprises a grid line and an opening area surrounded by the grid line; Wherein, the grid lines of each of the grid parts include a first fold line and a second fold line; The starting point of the first fold line is connected to the starting point of the second fold line; The end point of the first fold line is connected to the end point of the second fold line; and The vertices of the first fold line and the vertices of the second fold line are spaced apart in the second direction.

2. The array substrate according to claim 1, wherein: The first fold line includes a first line segment and a second line segment connected in sequence, and a connection point between the first line segment and the second line segment is a vertex of the first fold line; The second fold line includes a third line segment and a fourth line segment connected in sequence, and a connection point between the third line segment and the fourth line segment is a vertex of the second fold line; and The absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction, and the absolute value of the acute angle between the fourth line segment and the first direction are between 38 degrees and 55 degrees.

3. The array substrate according to claim 2, wherein: The absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction, and the absolute value of the acute angle between the fourth line segment and the first direction are between 42 degrees and 48 degrees.

4. The array substrate according to claim 2, wherein: The first fold line and the second fold line are symmetrical with respect to a line connecting a starting point of the first fold line and an end point of the first fold line.

5. The array substrate according to claim 4, wherein: The first line segment and the second line segment are symmetrical with respect to a line connecting a vertex of the first fold line and a vertex of the second fold line; and The third line segment and the fourth line segment are symmetrical with respect to a line connecting a vertex of the first fold line and a vertex of the second fold line.

6. The array substrate according to any one of claims 1 to 5, wherein: Each of the data lines has two overlapping positions with a grid line of a corresponding grid portion in a direction perpendicular to the array substrate, or overlaps with a connection point of two adjacent grid portions in a direction perpendicular to the array substrate.

7. The array substrate according to claim 6, further comprising a common electrode line extending along the second direction, in, The common electrode line overlaps with the connection points of two adjacent grid parts in a direction perpendicular to the array substrate, or has two overlapping positions with the grid line of a corresponding grid part in a direction perpendicular to the array substrate.

8. The array substrate according to any one of claims 1 to 5, wherein: The opening area surrounded by each grid portion and one or two light-control pixel units partially overlap in a direction perpendicular to the array substrate.

9. The array substrate according to any one of claims 1 to 5, wherein: The boundary line of each light-control pixel unit is formed by the corresponding data line and the first fold line of the grid portion of the gate line; and The second fold line of the grid portion of each gate line passes through the interior of the corresponding light-control pixel unit.

10. The array substrate according to any one of claims 1 to 5, further comprising a common electrode line extending along the second direction, in, The connection between the common electrode line and two adjacent mesh parts overlaps in a direction perpendicular to the array substrate; The boundary line of each of the light-control pixel units is formed by the corresponding common electrode line and the first fold line of the grid portion of the gate line; and The second fold line of the grid portion of each gate line passes through the interior of the corresponding light-control pixel unit.

11. The array substrate according to any one of claims 1 to 5, wherein: Each of the light-control pixel units further includes a switch element and a pixel electrode; The switch element includes a gate, a source and a drain, The gate of the switching element is electrically connected to the corresponding second zigzag line, and one of the source and the drain of the switching element is electrically connected to the pixel electrode; and The number of the switch elements is equal to the number of the second zigzag lines.

12. The array substrate according to any one of claims 1 to 5, wherein: The width of the first zigzag line and the second zigzag line are both between 9 micrometers and 11 micrometers.

13. The array substrate according to claim 1, wherein: The first fold line includes a first line segment and a second line segment connected in sequence, and a connection point between the first line segment and the second line segment is a vertex of the first fold line; The second fold line includes a third line segment and a fourth line segment connected in sequence, and the connection point between the third line segment and the fourth line segment is a vertex of the second fold line; The absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction, and the absolute value of the acute angle between the fourth line segment and the first direction are between 42 degrees and 48 degrees; The first fold line and the second fold line are symmetrical with respect to a line connecting a starting point of the first fold line and an end point of the first fold line; The first line segment and the second line segment are symmetrical with respect to a line connecting a vertex of the first fold line and a vertex of the second fold line; The third line segment and the fourth line segment are symmetrical with respect to a line connecting the vertices of the first fold line and the vertices of the second fold line; Each of the data lines has two overlapping positions with a grid line of a corresponding grid portion in a direction perpendicular to the array substrate; The array substrate further comprises a common electrode line extending along the second direction, wherein the common electrode line overlaps with two adjacent grid portions at a connection point in a direction perpendicular to the array substrate; The opening area surrounded by each grid portion and the two light-control pixel units partially overlap in a direction perpendicular to the array substrate; The boundary routing of the light-control pixel unit is formed by the corresponding data line and the first folded line routing of the grid portion of the gate line, and the second folded line routing of the grid portion of each gate line passes through the interior of the corresponding light-control pixel unit; Each of the light-control pixel units also includes a switching element and a pixel electrode; the switching element includes a gate, a source and a drain, the gate of the switching element is electrically connected to the corresponding second zigzag line, one of the source and the drain of the switching element is electrically connected to the pixel electrode, and the number of the switching elements is equal to the number of the second zigzag lines.

14. A light control panel, comprising the array substrate according to any one of claims 1 to 13, an opposing substrate and a liquid crystal layer, in, The array substrate and the counter substrate are arranged opposite to each other, and the liquid crystal layer is sandwiched between the array substrate and the counter substrate.

15. A display device, comprising: Display panel; The light control panel as claimed in claim 14; as well as Backlight unit, The display panel is located on the light emitting side of the light control panel, and the backlight unit is located on a side of the light control panel away from the display panel.

16. The display device according to claim 15, wherein: The display panel includes a plurality of display pixel units arranged in an array; The size of each of the grid parts in the first direction is equal to twice the size of each of the display pixel units in the first direction; as well as The size of each of the grid portions in the second direction is less than or equal to twice the size of each of the display pixel units in the second direction.

17. The display device according to claim 15, wherein: The size of each of the light-control pixel units in the first direction is equal to twice the size of each of the display pixel units in the first direction; as well as The size of each of the light-control pixel units in the second direction is equal to 2.5-3 times the size of each of the display pixel units in the first direction.

Images