Semiconductor Memory Device, Semiconductor Memory System, and Driving Method Thereof

Abstract

Provided are a semiconductor memory device, a semiconductor memory system, and a driving method thereof. The semiconductor memory device includes a resistive change memory device, and the resistive change memory device includes a control circuit block and a plurality of memory layers electrically connected to the control circuit block. The semiconductor memory device includes a pattern generation block, a position correction block, and a position determination block. The pattern generation block receives a row address, a column address, and a memory layer selection signal to generate a plurality of pattern generation signals for selecting a plurality of memory cells in the memory layer in various patterns. The position correction block receives a temporary code and reflects the position of the memory layer in the temporary code to output a correction code for classifying the memory cells into a temporary near cell region and a temporary far cell region. The position determination block is configured to generate a first reset signal to a third reset signal based on the pattern generation signals and the correction code to reset a near cell region, an intermediate cell region, and a far cell region.

Description

[0001] Cross - reference to Related Applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0102537, filed on August 21, 2019, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various exemplary embodiments of the present invention generally relate to a semiconductor memory device, a semiconductor memory system including the semiconductor memory device, and a method of driving the semiconductor memory system. More particularly, the present invention relates to a semiconductor memory device capable of distinguishing regions of a memory deck based on a position factor and a bit error ratio, a semiconductor memory system including the semiconductor memory device, and a method of driving the semiconductor memory system. Background Art

[0004] Recently, next - generation memory devices have been widely developed to replace DRAM and flash memory devices. The next - generation memory devices may include resistive - change memory devices, which include materials (i.e., variable - resistance materials) that rapidly change resistance according to an applied bias voltage to switch between at least two resistance states. The resistive - change memory devices may include phase - change random - access memory (PCRAM), resistive random - access memory (RRAM), magnetic random - access memory (MRAM), ferroelectric random - access memory (FRAM), etc.

[0005] The resistive - change memory device may include a memory cell array having a cross - point array structure. The cross - point array structure may be arranged between word lines and bit lines, where access elements and memory cells may be alternately arranged.

[0006] The cross - point array - type resistive - change memory device may have reliability problems such as read interference, cycle durability, etc. caused by a resistance difference between cells close to a control block and cells far from the control block. Summary of the Invention

[0007] In an exemplary embodiment of the present disclosure, a semiconductor memory device may include a resistive change memory device including a control circuit block and a plurality of memory decks electrically connected to the control circuit block. The semiconductor memory device may include a pattern generation block, a position correction block, and a position determination block. The pattern generation block may receive a row address, a column address, and a memory deck selection signal to generate a plurality of pattern generation signals for selecting a plurality of memory cells in the memory deck in various patterns. The position correction block may receive a temporary code and reflect the position of the memory deck in the temporary code to output a corrected code for classifying the memory cells into a temporary near cell region and a temporary far cell region. The position determination block may generate a first reset signal to a third reset signal based on the pattern generation signal and the corrected code to reset a near cell region, an intermediate cell region, and a far cell region.

[0008] In an exemplary embodiment of the present disclosure, a semiconductor memory system includes a controller and a memory device. The controller may include a temporary code setter configured to store and change information on a temporary far cell region and a temporary near cell region of a memory deck into a temporary code. The controller may output the temporary code and an address of a selected memory cell. The memory device includes a plurality of memory decks, a control circuit block, a region reset circuit, and a bit error determination block. The control circuit block is configured to generate signals for controlling the memory decks. The region reset circuit may receive the temporary code and the address to generate a first reset signal to a third reset signal for resetting a far cell region, an intermediate cell region, and a near cell region. The bit error determination block may receive the first reset signal to the third reset signal to determine a bit error ratio based on regions of the memory deck. The temporary code setter may receive the bit error ratio measured by the bit error determination block to change a boundary of the temporary far cell region and output the temporary code.

[0009] In an exemplary embodiment of the present disclosure, in a method of driving a semiconductor memory system, a bit error ratio of regions classified as a far cell region, an intermediate cell region, and a near cell region in a memory deck may be measured. A bit error ratio of a selected region among the cell regions is compared with a target bit error ratio of the selected region. When the measured bit error ratio is higher than the target bit error ratio, the temporary code is changed to increase an area of the selected region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above aspects, other aspects, features, and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram showing a semiconductor memory system according to an exemplary embodiment.

[0012] Figure 2 is a view showing a memory cell array (MCA) of a resistive change memory device according to an exemplary embodiment.

[0013] Figure 3 is a circuit diagram showing a memory cell according to an exemplary embodiment.

[0014] Figure 4 is a perspective view showing a memory cell array of a stacked resistive change memory device according to an exemplary embodiment.

[0015] Figure 5 is a block diagram showing a region reset circuit according to an exemplary embodiment.

[0016] Figure 6 is a block diagram showing a pattern generation block according to an exemplary embodiment.

[0017] Figure 7 is a diagram showing Figure 6 the control signal generator in

[0018] Figure 8 is a diagram showing Figure 7 the circuit diagrams of first to third control signal generators in

[0019] Figure 9 is a circuit diagram showing a first pattern generator according to an exemplary embodiment.

[0020] Figure 10 is a graph showing the distribution of memory cells selected according to a first pattern generation signal.

[0021] Figure 11 is a circuit diagram showing an n-th pattern generator (n = two, three, four) according to an exemplary embodiment.

[0022] Figure 12 is a graph showing the distribution of memory cells selected in a memory layer according to a second pattern generation signal.

[0023] Figure 13 is a graph showing the distribution of memory cells selected in a memory layer according to a third pattern generation signal.

[0024] Figure 14 is a graph showing the distribution of memory cells selected in a memory layer according to a fourth pattern generation signal.

[0025] Figure 15 is a graph showing the distribution of memory cells selected in a memory layer according to a fifth pattern generation signal.

[0026] Figure 16A and Figure 16B is a block diagram showing the position correction block 230 according to an exemplary embodiment.

[0027] Figure 17 is a plan view showing the distribution of near cell regions of a storage layer (deck) in each tile according to an exemplary embodiment.

[0028] Figure 18 is a block diagram showing a position determination block according to an exemplary embodiment.

[0029] Figure 19 is a circuit diagram showing a first mode combiner according to an exemplary embodiment.

[0030] Figures 20 to 23 is a graph showing the distribution of selected memory cells according to region setting codes according to an exemplary embodiment.

[0031] Figure 24 is a circuit diagram showing a signal combiner according to an exemplary embodiment.

[0032] Figure 25 is a view showing a method of setting a region of a storage layer according to an exemplary embodiment.

[0033] Figure 26 is a block diagram showing a semiconductor memory system including a bit error determination block according to an exemplary embodiment.

[0034] Figure 27 is a block diagram showing a temporary code setter according to an exemplary embodiment.

[0035] Figure 28 is a flowchart showing the operation of a temporary code setter according to an exemplary embodiment. Detailed Description

[0036] Various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The drawings are schematic diagrams of various embodiments (and intermediate structures). Thus, variations in the illustrated configurations and shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, the described embodiments should not be construed as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present invention as defined by the appended claims.

[0037] The present invention is described with reference to cross-sectional views and / or plan views of ideal embodiments of the present invention. However, embodiments of the present invention should not be construed as limiting the inventive concept. Although some embodiments of the present invention will be shown and described, those of ordinary skill in the art will understand that these embodiments can be changed without departing from the principles and spirit of the present invention.

[0038] Figure 1 is a block diagram showing a semiconductor memory system according to an exemplary embodiment, Figure 2 is a view showing a memory cell array (MCA) of a resistive change memory device according to an exemplary embodiment, and Figure 3 is a circuit diagram showing a memory cell according to an exemplary embodiment.

[0039] Referring to Figure 1 , the semiconductor memory system 10 may include a processor 50, a controller 100, and a semiconductor memory device M.

[0040] The processor 50 may be electrically connected to the controller 100 through a bus 15. The processor 50 may provide a memory address and a memory access request including data (such as a read request, a write request, etc.) to the controller 100.

[0041] The controller 100 may provide a command CMD, an address ADD, data DATA, and a control signal CTRL to the semiconductor memory device M by using the memory access request. The controller 100 may include a temporary code setter 110 configured to receive a bit error rate from the semiconductor memory device M. The temporary code setter 110 may store and set temporary codes TC1 and TC2. The temporary codes TC1 and TC2 may include address information to define a boundary between a far cell region and a near cell region based on the bit error rate of the semiconductor memory device M. The configuration and operation of the temporary code setter 110 will be described later. The controller 100 may include an ECC engine 120. Both the ECC engine 120 and the temporary code setter 110 may receive the bit error rate from the semiconductor memory device M. The ECC engine 120 may be designed to have a correctable error amount of the semiconductor memory device M.

[0042] In one embodiment, the semiconductor memory device M may include at least one memory cell array MCA. For example, the memory cell array MCA may include a plurality of memory layers and a control circuit block CB to control the operation of the memory layers.

[0043] Each memory layer may include a plurality of memory cells using variable resistance elements as storage media. Therefore, the semiconductor memory device M may include a resistive memory device.

[0044] Referring toFigure 2 , the storage layer may include a plurality of word lines WL0 to WL3 and a plurality of bit lines BL0 to BL4. The word lines WL0 to WL3 and the bit lines BL0 to BL4 may intersect with each other. The storage layer may include a plurality of memory cells MC, which are arranged at the intersection points between the word lines WL0 to WL3 and the bit lines BL0 to BL4. The structure of the memory cells MC included at the intersection points between the word lines WL0 to WL3 and the bit lines BL0 to BL4 may be referred to as a cross-point array structure.

[0045] Referring to Figure 3 , the memory cell MC may include a combination of a selection element S and a variable resistor R connected between the word line WL and the bit line BL. A combination of a selection element S and a variable resistor R may be included at each intersection point between the word line WL and the bit line BL. The selection element S may include a diode or a MOS transistor. The selection element S may use a Ovonic threshold switch (OTS), which includes a phase change memory layer.

[0046] The variable resistor R may correspond to a storage medium. Based on the voltage difference between the bit line BL and the word line WL, the variable resistor R may represent different resistance values. The variable resistor R may include a phase change layer or a resistance change layer. The phase change layer may include GaSb, InSb, InSe, Sb2Te3, GeTe, GeSbTe, GaSeTe, InSbTe, SnSb2Te4, InSbGe, AgInSbTe, (GeSn)SbTe, GeSb(SeTe), Te 81 Ge 15 Sb2S2, etc.

[0047] The phase change layer may have an amorphous state with a relatively high resistance and a crystalline state with a relatively low resistance. The phase change layer may have a phase changed due to the Joule heat generated by the current amount and the cooling time.

[0048] Each memory cell may include a single level cell configured to store one bit of data. In this case, according to the stored data, the memory cell may have two resistance distributions. Alternatively, each memory cell may include a multi-level cell configured to store not less than two bits of data. In this case, according to the stored data, the memory cell may have four or eight resistance distributions.

[0049] In the cross-point array type storage layer, the memory cells close to the control circuit block CB (hereinafter referred to as near cells) may have worse read interference and cycle durability than the cells far from the control circuit block CB (hereinafter referred to as far cells).

[0050] Therefore, a conventional controller can arbitrarily divide a memory cell array MCA (i.e., a memory layer) into a near-cell region close to a control circuit block CB and a far-cell region far from the control circuit block CB based on the address of a selected memory cell MC and perform control. However, since the memory layer of a semiconductor memory device can be three-dimensionally arranged, it may be difficult to precisely control the memory layer based on two-dimensional division.

[0051] Figure 4 is a perspective view showing a memory cell array of a stacked resistive change memory device according to an exemplary embodiment.

[0052] Referring to Figure 4 , the semiconductor substrate Sub may include a plurality of tile regions (T1 and T2) or a MAT region and a peripheral circuit region PB, and a memory cell array MCA may be formed in the plurality of tile regions (T1 and T2) or the MAT region.

[0053] A plurality of memory layers Deck1 to Deck4 may be stacked in each of the tile regions T1 and T2. However, the present invention is not limited thereto. In different embodiments, the four memory layers Deck1, Deck2, Deck3, and Deck4 may be stacked only in one of the tile regions T1 or T2.

[0054] The control circuit block CB may extend to the tile regions T1 and T2 and / or the peripheral circuit region PB between the tile regions T1 and T2. For example, the control circuit block CB may be integrated in the semiconductor substrate Sub under the memory layers Deck1 to Deck4.

[0055] Since the memory layers Deck1 to Deck4 can be three-dimensionally stacked, the three-dimensional distances (i.e., heights Ha and Hb) of the control circuit block CB need to be reflected in variables to distinguish the near-cell region and the far-cell region. For example, when comparing the near-cell region NC3 of the third memory layer Deck3 with the near-cell region NC1 of the first memory layer Deck1, it may be difficult to determine the near-cell region NC3 of the third memory layer Deck3 as the near-cell region NC.

[0056] Therefore, it may be necessary to reset the near-cell region and the far-cell region of the stacked variable resistive memory device based on the three-dimensional position of the memory cell and the actual error rate.

[0057] Figure 5is a block diagram showing a region reset circuit according to an exemplary embodiment. For example, each of the storage layers Deck1 to Deck4 may include a 16×16 storage cell region. For example, a storage cell region may be selected by the four most significant bits (MSBs) of the row address A<3:0> (hereinafter referred to as the MSB row address) and the four MSBs of the column address B<3:0> (hereinafter referred to as the MSB column address). In addition, in order to distinguish regions, the size of the MSBs may be increased.

[0058] Referring to Figure 5 , the region reset circuit 200 may be integrated into the control circuit block CB of the semiconductor memory device M. In addition, the region reset circuit 200 may be integrated into the semiconductor memory device M without being integrated into the control circuit block CB.

[0059] The region reset circuit 200 may include a mode generation block 210, a position correction block 230, and a position determination block 250.

[0060] The mode generation block 210 may receive a storage layer selection signal dec_sel, the MSB row address A<3:0>, and the MSB column address B<3:0> to generate a plurality of mode generation signals IEQ1 to IEQ5.

[0061] The first mode generation signal IEQ1 may alternately turn on the storage cells in the storage layer in units of one bit. The second mode generation signal IEQ2 may alternately turn on the storage cells in the storage layer in units of two bits. The third mode generation signal IEQ3 may alternately turn on the storage cells in the storage layer in units of four bits. The fourth mode generation signal IEQ4 may alternately turn on the storage cells in the storage layer in units of eight bits. The fifth mode generation signal IEQ5 may alternately turn on the storage cells in the storage layer in units of sixteen bits.

[0062] The position correction block 230 may receive the storage layer selection signal dec_sel and the temporary codes TC1<4:0> and TC2<4:0> to generate correction codes CC1<4:0> and CC2<4:0> reflecting the stacked positions of the storage layers Deck2 to Deck4.

[0063] The position determination block 250 may receive the mode generation signals IEQ1 to IEQ5 and the correction codes CC1<4:0> and CC2<4:0> to generate position reset signals FAR_EN, MID_EN, and NEAR_EN.

[0064] Figure 6 is a block diagram showing a mode generation block according to an exemplary embodiment, Figure 7 is showing Figure 6 the control signal generator in Figure 8 is showingFigure 7 Circuit diagrams of the first to third control signal generators in

[0065] Hereinafter, the MSB row address A<3:0> and the MSB column address B<3:0> for selecting a 16×16 memory cell region can be represented in binary notation by A<3>, A<2>, A<1>, A<0>, B<3>, B<2>, B<1>, and B<0>.

[0066] Referring to Figures 6 to 8 , the mode generation block 210 may include a control signal generator 2100, a first mode generator 2110, a second mode generator 2120, a third mode generator 2130, and a fourth mode generator 2140.

[0067] The control signal generator 2100 may include a first control signal generator 2100a, a second control signal generator 2100b, and a third control signal generator 2100c.

[0068] The first control signal generator 2100a may perform a logical operation on the second bit A<1> of the row address A<3:0> and the second bit B<1> of the column address B<3:0> to generate a first control signal S1 and a first inverted control signal / S1.

[0069] The second control signal generator 2100b may perform a logical operation on the third bit A<2> of the row address A<3:0> and the third bit B<2> of the column address B<3:0> to generate a second control signal S2 and a second inverted control signal / S2.

[0070] The third control signal generator 2100c may perform a logical operation on the MSB A<3> of the row address A<3:0> and the MSB B<3> of the column address B<3:0> to generate a third control signal S3 and a third inverted control signal / S3.

[0071] In an exemplary embodiment, the first to third control signal generators 2100a, 2100b, and 2100c may have substantially the same configuration.

[0072] For example, as Figure 8 shown, each of the first to third control signal generators 2100a, 2100b, and 2100c may be configured to perform an exclusive NOR operation, an exclusive OR operation, and an inversion operation. For example, each of the first to third control signal generators 2100a, 2100b, and 2100c may include an exclusive NOR gate 2101, an exclusive OR gate 2102, and an inverter 2103.

[0073] The exclusive NOR gate 2101 can receive the storage layer selection signal dec_sel and the row address bit A <n>(n = 1, 2, or 3) to perform a NAND-XOR operation. The NAND-XOR gate 2102 can use the output signal from the NAND-XOR gate 2101 and the column address bit B <n>(n = 1, 2, or 3) performs an exclusive OR operation to generate first to third inverted control signals / S1, / S2, and / S3. The inverter 2103 can invert the first to third inverted control signals / S1, / S2, and / S3 to generate first to third control signals S1, S2, and S3.

[0074] Figure 9 is a circuit diagram showing a first pattern generator according to an exemplary embodiment.

[0075] Referring to Figure 6 and Figure 9 , the first pattern generator 2110 can generate a first pattern generation signal IEQ1 to alternately select memory cells in units of one bit in a memory layer including a 16×16 memory cell region.

[0076] The first pattern generator 2110 can receive a memory layer selection signal dec_sel, a least significant bit (LSB) row address A<0>, and an LSB column address B<0> to generate a first pattern generation signal IEQ1 that conducts in units of one bit.

[0077] The first pattern generator 2110 can be configured to perform a NAND-XOR operation, a first NOR operation, a second NOR operation, an AND operation, and an inversion operation. The first pattern generator 2110 can include a NAND-XOR gate 2111, a first NOR gate 2112, an AND gate 2113, a second NOR gate 2114, and an inverter 2115.

[0078] The NAND-XOR gate 2111 can receive the memory layer selection signal dec_sel and the LSB row address A<0> and perform a NAND-XOR operation on them. The first NOR gate 2112 can perform a NOR operation by using the output signal from the NAND-XOR gate 2111 and the LSB column address B<0>. The inverter 2115 can invert the output signal from the first NOR gate 2112 to generate a first carry signal C1. The AND gate 2113 can perform an AND operation by using the output signal from the NAND-XOR gate 2111 and the LSB column address B<0>. The second NOR gate 2114 can perform a NOR operation by using the output signal from the first NOR gate 2112 and the output signal from the AND gate 2113 to generate the first pattern generation signal IEQ1. When the LSB row address A<0> is substantially the same as the LSB column address B<0>, the first pattern generation signal IEQ1 can be enabled to a high level. When the LSB row address A<0> is higher than the LSB column address B<0>, the first carry signal C1 can be enabled to a high level.

[0079] Figure 10 is a diagram showing the distribution of the selected memory cells according to the first pattern generation signal. In Figure 10 Among them, the x-axis can represent the row address A<3:0> in decimal numbers, and the y-axis can represent the column address B<3:0> in decimal numbers. Ms in the memory cell MC can represent the selected memory cell, while Mn can represent the unselected memory cell.

[0080] Referring to Figure 10 , the first-mode generation signal IEQ1 can be generated to alternately select the memory cell Mc in the memory layer one bit at a time in the row address direction and the column address direction. Since the first-mode generation signal IEQ1 can be generated by combining the LSB row address A<0> and the LSB column address B<0>, the selection of the memory cell can be controlled one bit at a time.

[0081] Figure 11 is a circuit diagram showing the n-mode generator (n = two, three, four) according to an exemplary embodiment. The second to fourth mode generators 2120, 2130, and 2140 can have substantially the same configuration. Therefore, the second to fourth mode generators 2120, 2130, and 2140 can be referred to as the n-mode generator (n = two, three, or four).

[0082] The n-mode generators 2120, 2130, and 2140 can be configured to perform an inversion operation and a transmission operation. The n-mode generators 2120, 2130, and 2140 can include first to fourth inverters In1 to In4 and first to fourth transmission gates TM1 to TM4.

[0083] The first inverter In1 can invert the (n - 1) carry signal Cn-1 provided by the (n - 1)-mode generator to output the (n - 1) inverted carry signal / Cn-1.

[0084] The first transmission gate TM1 can output the carry signal Cn-1 in response to a pair of (n - 1) control signals Sn-1 and / Sn-1. The second transmission gate TM2 and the third transmission gate TM3 can output the inverted carry signal / Cn-1 in response to a pair of (n - 1) control signals Sn-1 and / Sn-1. The (n - 1) control signal Sn-1 can be input to the NMOS transistor of the second transmission gate TM2, the PMOS transistor of the third transmission gate TM3, and the NMOS transistor of the fourth transmission gate TM4. The (n - 1) inverted control signal / Sn-1 can be input to the PMOS transistor of the second transmission gate TM2, the NMOS transistor of the third transmission gate TM3, and the PMOS transistor of the fourth transmission gate TM4. The fourth transmission gate TM4 can output the inverted (n - 1) column address bit / B in response to a pair of (n - 1) control signals Sn-1 and / Sn-1 <n-1>。

[0085] The second inverter In2 can invert and output the output signal from the first transmission gate TM1 or the second transmission gate TM2.

[0086] The third inverter In3 can invert the output signal from the second inverter In2 to generate the n-mode generation signal IEQn. The fourth inverter In4 can invert the output signal from the third transmission gate TM3 or the fourth transmission gate TM4 to output the n-carry signal Cn.

[0087] For example, when n is two, the second mode generator 2120 can operate as follows.

[0088] When the LSB row address A<0> is higher than the LSB column address B<0>, the first carry signal C1 enabled to a high level can be input into the first inverter In1. Therefore, the first inverter In1 can invert and output the first carry signal C1. When the LSB row address A<0> is equal to or lower than the LSB column address B<0>, the first inverted carry signal / C1 can be enabled to a high level.

[0089] Based on the levels of the control signals Sn-1, / Sn-1, the second inverter In2 receives the first inverted carry signal / C1 and outputs the buffered first carry signal C1. When the LSB row address A<0> is greater than the LSB column address B<0>, the buffered first carry signal C1 can be enabled to a high level.

[0090] When the second bit row address A<1> is different from the second bit column address B<1>, the first control signal S1 generated by the first control signal generator 2100a in Figure 7 and Figure 8 can be enabled to a high level.

[0091] Therefore, when the first control signal S1 is low (i.e., the second bit row address A<1> is substantially the same as the second bit column address B<1>), the first transmission gate TM1 can output the first carry signal C1 as the second mode generation signal IEQ2. That is, when the LSB row address A<0> is equal to or less than the LSB column address B<0> and the second bit row address A<1> is substantially the same as the second bit column address B<1>, the second mode signal IEQ2 can be enabled to a high level.

[0092] When the first control signal S1 is high (i.e., the second row address A<1> is different from the second column address B<1>), the second transmission gate TM2 can output the inverted first carry signal / C1 as the second mode signal IEQ2. When the first row address A<0> is greater than the first column address B<0> and the second row address A<1> is different from the second column address B<1>, the second mode signal IEQ2 output from the second transmission gate TM2 can be enabled to a high level.

[0093] When the first control signal S1 is low (i.e., the second row address A<1> is substantially the same as the second column address B<1>), the third transmission gate TM3 can output the inverted first carry signal / C1 enabled to a high level. The fourth inverter In4 can invert the inverted first carry signal / C1 to output the second carry signal C2.

[0094] When the first control signal S1 is high (i.e., the second row address A<1> is different from the second column address B<1>), the fourth transmission gate TM4 can output the inverted second column address / B<1>. The fourth inverter In4 can output the second column address B<1> as the second carry signal C2.

[0095] Figure 12 is a diagram showing the distribution of selected memory cells in the memory layer according to the generation of signals in the second mode, Figure 13 is a diagram showing the distribution of selected memory cells in the memory layer according to the generation of signals in the third mode, Figure 14 is a diagram showing the distribution of selected memory cells in the memory layer according to the generation of signals in the fourth mode, and Figure 15 is a diagram showing the distribution of selected memory cells in the memory layer according to the generation of signals in the fifth mode.

[0096] In Figures 12 to 15 , the x-axis can represent the row address in decimal numbers, while the y-axis can represent the column address in decimal numbers.

[0097] As Figure 12 shown, the second mode generation signal IEQ2 can alternately select memory cell regions in two-bit units along the row and column directions in the memory layer according to the operations of the n-mode generators 2120, 2130, and 2140.

[0098] As Figure 13 shown, the third mode generation signal IEQ3 can alternately select memory cell regions in four-bit units along the row and column directions in the memory layer.

[0099] As Figure 14 shown, the fourth mode generation signal IEQ4 can alternately select memory cell regions in eight-bit units along the row and column directions in the memory layer.

[0100] As Figure 15 shown, the fifth mode generation signal IEQ5 can alternately select memory cell regions in units of sixteen bits in both the row direction and the column direction in the memory layer.

[0101] The fifth mode generation signal IEQ5 can correspond to the fourth carry signal C4 of the fourth mode generator 2140. Therefore, when all row address bits A<3>, A<2>, A<1>, and A<0> are greater than all column address bits B<3>, B<2>, B<1>, and B<0>, the fifth mode generation signal IEQ5 can be enabled to a high level. As a result, the fifth mode generation signal IEQ5 can turn on memory cells in units of sixteen bits in both the row direction and the column direction in the memory layer.

[0102] Figure 9 and Figure 11 Examples of the mode generator that selects memory cells in units of one bit, two bits, four bits, eight bits, and sixteen bits can be shown. However, the present invention is not limited thereto.

[0103] Figure 16A and Figure 16B are block diagrams showing the position correction block 230 according to an exemplary embodiment.

[0104] Referring Figure 16A and Figure 16B , the position correction block 230 can receive the temporary codes TC1<4:0> and TC2<4:0> as binary codes. The position correction block 230 can reflect the variable positions of the stacked memory layers in the temporary codes TC1<4:0> and TC2<4:0> to output the correction codes CC1<4:0> and CC2<4:0>.

[0105] For example, the temporary code can further include boundary address information between a far cell region and a near cell region provided by the temporary code setter 110 of the controller 100. The temporary code can include a first temporary code TC1<4:0> and a second temporary code TC2<4:0>. The reason for distinguishing the temporary code into the first temporary code TC1<4:0> and the second temporary code TC2<4:0> and controlling them will be described in detail with reference to Figure 17 .

[0106] Figure 17 is a plan view showing the distribution of near cell regions of the memory layer in each die according to an exemplary embodiment.

[0107] Referring Figure 17 , in order to effectively electrically connect the storage layers on the same plane arranged on adjacent tiles T1 to T4, the control circuit blocks CB1 and CB2 can be arranged symmetrically with respect to each other. Therefore, depending on the positions of the control circuit blocks CB1 and CB2, the memory cells MC1 and MC2 can be included in the near cell region or the far cell region.

[0108] For example, when the memory cell MC1 connected to the control circuit block CB1 is selected, the memory cell MC1 can be classified as the near cell region. The memory cell MC2 connected to the control circuit block CB1 can be classified as the far cell region. Conversely, when the memory cell MC2 connected to the control circuit block CB2 is selected, the memory cell MC2 can be classified as the near cell region. Therefore, the memory cell MC1 can be classified as the far cell region based on the control circuit block CB2. Therefore, the far cell region and the near cell region in the storage layer can be changed based on the position of the selected memory cell and which control circuit block it is connected to in the storage layer. Therefore, in order to accurately identify the position of the selected memory cell, two temporary codes TC1<4:0> and TC2<4:0> are required.

[0109] In other words, the temporary code requires a first temporary code TC1<4:0> and a second temporary code TC2<4:0> to consider the relative position of the selected memory cell.

[0110] Return reference Figure 16A , the position correction block 230 can include an adder 230a configured to accumulate specific bits in response to the storage layer selection signal dec_sel.

[0111] The position correction block 230 can include: a first register R1 configured to store 000 bits representing the first storage layer Deck1; a second register R2 configured to store 010 bits representing the second storage layer Deck2; a third register R3 configured to store 011 bits representing the third storage layer Deck3; and a fourth register R4 configured to store 100 bits representing the fourth storage layer Deck4.

[0112] The storage layer selection signal dec_sel can enable any one of the first to fourth registers R1 to R4. The adder 230a can add the bits in the enabled registers R1 to R4 to the temporary codes TC1<4:0> and TC2<4:0> to output correction codes CC1<4:0> and CC2<4:0>.

[0113] For example, the correction codes CC1<4:0> and CC2<4:0> can include boundary address information. Depending on the position (or height) of the storage layer, the boundary address information of the correction codes CC1<4:0> and CC2<4:0> may be different.

[0114] Reference Figure 16B , the position correction block 230 can add the storage layer selection signal dec_sel to the temporary codes TC1<4:0> and TC2<4:0> to output the correction codes CC1<4:0> and CC2<4:0>. The position correction block 230 can include a first adder 231 and a second adder 232. For example, the storage layer selection signal dec_sel can include three or five bits that increase according to the position of the storage layer.

[0115] The first adder 231 can add the storage layer selection signal dec_sel to the first temporary code TC1<4:0> to generate the first correction code CC1<4:0>. The second adder 232 can add the storage layer selection signal dec_sel to the second temporary code TC2<4:0> to generate the second correction code CC2<4:0>.

[0116] Figure 18 is a block diagram showing a position determination block according to an exemplary embodiment.

[0117] Reference Figure 18 , the position determination block 250 can include a first mode combiner 260a, a second mode combiner 260b, and a signal combiner 270.

[0118] The first mode combiner 260a can receive the first to fifth mode generation signals IEQ1~IEQ5 and the first correction code CC1<4:0> to generate the first region setting code D_C1. For example, when selecting a storage unit connected to the first control block CB1 of the storage layer, the far unit region or the near unit region of the storage layer can be reset by the first region setting code D_C1.

[0119] The second mode combiner 260b can receive the first to fifth mode generation signals IEQ1~IEQ5 and the second correction code CC2<4:0> to generate the second region setting code D_C2. For example, when selecting a storage unit connected to the second control block CB2 of the storage layer, the far unit region or the near unit region of the storage layer can be reset by the second region setting code D_C2.

[0120] The first mode combiner 260a can include a first code register 261 configured to temporarily store the first correction code CC1<4:0>. The second mode combiner 260b can include a second code register 262 configured to temporarily store the second correction code CC2<4:0>.

[0121] The first mode combiner 260a and the second mode combiner 260b may logically combine the first correction code CC1<4:0> and the second correction code CC2<4:0> in the code registers 261 and 262 and the first to fifth mode generation signals IEQ1 to IEQ5 to generate a first area setting code D_C1 and a second area setting code D_C2 for resetting respective remote unit areas.

[0122] In different embodiments, the first mode combiner 260a and the second mode combiner 260b may have substantially the same configuration. Therefore, to avoid restating the components of the first mode combiner 260a and the second mode combiner 260b, only the first mode combiner 260a is described.

[0123] Figure 19 is a circuit diagram showing a first mode combiner according to an exemplary embodiment.

[0124] Referring to Figure 19 , the first mode combiner 260a may include a 1-2 bit combiner 2610, a 3-bit combiner 2630, a 4-bit combiner 2650, and a 5-bit combiner 2670.

[0125] The 1-2 bit combiner 2610 may receive the first bit CC1<0> and the second bit CC1<1> of the first correction code CC1<4:0>, the first mode generation signal IEQ1, and the second mode generation signal IEQ2 and combine them with each other to generate a 1-2 bit setting code L1. The 1-2 bit setting code L1 may determine the first bit and the second bit of the first area setting code D_C1.

[0126] The 1-2 bit combiner 2610 may perform an inversion operation, an OR operation, and a NAND operation. The 1-2 bit combiner 2610 may include a first inverter IN11 and a second inverter IN12, first to third OR gates OR11, OR12, and OR13, and a first NAND gate ND11 and a second NAND gate ND12.

[0127] The first OR gate OR11 can receive the second mode generation signal IEQ2 inverted by the first inverter IN11 and the second bit CC1<1> of the first correction code CC1<4:0>. The second OR gate OR12 can receive the second mode generation signal IEQ2 and the second bit CC1<1> of the first correction code CC1<4:0> inverted by the second inverter IN12. The first NAND gate ND11 can receive the output signal from the second OR gate OR12 and the first mode generation signal IEQ1. The third OR gate OR13 can receive the output signal from the first NAND gate ND11 and the first bit CC1<0> of the first correction code CC1<4:0>. The second NAND gate ND12 can receive the output signal from the first OR gate OR11 and the output signal from the third OR gate OR13 to generate the 1-2 bit setting code L1.

[0128] The 3-bit combiner 2630 can receive the 1-2 bit setting code L1, the third bit CC1<2> of the first correction code CC1<4:0>, and the third mode generation signal IEQ3 to generate the 3-bit setting code L2.

[0129] The 3-bit combiner 2630 can be configured to perform OR operations and NAND operations. The 3-bit combiner 2630 can include an OR gate OR14 and first to third NAND gates ND13, ND14, and ND15. The OR gate OR14 and the first NAND gate ND13 can receive the 1-2 bit setting code L1 and the third mode generation signal IEQ3. The second NAND gate ND14 can receive the output signal from the first NAND gate ND13 and the third bit CC1<2> of the first correction code CC1<4:0>. The third NAND gate ND15 can receive the output signal from the OR gate OR14 and the output signal from the second NAND gate ND14 to generate the 3-bit setting code L2.

[0130] The 4-bit combiner 2650 can receive the 3-bit setting code L2, the fourth bit CC1<3> of the first correction code CC1<4:0>, and the fourth mode generation signal IEQ4 to generate the 4-bit setting code L3.

[0131] The 4-bit combiner 2650 can be configured to perform OR operation, NAND operation, and inversion operation. The 4-bit combiner 2650 may include an OR gate OR15, first to third NAND gates ND16, ND17, and ND18, and an inverter IN13. The OR gate OR15 and the first NAND gate ND16 can receive the 3-bit setting code L2 and the fourth bit CC1<3> of the first correction code CC1<4:0>. The second NAND gate ND17 can receive the output signal from the first NAND gate ND16 and the fourth mode generation signal IEQ4. The third NAND gate ND18 can receive the output signal from the OR gate OR15 and the output signal from the second NAND gate ND17. The inverter IN13 can invert the third NAND gate ND18 to generate the 4-bit setting code L3.

[0132] The 5-bit combiner 2670 can receive the 4-bit setting code L3, the fifth bit CC1<4> of the first correction code CC1<4:0>, and the fifth mode generation signal IEQ5 to generate the first region setting code D_C1.

[0133] The 5-bit combiner 2670 can be configured to perform OR operation, NAND operation, and inversion operation. The 5-bit combiner 2670 may include an OR gate OR16, first to third NAND gates ND19, ND20, and ND21, and an inverter IN14. The OR gate OR16 and the first NAND gate ND19 can receive the fifth bit CC1<4> of the first correction code CC1<4:0> and the fifth mode generation signal IEQ5. The second NAND gate ND20 can receive the inverted 4-bit setting code / L3 which is the output signal of the inverter IN14 and the output signal from the first NAND gate ND19. The third NAND gate ND21 can receive the output signal from the OR gate OR16 and the output signal from the second NAND gate ND20 to generate the first region setting code D_C1.

[0134] As a result, the first mode combiner 260a can generate the first region setting code D_C1 capable of changing the boundary of the far unit region in the first correction code CC1<4:0>. For example, the first mode combiner 260a can add the far unit region defined by the first correction code CC1<4:0> to the mode region of the memory cell selected by at least one of the first to fifth mode generation signals IEQ1 to IEQ5 or subtract the far unit region defined by the first correction code CC1<4:0> from the mode region of the memory cell selected by at least one of the first to fifth mode generation signals IEQ1 to IEQ5 to generate the first region setting code D_C1 capable of changing the boundary of the far unit region of the memory layer.

[0135] Similarly, the second mode combiner 260b can generate a second region setting code D_C2 capable of changing the boundary of the far cell region in the second correction code CC2<4:0>. For example, the second mode combiner 260b can subtract the far cell region defined by the second correction code CC2<4:0> from the mode region of the memory cell selected by at least one of the signals IEQ1 to IEQ5 generated by the first to fifth modes to generate a second region setting code D_C2 capable of changing the boundary of the far cell region of the memory layer.

[0136] Figures 20 to 23 is a diagram showing the distribution of memory cells selected according to a region setting code according to an exemplary embodiment.

[0137] Figure 20 can show the distribution of the memory cell Ms selected by the first region setting code D_C1 or the second region setting code D_C2 when the first correction code CC1<4:0> is "00011". For example, when "00011" is input as the first correction code CC1<4:0> into the first mode combiner 260a, the first mode combiner 260a can select a memory cell MC(n, n to n + 11) among 16×16 memory cells MC(0 to 15, 0 to 15), where n is an integer between 0 and 3. The selected memory cell Ms can form a first far cell region F1. The first far cell region F1 can be defined by the combination of the initial far cell region in the temporary codes TC1 and TC2 and the far cell region in the correction codes CC1<4:0> and CC2<4:0>.

[0138] Figure 21 can show the distribution of the memory cell Ms selected by the first region setting code D_C1 or the second region setting code D_C2 when "01100" is input as the first correction code CC1<4:0> or the second correction code CC2<4:0>. For example, when "01100" is input as the first correction code CC1<4:0> into the first mode combiner 260a, the first mode combiner 260a can select a memory cell MC(n, 0 to n + 2) among 16×16 memory cells MC(0 to 15, 0 to 15), where n is an integer between 0 and 15, to form a second far cell region F2. The area of the second far cell region F2 can be smaller than the area of the first far cell region F1.

[0139] Figure 22 The distribution of the memory cells Ms selected by the first region setting code D_C1 or the second region setting code D_C2 when the first correction code CC1<4:0> or the second correction code CC2<4:0> is "10101" can be shown. For example, when "10101" is input as the first correction code CC1<4:0> into the first mode combiner 260a, the first mode combiner 260a can select the memory cells MC(n + 7 to 15, n to 8) among the 16×16 memory cells MC(0 to 15, 0 to 15), where n is an integer between 0 and 8, to form the third far cell region F3. The area of the third far cell region F3 can be smaller than the areas of the first far cell region F1 and the second far cell region F2.

[0140] Figure 23 The distribution of the memory cells Ms selected by the first region setting code D_C1 or the second region setting code D_C2 when the first correction code CC1<4:0> or the second correction code CC2<4:0> is "11010" can be shown. For example, when "11010" is input as the first correction code CC1<4:0> into the first mode combiner 260a, the first mode combiner 260a can select the memory cells MC(n + 12 to 15, n) among the 16×16 memory cells MC(0 to 15, 0 to 15), where n is an integer between 0 and 3, to form the fourth far cell region F4. The area of the fourth far cell region F4 can be smaller than the areas of the first far cell region F1, the second far cell region F2, and the third far cell region F3.

[0141] The "00011" code, "01100" code, "10101" code, and "11010" code as the first correction code CC1<4:0> or the second correction code CC2<4:0> can be used to set the first to fourth far cell regions F1, F2, F3, and F4, thereby obtaining various mode combinations, because the 1-bit and 2-bit, 1-bit to 3-bit, and / or 1-bit to 4-bit of each of the 00011 code, 01100 code, 10101 code, and 11010 code may be different.

[0142] Figure 24 is a circuit diagram showing a signal combiner according to an exemplary embodiment, and Figure 25 is a view showing a method of setting regions of a storage layer according to an exemplary embodiment.

[0143] Referring to Figure 24 , the signal combiner 270 can include a far cell region setter 2710, an intermediate cell region setter 2720, and a near cell region setter 2730.

[0144] The far unit area setter 2710 can receive a first area setting code D_C1 and a second area setting code D_C2. The far unit area setter 2710 can generate a first reset signal FAR_EN, which sets the common part between the area set by the first area setting code D_C1 and the area set by the second area setting code D_C2 as the far unit area. The far unit area setter 2710 can include a logic circuit configured to perform the AND operation of the first area setting code D_C1 and the second area setting code D_C2. For example, as Figure 2 shown, as Figure 25 shown, when the first far unit area F1 is defined by the first area setting code D_C1 and the third far unit area F3 is defined by the second area setting code D_C2 (see (a)), the reset far unit area (b) FAR_END can be the third far unit area F3 corresponding to the common part between the first far unit area F1 and the third far unit area F3.

[0145] The middle unit area setter 2720 can receive the first area setting code D_C1 and the second area setting code D_C2. The middle unit area setter 2720 can generate a second reset signal MID_EN, which is used to set the middle unit area formed by subtracting the far unit area from the combined area of the area set by the first area setting code D_C1 and the area set by the second area setting code D_C2. The middle unit area setter 2720 can include a logic circuit configured to perform the XOR operation of the first area setting code D_C1 and the second area setting code D_C2. Therefore, as Figure 25 shown, the middle unit area (c) MID_EN can be defined by subtracting the reset far unit area (b) from the first far unit area F1.

[0146] The near unit area setter 2730 can receive the first area setting code D_C1 and the second area setting code D_C2. The near unit area setter 2730 can generate a third reset signal NEAR_EN, which is used to set the area that does not correspond to the area set by the first area setting code D_C1 and the area set by the second area setting code D_C2 as the near unit area. The near unit area setter 2730 can include a logic circuit configured to perform the NOR operation on the first area setting code D_C1 and the second area setting code D_C2. Therefore, as Figure 25 shown, the near unit area (d) NEAR_EN can be defined as the area not included in the first far unit area F1 and the third far unit area F3.

[0147] Figure 26 It is a block diagram showing a semiconductor memory system including a bit error determination block according to an exemplary embodiment.

[0148] Referring to Figure 26 , the first to third reset signals FAR_EN, MID_EN, and NEAR_EN generated from the region reset circuit 200 can be sent to the bit error determination block 300 in the semiconductor memory device M.

[0149] As described above, the region reset circuit 200 can reset the positions of the far unit region, the middle unit region, and the near unit region temporarily set by the controller 100 based on the position of the storage layer, the connection relationship between the control circuit blocks CB1 and CB2 and the storage cells, etc. Therefore, the bit error determination block 300 can detect the bit error rate of the regions distinguished according to the first to third reset signals FAR_EN, MID_EN, and NEAR_EN in response to the first to third reset signals FAR_EN, MID_EN, and NEAR_EN for resetting the boundaries between the far unit region, the middle unit region, and the near unit region.

[0150] The bit error rate measured by the bit error determination block 300 of the semiconductor memory device M can be sent to the temporary code setter 110. The temporary code setter 110 can change the boundary between the temporary far unit region and the temporary near unit region of the storage layer based on the measured bit error rate. Then the temporary code setter 110 can send the changed boundary codes A<3:0> and B<3:0> to the storage device M to compensate for the bit error rate.

[0151] The temporary code setter 110 in the controller 100 can change the address information (i.e., the boundary address of the far unit region) of the far unit region and the near unit region in the temporary codes TC1<4:0> and TC2<4:0> based on the bit error rate.

[0152] Figure 27 It is a block diagram showing a temporary code setter according to an exemplary embodiment, and Figure 28 It is a flowchart showing the operation of a temporary code setter according to an exemplary embodiment.

[0153] Referring to Figure 27 , the temporary code setter 110 can include a target bit error rate (BER) memory 111, a comparator 113, and a code regulator 115.

[0154] The target bit error rate (BER) memory 111 can store the target bit error rates of the far unit region, the middle unit region, and the near unit region. The target bit error rate can refer to the maximum error rate determined to be abnormal (or incorrect). The target bit error rate memory 111 can include registers.

[0155] Comparator 113 can compare the bit error rate (BER) of the corresponding region measured by the bit error determination block 300 of the semiconductor memory device M (as Figure 26 shown) with the target bit error rate provided by the target bit error rate memory 111. Then, comparator 113 can send the comparison result to the code regulator 115.

[0156] The code regulator 115 can change the boundary between the near cell region, the middle cell region, and / or the far cell region of the temporary codes TC1<4:0> and TC2<4:0> based on the comparison result.

[0157] Hereinafter, the operation of the temporary code setter of the exemplary embodiment will be described with reference to Figure 28 In the following, the operation of the temporary code setter of the exemplary embodiment will be described with reference to

[0158] Referring to Figure 28 , in step S1, the bit error rate BER of the corresponding region measured by the bit error determination block 300 of the semiconductor memory device M can be input to the temporary code setter 110.

[0159] In step S2, the comparator 113 of the temporary code setter 110 can compare the measured bit error rate BER with the target bit error rate of the corresponding region. In step S3, when the measured bit error rate is substantially the same as the target bit error rate BER of the corresponding region, the boundary of the corresponding region can be maintained.

[0160] In step S4, when the measured bit error rate BER is higher than the target bit error rate BER of the corresponding region, in step S5, the area of the corresponding region can be reduced to lower the bit error rate of the corresponding region. That is, the code regulator 115 can change the address bits of the temporary codes TC1<4:0> and TC2<4:0> based on the comparison result input from the comparator 113 to change the boundary of the corresponding region of the temporary codes TC1<4:0> and TC2<4:0>.

[0161] Conversely, in step S6, when the measured bit error rate is smaller than the allowable range measured from the target bit error rate of the corresponding region, the area of the corresponding region can be set very large to reduce the BER of the corresponding region (step S7). That is, the code regulator 115 can change the address bits of the temporary codes TC1<4:0> and TC2<4:0> to reduce the area of the corresponding region.

[0162] In step S3, when the measured bit error rate BER is within the allowable range, the area of the corresponding region can be maintained.

[0163] According to an exemplary embodiment, each region of a stacked resistive change memory device may be reset based on an actual position of a memory cell and a bit error rate to prevent a yield of a semiconductor memory device from being reduced due to errors being concentrated in a specific region.

[0164] The above embodiments of the present invention are intended to illustrate and not limit the present invention. There may be various alternatives and equivalent schemes. The present invention is not limited by the embodiments described herein. The present invention is also not limited to any specific type of semiconductor device. Based on this disclosure, other additions, subtractions, or modifications are obvious and fall within the scope of the appended claims. < / n> < / n>

Claims

1. A semiconductor memory device includes a control circuit block and a plurality of memory layers electrically connected to the control circuit block. Each of the plurality of memory layers includes a plurality of memory cells using variable resistance elements as storage media. The semiconductor memory device includes: A region reset circuit configured to receive a temporary code and an address of a selected memory cell to reset a far cell region, an intermediate cell region, and a near cell region based on a bit error rate of the plurality of memory layers. Wherein, the region reset circuit includes: A mode generation block configured to receive a row address, a column address, and a memory layer selection signal to generate a plurality of mode generation signals for selecting a plurality of memory cells in the selected memory layer in various modes. A position correction block configured to receive the temporary code to reflect a position of the memory layer in the temporary code and output a correction code, the temporary code being used to classify the memory cells into a temporary near cell region and a temporary far cell region; and A position determination block configured to generate a first reset signal to a third reset signal based on the plurality of mode generation signals and the correction code to reset the near cell region, the intermediate cell region, and the far cell region.

2. The semiconductor memory device according to claim 1, wherein, The mode generation block is configured to generate the plurality of mode generation signals for selecting the plurality of memory cells in the selected memory layer in units of one bit, two bits, four bits, eight bits, and sixteen bits based on the row address, the column address, and the memory layer selection signal.

3. The semiconductor memory device according to claim 1, wherein, The mode generation block includes: A first mode generator configured to combine a first bit of the row address with a first bit of the column address to output a first mode generation signal for selecting a memory cell in units of one bit and a first carry signal. A second mode generator configured to output at least one of a second mode generation signal for selecting a memory cell in units of two bits and a second carry signal in response to a pair of first control signals generated by combining a second bit of the row address with a second bit of the column address, wherein the second mode generation signal and the second carry signal include the first carry signal or a second bit signal of the column address. A third mode generator configured to output at least one of a third mode generation signal for selecting a memory cell in units of four bits and a third carry signal in response to a pair of second control signals generated by combining a third bit of the row address with a third bit of the column address, wherein the third mode generation signal and the third carry signal include the second carry signal or a third bit signal of the column address; and A fourth mode generator configured to output a fourth mode generation signal for selecting a memory cell in units of eight bits or in units of sixteen bits and a fourth carry signal in response to a pair of third control signals generated by combining a fourth bit of the row address with a fourth bit of the column address.

4. The semiconductor memory device according to claim 1, wherein, The position correction block includes: At least one register configured to store the position code of the storage layer and output the position code of the storage layer selected in response to the storage layer selection signal; and An adder configured to add the temporary code to the position code of the selected storage layer output from the register and output the correction code.

5. The semiconductor memory device according to claim 1, wherein, The storage layer selection signal includes a plurality of address bits that vary according to the stacking position, and the position correction block includes an adder configured to add the address bits of the storage layer selection signal to the address bits of the temporary code.

6. The semiconductor memory device according to claim 3, wherein The temporary code includes a first temporary code and a second temporary code, wherein the position determination block includes: A first mode combiner configured to generate a first area setting code based on a first correction code generated based on the first temporary code and the plurality of mode generation signals; A second mode combiner configured to generate a second area setting code based on a second correction code generated based on the second temporary code and the plurality of mode generation signals; and A signal combiner configured to generate the first reset signal to the third reset signal based on the first area setting code and the second area setting code, wherein when a storage unit connected to the control circuit block at the first area of the storage layer is selected, the first temporary code defines the boundary of the far unit area, and wherein when a storage unit connected to the control circuit block at the second area of the storage layer is selected, the second temporary code defines the boundary of the far unit area, wherein the second area of the storage layer is opposite to the first area of the storage layer.

7. The semiconductor memory device according to claim 6, wherein, Each of the first mode combiner and the second mode combiner is configured to add the far unit area set by the first correction code or the second correction code to the area of the selected storage unit set by the first mode generation signal to the fifth mode generation signal or subtract the far unit area set by the first correction code or the second correction code from the area of the selected storage unit set by the first mode generation signal to the fifth mode generation signal to generate the first area setting code or the second area setting code.

8. The semiconductor memory device according to claim 6, wherein, Each of the first mode combiner and the second mode combiner includes: A 1-2 bit combiner configured to combine the first mode generation signal, the second mode generation signal, the first bit of the first correction code or the second correction code, and the second bit of the first correction code or the second correction code with each other to generate a 1-2 bit setting code; A 3-bit combiner configured to combine the third bit of the first correction code or the second correction code with the third mode generation signal to generate a 3-bit setting code; A 4-bit combiner configured to combine the fourth bit of the first correction code or the second correction code with the fourth mode generation signal to generate a 4-bit setting code; and A 5-bit combiner configured to combine the fifth bit of the first correction code or the second correction code with a fifth pattern generation signal to generate a 5-bit setting code.

9. The semiconductor memory device according to claim 6, wherein, The signal combiner is configured to output a first reset signal to reset a common portion between a portion defined by the first region setting code and a portion defined by the second region setting code to the far cell region. wherein the signal combiner is configured to output a second reset signal to reset a non-common portion between a portion defined by the first region setting code and a portion defined by the second region setting code to the middle cell region, and wherein the signal combiner is configured to output a third reset signal to reset a portion other than a portion defined by the first region setting code and a portion defined by the second region setting code to the near cell region.

10. A semiconductor storage system, comprising: A controller including a temporary code setter configured to store and change information on a temporary far cell region and a temporary near cell region of a storage layer into a temporary code, the controller being configured to output the temporary code and an address of a selected storage cell; and A storage device, comprising: A plurality of storage layers, each of the plurality of storage layers including a plurality of storage cells using variable resistance elements as storage media; A control circuit block configured to generate signals for controlling the storage layer; A region reset circuit configured to receive the temporary code and the address and generate first to third reset signals for resetting a far cell region, a middle cell region, and a near cell region; and A bit error determination block configured to receive the first to third reset signals and determine a bit error rate based on regions of the storage layer, wherein the temporary code setter is configured to receive the bit error rate measured by the bit error determination block, change a boundary of the temporary far cell region, and output the temporary code.

11. The semiconductor memory system according to claim 10, wherein, The region reset circuit includes: A pattern generation block configured to receive a row address, a column address, and a storage layer selection signal provided from the controller and generate a plurality of pattern generation signals for selecting the plurality of storage cells in the selected storage layer in various patterns; A position correction block configured to receive the temporary code, reflect a position of the storage layer in the temporary code, and output a correction code; and A position determination block configured to generate first to third reset signals for resetting a near cell region, a middle cell region, and a far cell region based on the pattern generation signals and the correction code.

12. The semiconductor memory system according to claim 11, wherein, The pattern generation block is configured to generate, based on the row address, the column address, and the storage layer selection signal: A first pattern generation signal for selecting the storage layer in units of one-bit storage cells; A second pattern generation signal for selecting the storage layer in units of two-bit storage cells; A third pattern generation signal for selecting the storage layer in units of four-bit storage cells; A fourth mode generating signal for selecting the storage layer in units of the eight-bit storage cells; and A fifth mode generating signal for selecting the storage layer in units of the sixteen-bit storage cells.

13. The semiconductor memory system according to claim 12, wherein, The position correction block includes: At least one register configured to store a position code for indicating the position of the storage layer and output the position code of the selected storage layer in response to the storage layer selection signal; and An adder configured to add the temporary code to the position code of the selected storage layer output from the register and output the correction code.

14. The semiconductor memory system according to claim 12, wherein, The storage layer selection signal includes a plurality of address bits that increase according to the stacking position, and the position correction block includes an adder configured to add the address bits of the storage layer selection signal to the address bits of the temporary code.

15. The semiconductor memory system according to claim 12, wherein, The temporary code includes a first temporary code and a second temporary code, wherein the position determination block includes: A first mode combiner configured to generate a first region setting code based on a first correction code generated based on the first temporary code and the mode generating signal; A second mode combiner configured to generate a second region setting code based on a second correction code generated based on the second temporary code and the mode generating signal; and A signal combiner configured to generate the first reset signal to the third reset signal based on the first region setting code and the second region setting code, wherein when a storage cell connected to the control circuit block at the first area of the storage layer is selected, the first temporary code defines the boundary of the far cell region, and wherein when a storage cell connected to the control circuit block at the second area of the storage layer is selected, the second temporary code defines the boundary of the far cell region, where the second area of the storage layer is opposite to the first area of the storage layer.

16. The semiconductor memory system according to claim 15, wherein, Each of the first mode combiner and the second mode combiner is configured to add the far cell region set by the first correction code or the second correction code to the region of the selected storage cell set by the first mode generating signal to the fifth mode generating signal or subtract the far cell region set by the first correction code or the second correction code from the region of the selected storage cell set by the first mode generating signal to the fifth mode generating signal to generate the first region setting code or the second region setting code.

17. The semiconductor memory system according to claim 15, wherein, The signal combiner is configured to output a first reset signal to reset the common part between the part defined by the first region setting code and the part defined by the second region setting code to the far cell region, wherein the signal combiner is configured to output a second reset signal to reset the non-common part between the part defined by the first region setting code and the part defined by the second region setting code to the middle cell region, and The signal combiner is configured to output a third reset signal to reset a portion other than a portion defined by the first region setting code and a portion defined by the second region setting code to the near cell region.

18. The semiconductor memory system according to claim 10, wherein, The bit error determination block is configured to measure bit error rates of the far cell region, the middle cell region, and the near cell region reset by the first to third reset signals, and The bit error determination block is configured to transmit the measured bit error rates to the controller.

19. The semiconductor memory system according to claim 10, wherein, The temporary code setter includes: a memory configured to store target bit error rates of the far cell region, the middle cell region, and the near cell region; a comparator configured to compare the measured bit error rate with the target bit error rate and output a comparison result; and a code adjuster configured to adjust bits of the temporary code based on the comparison result to change boundaries of corresponding regions.

20. The semiconductor memory system according to claim 19, wherein, When the measured bit error rate of the corresponding region is higher than the target bit error rate of the corresponding region, the code adjuster adjusts bits of the temporary code to increase an area of the corresponding region.

21. A driving method for driving a semiconductor memory system according to any one of claims 10 to 20, the method comprising: measuring bit error rates of a far cell region, a middle cell region, and a near cell region in a storage layer of the semiconductor memory system; comparing a bit error rate of a selected region among the cell regions with a target bit error rate of the selected region; and when the measured bit error rate of the corresponding region is higher than the target bit error rate of the corresponding region, changing a temporary code to increase an area of the corresponding region.

22. The method according to claim 21, wherein, The temporary code includes address information for defining boundaries of the far cell region of the storage layer.

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