FINFET contacts and methods of forming the same

Abstract

The present disclosure relates to FINFET contacts and methods for forming the same. A device includes: a semiconductor fin protruding from a substrate; a first gate stack located above the semiconductor fin and a second gate stack located above the semiconductor fin; a first source / drain region located in the semiconductor fin adjacent to the first gate stack and a second source / drain region located in the semiconductor fin adjacent to the second gate stack; a first layer of a first dielectric material located on the first gate stack and a second layer of the first dielectric material located on the second gate stack; a first source / drain contact located on the first source / drain region and adjacent to the first gate stack; a first layer of a second dielectric material located on a top surface of the first source / drain contact; and a second source / drain contact located on the second source / drain region and adjacent to the second gate stack, wherein the top surface of the second source / drain contact does not contain the second dielectric material.

Description

Technical Field

[0001] The present disclosure relates generally to FINFET contacts and methods of forming the same. Background Art

[0002] In the latest development of transistor manufacturing technology, metal is used to form contact plugs and metal gates. The contact plugs are used to connect to the source and drain regions and the gate of the transistor. The source / drain contact plugs are usually connected to the source / drain silicide region, which is formed by depositing a metal layer and then performing annealing to react the metal layer with the silicon in the source / drain region. The gate contact plug is used to connect to the metal gate.

[0003] The formation of the metal gate may include forming a dummy gate stack, removing the dummy gate stack to form an opening, filling the opening with a metal material, and performing planarization to remove excess metal material to form a metal gate. The metal gate is then recessed to form a groove, and a dielectric hard mask is filled into the groove. When forming a gate contact plug, the hard mask is removed so that the gate contact plug can contact the metal gate.

[0004] Source / drain contact plugs are also formed to be electrically coupled to the source / drain regions. The formation of the source / drain contact plugs includes etching an interlayer dielectric (ILD) to form contact openings, and forming source / drain silicide regions and contact plugs in the contact openings. Summary of the invention

[0005] According to an embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a semiconductor fin over a substrate; forming a first gate stack and a second gate stack over the semiconductor fin, wherein the first gate stack and the second gate stack are surrounded by an interlayer dielectric (ILD); forming a first dielectric material over the first gate stack and the second gate stack, wherein a top surface of the first dielectric material is higher than a first height of the substrate; performing an etching process to form a first opening in the ILD adjacent to the first gate stack, and forming a second opening in the ILD adjacent to the second gate stack, wherein after the etching process, a top surface of the first dielectric material located on the first gate stack is higher than a second height of the substrate, and the second height is less than the first height; forming a first conductive material in the first opening to form a first contact plug, and forming the first conductive material in the second opening to form a second contact plug; forming a second dielectric material over the first contact plug and over the second contact plug; and performing a planarization process on the second dielectric material, wherein after the planarization process, the first conductive material of the second contact plug is exposed, and the first conductive material of the first contact plug is covered by the second dielectric material.

[0006] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a first gate stack above a first fin, and forming a second gate stack above a second fin; depositing a first dielectric material above the first gate stack and above the second gate stack; forming a first opening in the first dielectric material adjacent to the first gate stack, and forming a second opening in the first dielectric material adjacent to the second gate stack; etching the first dielectric material above the first gate stack, wherein the etching forms a groove having a first depth in the first dielectric material; and forming a first contact in the first opening and forming a second contact in the second opening, comprising: depositing a conductive material in the first opening and the second opening, wherein the conductive material has a first height above the first opening, and the first height is less than the first depth; depositing a second dielectric material above the conductive material in the first opening and above the conductive material in the second opening; and removing the second dielectric material above the conductive material in the second opening using a planarization process.

[0007] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor fin, the semiconductor fin protruding from a substrate; a first gate stack and a second gate stack, the first gate stack being located above the semiconductor fin, and the second gate stack being located above the semiconductor fin; a first source / drain region and a second source / drain region, the first source / drain region being located in the semiconductor fin adjacent to the first gate stack, and the second source / drain region being located in the semiconductor fin adjacent to the second gate stack; a first layer of a first dielectric material and a second layer of a first dielectric material, the first layer of the first dielectric material being located on the first gate stack, and the second layer of the first dielectric material being located on the second gate stack; a first source / drain contact, the first source / drain contact being located on the first source / drain region and adjacent to the first gate stack; a first layer of a second dielectric material, the first layer of the second dielectric material being located on a top surface of the first source / drain contact; and a second source / drain contact, the second source / drain contact being located on the second source / drain region and adjacent to the second gate stack, wherein the top surface of the second source / drain contact does not contain the second dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1-Figure 6 A perspective view is shown of an intermediate stage in forming source / drain contact plugs in accordance with some embodiments.

[0010] Figure 7A-7B Perspective and cross-sectional views illustrate intermediate stages of forming source / drain contact plugs in accordance with some embodiments.

[0011] Figure 8 A cross-sectional view illustrating an intermediate stage of forming source / drain contact plugs according to some embodiments.

[0012] Figure 9A-9B Perspective and cross-sectional views illustrate intermediate stages of forming source / drain contact plugs in accordance with some embodiments.

[0013] Figure 10-11 A perspective view is shown of an intermediate stage in forming source / drain contact plugs in accordance with some embodiments.

[0014] Figure 12-Figure 20A cross-sectional view illustrating an intermediate stage of forming source / drain contact plugs according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0017] According to some embodiments, a transistor with a source / drain contact plug and a method for forming the same are provided. According to some embodiments, an intermediate stage of forming a source / drain contact plug is shown. Some variations of some embodiments are discussed. In some embodiments, grooves and openings are formed in a dielectric material to form a self-aligned contact. The grooves and openings are partially filled with a conductive material (rather than, for example, being overfilled), which allows the use of fewer planarization steps to form a self-aligned contact. The use of fewer planarization steps to form a self-aligned contact allows a thicker dielectric material layer to be retained, which can increase process flexibility and increase yield. In various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. In some illustrated embodiments, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concepts of the present disclosure. Planar transistors may also employ the concepts of the present disclosure.

[0018] exist Figure 1In the embodiment of the present invention, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor substrate 20 may be a portion of the wafer 10, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0019] Further references Figure 1 , a well region 22 is formed in the substrate 20. According to some embodiments of the present disclosure, the well region 22 is an n-type well region formed by injecting n-type impurities (which may be phosphorus, arsenic, antimony, etc.) into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is a p-type well region formed by injecting p-type impurities (which may be boron, indium, etc.) into the substrate 20. The resulting well region 22 may extend to the top surface of the substrate 20. The n-type or p-type impurity concentration may be equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm -3 in the range between.

[0020] refer to Figure 2, the isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is alternatively referred to as a shallow trench isolation (STI) region. The portion of the substrate 20 between adjacent STI regions 24 is referred to as a semiconductor strip 26. In order to form the STI region 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, by using low pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etching mask to form a Figure 2 A hard mask 30 is shown.

[0021] Next, the patterned hard mask layer 30 is used as an etching mask to etch the pad oxide layer 28 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with (one or more) dielectric materials. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to remove excess portions of the dielectric material, and the remaining portions of the (one or more) dielectric materials are the STI regions 24. The CMP process may use a slurry containing a grinding material such as Ce(OH) x , CeO2, SiO2, TiO2, Al2O3, ZrO2, MnO, etc., or a combination thereof. In some embodiments, the size of the abrasive material may be between about 1 nm and about 150 nm. The STI region 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc. formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI region 24 may also include a dielectric material above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material above the liner dielectric may include silicon oxide.

[0022] The top surface of hard mask 30 and the top surface of STI region 24 may be substantially flush with each other. Semiconductor strips 26 are between adjacent STI regions 24. According to some embodiments of the present disclosure, semiconductor strips 26 are part of original substrate 20, and thus the material of semiconductor strips 26 is the same as the material of substrate 20. According to alternative embodiments of the present disclosure, semiconductor strips 26 are replacement strips formed by etching a portion of substrate 20 between STI regions 24 to form a groove, and performing epitaxy to re-grow another semiconductor material in the groove. Therefore, semiconductor strips 26 are formed of a semiconductor material different from that of substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon germanium, silicon carbon, or III-V compound semiconductor materials.

[0023] refer to Figure 3 , the STI region 24 is recessed so that the top of the semiconductor strip 26 protrudes higher than the top surface 24A of the rest of the STI region 24 to form a protruding fin 36. The etching can be performed using a dry etching process, wherein, for example, HF3 and NH3 are used as etching gases. During the etching process, plasma may be generated. Argon may also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 24 is performed using a wet etching process. The etching chemicals may include, for example, HF.

[0024] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns with, for example, smaller pitches than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0025] refer to Figure 4 , the dummy gate stack 38 is formed to extend on the top surface and sidewalls of the (protruding) fin 36. The dummy gate stack 38 may include a dummy gate dielectric 40, and a dummy gate electrode 42 above the dummy gate dielectric 40. The dummy gate electrode 42 may be formed, for example, using polysilicon, and other materials may also be used. Each dummy gate stack 38 may also include one (or more) hard mask layers 44 above the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 may span a single or multiple protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a length direction perpendicular to the length direction of the protruding fin 36.

[0026] Next, a gate spacer 46 is formed on the sidewall of the dummy gate stack 38. According to some embodiments of the present disclosure, the gate spacer 46 is formed of one or more dielectric materials such as silicon nitride, silicon carbonitride, etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0027] Then, an etching process is performed to etch the portion of the protruding fin 36 that is not covered by the dummy gate stack 38 and the gate spacer 46, resulting in Figure 5 The structure shown. The recess may be anisotropic, so that the portion of the fin 36 directly below the dummy gate stack 38 and the gate spacer 46 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 may be lower than the top surface 24A of the STI region 24. A groove 50 is formed accordingly. The groove 50 includes portions on opposite sides of the dummy gate stack 38 and portions between the remaining portions of the protruding fin 36.

[0028] Next, epitaxial regions (source / drain regions) 54 are formed by selectively growing (by epitaxy) semiconductor material in the recesses 50, resulting in Figure 6 . Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities may be in-situ doped as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) or silicon boron (SiB) may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP) or silicon carbon phosphorus (SiCP) may be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 54 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, multiple layers thereof, and the like. After the recess 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and facets may be formed. Further growth of the epitaxial region 54 may also cause adjacent epitaxial regions 54 to merge with each other. A void (air gap) 56 may be generated. According to some embodiments of the present disclosure, when the top surface of the epitaxial region 54 is still wavy, or when the top surface of the merged epitaxial region 54 has become substantially flat (this is achieved by further growth on the epitaxial region 54, such as Figure 6 As shown), the formation of the epitaxial region 54 can be completed.

[0029] After the epitaxial process, the epitaxial region 54 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also indicated by reference numeral 54. According to an alternative embodiment of the present disclosure, when the epitaxial region 54 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation step is skipped.

[0030] Fig. 7A A perspective view of a structure after forming a contact etch stop layer (CESL) 58 and a first interlayer dielectric (ILD) 60 is shown. The CESL 58 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. The first ILD 60 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. The first ILD 60 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as tetraethylorthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical grinding process may be performed to make the top surfaces of the first ILD 60, the dummy gate stack 38, and the gate spacer 46 flush with each other.

[0031] Figure 7B Shows Fig. 7A 7B-7B in the reference cross section, which shows the dummy gate stack 38. Next, as Figure 8 As shown, the dummy gate stack 38 including the hard mask layer 44, the dummy gate electrode 42 and the dummy gate dielectric 40 is etched to form trenches 62 between the gate spacers 46. The top surface and sidewalls of the protruding fins 36 are exposed to the trenches 62.

[0032] Next, if Fig.9A and Fig. 9B As shown, in the groove 62 ( Figure 8 ) to form a replacement gate stack 72. Fig. 9B Shows Fig.9A The replacement gate stack 72 includes a gate dielectric 68 and a corresponding gate electrode 70 .

[0033] According to some embodiments of the present disclosure, the gate dielectric 68 includes an interfacial layer (IL) 64 as its lower portion. The IL 64 is formed on the exposed surface of the protruding fin 36. The IL 64 may include an oxide layer such as a silicon oxide layer, which is formed by thermal oxidation, chemical oxidation process or deposition process of the protruding fin 36. The gate dielectric 68 may also include a high-k dielectric layer 66 formed above the IL 64. The high-k dielectric layer 66 includes a high-k dielectric material, for example, hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0, and sometimes up to 21.0 or higher. The high-k dielectric layer 66 covers the IL 64 and may be in contact with it. The high-k dielectric layer 66 is formed as a conformal layer and extends on the sidewalls of the protruding fin 36 and the top surface and sidewalls of the gate spacer 46. According to some embodiments of the present disclosure, high-k dielectric layer 66 is formed using ALD, CVD, PECVD, molecular beam deposition (MBD), or the like.

[0034] Further references Fig. 9B , a gate electrode 70 is formed on the gate dielectric 68. The gate electrode 70 may include a plurality of metal-containing layers 74 (which may be formed as a conformal layer), and a fill metal region 76 (filling the remainder of the trench not filled by the plurality of metal-containing layers 74). The metal-containing layer 74 may include a barrier layer, a work function layer over the barrier layer, and one or more metal capping layers over the work function layer. In some embodiments, an optional capping layer (not shown) is formed over the gate stack 72, the gate spacer 46, and the first ILD 60. The capping layer may be formed of a suitable material such as silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, or the like, or a combination thereof.

[0035] Fig.10 8 shows the formation of a first self-aligned contact dielectric (SACD) 80 according to some embodiments. The first SACD 80 is formed over the gate stack 72 and the gate spacer 46, and portions of the first SACD 80 may be used as a hard mask. The SACD 80 allows the formation of a self-aligned contact 118A (see FIG. 1 ) within the first spacing region 81A. Fig. 20 ). For example, SACD 80 may then contact 118A (see Fig. 20 ) provides protection for the gate stack 72 and the gate spacers 46 during the etching of the opening 83A into the epitaxial region 54. Due to the presence of the first SACD 80, small process variations in the etching of the opening 83A are less likely to form an electrical short between the contact 118A and the gate stack 72. In this manner, the contact 118A is a "self-aligned" contact.

[0036] The formation of the first SACD 80 may include performing an etching process to form a groove in the gate stack 72, filling the groove with a dielectric material, and then performing a planarization process such as a CMP process or a mechanical grinding process to remove excess portions of the dielectric material. The gate spacer 46 may also be recessed in the etching process. In some embodiments, the first SACD 80 may have a top surface that is approximately flush with the top surface of the gate spacer 46, or the first SACD 80 may have a top surface that protrudes above the top surface of the gate spacer 46. The size and position of the portion of the first SACD 80 are self-aligned with the gate stack 72 and the gate spacer 46. The material of the first SACD 80 may be selected from, but not limited to, titanium nitride, hafnium oxide, zirconium nitride, aluminum oxide, aluminum oxynitride, silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, other nitrides, other oxides, other dielectric materials, etc., or combinations thereof. The first SACD 80 may be formed using a suitable deposition process, such as CVD, ALD, FCVD, PECVD, MOCVD, spin coating, or other deposition methods.

[0037] Fig.11 The formation of a second ILD 61 according to some embodiments is shown. The second ILD 61 is formed over the gate stack 72, the gate spacer 46, and the first ILD 60. The second ILD 61 may be formed over a cap layer (if present). The second ILD 61 may be formed of a dielectric material similar to the first ILD 60, a different dielectric material having a different composition, or a dielectric material formed using a different process. The second ILD 61 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method.

[0038] Figure 12-20 The contact 118 is shown according to some embodiments (see Fig. 20 Formation of contacts 118A-B). Figure 12-20 Shows Fig.11 Some details of these structures are not shown in Figure 12-20 For example, in Figure 12-20 , source / drain regions 54, source / drain silicide regions, semiconductor fins 36, STI regions 24, etc. are not shown. Fig. 9B or Fig.11 ) found some Figure 12-20 Details shown in .

[0039] Fig.12 Shown with Fig.11 The structure shown is similar to that shown, except that multiple gate stacks 72 are shown separated by regions of the first ILD 60 . Fig.12 The example structure shown includes gate stacks 72 with different pitches. For reference, the first pitch region 81B includes gate stacks 72 with relatively smaller pitches (an example smaller pitch P1 is shown), and the second pitch region 81B includes gate stacks 72 with relatively larger pitches (an example larger pitch P2 is shown). In some embodiments, the pitch of the gate stacks 72 (e.g., P1 or P2) can be about Peace In some embodiments, the ratio of P1:P2 can be between about 1:1 and about 1:100. In some cases, regions with smaller pitches (e.g., pitch P1) can allow for the formation of source / drain contacts in these regions (see Fig. 20 The contacts 118A in the region are more sensitive to process variations. Therefore, contacts with different pitches (e.g., different pitches P1 and P2) can be formed in regions to reduce the chance of defects in any one region. For example, self-aligned contacts (e.g., P1) can be formed in regions with smaller pitches (e.g., P1). Fig. 20 118A in the contact), and non-self-aligned contacts (e.g., Fig. 20 The process described herein allows contacts with different pitches to be formed in regions with a reduced chance of process defects and using a reduced number of process steps.

[0040] Fig.13 8. The formation of openings 83A and 83B through the first ILD 60 and the second ILD 61 is shown. The opening 83A is formed in the first spacing region 81A, and the opening 83B is formed in the second spacing region 81B. The formation of the openings 83A and 83B includes etching the first ILD 60 and the second ILD 61 to expose the underlying portion of the CESL 58, and then etching the exposed portion of the CESL 58 to expose the source / drain epitaxial regions 54 ( Figure 12-20 In some embodiments, a groove 85 may be formed in the first SACD 80 in the first spacing region 81A. The groove 85 may be formed so that the opening 83A is self-aligned to form the contact 118A (see FIG. Fig. 20 ). For example, the etching process used to form the self-aligned opening 83A may remove some of the upper portion of the first SACD 80, but may not completely etch through the first SACD 80 in the first spacing region 81A. As a result, a portion of the first SACD 80 remains above the gate stack 72 in the first spacing region 81A, thereby allowing the contact 118A to be a self-aligned contact. For example, the etching process may etch the first SACD 80 approximately to about . Within groove 85, the portion of first SACD 80 within first spacing region 81A may have a top surface closer to the substrate than the portion of first SACD 80 within second spacing region 81B. Due to the larger spacing (one or more) of second spacing region 81B, it may not be necessary to use groove 85 to form a self-aligned opening, and opening 83B may be formed to extend through the entire thickness of first SACD 80 into second spacing region 81B, rather than first etching a groove (e.g., similar to groove 85) in first SACD 80 and then forming opening 83B within the groove. In some embodiments, opening 83A may be wider than opening 83B to allow conductive layer 82 to more completely fill opening 83A (see Fig.13 In some embodiments, the opening 83A may have a width of about To date and the opening 83B may have a width of about To date The width between.

[0041] The recess 85, the opening 83A, and the opening 83B may be formed by using acceptable photolithography and etching techniques. For example, a photoresist structure or a hard mask may be formed and patterned over the second ILD 61, and the pattern is used to etch the first ILD 60, the second ILD 61, or the first SACD 80. In some embodiments, the recess 85 is etched in one etching process, and the opening 83A and / or the opening 83B are etched in one or more different processes. In other embodiments, the recess 85 and the opening 83A are etched in one etching process, and the opening 83B is etched in a different etching process. In some embodiments, the recess 85, the opening 83A, and the opening 83B are formed by one or more anisotropic dry etching processes. For example, the etching process may include a dry etching process using a process gas that selectively etches the ILDs 60 and 61 at a greater rate than the first SACD 80. In some embodiments, the process gas may include a gas or a mixture of gases, for example, C4F6, CF4, C5F, NF3, O2, N2, Ar, Cl, etc., or a combination thereof. In some embodiments, the process gas may be supplied to the process chamber at a total gas flow rate from about 50 sccm to about 2000 sccm. In some embodiments, the pressure of the etching chamber during the etching process is about 10 mTorr to about 200 mTorr.

[0042] Still refer to Fig.13, once the source / drain epitaxial regions 54 have been exposed through openings 83A and openings 83B, optional silicide contacts (not shown separately) may be formed on the epitaxial regions 54. The silicide contacts may include titanium, nickel, cobalt, or erbium to reduce the Schottky barrier height of the contacts. However, other metals, such as platinum, palladium, etc., may also be used. Silicidation may be performed by blanket deposition of an appropriate metal layer, followed by an annealing step that reacts the metal with the exposed silicon below. The unreacted metal is then removed, for example, by a selective etching process. The thickness of the silicide contacts may be between about 5 nm and about 50 nm.

[0043] Fig.14 The conductive layer 82 is shown formed in the openings 83A and 83B according to some embodiments. The conductive layer 82 is physically connected to the silicide contact (if present) or the epitaxial region 54. The conductive layer 82 is formed so that the conductive layer 82 extends over the first SACD 80 in the recess 85 of the first spacing region 81A and over the second ILD 61 in the second spacing region 81B. The amount of the conductive layer 82 is deposited so that the recess 85 is not completely filled with the material of the conductive layer 82. For example, the top surface of the conductive layer 82 in the recess 85 can be lower than the top surface of the second ILD 61 by a distance D1 of about Peace When openings 83A and 83B have been completely filled with conductive layer 82, but before recess 85 is completely filled with conductive layer 82, deposition of conductive layer 82 may be stopped. The depth of recess 85 and / or the larger width of opening 83A may allow both openings 83A and 83B to be filled before recess 85 is filled. In some embodiments, conductive layer 82 in first spacing region 81A may be deposited about 100 mm above substrate 20. Peace In some embodiments, the conductive layer 82 in the second spacing region 82A may be deposited about 100 mm above the substrate 20. Peace The height between them is greater than the height of the conductive layer 82 in the first spacing region 81A.

[0044] In some embodiments, the conductive layer 82 includes a barrier layer (not shown separately). The barrier layer helps to block the subsequently formed conductive layer 82 from diffusing into adjacent dielectric materials such as ILD 60 or 61. The barrier layer can be made of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, cobalt, cobalt oxide, cobalt nitride, nickel, nickel oxide, nickel nitride, silicon carbide, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, polymers (e.g., polyimide, polybenzoxazole (PBO), etc.), or combinations thereof. The barrier layer can be formed by CVD, PVD, PECVD, ALD, SOD, etc., or combinations thereof. In some embodiments, the barrier layer is omitted.

[0045] Conductive layer 82 includes a conductive material formed within openings 83A and 83B and over a barrier layer (if present). The conductive material may include a suitable conductive material, such as cobalt, W, Al, Cu, AlCu, W, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Ni, Ti, TiAlN, Ru, Mo, or WN, but any suitable material, such as aluminum, copper, alloys thereof, combinations thereof, etc., may be deposited using a deposition process such as sputtering, CVD, electroplating, chemical plating, etc.

[0046] Go to Fig.15 According to some embodiments, the conductive layer 82 is recessed. The conductive layer 82 may be recessed to a level below the top surface of the first SACD 80 in the first spacing region 81A, and may be recessed to a level below the top surface of the second ILD 61 in the second spacing region 81B. In some embodiments, the conductive layer 82 may be recessed by a distance D2 of about Peace In some embodiments, the conductive layer 82 in the first spacing region 81A may have a top surface closer to the substrate than the top surface of the conductive layer 82 in the second spacing region 81B. For example, the conductive layer 82 in the first spacing region 81A may have a top surface above the substrate 20 of about Peace and the conductive layer 82 in the second spacing region 81B may have a height of about Peace The height between the first SACD 80 and the second ILD 61 can be etched. However, any suitable distance can be used, and the conductive layer 82 can be recessed by different distances in different areas of the structure. The conductive layer 82 can be recessed using a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the conductive layer 82 can be recessed using one or more etchants that are selective to the material of the conductive layer 82 above the material of the first SACD 80 and / or the material of the second ILD 61.

[0047] In some cases, completely filling recess 85 with conductive layer 82 requires removing excess conductive layer 82 in a separate step (e.g., using a CMP process or other planarization process) prior to performing the recessing to achieve uniform recessing in both first spacing region 81A and second spacing region 81B. For example, if recess 85 is completely filled with conductive layer 82, the thickness of conductive layer 82 above opening 83A in first spacing region 81A may be significantly greater than the thickness of conductive layer 82 extending above opening 83B in second spacing region 81B. For example, if a CMP process is not performed first, such a difference in thickness of conductive layer 82 may result in an unacceptable difference in recessing between first spacing region 81A and second spacing region 81B. Figure 14-15 In the illustrated embodiment, because the groove 85 only partially fills the conductive layer 82 instead of completely filling the conductive layer 82, the recessing of the conductive layer 82 can be performed without first removing excess conductive layer 82 (for example, using a CMP process or other planarization process). By depositing the conductive layer 82 so that the recess 85 is not completely filled, the difference between the thickness of the conductive layer 82 above the opening 83A and the thickness of the conductive layer 82 above the opening 83B can be reduced, thereby allowing more uniform recessing in the first spacing region 81B and the second spacing region 81B without first performing a planarization process. In this way, by not first performing a planarization process, the number of process steps can be reduced. In addition, reducing the total number of planarization processes performed during the process can allow a greater height of the first SACD 80 to remain on each gate stack 72 in the FinFET device (see Fig.17 ).

[0048] Fig.16 The formation of a second self-aligned contact dielectric (SACD) 88 is shown in accordance with some embodiments. The second self-aligned contact dielectric 88 allows for the formation of a self-aligned contact 118 within the first spacing region 81A (see Fig. 20 For example, the second SACD 88 can protect the conductive layer 82 in the first spacing region 81A during subsequent processing to reduce the conductive material 116 at the contact 118A (see Fig. 20) and other conductive components to form an electrical short. A second SACD 88 is formed over the first SACD 80, the conductive layer 82, and the second ILD 61. For example, in the first spacing region 81A, the second SACD 88 is formed over the first SACD 80 and the conductive layer 82, and in the second spacing region 81B, the second SACD 88 is formed over the second ILD 61 and the conductive layer 82. In some embodiments, the second SACD 88 may fill the groove 85. For example, the top surface of the second SACD 88 in the first spacing region 81A may be higher than the top surface of the second ILD 61 in the second spacing region 81B above the substrate 20. The material of the second SACD 88 may be selected from, but not limited to, titanium nitride, hafnium oxide, zirconium nitride, aluminum oxide, aluminum oxynitride, silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, other nitrides, other oxides, other dielectric materials, etc., or combinations thereof. The second SACD 88 can be formed using a suitable deposition process, such as CVD, ALD, FCVD, PECVD, MOCVD, spin coating or other deposition methods. In some embodiments, the material of the second SACD 88 is different from the material of the first SACD 80, so that a subsequent etching process can be selective to the material of the second SACD 88 relative to the material of the first SACD 80.

[0049] Go to Fig.17 , a planarization process is performed on the second SACD 88 to planarize the first SACD 80, the second SACD 88, and the conductive layer 82. The planarization may include one or more etching processes or grinding processes, such as a CMP process. Due to the greater thickness of the conductive layer 82 in the second spacing region 81B (see Fig.16 ), so the second SACD 88 is removed from above the conductive layer 82 during the planarization process. Therefore, in the first pitch region 81A, the second SACD 88 remains above the conductive layer 82, and in the second pitch region 81B, the conductive layer 82 is free of the second SACD 88. After the planarization process, the exposed top surfaces of the first SACD 80, the second SACD 88, the conductive layer 82, and the first ILD 60 are level.

[0050] Since the groove 85 is not completely filled with the conductive layer 82 (see Fig.14 ), so less planarization process is performed before planarization of second SACD 88, and thus the height of first SACD 80 above gate stack 72 may be greater than if more planarization process is performed. In some embodiments, after performing the planarization process on second SACD 88, first SACD 80 has a height D3 above gate stack 72 that is approximately About In some embodiments, after planarization is performed on the second SACD 88, the top surface of the first SACD 80 is above the substrate 20 by a distance D4, which is about About In some embodiments, after performing the planarization process, the second SACD 88 has about Peace In some embodiments, after the planarization process is performed, the conductive layer 82 in the first spacing region 81A has a thickness of about Peace and the conductive layer 82 in the second spacing region 82A has a height of about Peace The height between.

[0051] In some cases, having a greater available thickness of the first SACD 80 above the gate stack 72 can increase process flexibility in forming FinFET devices. For example, due to the greater thickness of the first SACD 80, the margin for over-planarization or under-planarization may be greater, thereby increasing yield. In addition, the greater thickness of the first SACD 80 may allow planarization to be performed more thoroughly or more cleanly. In addition, the greater thickness of the first SACD 80 above the gate stack 72 can reduce the chance of short circuits (e.g., contact to gate shorts, gate to gate shorts, or contact to contact shorts), thereby increasing yield. By reducing the number of planarization processes performed, process costs can also be reduced.

[0052] Fig.18 1 and 2. The formation of an etch stop layer 102 and a hard mask 104 is shown in accordance with some embodiments. The etch stop layer 102 and the hard mask 104 are used to form and preserve the pattern of the source / drain contact openings 106 (see Fig.19 ). The etch stop layer 102 may be formed of oxide, nitride, carbide, oxycarbide, etc., or a combination thereof. The etch stop layer 102 may be formed by a suitable deposition process such as CVD, PVD, ALD, etc. The hard mask 104 may be formed of titanium nitride, boron nitride, oxide, nitride, etc., or a combination thereof. The hard mask 104 may be formed by a suitable deposition process such as CVD, PVD, ALD, spin coating, etc.

[0053] Go to Fig.19According to some embodiments, source / drain contact openings 106 are formed. The source / drain contact openings 106 are formed to expose the contact plugs 82 in the first spacing region 81A. The source / drain contact openings 106 may be formed using appropriate photolithography and etching processes. For example, the hard mask 104 may be patterned and then used as an etching mask to form the source / drain contact openings 106. The source / drain contact openings 106 may be formed using an appropriate etching process (e.g., a dry etching process). The etching process removes the second SACD 88 above the conductive layer 82 to expose the conductive layer 82 where the contact 118A will be formed (see Fig. 20 In some embodiments, the etching process is selective to the material of the second SACD 88 relative to the material of the first SACD 80 .

[0054] Go to Fig. 20 , according to some embodiments, contact 118A and contact 118B are formed. Contact 118A and contact 118B provide electrical connections to epitaxial region 54. Due to the presence of first SACD 80 and / or second SACD 88, contact 118A can be considered a "self-aligned" contact. Contact 118A can be formed by filling conductive material 116 into opening 106 and performing a planarization process (e.g., a CMP process or a grinding process) to remove excess portions of conductive material 116. The planarization process also exposes conductive layer 82 in second spacing region 81B, thereby forming contact 118B. After the planarization process, the exposed surfaces of conductive material 116, conductive layer 82, first SACD 80, and second SACD 88 can be level. As shown in FIG. Fig. 20 As shown, the contact 118A in the first spacing region 81A may include a conductive material 116 disposed above the conductive layer 82, and the contact 118B in the second spacing region 81B may not have the conductive material 116. According to some embodiments of the present disclosure, the conductive material 116 includes a diffusion barrier layer that may be formed of titanium nitride, tantalum nitride, titanium, or tantalum, and a filling material such as copper, tungsten, cobalt, ruthenium, etc. The conductive material 116 may be formed by a deposition process such as electrochemical plating, PVD, CVD, etc., or a combination thereof.

[0055] Embodiments of the present disclosure have some advantageous features. As the feature size in the integrated circuit decreases, the size of the source / drain contact plug and the gate contact plug also decreases. For example, due to the limitations of the topology and the lithography process, it is difficult to form a contact plug with a small size. In some cases, multiple self-aligned dielectrics are used to form self-aligned contacts in some areas with small features or spacing. Multiple planarization steps can be used during the formation of the self-aligned contact. The present disclosure describes a technique for forming a self-aligned contact of a FinFET device using fewer planarization steps, which allows a self-aligned dielectric material of a larger height to remain above the gate stack of the FinFET device. By reducing the number of planarization steps, the cost and time of processing FinFET devices can be reduced. In addition, the self-aligned dielectric material with a larger thickness above the gate stack allows more process variations without increasing the risk of process-related yield losses. The self-aligned dielectric material with a larger thickness can also increase yield by reducing the risk of forming an electrical short circuit during the process.

[0056] According to some embodiments of the present disclosure, a method includes: forming a semiconductor fin above a substrate; forming a first gate stack and a second gate stack above the semiconductor fin, the first gate stack and the second gate stack being surrounded by an interlayer dielectric (ILD); forming a first dielectric material on the first gate stack and the second gate stack, wherein a top surface of the first dielectric material is higher than a first height of the substrate; performing an etching process to form a first opening in the ILD adjacent to the first gate stack, and forming a second opening in the ILD adjacent to the second gate stack, wherein after the etching process, a top surface of the first dielectric material located on the first gate stack is higher than a second height of the substrate, the second height being less than the first height; forming a first conductive material in the first opening to form a first contact plug, and forming the first conductive material in the second opening to form a second contact plug; forming a second dielectric material above the first contact plug and above the second contact plug; and performing a planarization process on the second dielectric material, wherein after the planarization process, the first conductive material of the second contact plug is exposed, and the first conductive material of the first contact plug is covered by the second dielectric material. In an embodiment, forming the first conductive material in the first opening and the second opening includes: depositing the first conductive material over the first dielectric material on the first gate stack and over the first dielectric material on the second gate stack, wherein the top surface of the first conductive material located over the first dielectric material on the first gate stack is higher than a fifth height of the substrate, the fifth height being between the second height and the first height. In an embodiment, the method includes: recessing the first conductive material to expose the first dielectric material on the first gate stack and the first dielectric material on the second gate stack. In an embodiment, after performing a planarization process on the second dielectric material, the top surface of the first conductive material of the second contact plug is flush with the top surface of the second dielectric material covering the first contact plug. In an embodiment, the method includes: removing the second dielectric material to expose the first contact plug, and depositing the second conductive material on the exposed first contact plug. In an embodiment, the first gate stack is one of a plurality of first gate stacks having a first spacing, wherein the second gate stack is one of a plurality of second gate stacks having a second spacing, wherein the first spacing is less than the second spacing. In an embodiment, the first dielectric material is different from the second dielectric material. In an embodiment, the method includes: forming a first source / drain region in a semiconductor fin adjacent to the first gate stack, wherein the first contact plug is electrically connected to the first source / drain region. In an embodiment, after the etching process, a top surface of the first dielectric material located on the second gate stack is higher than a first height of the substrate.

[0057] According to some embodiments of the present disclosure, a method includes: forming a first gate stack over a first fin and forming a second gate stack over a second fin; depositing a first dielectric material over the first gate stack and over the second gate stack; forming a first opening in the first dielectric material adjacent to the first gate stack and forming a second opening in the first dielectric material adjacent to the second gate stack; etching the first dielectric material over the first gate stack, wherein the etching forms a groove having a first depth in the first dielectric material; and forming a first contact in the first opening and forming a second contact in the second opening, which includes: depositing a conductive material in the first opening and the second opening, wherein the conductive material has a first height over the first opening, the first height being less than the first depth; depositing a second dielectric material over the conductive material in the first opening and over the conductive material in the second opening; and removing the second dielectric material over the conductive material in the second opening using a planarization process. In an embodiment, the second dielectric material extends over the first gate stack and over the second gate stack, wherein a top surface of the second dielectric material over the first gate stack is lower than a top surface of the second dielectric material over the second gate stack. In an embodiment, after the planarization process is performed, the conductive material in the first opening remains covered by the second dielectric material. In an embodiment, after the planarization process is performed, the first dielectric material in the first opening has a and In an embodiment, the method includes: recessing the conductive material before depositing the second dielectric material. In an embodiment, after recessing the conductive material, the first dielectric material located above the second gate stack is thicker than the first dielectric material located above the first gate stack. In an embodiment, the method includes: forming a first epitaxial source / drain region in the first fin and forming a second epitaxial source / drain region in the second fin, wherein the first opening exposes the first epitaxial source / drain region and the second opening exposes the second epitaxial source / drain region.

[0058] According to some embodiments of the present disclosure, a device includes: a semiconductor fin protruding from a substrate; a first gate stack and a second gate stack, the first gate stack being located above the semiconductor fin, and the second gate stack being located above the semiconductor fin; a first source / drain region and a second source / drain region, the first source / drain region being located in the semiconductor fin adjacent to the first gate stack, and the second source / drain region being located in the semiconductor fin adjacent to the second gate stack; a first layer of a first dielectric material and a second layer of a first dielectric material, the first layer of the first dielectric material being located on the first gate stack, and the second layer of the first dielectric material being located on the second gate stack; a first source / drain contact being located on the first source / drain region and adjacent to the first gate stack; a first layer of a second dielectric material being located on a top surface of the first source / drain contact; and a second source / drain contact being located on the second source / drain region and adjacent to the second gate stack, wherein the top surface of the second source / drain contact does not contain the second dielectric material. In an embodiment, the second source / drain contact extends above the first source / drain contact. In an embodiment, the first dielectric material is different from the second dielectric material. In an embodiment, the first dielectric material has a and The height between.

[0059] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments or examples introduced herein and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0060] Example 1 is a method for forming a semiconductor device, comprising: forming a semiconductor fin above a substrate; forming a first gate stack and a second gate stack above the semiconductor fin, the first gate stack and the second gate stack being surrounded by an interlayer dielectric (ILD); forming a first dielectric material on the first gate stack and the second gate stack, wherein a top surface of the first dielectric material is higher than a first height of the substrate; performing an etching process to form a first opening in the ILD adjacent to the first gate stack, and forming a second opening in the ILD adjacent to the second gate stack, wherein, after the etching process, a top surface of the first dielectric material located on the first gate stack is higher than a second height of the substrate, the second height being less than the first height; forming a first conductive material in the first opening to form a first contact plug, and forming the first conductive material in the second opening to form a second contact plug; forming a second dielectric material above the first contact plug and above the second contact plug; and performing a planarization process on the second dielectric material, wherein, after the planarization process, the first conductive material of the second contact plug is exposed, and the first conductive material of the first contact plug is covered by the second dielectric material.

[0061] Example 2 is the method described in Example 1, wherein forming a first conductive material in the first opening and the second opening includes: depositing the first conductive material above the first dielectric material on the first gate stack and above the first dielectric material on the second gate stack, wherein a top surface of the first conductive material located above the first dielectric material on the first gate stack is higher than a fifth height of the substrate, and the fifth height is between the second height and the first height.

[0062] Example 3 is the method of Example 2, further comprising: recessing the first conductive material to expose the first dielectric material on the first gate stack and the first dielectric material on the second gate stack.

[0063] Example 4 is the method of Example 1, wherein after performing the planarization process on the second dielectric material, a top surface of the first conductive material of the second contact plug is flush with a top surface of the second dielectric material covering the first contact plug.

[0064] Example 5 is the method of Example 1, further comprising: removing the second dielectric material to expose the first contact plug, and depositing a second conductive material on the exposed first contact plug.

[0065] Example 6 is the method described in Example 1, wherein the first gate stack is a first gate stack among multiple first gate stacks having a first spacing, wherein the second gate stack is a second gate stack among multiple second gate stacks having a second spacing, and wherein the first spacing is smaller than the second spacing.

[0066] Example 7 is the method of Example 1, wherein the first dielectric material is different from the second dielectric material.

[0067] Example 8 is the method of Example 1, further comprising: forming a first source / drain region in the semiconductor fin adjacent to the first gate stack, wherein the first contact plug is electrically connected to the first source / drain region.

[0068] Example 9 is the method described in Example 1, wherein, after the etching process, a top surface of the first dielectric material located on the second gate stack is higher than the first height of the substrate.

[0069] Example 10 is a method for forming a semiconductor device, comprising: forming a first gate stack above a first fin and forming a second gate stack above a second fin; depositing a first dielectric material above the first gate stack and above the second gate stack; forming a first opening in the first dielectric material adjacent to the first gate stack and forming a second opening in the first dielectric material adjacent to the second gate stack; etching the first dielectric material above the first gate stack, wherein the etching forms a groove having a first depth in the first dielectric material; and forming a first contact in the first opening and a second contact in the second opening, comprising: depositing a conductive material in the first opening and the second opening, wherein the conductive material has a first height above the first opening, the first height being less than the first depth; depositing a second dielectric material above the conductive material in the first opening and above the conductive material in the second opening; and removing the second dielectric material above the conductive material in the second opening using a planarization process.

[0070] Example 11 is the method described in Example 10, wherein the second dielectric material extends above the first gate stack and above the second gate stack, wherein a top surface of the second dielectric material above the first gate stack is lower than a top surface of the second dielectric material above the second gate stack.

[0071] Example 12 is the method of Example 10, wherein after performing the planarization process, the conductive material in the first opening remains covered by the second dielectric material.

[0072] Example 13 is the method of Example 12, wherein after performing the planarization process, the first dielectric material within the first opening has a and The thickness between.

[0073] Example 14 is the method of Example 10, further comprising recessing the conductive material before depositing the second dielectric material.

[0074] Example 15 is the method of Example 10, further comprising: after recessing the conductive material, the first dielectric material located above the second gate stack is thicker than the first dielectric material located above the first gate stack.

[0075] Example 16 is the method described in Example 10, further including: forming a first epitaxial source / drain region in the first fin and forming a second epitaxial source / drain region in the second fin, wherein the first opening exposes the first epitaxial source / drain region and the second opening exposes the second epitaxial source / drain region.

[0076] Example 17 is a semiconductor device comprising: a semiconductor fin protruding from a substrate; a first gate stack and a second gate stack, the first gate stack being located above the semiconductor fin and the second gate stack being located above the semiconductor fin; a first source / drain region and a second source / drain region, the first source / drain region being located in the semiconductor fin adjacent to the first gate stack and the second source / drain region being located in the semiconductor fin adjacent to the second gate stack; a first layer of a first dielectric material and a second layer of a first dielectric material, the first layer of the first dielectric material being located on the first gate stack and the second layer of the first dielectric material being located on the second gate stack; a first source / drain contact, the first source / drain contact being located on the first source / drain region and adjacent to the first gate stack; a first layer of a second dielectric material, the first layer of the second dielectric material being located on a top surface of the first source / drain contact; and a second source / drain contact, the second source / drain contact being located on the second source / drain region and adjacent to the second gate stack, wherein the top surface of the second source / drain contact does not contain the second dielectric material.

[0077] Example 18 is the device of Example 17, wherein the second source / drain contact extends higher than the first source / drain contact.

[0078] Example 19 is the device of Example 17, wherein the first dielectric material is different from the second dielectric material.

[0079] Example 20 is the device of Example 17, wherein the first dielectric material has a and The height between.

Claims

1. A method for forming a semiconductor device, comprising: forming a semiconductor fin over the substrate; forming a first gate stack and a second gate stack over the semiconductor fin, wherein the first gate stack and the second gate stack are surrounded by an interlayer dielectric ILD; forming a first dielectric material on the first gate stack and the second gate stack, wherein a top surface of the first dielectric material is higher than a first height of the substrate; performing an etching process to form a first opening in the ILD adjacent to the first gate stack, and forming a second opening in the ILD adjacent to the second gate stack, wherein after the etching process, a top surface of the first dielectric material located on the first gate stack is higher than a second height of the substrate, the second height being less than the first height; forming a first conductive material in the first opening to form a first contact plug, and forming the first conductive material in the second opening to form a second contact plug; forming a second dielectric material over the first contact plug and over the second contact plug; and A planarization process is performed on the second dielectric material, wherein after the planarization process, the first conductive material of the second contact plug is exposed and the first conductive material of the first contact plug is covered by the second dielectric material.

2. The method according to claim 1, wherein: Forming a first conductive material in the first opening and the second opening includes: depositing the first conductive material above the first dielectric material on the first gate stack and above the first dielectric material on the second gate stack, wherein a top surface of the first conductive material above the first dielectric material on the first gate stack is higher than a fifth height of the substrate, and the fifth height is between the second height and the first height.

3. The method according to claim 2, further comprising: The first conductive material is recessed to expose the first dielectric material on the first gate stack and the first dielectric material on the second gate stack.

4. The method according to claim 1, wherein: After the planarization process is performed on the second dielectric material, a top surface of the first conductive material of the second contact plug is flush with a top surface of the second dielectric material covering the first contact plug.

5. The method according to claim 1, further comprising: The second dielectric material is removed to expose the first contact plug, and a second conductive material is deposited on the exposed first contact plug.

6. The method according to claim 1, wherein: The first gate stack is a first gate stack among a plurality of first gate stacks having a first pitch, wherein the second gate stack is a second gate stack among a plurality of second gate stacks having a second pitch, wherein the first pitch is smaller than the second pitch.

7. The method according to claim 1, wherein: The first dielectric material is different from the second dielectric material.

8. The method according to claim 1, further comprising: A first source / drain region is formed in the semiconductor fin adjacent to the first gate stack, wherein the first contact plug is electrically connected to the first source / drain region.

9. The method according to claim 1, wherein: After the etching process, a top surface of the first dielectric material located on the second gate stack is higher than the substrate by the first height.

10. A method of forming a semiconductor device, comprising: forming a first gate stack over the first fin and forming a second gate stack over the second fin; depositing a first dielectric material over the first gate stack and over the second gate stack; forming a first opening in the first dielectric material adjacent to the first gate stack and forming a second opening in the first dielectric material adjacent to the second gate stack; etching the first dielectric material over the first gate stack, wherein the etching forms a recess having a first depth in the first dielectric material; and Forming a first contact in the first opening and forming a second contact in the second opening, comprising: Depositing a conductive material in the first opening and the second opening, wherein the conductive material has a first height above the first opening, and the first height is less than the first depth; depositing a second dielectric material over the conductive material in the first opening and over the conductive material in the second opening; and The second dielectric material overlying the conductive material in the second opening is removed using a planarization process.

11. The method according to claim 10, wherein: The second dielectric material extends over the first gate stack and over the second gate stack, wherein a top surface of the second dielectric material over the first gate stack is lower than a top surface of the second dielectric material over the second gate stack.

12. The method according to claim 10, wherein: After performing the planarization process, the conductive material in the first opening remains covered by the second dielectric material.

13. The method according to claim 12, wherein: After performing the planarization process, the first dielectric material in the first opening has a and The thickness between.

14. The method according to claim 10, further comprising: The conductive material is recessed prior to depositing the second dielectric material.

15. The method according to claim 10, further comprising: After recessing the conductive material, the first dielectric material over the second gate stack is thicker than the first dielectric material over the first gate stack.

16. The method according to claim 10, further comprising: A first epitaxial source / drain region is formed in the first fin, and a second epitaxial source / drain region is formed in the second fin, wherein the first opening exposes the first epitaxial source / drain region and the second opening exposes the second epitaxial source / drain region.

17. A semiconductor device comprising: a semiconductor fin protruding from the substrate; a first gate stack and a second gate stack, the first gate stack being located above the semiconductor fin and the second gate stack being located above the semiconductor fin; a first source / drain region and a second source / drain region, the first source / drain region being located in the semiconductor fin adjacent to the first gate stack, and the second source / drain region being located in the semiconductor fin adjacent to the second gate stack; a first layer of a first dielectric material and a second layer of a first dielectric material, the first layer of the first dielectric material being located on the first gate stack and the second layer of the first dielectric material being located on the second gate stack; a first source / drain contact located on the first source / drain region and adjacent to the first gate stack; a first layer of a second dielectric material, the first layer of the second dielectric material being located on a top surface of the first source / drain contact; as well as A second source / drain contact is located on the second source / drain region and adjacent to the second gate stack, wherein a top surface of the second source / drain contact does not contain the second dielectric material, and wherein the second source / drain contact extends higher than the first source / drain contact.

18. The device according to claim 17, wherein The first dielectric material is different from the second dielectric material.

19. The device according to claim 17, wherein: The first dielectric material has a and The height between.

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