A semiconductor device having a cavity at an interface between an encapsulant and a die pad or a lead

Abstract

Embodiments of the present disclosure relate to semiconductor devices having cavities at the interface between an encapsulant and a die pad or lead. In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, the device includes a die pad, a lead spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extend from the surface of at least one of the die pad or the lead to a depth into at least one of the die pad or the lead. The depth is in the range of 0.5 μm to 5 μm. The encapsulant extends into the plurality of cavities. Since the cavities increase the surface area in contact with the encapsulant, the cavities facilitate improved adhesion between the die pad or the lead and the encapsulant, and since the cavities can have a circular or hemispherical shape, further increasing the mechanical interlock with the encapsulant.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor devices, packages, and methods of forming an interface between an encapsulant and a die pad or lead. Background Art

[0002] Semiconductor packages typically include one or more semiconductor electronic components (e.g., semiconductor dies including one or more integrated circuits (ICs)), and a housing for protecting the semiconductor die and other internal electronic components. Semiconductor packages come in various forms, including ball grid array (BGA) packages, land grid array (LGA) packages, and quad flat no-lead ("QFN") packages.

[0003] A QFN package typically includes a lead frame, where the back side of the die pad of the lead frame is exposed on the back side of the package. The leads are also exposed on the back side of the package, spaced apart from and surrounding the die pad. Inside the package, the lead frame supports the die at a central location and typically includes wire bonding from the die to the leads. A molding compound or sealant is formed over the die, the wiring, and the lead frame to complete the package.

[0004] The molding compound typically contacts the inner surfaces of the die pad and the leads, and the molding compound should typically adhere to the inner surfaces of the die pad and the leads. Poor adhesion between the molding compound and the die pad and the leads can cause delamination of the molding compound, which may lead to device failure due to the entry of liquids, moisture, or other contaminants. Summary of the Invention

[0005] In various embodiments, the present disclosure provides semiconductor packages, devices, and methods. In the method, one or more surfaces of a die pad or a lead frame include a plurality of cavities that improve the adhesion between the die pad or the lead and an encapsulating material (e.g., a molding compound or an epoxy molding compound). The cavities can be formed by an immersion porous copper adhesion promoter (IPC-AP) process, where microstructures are embedded in a deposited copper layer by an electroless copper process. The microstructures can be removed by, for example, a solvent, and cavities are formed due to the removal of the microstructures. The cavities provide a rough surface for better adhesion and mechanical interlocking with the molding compound, thereby reducing or preventing delamination between the molding compound and the die pad or the leads.

[0006] In one embodiment, the present disclosure provides a device that includes a die pad, leads spaced apart from the die pad, and an encapsulant on the die pad and the leads. A plurality of cavities extend from a surface of at least one of the die pad or the leads to a depth into at least one of the die pad or the leads. The depth ranges from 0.5 μm to 5 μm, including the end values. The encapsulant extends into the plurality of cavities.

[0007] In another embodiment, the present disclosure provides a method of forming a semiconductor device, the method comprising: forming a conductive layer on a conductive substrate, the conductive layer including a plurality of microstructures at least partially embedded in the conductive layer; forming a plurality of cavities in the conductive layer by removing the plurality of microstructures; and at least partially filling the plurality of cavities with an encapsulating material.

[0008] In yet another embodiment, the present disclosure provides an electronic device including a microprocessor and a semiconductor package electrically coupled to the microprocessor. The semiconductor package includes die pads, leads spaced apart from the die pads, and an encapsulant on the die pads and the leads. A plurality of cavities extend from a surface of at least one of the die pads or the leads into at least one of the die pads or the leads to a depth. The depth is in the range of 0.5 μm to 5 μm, including the end values. The encapsulant extends into the plurality of cavities. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view of a semiconductor package in accordance with one or more embodiments of the present disclosure.

[0010] Figures 2A to 2C is a cross-sectional view showing stages of a method of forming cavities in a substrate in accordance with one or more embodiments of the present disclosure.

[0011] Figures 3A to 3E is a cross-sectional view showing stages of a method of manufacturing a semiconductor package (such as Figure 1 the semiconductor package) in accordance with one or more embodiments of the present disclosure.

[0012] Figure 4 is a block diagram of an electronic device including a semiconductor package in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] In the following description, certain specific details are set forth in order to provide a more thorough understanding of the various disclosed embodiments. However, those of ordinary skill in the relevant art will understand that the embodiments may be practiced without one or more of the specific details, or with the use of other methods, components, materials, etc. In other instances, well-known structures associated with semiconductor dies, lead frames, and semiconductor packages have not been shown or described in detail to avoid unnecessarily obscuring the description of the various embodiments provided herein.

[0014] Unless the context otherwise requires, throughout the specification and the appended claims, the word "comprise" and variations thereof (such as "comprises" and "comprising") shall be interpreted in an open, inclusive sense, i.e., "including but not limited to". Additionally, unless the context clearly indicates otherwise, the terms "first", "second" and their similar ordinal indicators shall be interpreted as interchangeable.

[0015] References to "an embodiment" or "embodiments" in the specification throughout refer to a particular feature, structure, or characteristic described in connection with that embodiment being included in at least one embodiment. Thus, the phrases "in an embodiment" or "in embodiments" that appear in various places throughout the specification are not necessarily all referring to the same embodiment. Additionally, the particular feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments of the present disclosure.

[0016] Unless the context clearly indicates otherwise, as used in the specification and the appended claims, the singular forms "a", "an" and "the" include plural referents. It should also be noted that unless the context clearly indicates otherwise, the term "or" generally takes its broadest meaning, i.e., meaning "and / or".

[0017] The present disclosure generally relates to semiconductor devices, packages, and methods of forming semiconductor devices and packages. In the method, the surface of one or more substrates is processed to improve the adhesion between the substrate and an encapsulant material (such as molding compound or epoxy molding compound). An immersion porous copper adhesion promoter (IPC-AP) process is performed on the substrate, which may be a copper substrate or a lead frame, and the process utilizes microbeads in an electroless copper process. The microbeads are embedded during the process of depositing a copper layer on the copper substrate. The microbeads may be soluble and can be removed by any solvent, leaving a rough surface in the copper layer. The rough surface promotes better adhesion to the molding compound, thereby reducing or preventing delamination between the molding compound and the substrate.

[0018] Figure 1 is a cross-sectional view showing a semiconductor package 10 according to one or more embodiments of the present disclosure. In some embodiments, the package 10 may be a QFN semiconductor package as shown. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the package 10 may be a QFN multi-row (QFN-mr) package having multiple rows of exposed leads or lead pads.

[0019] The package 10 includes a die pad 12 and a plurality of leads 14 spaced apart from the die pad 12 in a lateral direction (such as Figure 1 the horizontal direction shown). The package 10 may include an array of leads 14 surrounding the die pad 12.

[0020] The semiconductor die 16 is located on the die pad 12. The semiconductor die 16 can be any semiconductor die including one or more electronic components (such as an integrated circuit). The semiconductor die 16 is made of a semiconductor material (such as silicon) and includes an active surface 17 on which an integrated circuit is formed. The integrated circuit can be an analog or digital circuit implemented as active devices, passive devices, conductive layers, and dielectric layers, and the active devices, passive devices, conductive layers, and dielectric layers are formed within the semiconductor die 16 and electrically interconnected according to the electrical design and function of the semiconductor die 16.

[0021] In some embodiments, the semiconductor die 16 is fixed to the inner surface of the die pad 12 by an adhesion material 18. The adhesion material 18 can be any material suitable for mechanically coupling and / or electrically coupling the semiconductor die 16 to the die pad 12 (such as a conductive adhesive, paste, tape, or similar material). In one or more embodiments, the adhesion material 18 can be a pad attachment film suitable for attaching the semiconductor die 16 to the die pad 12.

[0022] The semiconductor die 16 is fixed to the die pad 12, and the active surface 17 of the semiconductor die 16 faces away from the inner surface of the die pad 12, as Figure 1 shown.

[0023] The wire 20 electrically couples the semiconductor die 16 to the lead 14. For example, the wire 20 can electrically couple the corresponding bond pads on the active surface 17 of the semiconductor die 16 to the corresponding leads 14, and the wire 20 can extend between the active surface 17 of the semiconductor die 16 and the inner surface of the lead 14.

[0024] A layer of encapsulation material 22 is formed over the semiconductor die 16 and covers the semiconductor die 16 and the wire 20. The encapsulation material 22 has a first surface 23 (such as Figure 1 the upper surface shown) and a second surface 25 opposite to the first surface 23 (such as Figure 1 the lower surface shown). The second surface 25 extends between the die pad 12 and the lead 14. The first surface 23 and the second surface 25 can be exposed surfaces that form part of the exterior of the semiconductor package 10.

[0025] The die pad 12 and the lead 14 can be formed of the same material. For example, the die pad 12 and the lead 14 can be part of the same lead frame, and in some embodiments, can be a QFN lead frame. In some embodiments, the die pad 12 and the lead 14 can be formed of copper (such as a copper lead frame).

[0026] The die pad 12 and the lead 14 have multiple surfaces, and a plurality of cavities 32 may extend from at least one of the multiple surfaces into the die pad 12 or the lead 14. For example, as shown in the enlarged view of region A, the lead 14 may include a plurality of cavities 32 that extend from the side surface 31 into the lead 14. The inner surface of the cavity 32 may be circular, as shown, which can increase the surface area of the cavity 32, thereby promoting increased contact and adhesion with the encapsulating material 22. In some embodiments, the cavity 32 may be a hemispherical cavity. However, the embodiments of the present disclosure are not limited thereto, and in various embodiments, the cavity 32 may have various other shapes. Figure 1 As shown in the enlarged view of region A, the lead 14 may include a plurality of cavities 32 that extend from the side surface 31 into the lead 14. The inner surface of the cavity 32 may be circular, as shown, which can increase the surface area of the cavity 32, thereby promoting increased contact and adhesion with the encapsulating material 22. In some embodiments, the cavity 32 may be a hemispherical cavity. However, the embodiments of the present disclosure are not limited thereto, and in various embodiments, the cavity 32 may have various other shapes.

[0027] The lead frame that may include both the die pad 12 and the lead 14 may have a multi-layer structure. For example, as shown in region A, the lead 14 may include a first layer 14a and a second layer 14b disposed on the first layer 14a. The first layer 14a and the second layer 14b may be formed of the same material (e.g., copper). For example, the second layer 14b may be a copper layer deposited on the first layer 14a, which may itself also be copper.

[0028] As will be discussed in more detail herein Figures 2A to 2C with respect to, the cavity 32 may be formed during the deposition of the second layer 14b by the introduction of microstructures (e.g., microbeads or similar microstructures). The microstructures may then be removed (e.g., by dissolution), leaving the cavity 32 in the second layer 14b. Depending on the size and shape of the microstructures, the cavity 32 may thus have various different sizes and shapes.

[0029] In some embodiments, the thickness of the second layer 14b may be in the range of 0.5 μm to 10 μm, including the end values. In some embodiments, the thickness of the second layer 14b may be in the range of 1 μm to 5 μm, including the end values, and in some embodiments, the thickness of the second layer 14b may be in the range of 1 μm to 2 μm, including the end values. The cavity 32 may have a width less than the thickness of the second layer 14b (e.g., extending into the second layer 14b), such that the cavity 32 does not extend into the first layer 14a. In some embodiments, the width of the cavity 32 may be in the range of 0.5 μm to 5 μm, including the end values, and in some embodiments, the width of the cavity 32 may be in the range of 0.5 μm to 2 μm, including the end values. That is, in some embodiments, the cavity 32 may extend into the second layer 14b to a depth in the range of 0.5 μm to 5 μm, and in some embodiments may extend into it to a depth in the range of 0.5 μm to 2 μm. In embodiments where the cavity 32 is spherical or hemispherical, the radius of the cavity 32 may be in the range of 0.25 μm to 1 μm, including the end values.

[0030] Although the enlarged region A is shown as being an area of the side surface of the lead 14, it will be readily understood that the same structure can be provided on any surface of the die pad 12 or the lead 14. For example, one or more surfaces of the die pad 12 may include a first layer and a second layer (e.g., a copper layer) of lead frame material, and due to the introduction of microstructures during the formation of the second layer, the cavity 32 may extend into the second layer of the material, and subsequently the microstructures are removed to leave the cavity. In various embodiments, some or all surfaces of the die pad 12 and the leads 14 may be exposed during the formation of the cavity 32 and may include the cavity 32.

[0031] As Figure 1 shown by the enlarged region A of Figure 1 , the encapsulant material 22 substantially fills the cavity 32. For example, the encapsulant material 22 may contact the lead 14 (e.g., the second layer 14b) within the cavity 32. Additionally, the encapsulant material 22 may contact the surface 31 of the lead 14. By filling the cavity 32 and contacting the lead 14 at the surface 31, the adhesion between the encapsulant material 22 and the lead 14 is improved. More particularly, a mechanical interlock is provided at the interface between the lead 14 (or die pad 12) and the encapsulant material 22, and the surface area is increased to increase the interfacial interaction between the lead 14 or die pad 12 and the encapsulant material 22.

[0032] In some embodiments, the upper surface 11 of the die pad 12 (e.g., the surface of the die pad 12 facing the semiconductor die 16), the lower surface 13 of the die pad 12 (e.g., the exposed surface of the die pad 12), and one or more of the side surfaces 15 of the chip pad 12 may include a plurality of cavities 32.

[0033] In some embodiments, the die pad 12 may include a recessed portion 19, and the recessed portion 19 may include a cavity 32 at its surface. For example, the recessed portion 19 may be formed as a recess that extends from the lower surface 13 of the die pad 12 into the die pad 12 at the side edge of the die pad 12. The recessed portion 19 also increases the contact surface area between the die pad 12 and the encapsulant material 22, thereby increasing the adhesion of the encapsulant material 22 to the die pad 12.

[0034] As Figure 1 shown, the lead 14 may similarly include a recessed portion that is substantially similar to the recessed portion 19 of the die pad 12 and increases the adhesion between the encapsulant material 22 and the lead 14.

[0035] In some embodiments, the second surface 25 of the encapsulation material 22 is the exposed surface, which together with the outer surface of the die pad 12 (e.g., the lower surface 13 of the die pad 12) and the outer surfaces of the leads 14 (e.g., the lower surface and outer side surfaces of the leads 14) forms a part of the exterior of the package 10 (e.g., a part of the bottom surface). The encapsulation material 22 can substantially fill any space or gap between the various components in the package 10. As Figure 1 shown, in some embodiments, the encapsulation material 22 is formed on the inner surfaces of the die pad 12 and the leads 14. The encapsulation material 22 can thus fill or substantially fill the cavities 32 formed in any of the multiple surfaces of the die pad 12 and the leads 14.

[0036] The encapsulation material 22 is an electrically insulating material that protects the semiconductor die 16, the wires 20, and any other electronic components or wirings from damage (e.g., corrosion, physical damage, moisture damage, or other causes of damage to electrical devices and materials). Additionally, the encapsulation material 22 provides structural support for the die pad 12 and the leads 14. In one or more embodiments, the encapsulation material 22 is a molding compound or an epoxy molding compound, which can include, for example, a polymeric resin.

[0037] The exposed bottom surface or outer surface of the lead 14 (which can be referred to as the plane of the package 10) and the exposed lower surface 13 of the die pad 12 are configured to electrically couple or mechanically couple the package 10 to an external circuit device, other device, or board (e.g., an external printed circuit board).

[0038] In some embodiments, a plated conductive layer 30 can be formed on one or more surfaces of the lead 14. For example, a plated conductive layer 30 can be formed at the junction of the upper surface of the lead 14 and the wire 20. The plated conductive layer 30 can resist the formation of copper (e.g., when forming a second layer of material that includes a microstructure that creates the cavity 32), and thus, the plated conductive layer 30 can remain substantially smooth and cavity - free, providing a suitable conductive surface for bonding with the wire 20.

[0039] The plated conductive layer 30 can include any conductive material. In some embodiments, the plated conductive layer 30 includes multiple metal layers. In some embodiments, the plated conductive layer 30 is a multi - layer structure that includes a first layer of nickel (Ni), a second layer of palladium (Pd), and a third layer of gold (Au).

[0040] The plated conductive layer 30 can be substantially thinner than the lead 14. In some embodiments, the plated conductive layer 30 can have a thickness of less than about 50 μm.

[0041] Figures 2A to 2CFIG. 0 is a cross-sectional view showing various stages of a method of forming a cavity in a substrate (e.g., a copper lead frame or a copper substrate) in accordance with one or more embodiments of the present disclosure. The cavity forming method may be referred to herein as an Immersion Porous Copper Adhesion Promoter (IPC-AP) process.

[0042] As Figure 2A shown, a substrate 112 is provided. The substrate 112 may be, for example, a copper lead frame forming die pads 12 and leads 14 of the semiconductor package 10 as Figure 1 shown. The substrate 112 may have a substantially flat surface 111, such as Figure 2A the upper surface shown. In some embodiments, the method includes pre-treating the substrate 112 to provide a clean, substantially flat surface 111. The pre-treatment may include, for example, degreasing the substrate 112 to remove organic surface contaminants or similar steps. The pre-treatment may also include removing oxides at the surface 111, such as by micro-etching or similar methods.

[0043] As Figure 2B shown, a conductive layer 112b is formed on the substrate 112. The conductive layer 112b may be formed of the same material as the substrate 112. For example, the conductive layer 112b may be a copper layer formed on a copper substrate 112. In some embodiments, the conductive layer 112b may be formed by electroless copper deposition or autocatalytic copper deposition or plating process, wherein the copper substrate 112 is immersed in a copper bath, which forms a plating or thin layer of the conductive layer 112b on the substrate 112. In various embodiments, the conductive layer 112b may have a thickness in the range of 0.5 μm to 10 μm, including the end values, in the range of 1 μm to 5 μm, including the end values, or in the range of 1 μm to 2 μm, including the end values.

[0044] As Figure 2B shown, a plurality of microstructures 142 are formed while forming the conductive layer 112b such that the microstructures 142 are at least partially embedded in the conductive layer 112b. The microstructures 142 may be any soluble microstructures that can be removed by exposure to a suitable solvent. In some embodiments, the microstructures 142 may be polymeric beads. In some embodiments, the microstructures 142 may be beads formed of or including at least one of polystyrene or polydimethylsiloxane.

[0045] The microstructures 142 may have any shape. In some embodiments, the microstructures 142 may have an outer portion that is at least partially circular such that the cavity is formed to have an at least partially circular shape. In some embodiments, the microstructures 142 may be hemispherical microstructures.

[0046] The microstructure 142 may have a width W that is less than the thickness of the conductive layer 112b, and the microstructure 142 may be spaced apart from the substrate 112 (e.g., the microstructure 142 does not extend into the substrate 112). In some embodiments, the width W of the microstructure 142 may range from 0.5 μm to 2 μm, including the end values. In embodiments where the microstructure 142 is spherical or hemispherical, the radius of the microstructure 142 may range from 0.25 μm to 1 μm, including the end values.

[0047] In various embodiments, the size and shape of the microstructure 142 may vary from each other, depending on, for example, the size and shape of the cavity desired to be formed in the lead frame (e.g., the die pad 12 or the lead 14).

[0048] As previously described, the conductive layer 112b and the microstructure 142 may be formed or plated on the substrate 112 simultaneously by electroless copper deposition or plating processes. In some embodiments, the electroless copper deposition or plating process includes immersing the substrate 112 (e.g., a copper substrate) into a plating bath that includes copper ions (e.g., Cu 2+ ) and the microstructure 142. The microstructure 142 may be a chemically active component in the plating bath, for example, by forming bonds between the microstructure 142 and one or more components of the plating bath. In some embodiments, the plating bath may include copper ions (e.g., Cu 2+ ), the microstructure 142, and one or more of a reducing agent, an additive, and a complexing agent. In such embodiments, the microstructure 142 may be selected to combine with the reducing agent, the additive, or the complexing agent. Accordingly, the microstructure 142 may become an active component of the plating bath and may be included as part of the growth or deposition of the conductive layer 112b.

[0049] The electroless copper deposition or plating process may enable or facilitate the autocatalytic reaction of the Cu 2+ ions in the plating bath with the exposed copper surface of the substrate 112, and thus only affects the exposed copper surface. Accordingly, in various embodiments, the entire lead frame (e.g., including Figure 1 the shown die pad 12 and the lead 14) may be immersed in the plating bath, and only the exposed copper portions of the lead frame may react with the plating bath to grow or deposit on the conductive layer 112b, while the unexposed surfaces (e.g., the surface of the lead 14 covered by the plated conductive layer 30) may be protected from the reaction and thus cavities may not be formed on the unexposed surfaces. Thereby, the bonding surface (e.g., the plated conductive layer 30 on the lead 14) may be unaffected by the IPC-AP process, thus maintaining a substantially smooth surface suitable for wire bonding.

[0050] As Figure 2BAs shown, portions of microstructure 142 may extend outwardly beyond the upper surface of conductive layer 112b. This facilitates exposing microstructure 142 using a solvent to remove microstructure 142 and form a cavity, such as in Figure 2C A more detailed discussion will be given.

[0051] like Figure 2C As shown, cavity 132 will be formed in conductive layer 112b by removing microstructure 142.

[0052] In some embodiments, microstructure 142 can be removed by exposure to a suitable solvent. The solvent can be any solvent capable of dissolving microstructure 142, which can be formed of any soluble material. In some embodiments, the solvent includes one or more of acetone, diethyl ether, or dioxane.

[0053] The solvent may be applied to the microstructures 142 by any suitable technique, including, for example, immersing the conductive layer 112b and the microstructures 142 in a solvent bath, spraying or otherwise introducing the solvent into the microstructures 142. Figure 2B The upper surface of the structure shown (e.g., the exposed portion of microstructure 142 and the upper surface of conductive layer 112b), or any other suitable technique. In some embodiments, Figure 2B The entire structure shown (eg, including substrate 112 , conductive layer 112 b , and microstructure 142 ) may be immersed in a solvent bath to remove microstructure 142 .

[0054] After removing microstructure 142, cavity 132 is formed and extends from surface 131 of substrate into the substrate (e.g., into conductive layer 112b of substrate 112). Cavity 132 provides increased surface area for bonding with encapsulation material 22, and the rounded or hemispherical shape of cavity 132 provides better mechanical interlocking with encapsulation material 22.

[0055] Figures 3A - 3E According to one or more embodiments of the present disclosure, a method for manufacturing a semiconductor package (eg Figure 1 Cross-sectional views of various stages of a method of semiconductor packaging).

[0056] like Figure 3A As shown, a substrate or lead frame including a die pad 12 and a plurality of leads 14 is provided. A plated conductive layer 30 may be formed on a surface (eg, an upper surface) of each lead 14. A plurality of cavities 32 (see Figure 1 ) is formed on the exposed surface of the die pad 12 or the lead 14. The cavity may be formed on any exposed surface of the die pad 12 or the lead 14 (e.g., any upper surface, lower surface, or side surface of the die pad 12 and any lower surface or side surface of the lead 14). The upper surface of the lead 14 can avoid the formation of a cavity due to the presence of the plated conductive layer 30.

[0057] The cavity can be the same as Figure 1 the cavity 32 described or Figure 2C substantially the same as the cavity 132 described.

[0058] The substrate (e.g., the substrate forming the die pad 12 and the lead 14) can be any suitable substrate in which a cavity is formed. In some embodiments, the substrate is a metal substrate (e.g., a lead frame). In some embodiments, the substrate is a copper substrate.

[0059] Multiple cavities can be formed by any suitable technique, including, for example, according to the cavity formation method described herein with respect to Figures 2A to 2C the cavity described. For example, the cavity can be formed by immersing the exposed surfaces of the die pad 12 and the lead 14 into an electroless copper deposition or plating bath including the microstructures 142. The microstructures 142 can thus be embedded in the conductive layer 112b, and subsequently the microstructures 142 are removed by a solvent leaving the cavity 132, e.g., as Figures 2A to 2C described.

[0060] In some embodiments, the die pad 12 or the lead 14 can include a recessed portion 19, which can be the exposed surface in which a cavity can be formed. For example, the recessed portion 19 can be formed as a recess extending from the upper surface of the die pad 12 or the lead 14 into the die pad 12 or the lead 14. The recessed portion 19 further increases the contact surface area between the die pad 12 or the lead 14 and the encapsulating material 22, thereby increasing the adhesion of the encapsulating material 22 to the die pad 12 or the lead 14.

[0061] The plated conductive layer 30 on the lead 14 can include any conductive material. In some embodiments, the plated conductive layer 30 is formed of a conductive material that is resistant to the chemicals in the electroless copper deposition or plating bath, such that no cavity is formed in the plated conductive layer 30.

[0062] In some embodiments, the plated conductive layer 30 is a multilayer structure that includes a first layer of nickel (Ni), a second layer of palladium (Pd), and a third layer of gold (Au). The plated conductive layer 30 can be formed by any suitable technique, including, for example, deposition, electroplating, or the like.

[0063] As Figure 3B shown, the semiconductor die 16 is attached to the die pad 12, and a wire bond or wire 20 is formed between the active surface 17 of the semiconductor die 16 and the plated conductive layer 30 on the lead 14.

[0064] The semiconductor die 16 can be attached to the surface 11 (e.g., the upper surface) of the die pad 12 by an adhesive material 18. The adhesive material 18 can be any material suitable for mechanically and / or electrically coupling the semiconductor die 16 to the die pad 12 (e.g., a conductive adhesive, paste, tape, or similar material). In one or more embodiments, the adhesive material 18 is a die attach film suitable for attaching the semiconductor die 16 to the die pad 12.

[0065] In some embodiments, the surface 11 of the die pad 12 includes cavities formed, e.g., by Figures 2A to 2C the method shown. That is, a plurality of cavities can extend from the surface 11 into the chip pad 12. In such embodiments, the adhesive material 18 can extend into the cavities in the surface 11 of the chip pad 12 and can substantially fill the cavities in the surface 11 of the chip pad 12, thereby facilitating improved adhesion between the die pad 12 and the adhesive material 18, which also improves the adhesion between the die pad 12 and the semiconductor die 16.

[0066] The wire 20 can be formed by, e.g., wire bonding, and the wire 20 electrically couples the bonding pads on the active surface 17 of the semiconductor die 16 to the leads 14.

[0067] As Figure 3C shown, a carrier tape 340 can be applied to Figure 3B the components (e.g., including the die pad 12, the leads 14, the semiconductor die 16, and the wire 20). More particularly, the carrier tape 340 can be applied to the lower surfaces of the die pad 12 and the leads 14. The carrier tape 340 facilitates the transportation of the components, e.g., for forming the cavity mold for the encapsulation 22. In some embodiments, the carrier tape 340 can be omitted.

[0068] As Figure 3D shown, an encapsulation material 22 is formed over the semiconductor die 16 and covers the semiconductor die 16 and the wire 20. The encapsulation material 22 further covers the plated conductive layer 30, a portion of the surface 11 of the die pad 12, and the exposed side surfaces of the die pad 12 and the leads 14. The encapsulation material 22 can further fill the recessed portions 19 of the die pad 12 and the leads 14. The encapsulation material 22 substantially fills a plurality of cavities formed in the surfaces of the die pad 12 and the leads 14, e.g., Figure 1 as shown in the enlarged region A. Accordingly, better adhesion and mechanical interlocking are provided at the surface of the die pad 12 or the leads 14 and the encapsulation material 22.

[0069] The encapsulation material 22 has a first surface 23 and a second surface 25 opposite the first surface 23. The second surface 25 extends between the die pad 12 and the leads 14. The first surface 23 and the second surface 25 can be exposed surfaces that form part of the exterior of the semiconductor package 10.

[0070] The encapsulation material 22 can be formed by any conventional technique, such as a molding process. For example, the molding process can include positioning the Figure 3C components shown (e.g., including the die pad 12, leads 14, semiconductor die 16, and conductive wires 20) into a mold and injecting a molding material, such as molding compound, epoxy molding compound, polymeric resin, or similar materials. The injected material then hardens, which may involve a curing step.

[0071] As Figure 3E shown, after the encapsulation 22 is formed, the carrier tape 340 is removed. The carrier tape 340 can be removed by any suitable technique, including mechanical separation, cutting, etching, or similar methods.

[0072] The encapsulation material 22 provides suitable structural support for the die pad 12 and the leads 14 such that after the carrier tape 340 is removed, the die pad 12 and the leads 14 can substantially maintain their shape and structure.

[0073] As Figure 3E shown, the complete semiconductor package 10 is formed after the carrier tape 340 is removed. By removing the carrier tape 340, the outer surfaces of the die pad 12 and the leads 14 are exposed, and the second surface 25 of the die pad 12 and the leads 14 and the encapsulation material 22 form the outer surface of the semiconductor package 10. The exposed outer surfaces of the leads 14 and the die pad 12 can be electrically coupled and / or mechanically coupled to another device or board, such as a printed circuit board.

[0074] Figure 4 An electronic device 400 is shown that includes a semiconductor package (e.g., semiconductor package 10) described herein. The semiconductor package 10 is electrically coupled to a microprocessor 402. The microprocessor 402 can be any circuit configured to receive electrical signals or transmit electrical signals to the semiconductor package 10. The electronic device 400 can also include a power source 404 configured to provide power to the device 400. The power source 404, which can be a battery, can be coupled to the microprocessor 402. The electronic device 400 can also include a memory 406 coupled to the microprocessor 402 or incorporated into the microprocessor 402.

[0075] In one or more embodiments, the electronic device 400 can be a mobile phone, smartphone, tablet, camera, and / or a wearable computing device that can be located in clothing, shoes, watches, glasses, or any other wearable structure. In some embodiments, the electronic device 400, or the semiconductor package 10 itself, can be located in a vehicle (e.g., a boat and a car), a robot, or any other movable structure or machine.

[0076] As described herein in various embodiments of semiconductor devices, packages, and methods, one or more surfaces of a substrate (such as a copper lead frame) are treated to improve the adhesion between the substrate and an encapsulant material (such as molding compound or epoxy molding compound). An electroless copper deposition or plating process is performed on the substrate, in which microstructures (such as microbeads) are embedded in a deposited or plated copper layer formed on the substrate surface. The microbeads can be dissolved and removed by any solvent, leaving a rough surface in the copper layer. The rough surface is a surface in which a plurality of cavities are formed and extend from its surface into the substrate. The rough surface (such as the plurality of cavities) promotes better adhesion to the molding compound, thereby reducing or preventing delamination between the molding compound and the substrate (such as die pads or leads).

[0077] The increased adhesion between the molding compound and the die pads or leads provided by various embodiments of the present disclosure is superior to other methods that may increase adhesion. For example, since functional groups in the molding compound may interact preferentially with oxides compared to unoxidized copper, an oxide layer can be introduced into the chip pads or leads to increase adhesion. However, copper oxide (such as Cu2O) can be a metastable oxide that has a tendency to further oxidize (such as to form CuO), which is a brittle and fragile material. This may lead to delamination between the molding compound and the die pads or leads. On the other hand, the solution provided by the present disclosure (such as forming cavities filled with encapsulant) avoids the formation of such oxides, thereby avoiding delamination.

[0078] In addition, the embodiments provided herein provide increased adhesion between the molding compound and the die pads and leads without mechanically roughening the surfaces of the die pads and leads. This mechanical roughening, for example, may disadvantageously result in roughening of the lead surfaces bonded by wire bonding. On the other hand, the embodiments of the present disclosure facilitate the formation of cavities through a chemical process, and the bonding surfaces of the leads (such as plated conductive layers) can resist the formation of cavities, thereby avoiding wire bonding problems. That is, a substantially smooth bonding surface of the lead can be retained after other surfaces of the die pad or lead are roughened (such as cavities are formed therein) to increase adhesion to the encapsulant material.

[0079] The various embodiments described above can be combined to produce other embodiments. These and other changes can be made to the embodiments in accordance with the above detailed description. Generally, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents of such claims. Accordingly, the claims are not limited by the present disclosure.

Claims

1. An electronic device, comprising: Die pad; A lead pad that is laterally spaced apart from the die pad, the lead pad having an exposed lower surface and a side surface facing the die pad; And An encapsulant on the die pad and the lead pad, Wherein, a first plurality of cavities extend from the side surface of the lead pad into the side surface of the lead pad to a depth within the range of 0.5 μm to 5 μm, including the end values, and the encapsulant extends into the first plurality of cavities.

2. The electronic device according to claim 1, wherein, The die pad and the lead pad are formed of copper.

3. The electronic device according to claim 1, wherein, A second plurality of cavities extend from the side surface of the die pad into the side surface of the die pad to a depth within the range of 0.5 μm to 5 μm, including the end values, and the encapsulant extends into the second plurality of cavities.

4. The electronic device according to claim 3, further comprising a plated conductive layer on the lead pad, the plated conductive layer having a smooth surface.

5. The electronic device according to claim 4, further comprising: A semiconductor die on the die pad, the semiconductor die having an active surface spaced apart from the die pad; And A wire electrically coupled between the active surface of the semiconductor die and a plated conductive layer on the lead pad.

6. The electronic device according to claim 1, wherein, The cavities are hemispherical cavities.

7. The electronic device according to claim 6, wherein, The cavities have a radius within the range of 0.25 μm to 1 μm, including the end values.

8. The electronic device according to claim 1, wherein, The lead pad includes a first copper layer and a second copper layer plated on the first copper layer, the second copper layer having a thickness within the range of 0.5 μm to 10 μm, including the end values, and The first plurality of cavities extend into the second copper layer.

9. The electronic device according to claim 1, wherein, Each of the first plurality of cavities has a circular shape, and the encapsulant fills each of the first plurality of cavities.

10. The electronic device according to claim 1, wherein, The encapsulant is an epoxy molding compound.

11. The electronic device according to claim 1, wherein, At least one of the die pad or the lead pad includes a recessed portion that extends inwardly from an exposed outer portion of at least one of the die pad or the lead pad, and the encapsulant extends into the recessed portion.

12. A method of forming a semiconductor device, comprising: Forming a conductive layer on a conductive substrate, the conductive layer including a plurality of microstructures at least partially embedded in the conductive layer; Forming a plurality of cavities in the conductive layer by removing the plurality of microstructures; And Using an encapsulating material to at least partially fill the plurality of cavities.

13. The method according to claim 12, wherein, The conductive substrate is a copper substrate, and forming the conductive layer includes forming a copper layer on the copper substrate by electroless deposition.

14. The method according to claim 12, wherein, Removing the plurality of microstructures includes dissolving the microstructures in a solvent.

15. The method according to claim 14, wherein, The microstructures include at least one of polystyrene or polydimethylsiloxane, and the solvent includes at least one of acetone, diethyl ether, or dioxane.

16. The method according to claim 12, wherein, Forming the conductive layer includes forming the conductive layer to have a thickness within the range of 0.5 μm to 10 μm, including the end values, and the cavities have a width less than the thickness of the conductive layer.

17. According to the method of claim 12, wherein, Each of the plurality of microstructures has a hemispherical shape.

18. The method of claim 12 further comprising: Attaching a semiconductor die to a die pad portion of the conductive substrate; Forming a wire bond between the active surface of the semiconductor die and a lead portion of the conductive substrate, the lead portion being laterally spaced apart from the die pad portion; And An encapsulant material is formed over the active surface of the semiconductor die, the wire bond, the die pad portion of the conductive substrate, and the lead portion of the conductive substrate.

19. An electronic device, comprising: A microprocessor; and A semiconductor package electrically coupled to the microprocessor, the semiconductor package comprising: A die pad; A lead pad laterally spaced from the die pad, the lead pad having an exposed lower surface and a side surface facing the die pad; and An encapsulant on the die pad and the lead pad, wherein a plurality of cavities extend from the side surface of the lead pad to the side surface of the lead pad at a depth in the range of 0.5 μm to 5 μm, inclusive, and the encapsulant extends into the plurality of cavities.

20. According to the electronic device of claim 19, wherein, The electronic device is at least one of a mobile phone, a smart phone, a tablet computer device, a camera, a wearable computing device, a vehicle, or an automated machine.

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