Semiconductor Devices

Abstract

A semiconductor device includes: a lower contact pattern including a first metal; an upper contact pattern including a second metal, the first metal having a first resistivity greater than a second resistivity of the second metal; and a metal barrier layer located between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first metal and the second metal. The lower width of the upper contact pattern may be smaller than the upper width of the lower contact pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0103566 filed on August 23, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to semiconductor devices, and more particularly, to semiconductor devices including a low resistance contact structure. Background Art

[0004] As semiconductor devices become highly integrated, the scaling down of elements (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) included in semiconductor devices is gradually accelerating. In this case, since the reduction of critical dimension (CD) increases the resistance of wiring and the capacitance between wirings, it is difficult to achieve high-speed operation of semiconductor devices. Therefore, various studies have been conducted to manufacture semiconductor devices with improved performance while overcoming limitations caused by the high integration of semiconductor devices. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a semiconductor device including a low resistance contact structure.

[0006] The objects of the inventive concept are not limited to the above objects, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0007] According to some example embodiments of the inventive concept, a semiconductor device may include: a lower contact pattern including a first metal; an upper contact pattern including a second metal, a first resistivity of the first metal being greater than a second resistivity of the second metal; and a metal barrier layer located between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first metal and the second metal. A lower width of the upper contact pattern may be smaller than an upper width of the lower contact pattern.

[0008] According to some example embodiments of the present inventive concept, a semiconductor device may include: a semiconductor substrate; an interlayer dielectric layer located on the semiconductor substrate; an upper contact pattern penetrating the interlayer dielectric layer, the upper contact pattern including a first metal; a lower contact pattern surrounding a lower portion of the upper contact pattern, the lower contact pattern including a second metal, the second metal being different from the first metal; and a metal barrier layer located between the lower contact pattern and the lower portion of the upper contact pattern, the metal barrier layer including a third metal different from the first metal and the second metal. The lower contact pattern may have a first upper width and a first lower width that is smaller than the first upper width. The upper contact pattern may have a second upper width and a second lower width, both of which are smaller than the first lower width. The bottom surface of the upper contact pattern may be located between the top and the bottom of the lower contact pattern.

[0009] According to some example embodiments conceived in the present invention, a semiconductor device may include: a semiconductor substrate including an active pattern; a gate structure spanning the active pattern and extending along a first direction; a plurality of source / drain patterns located on the active pattern, each source / drain pattern of the plurality of source / drain patterns being located on an opposite side of the gate structure; and a contact structure coupled to a corresponding source / drain pattern of the plurality of source / drain patterns.

[0010] The contact structure may include: a lower contact pattern located in the corresponding source / drain pattern, the lower contact pattern including a first metal; an upper contact pattern including a lower portion located in a recess defined by a top surface of the lower contact pattern, the upper contact pattern including a second metal; and a metal barrier layer located between the lower contact pattern and the lower portion of the upper contact pattern, the metal barrier layer including a third metal. The bottom of the upper contact pattern may be lower than the top of the lower contact pattern.

[0011] Details of some example embodiments are included in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A top view showing a semiconductor device according to some example embodiments of the inventive concepts is illustrated.

[0013] Figure 2 Shown along Figure 1 sectional views taken along lines II′ and II-II′ in FIG. 1 show semiconductor devices according to some example embodiments of the inventive concept.

[0014] Figure 3A and Figure 3B Shows the display Figure 2 Magnified view of section A in FIG.

[0015] Figure 4 A graph showing a relationship between a resistivity of a metal included in a contact structure according to some example embodiments of the inventive concepts and a width or size is illustrated.

[0016] FIG. 5A to FIG. 5D Shown along Figure 1 A cross-sectional view taken along line II' in FIG. 1 shows a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.

[0017] FIG. 6A to FIG. 6C Shown along Figure 1 A cross-sectional view taken along line II' in FIG. 1 shows a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.

[0018] Figure 7 A top view showing a semiconductor device according to some example embodiments of the inventive concepts is illustrated.

[0019] Fig. 8A Shown along Figure 7 A cross-sectional view taken along line III-III' in FIG. 1 shows a semiconductor device according to some example embodiments of the inventive concept.

[0020] Figure 8B and Figure 8C Shown along Figure 7 A cross-sectional view taken along line IV-IV' in FIG. 1 shows a semiconductor device according to some example embodiments of the inventive concept.

[0021] Fig. 9 Shows the display Fig. 8A Magnified view of section B in FIG.

[0022] FIG. 10A to FIG. 10D Shown along Figure 7 A cross-sectional view taken along line III-III' in FIG. 1 shows a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.

[0023] Fig.11A and Fig. 11B The Figure 7 sectional views taken along lines III-III′ and IV-IV′ in FIG. 1 show semiconductor devices according to some example embodiments of the inventive concept.

[0024] Fig.12 A top view showing a semiconductor device according to some example embodiments of the inventive concepts is illustrated.

[0025] Fig.13Aand Fig. 13B The Fig.12 sectional views taken along lines VV′ and VI-VI′ in FIG. 1 show semiconductor devices according to some example embodiments of the inventive concept.

[0026] Fig.14 Cross-sectional views showing semiconductor devices according to some example embodiments of the inventive concepts are illustrated. DETAILED DESCRIPTION

[0027] Now, a semiconductor device and a method of manufacturing the same according to some example embodiments of the inventive concept will be described below with reference to the accompanying drawings.

[0028] Although the terms "same" or "same" are used in the description of example embodiments, it should be understood that a certain degree of imprecision may exist. Therefore, when an element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element or value within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0029] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, the relevant numerical value is intended to include a manufacturing or operating tolerance (e.g., ±10%) around the recited numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but the range of variation in shape is within the scope of the present disclosure.

[0030] As used herein, expressions such as "at least one of" when preceding a list of elements modify the entire list of elements rather than modifying the individual elements of the list. Thus, "at least one of A, B, or C" and "A, B, and C" modify the entire list of elements rather than modifying the individual elements of the list, thus referring to A, B, C, or any combination thereof.

[0031] Figure 1 A top view showing a semiconductor device according to some example embodiments of the inventive concepts is illustrated. Figure 2 Shown along Figure 1 sectional views taken along lines II′ and II-II′ in FIG. 1 show semiconductor devices according to some example embodiments of the inventive concept. Figure 3A and Figure 3B Shows the display Figure 2 Magnified view of section A in FIG. Figure 4 A graph showing a relationship between a resistivity and a width or size of a metal included in a contact structure according to some example embodiments of the inventive concepts is illustrated.

[0032] Reference Figure 1 and Figure 2The semiconductor substrate 100 may be a compound semiconductor substrate or a semiconductor substrate including silicon, germanium, silicon germanium, etc. For example, the semiconductor substrate 100 may be a silicon substrate.

[0033] The semiconductor substrate 100 may include an active pattern 101. The active pattern 101 may be a portion of the semiconductor substrate 100, and may be defined by a trench (eg, a device isolation layer 102) formed on the semiconductor substrate 100. The active pattern 101 may extend in a first direction D1.

[0034] The active pattern 101 may be disposed between the device isolation layers 102. A top surface of the device isolation layer 102 may be lower than a top surface of the active pattern 101. In other words, the active pattern 101 may protrude upward relative to the top surface of the device isolation layer 102. An upper portion of the active pattern 101 may be exposed by the device isolation layer 102. The device isolation layers 102 may extend in a first direction D1 and may be spaced apart from each other in a second direction D2 intersecting the first direction D1.

[0035] The semiconductor substrate 100 may be provided with a gate structure GS crossing the active pattern 101. The gate structures GS may extend across the active pattern 101 in the second direction D2 and may be spaced apart from each other in the first direction D. The gate structures GS may have the same or substantially similar widths and may be spaced apart from each other at regular intervals.

[0036] Each gate structure GS may include a gate dielectric layer 111, a gate conductive pattern 113, and a capping dielectric pattern 115. Gate spacers 121 may be disposed on opposite sidewalls of each gate structure GS.

[0037] The gate dielectric layer 111 may extend along the second direction D2 and may conformally cover the upper portion of the active pattern 101. The gate dielectric layer 111 may extend from between the gate conductive pattern 113 and the active pattern 101 to between the gate conductive pattern 113 and the gate spacer 121. For example, the gate dielectric layer 111 may extend from the bottom surface of the gate conductive pattern 113 toward the opposite sidewalls of the gate conductive pattern 113. In other words, the gate dielectric layer 111 may extend upward from the bottom surface of the gate conductive pattern 113 along the sidewalls of the gate conductive pattern 113. The gate dielectric layer 111 may include a high-k dielectric material having a dielectric constant greater than that of silicon oxide. The gate dielectric layer 111 may include, for example, a metal oxide, a metal silicate, or a metal silicate nitride.

[0038] The gate conductive pattern 113 may include a barrier metal pattern (not specifically shown) and a metal pattern (not specifically shown). The barrier metal pattern may include a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride). The metal pattern may include a metal material (e.g., tungsten, aluminum, titanium, and / or tantalum).

[0039] The capping dielectric pattern 115 may cover the top surface of the gate conductive pattern 113. The top surface of the capping dielectric pattern 115 may be coplanar or substantially coplanar with the top surface of the gap-filling dielectric layer 161. The capping dielectric pattern 115 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride (SiCN), or silicon carbon oxynitride (SiCON). The gate spacer 121 may include a dielectric material, such as silicon oxide or silicon nitride.

[0040] The source / drain region 130 may be disposed on the upper portion of the active pattern 101 at opposite sides of each gate structure GS. Each source / drain region 130 may include n-type or p-type impurities. The active pattern 101 may have a portion (e.g., a channel region) located between the source / drain regions 130 spaced apart from each other in a horizontal direction.

[0041] The gap-fill dielectric layer 161 may fill the space between the gate structures GS and may cover the source / drain regions 130. For example, a top surface of the gap-fill dielectric layer 161 may be coplanar or substantially coplanar with a top surface of the gate structure GS.

[0042] A first interlayer dielectric layer 163 covering the top surface of the gate structure GS may be disposed on the gap-fill dielectric layer 161. The gap-fill dielectric layer 161 and the first interlayer dielectric layer 163 may be formed of a dielectric material having an etching selectivity with respect to the gate spacer 121, and may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0043] The contact structure CP may penetrate the first interlayer dielectric layer 163 and the gap-filling dielectric layer 161 and may be coupled to the source / drain region 130. According to some example embodiments, each contact structure CP may include a lower contact pattern 140, an upper contact pattern 150, and a metal barrier layer therebetween.

[0044] For example, the lower contact pattern 140 may be disposed in the source / drain region 130. In this case, the lower contact pattern 140 may be disposed in a recess of the source / drain region 130. The bottom surface of the lower contact pattern 140 may be located at a level lower than the level of the top of the source / drain region 130. The top of the lower contact pattern 140 may be the same as or substantially similar to the level of the top of the source / drain region 130.

[0045] The lower contact pattern 140 may have a first upper width A1 at its top, and a first lower width A2 less than the first upper width A1 at its bottom. The top of the lower contact pattern 140 may be partially removed to form a recess. The width of the recess may be less than the first upper width A1. For example, the lower contact pattern 140 may have a width of about 5 nm to about 30 nm.

[0046] Reference Figure 3A , the lower contact pattern 140 may include a first barrier metal pattern 141 and a first metal pattern 143. The first metal pattern 143 may include a first metal. The first metal may include, for example, one selected from cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), and tantalum (Ta). The first barrier metal pattern 141 may conformally cover the bottom surface and sidewalls of the first metal pattern 143. The first barrier metal pattern 141 may be formed of, for example, one or more of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, and WN.

[0047] The second metal barrier layer 145 may be locally disposed in a recess defined by the lower contact pattern 140. The second metal barrier layer 145 may substantially conformally cover the recess of the lower contact pattern 140. The second metal barrier layer 145 may include a second metal different from the first metal of the lower contact pattern 140. The second metal may include, for example, one selected from tungsten (W), molybdenum (Mo), manganese (Mn), indium (In), aluminum (Al), and nickel (Ni). The second metal barrier layer 145 may mitigate or prevent diffusion and / or intermixing between the first metal included in the lower contact pattern 140 and the third metal included in the upper contact pattern 150.

[0048] The upper contact pattern 150 may penetrate the first interlayer dielectric layer 163 and the gap-filling dielectric layer 161, and may be disposed on the lower contact pattern 140. A lower portion of the upper contact pattern 150 may be located in a recess of the lower contact pattern 140.

[0049] The upper contact pattern 150 may have a second upper width B1 at its top and a second lower width B2 at its bottom, the second lower width B2 being smaller than the second upper width B1. The second lower width B2 of the upper contact pattern 150 may be smaller than the first upper width A1 and the first lower width A2 of the lower contact pattern 140. For example, the upper contact pattern 150 may have a width of about 3 nm to about 15 nm.

[0050] The third metal of the upper contact pattern 150 may be a noble metal material. The upper contact pattern 150 may include, for example, one or more of rhenium (Re), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au).

[0051] The third metal of the upper contact pattern 150 may be in direct contact with the gap-fill dielectric layer 161, such as Figure 3A For another example, refer to Figure 3B , similar to the lower contact pattern 140 , the upper contact pattern 150 may include an upper barrier metal pattern 151 conformally covering a bottom surface and sidewalls of an upper metal pattern 153 .

[0052] A metal silicide layer 135 may be disposed between each contact structure CP and each source / drain region 130. The metal silicide layer 135 may contact a bottom surface and a sidewall of the lower contact pattern 140. The metal silicide layer 135 may include, for example, one or more of titanium, nickel, cobalt, tungsten, tantalum, platinum, palladium, and erbium.

[0053] Reference Figure 4 , the first metal M1 of the lower contact pattern 140 may have a resistivity that increases rapidly below a certain width W. At the second lower width B2 , the resistivity of the third metal M3 of the upper contact pattern 150 may be lower than that of the first metal M1 below the certain width W.

[0054] According to some example embodiments, the resistivity of the contact structure CP may be reduced because a portion of the lower contact pattern 140 is filled with a third metal having a resistivity lower than that of the first metal below a certain width W. Therefore, a signal delay through the contact structure CP may be reduced, thereby increasing an operating speed of the semiconductor device.

[0055] FIG. 5A to FIG. 5D Shown along Figure 1 A cross-sectional view taken along line II' in FIG. 1 shows a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.

[0056] Reference Figure 5A , the semiconductor substrate 100 may be patterned to form an active pattern 101 vertically protruding from the semiconductor substrate 100. A device isolation layer (see Figure 2 The device isolation layer 102 may have a top surface recessed from a top surface of the active pattern 101.

[0057] The gate structure GS may be formed to cross the active pattern 101. The formation of the gate structure GS may include: forming a sacrificial gate pattern (not shown); forming a gate spacer 121 on opposite sidewalls of the sacrificial gate pattern; sequentially forming a gate dielectric layer 111 and a gate conductive pattern 113 in a gate region between a pair of gate spacers 121 after removing the sacrificial gate pattern; and forming a capping dielectric pattern 115 on the gate dielectric layer 111 and the gate conductive pattern 113.

[0058] Source / drain regions 130 may be formed at opposite sides of each gate structure GS. As described above, the source / drain regions 130 may be in-situ doped with dopants having conductivity types opposite to those of corresponding portions of the semiconductor substrate 100, respectively.

[0059] The gate spacer 121 may be used as an etching mask to etch a portion of the source / drain region 130, thereby forming a first recess RS1 on each source / drain region 130. The depth of the first recess RS1 may be determined based on electrical characteristics of the semiconductor device.

[0060] Reference Figure 5B , a metal silicide layer 135 and a lower contact pattern 140 may be formed in the first recess RS1 of the source / drain region 130 .

[0061] The lower contact pattern 140 may be formed by sequentially depositing a first metal barrier layer and a first metal layer in the first recess RS1 of the source / drain region 130; and then partially etching the first metal barrier layer and the first metal layer located on the top surface of the active pattern 101. The first metal barrier layer may conformally cover the surface of the first recess RS1. While the first metal barrier layer and the first metal layer are deposited and annealed, the first metal barrier layer and the source / drain region 130 may react with each other to form a silicide layer 135 on the surface of the first recess RS1 of the source / drain region 130.

[0062] Reference Figure 5C After forming the lower contact pattern 140, a gap-filling dielectric layer 161 filling the space between the gate structures GS may be formed, and then a first interlayer dielectric layer 163 covering the gate structure GS may be formed. The contact hole CH may be formed to penetrate the first interlayer dielectric layer 163 and the gap-filling dielectric layer 161, thereby exposing a portion of the lower contact pattern 140. The formation of the contact hole CH may include: forming an etching mask on the first interlayer dielectric layer 163, and sequentially etching a portion of the first interlayer dielectric layer 163, a portion of the gap-filling dielectric layer 161, and a portion of the lower contact pattern 140 using the etching mask. Therefore, a portion of the top surface of the lower contact pattern 140 may be partially recessed to form a second recess RS2.

[0063] Reference Figure 5D , a second metal barrier layer 145 may be formed on the surface of the lower contact pattern 140 exposed to the contact hole CH. The second metal barrier layer 145 may be formed by performing a selective deposition process. The selective deposition process may use different deposition rates depending on the quality of the underlying film. The selective deposition process may allow the second metal barrier layer 145 to be deposited only on the surface of the lower contact pattern 140 exposed to the contact hole CH.

[0064] The second metal barrier layer 145 may include a second metal different from the first metal of the lower contact pattern 140. The second metal barrier layer 145 may be formed of a metal layer or a metal nitride layer including, for example, one or more of tantalum (Ta), titanium (Ti), tungsten (W), cobalt (Co), molybdenum (Mo), manganese (Mn), nickel (Ni), and aluminum (Al). In example embodiments, the second metal barrier layer 145 may include tungsten (W) or molybdenum (Mo).

[0065] An upper contact pattern may be formed in the contact hole CH in which the second metal barrier layer 145 is formed (see Figure 2 150). The upper contact pattern 150 may be formed by depositing a metal layer including a third metal different from the second metal; and etching the metal layer to expose the top surface of the first interlayer dielectric layer 163. The upper contact pattern 150 may include a noble metal material. The upper contact pattern 150 may include, for example, one or more of rhenium (Re), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au).

[0066] FIG. 6A to FIG. 6C Shown along Figure 1 A cross-sectional view taken along line II' in FIG. 1 shows a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.

[0067] For the sake of brevity, the above references may be omitted. FIG. 5A to FIG. 5D The technical features of the discussed example embodiments are the same as the technical features.

[0068] Reference Fig. 6A , in the above Figure 5B After the steps discussed in , a lower contact pattern 140 may be formed in the source / drain region 130 , and then a portion of the lower contact pattern 140 may be etched to form a second recess RS2 .

[0069] Reference Figure 6B, a second metal barrier layer 145 may be formed on the second recess RS2 of the lower contact pattern 140. The second metal barrier layer 145 may be selectively deposited on the surface of the lower contact pattern 140 having the second recess RS2 using a selective deposition process.

[0070] The first upper contact pattern 150a may be formed to fill the second recess RS2 in which the second metal barrier layer 145 is formed. The first upper contact pattern 150a may include a third metal having a resistivity lower than that of the lower contact pattern 140.

[0071] Reference Figure 6C , a first interlayer dielectric layer 163 may be formed to cover the gate structure GS. A contact hole CH may be formed to penetrate the first interlayer dielectric layer 163 and expose a portion of the first upper contact pattern 150a. The formation of the contact hole CH may include: forming an etching mask on the first interlayer dielectric layer 163; and etching a portion of the first interlayer dielectric layer 163 using the etching mask until the first upper contact pattern 150a is exposed.

[0072] A second upper contact pattern 150 b including the same third metal as that in the first upper contact pattern 150 a may be formed in the contact hole CH.

[0073] Figure 7 A top view showing a semiconductor device according to some example embodiments of the inventive concepts is illustrated. Fig. 8A Shown along Figure 7 A cross-sectional view taken along line III-III' in FIG. 1 shows a semiconductor device according to some example embodiments of the inventive concept. Figure 8B and Figure 8C Shown along Figure 7 A cross-sectional view taken along line IV-IV' in FIG. 1 shows a semiconductor device according to some example embodiments of the inventive concept.

[0074] For the sake of brevity, the references may be omitted. Figure 1 and Figure 2 The technical features of the discussed embodiments are the same as the technical features.

[0075] The semiconductor substrate 100 may include a first active region R1 and a second active region R2. The first active region R1 and the second active region R2 may be included in a logic cell region in which a logic transistor constituting a logic circuit of a semiconductor device is disposed. For example, a PMOS field effect transistor may be disposed on the first active region R1, and an NMOS field effect transistor may be disposed on the second active region R2. The semiconductor substrate 100 may include a dopant having a different conductivity type in the first active region R1 from that in the second active region R2.

[0076] On the first active region R1, a plurality of first active patterns 101a may extend along a first direction D1 and may be spaced apart from each other in a second direction D2 intersecting the first direction D1. On the second active region R2, a plurality of second active patterns 101b may extend along the first direction D1 and may be spaced apart from each other in a second direction D2 intersecting the first direction D1. The first active pattern 101a and the second active pattern 101b may be part of the semiconductor substrate 100 and may be defined by a first trench formed on the semiconductor substrate 100. In the example embodiment, three first active patterns 101a are shown, but the number of the first active patterns 101a may be variously changed. The same may also be true for the second active pattern 101b.

[0077] The first device isolation layer 102 may be disposed between the first active patterns 101a and between the second active patterns 101b. The first device isolation layer 102 may separate the first active pattern 101a and the second active pattern 101b from each other in the second direction D2. The first device isolation layer 102 may expose an upper portion of the first active pattern 101a and an upper portion of the second active pattern 101b. For example, a top surface of the first device isolation layer 102 may be lower than a top surface of the first active pattern 101a and a top surface of the second active pattern 101b, and an upper portion of the first active pattern 101a and an upper portion of the second active pattern 101b may protrude upward from a top surface of the first device isolation layer 102.

[0078] The second device isolation layer 105 may extend in the first direction D1 and may define the first active region R1 and the second active region R2. The second device isolation layer 105 may be disposed between the outermost first active pattern 101a of the first active pattern 101a of the first active region R1 and the adjacent outermost second active pattern 101b of the second active pattern 101b of the second active region R2. The width of the second device isolation layer 105 in the second direction D2 may be greater than the width of the first device isolation layer 102 in the second direction D2. The level at which the bottom surface of the second device isolation layer 105 is located may be lower than, equal to, or substantially similar to the level at which the bottom surface of the first device isolation layer 102 is located. The second device isolation layer 105 may separate the first active region R1 and the second active region R2 from each other in the second direction D2.

[0079] The gate structure GS may extend along the second direction D2 while crossing the first active pattern 101a of the first active region R1 and the second active pattern 101b of the second active region R2. The gate structures GS may be arranged at a regular pitch. For example, the gate structures GS may have the same or substantially similar widths and may be spaced apart from each other at regular intervals.

[0080] Each gate structure GS may include a gate dielectric layer 111, a gate conductive pattern 113, and a capping dielectric pattern 115. Gate spacers 121 may be disposed on opposite sidewalls of each gate structure GS.

[0081] The source / drain pattern 130a may be disposed at opposite sides of each gate structure GS. The source / drain pattern 130a may include a first source / drain pattern located at an upper portion of the first active pattern 101a and a second source / drain pattern located at an upper portion of the second active pattern 101b. The first active pattern 101a or the second active pattern 101b may have a portion (e.g., a channel region) located between the source / drain patterns 130a spaced apart from each other in a horizontal direction.

[0082] When the first active region R1 is provided with an NMOS field effect transistor (FET), the first source / drain pattern may be configured to provide tensile strain to the channel region of the NMOSFET (e.g., to the upper portion of the active pattern 101). For example, the first source / drain pattern may be an epitaxial layer of silicon carbide (SiC). When the second active region R2 is provided with a PMOSFET, the second source / drain pattern may be configured to provide compressive strain to the channel region of the PMOSFET. For example, the second source / drain pattern may be an epitaxial layer of silicon germanium (SiGe).

[0083] The first source / drain pattern on the first active region R1 may include a p-type impurity, and the second source / drain pattern on the second active region R2 may include an n-type impurity. For example, the source / drain pattern 130a may be an epitaxial layer grown from the first active pattern 101a and the second active pattern 101b. The first source / drain pattern on the first active region R1 may be an epitaxial layer of silicon germanium (SiGe), and the second source / drain pattern on the second active region R2 may be an epitaxial layer of silicon carbide (SiC). For example, the volume of the first source / drain pattern may be greater than the volume of the second source / drain pattern. The bottom end of the first source / drain pattern may be lower than the bottom end of the second source / drain pattern.

[0084] The gap-filling dielectric layer 161 may fill the space between the gate structures GS and may cover the first source / drain pattern and the second source / drain pattern. For example, the top surface of the gap-filling dielectric layer 161 may be coplanar or substantially coplanar with the top surface of the gate structure GS.

[0085] A first interlayer dielectric layer 163 covering the top surface of the gate structure GS may be disposed on the gap-fill dielectric layer 161. The gap-fill dielectric layer 161 and the first interlayer dielectric layer 163 may be formed of a dielectric material having an etching selectivity with respect to the gate spacer 121, and may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0086] On the first and second active regions R1 and R2 , the active contact structure ACP may penetrate the first interlayer dielectric layer 163 and the gap-filling dielectric layer 161 , and may be coupled to the source / drain patterns 130 a .

[0087] With reference to above Figure 2 Similar to the contact structures CP discussed above, each active contact structure ACP may include a lower contact pattern 140 , an upper contact pattern 150 , and a metal barrier layer 145 between the lower contact pattern 140 and the upper contact pattern 150 .

[0088] For example, refer to Fig. 9 The bottom of the lower contact pattern 140 may be located at a level lower than the top of the source / drain pattern 130a. The top of the lower contact pattern 140 may be located at a level substantially the same as the top of the source / drain pattern 130a.

[0089] Reference Figure 7 , Fig. 8A and Figure 8B , the gate contact structure GCP may be coupled to the corresponding gate conductive pattern 113 of the gate structure GS, respectively. The gate contact structure GCP may penetrate the first interlayer dielectric layer 163 and the covering dielectric pattern 115 of the gate structure GS. Although not specifically shown, the gate contact structure GCP may also penetrate the gap-filling dielectric layer 161. The gate contact structure GCP may be formed simultaneously with the active contact structure ACP and may include the same metal material as the metal material of the active contact structure ACP. The top surface of the gate contact structure GCP may be coplanar or substantially coplanar with the top surface of the active contact structure ACP.

[0090] For example, refer to Figure 8B , similar to the active contact structure ACP, the gate contact structure GCP may include a lower contact pattern 140 , a metal barrier layer 145 , and an upper contact pattern 150 , and a lower portion of the upper contact pattern 150 may be disposed in a recess defined by a top surface of the lower contact pattern 140 .

[0091] For another example, see Figure 8C , the gate contact structure GCP may include a metal barrier layer and an upper contact pattern, but does not include a lower contact pattern. In this case, the metal barrier layer may directly contact the gate conductive pattern 113 of the gate structure GS.

[0092] Reference Figure 7 , Fig. 8A and Figure 8BThe via pattern VP may be disposed in the second interlayer dielectric layer 165 and may be coupled to the active contact structure ACP. The via pattern VP may include a metal (e.g., one or more of tungsten, titanium, tantalum, cobalt, and copper) and a conductive metal nitride (e.g., one of titanium nitride, tantalum nitride, and tungsten nitride).

[0093] The interconnection pattern ICP may be disposed in the third interlayer dielectric layer 167 and may be coupled to the via pattern VP. On each of the first active region R1 and the second active region R2, the interconnection pattern ICP may cross one gate structure GS. For example, the interconnection pattern ICP may have a bar shape or a line shape extending along the first direction D1 on the second device isolation layer 105.

[0094] FIG. 10A to FIG. 10D Shown along Figure 7 A cross-sectional view taken along line III-III' in FIG. 1 shows a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.

[0095] Reference Fig. 10A , the semiconductor substrate 100 may be patterned to form an active pattern 101a vertically protruding from the semiconductor substrate 101. A device isolation layer (see Figure 8B The device isolation layer 102 may have a top surface recessed from a top surface of the active pattern 101a.

[0096] The gate structure GS may be formed to cross the active pattern 101a. The formation of the gate structure GS may include: forming a sacrificial gate pattern (not shown); forming a gate spacer 121 on opposite sidewalls of the sacrificial gate pattern; after removing the sacrificial gate pattern, sequentially forming a gate dielectric layer 111 and a gate conductive pattern 113 in the gate region between a pair of gate spacers 121; and forming a capping dielectric pattern 115 on the gate dielectric layer 111 and the gate conductive pattern 113.

[0097] The source / drain pattern 130a may be formed at opposite sides of each gate structure GS. The source / drain pattern 130a may be formed by epitaxial growth from the active pattern 101a. The source / drain pattern 130a may include an epitaxial layer of silicon germanium (SiGe) or silicon carbide (SiC).

[0098] According to some example embodiments, after forming the source / drain patterns 130 a , a gate structure GS including a metal material may be formed. A gap-filling dielectric layer 161 may fill a space between the gate structures GS.

[0099] Reference Fig. 10B, a lower contact pattern 140 may be formed to penetrate the gap-fill dielectric layer 161 to be coupled to the corresponding source / drain pattern 130 a .

[0100] As mentioned above Figure 5B As discussed, the formation of the lower contact pattern 140 may include depositing a first metal barrier layer and a first metal layer.

[0101] While the lower contact pattern 140 is being formed, a silicide layer 135 may be formed between the source / drain pattern 130 a and the lower contact pattern 140 .

[0102] Reference Fig. 10C , an interlayer dielectric layer 163 may be deposited on the lower contact pattern 140. The interlayer dielectric layer 163 may cover a top surface of the lower contact pattern 140 and a top surface of the gate structure GS.

[0103] The contact hole CH may be formed to penetrate the interlayer dielectric layer 163 and expose a portion of the lower contact pattern 140. The formation of the contact hole CH may include: forming an etching mask on the interlayer dielectric layer 163; and sequentially etching the interlayer dielectric layer 163 and a portion of the lower contact pattern 140 using the etching mask. Thus, the top of the lower contact pattern 140 may be partially removed or partially recessed to form a recess. The level at which the bottom surface of the recess is located may be lower than the level of the top surface of the gate structure GS.

[0104] Reference Fig. 10D , as referenced above Figure 5D As discussed, a second metal barrier layer 145 may be formed on the surface of the lower contact pattern 140 exposed to the contact hole CH. The second metal barrier layer 145 may be deposited only on the surface of the lower contact pattern 140 exposed to the contact hole CH. The second metal barrier layer 145 may include a second metal different from the first metal of the lower contact pattern 140.

[0105] An upper contact pattern may be formed in the contact holes CH each having the second metal barrier layer 145 formed therein (see Fig. 8A As described above, the upper contact pattern 150 may include a third metal different from the first metal of the lower contact pattern 140. The third metal may have a lower resistivity than the first metal, and the third metal may include a noble metal material.

[0106] Fig.11A and Fig. 11B The Figure 7 sectional views taken along lines III-III′ and IV-IV′ in FIG. 1 show semiconductor devices according to some example embodiments of the inventive concept.

[0107] For the sake of brevity, the references may be omitted. Figure 7 , Fig. 8A and Figure 8C The technical features of the discussed embodiments are the same as the technical features.

[0108] Fig.11A and Fig. 11B The semiconductor device shown may be a multi-bridge channel field effect transistor (MBCFET). The MBCFET may include multiple thin rectangular nanosheet channels and gate electrodes surrounding the channels up and down and left and right. Multiple thin nanosheets may be stacked in a vertical direction.

[0109] For example, refer to Fig.11A and Fig. 11B , first channel patterns CH1 vertically stacked and spaced apart from each other may be disposed on each of the first active patterns 101a. The first channel patterns CH1 stacked on the first active patterns 101a may vertically overlap each other.

[0110] Each second active pattern 101b may be provided with second channel patterns CH2 stacked vertically and spaced apart from each other. The second channel patterns CH2 stacked on the second active pattern 101b may vertically overlap each other. The first channel pattern CH1 and the second channel pattern CH2 may include one or more of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0111] The first source / drain pattern 130a may be disposed on each of the first active patterns 101a. The stacked first channel pattern CH1 may be disposed between the pair of adjacent first source / drain patterns 130a. The stacked first channel pattern CH1 may connect the pair of adjacent first source / drain patterns 130a.

[0112] The second source / drain pattern may be disposed on each of the second active patterns 101b. The stacked second channel pattern CH2 may be disposed between the pair of adjacent second source / drain patterns. The stacked second channel pattern CH2 may connect the pair of adjacent second source / drain patterns.

[0113] As described above, each gate structure GS may include a gate dielectric layer 111, a gate conductive pattern 113, and a capping dielectric pattern 115, and a gate spacer 121 may be disposed on opposite sidewalls of each gate structure GS. In some example embodiments, the capping dielectric pattern 115 may have a rounded bottom surface, and the rounded bottom surface may be in contact with a top surface of the gate conductive pattern 113. The rounded surface of the capping dielectric pattern 115 may be in contact with a sidewall of the gate spacer 121.

[0114] On each gate structure GS, the gate conductive pattern 113 may surround the first channel pattern CH1 and the second channel pattern CH2. For example, the gate conductive pattern 113 may surround the top and bottom surfaces and opposite sidewalls of each of the first channel pattern CH1 and the second channel pattern CH2. In this sense, the transistors disposed on the first active region R1 and the second active region R2 may be gate-all-around field effect transistors.

[0115] The gate dielectric layer 111 may be disposed between the gate conductive pattern 113 and each of the first and second channel patterns CH1 and CH2. The gate dielectric layer 111 may surround a corresponding channel pattern of the first and second channel patterns CH1 and CH2.

[0116] The inner spacer 112 may be disposed below the gate spacer 121 and on the sidewall of the gate structure GS. When viewed in a cross-sectional view, the inner spacer 112 may be locally disposed between adjacent first channel patterns CH1 and between the first active pattern 101a and the lowermost first channel pattern CH1. When viewed in a top view, one or more inner spacers 112 may be locally disposed between the first source / drain pattern 130a and the opposite sidewall of the gate structure GS. The inner spacer 112 may contact the gate dielectric layer 111 and may be formed of a dielectric material.

[0117] According to some embodiments, as described above, the active contact structure ACP may penetrate the first interlayer dielectric layer 163 and may be coupled to the first source / drain pattern 130a. Although not specifically shown, the active contact structure ACP may also penetrate the gap-filling dielectric layer 161. The active contact structure ACP may be disposed in a portion of the first source / drain pattern 130a. A metal silicide layer 135 may be formed between the active contact structure ACP and the first source / drain pattern 130a.

[0118] The gate contact structure GCP may be coupled to the gate conductive pattern 113 of the gate structure GS. As described above, the gate contact structure GCP may include the same metal material as that of the active contact structure ACP.

[0119] Fig.12 A top view showing a semiconductor device according to some example embodiments of the inventive concepts is illustrated. Fig.13A and Fig. 13B Shown are Fig.12 The cross-sectional views taken along the lines V-V' and VI-VI' in FIG. 1 show semiconductor devices according to some exemplary embodiments of the present invention. Figure 1 and Figure 2The technical features of the discussed embodiments are the same as the technical features.

[0120] Reference Fig.12 , Fig.13A and Fig. 13B A selection transistor as a selection element of a memory cell may be disposed on the semiconductor substrate 100. The selection transistor may include a cell active pattern CA, a gate structure GS crossing the cell active pattern CA, and first and second impurity regions formed in the cell active pattern CA at opposite sides of each gate structure GS.

[0121] For example, a device isolation pattern 102 defining a unit active pattern CA may be disposed on the first region R1 of the semiconductor substrate 100. Each unit active pattern CA may be defined between the device isolation patterns 102 adjacent to each other. In example embodiments, the unit active pattern CA may have a line shape or a bar shape having a major axis in the first direction D1. The unit active pattern CA may include impurities having a first conductivity type.

[0122] On the semiconductor substrate 100, the gate structures GS may cross the cell active patterns CA and the device isolation patterns 102. The gate structures GS may each have a line shape extending along the second direction D2. The gate dielectric layer 111 may be disposed between the semiconductor substrate 100 and the cell gate electrodes CG.

[0123] The gate structure GS may include, for example, one or more of a doped semiconductor material, a metal, a conductive metal nitride, and a metal-semiconductor compound. The gate dielectric layer 111 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric.

[0124] The source / drain region 130 may be disposed in the cell active pattern CA at opposite sides of each cell gate electrode CG. The source / drain region 130 may be doped with a dopant having a second conductivity type (eg, n type) different from a first conductivity type (eg, p type) of the cell active pattern CA.

[0125] The lower dielectric layer 210 may cover the entire surface of the semiconductor substrate 100. For example, the lower dielectric layer 210 may cover the selection transistor.

[0126] The source line SL may penetrate the lower dielectric layer 210 and may be connected to one of the source / drain regions 130. The source line SL may extend parallel to the gate structure GS. When viewed in a top view, each source line SL may be disposed between gate structures GS adjacent to each other. The top surface of the source line SL may be coplanar or substantially coplanar with the top surface of the lower dielectric layer 210. The contact plug ACP may penetrate the lower dielectric layer 210 and may be electrically connected to the source / drain region 130.

[0127] According to some example embodiments, the source line SL and the contact plug ACP may have the same characteristics as those of the above-described contact structure.

[0128] A conductive pad 225 disposed in the dielectric layer 220 may be disposed on the contact plug ACP, and an intermediate dielectric layer 230 may be disposed on the conductive pad 225. A lower contact plug 235 may be disposed in the intermediate dielectric layer 230. A data storage pattern DSP may be disposed on the intermediate dielectric layer 230. When viewed in a top view, the data storage patterns DSP may be arranged to be spaced apart from each other along a first direction D1 and a second direction D2 intersecting each other, and may be coupled to the corresponding lower contact plug 235. The data storage pattern DSP may be coupled to the corresponding source / drain region 130 through the lower contact plug 235 and the contact plug ACP. For example, the data storage pattern DSP may be electrically connected to the corresponding selection transistor.

[0129] The bottom electrode BE may be disposed between the data storage pattern DSP and the lower contact plug 235. The top electrode TE may be disposed on a top surface of the data storage pattern DSP. The top electrode TE, the data storage pattern DSP, and the bottom electrode BE may have sidewalls aligned with each other.

[0130] The bottom electrode BE and the top electrode TE may include conductive metal nitrides. For example, the bottom electrode BE may include one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0131] An upper dielectric layer 240 filling a space between the data storage patterns DSP may be disposed on the intermediate dielectric layer 230 .

[0132] The bit lines BL disposed in the dielectric layer 250 may be disposed on the upper dielectric layer 240. Each of the bit lines BL may make contact with the top electrodes TE arranged in the first direction D1.

[0133] Fig.14 A cross-sectional view of a semiconductor device showing some example embodiments of the present invention is shown. Figure 1 and Figure 2 The technical features of the embodiments discussed are the same as the technical features of the embodiments discussed. Fig.14 In the example embodiment shown, the contact structure CP may electrically connect the upper connection line UCL to the lower connection line LCL.

[0134] For example, refer to Fig.14, a gate structure GS crossing the active pattern 101 may be disposed on the semiconductor substrate 100. A source / drain pattern 130 may be disposed in the active pattern 101 at opposite sides of each gate structure GS. The source / drain pattern 130 may be doped with a dopant having a second conductivity type (e.g., n-type) different from a first conductivity type (e.g., p-type) of the active pattern 101.

[0135] The lower dielectric layer 210 may cover the gate structure GS and the source / drain pattern 130. The contact plug ACP may penetrate the interlayer dielectric layer 163 and may be electrically coupled to the source / drain pattern 130. In example embodiments, it is shown that the lower dielectric layer 210 covers the gate structure GS and the source / drain pattern 130, but the lower dielectric layer 210 may cover capacitors, resistors, contact plugs, and connection lines formed on the semiconductor substrate 100.

[0136] The lower dielectric layer 210 may be provided with a lower connection line LCL disposed in the dielectric layer 220 .

[0137] The intermediate dielectric layer 230 and the upper dielectric layer 240 may be stacked on the lower connection line LCL, and the contact structure CP may penetrate the intermediate dielectric layer 230 and the upper dielectric layer 240 and may be coupled to the lower connection line LCL. As described above, the contact structure CP may include: a lower contact pattern 140 including a first metal, a metal barrier layer 145 including a second metal, and an upper contact pattern 150 including a third metal. The lower portion of the upper contact pattern 150 may be disposed in a recess defined by the top surface of the lower contact pattern 140.

[0138] The upper connection lines UCL disposed in the dielectric layer 250 may intersect the lower connection lines LCL and may be coupled to the contact structures CP.

[0139] According to some example embodiments of the present invention, a semiconductor device may include a contact structure having a lower contact pattern and an upper contact pattern. The upper contact pattern may include a second metal, the resistivity of the second metal below a certain width is lower than the resistivity of the first metal of the lower contact pattern, and a portion of the upper contact pattern may be disposed in a recess of the lower contact pattern. Therefore, the lower contact pattern may have a reduced resistivity, and then the resistivity of the contact structure may be reduced. Therefore, a signal delay through the contact structure may be reduced, thereby increasing the operating speed of the semiconductor device.

[0140] Although the present inventive concept has been described in conjunction with some example embodiments shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential features of the present inventive concept.

Claims

1. A semiconductor device, comprising: a lower contact pattern, the lower contact pattern comprising a first metal; an upper contact pattern, the upper contact pattern comprising a second metal, a first resistivity of the first metal being greater than a second resistivity of the second metal; a metal barrier layer, the metal barrier layer being located between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer comprising a third metal, the third metal being different from the first metal and the second metal; Semiconductor layer; an interlayer dielectric layer, the interlayer dielectric layer being located on the semiconductor layer; as well as A conductive line, wherein the conductive line is located on the interlayer dielectric layer, wherein the lower contact pattern is located in the semiconductor layer, wherein the upper contact pattern penetrates the interlayer dielectric layer and connects the conductive line to the lower contact pattern, wherein the lower width of the upper contact pattern is smaller than the upper width of the lower contact pattern, and Wherein, a top surface of the metal barrier layer is coplanar with a top surface of the lower contact pattern.

2. The semiconductor device according to claim 1, wherein A bottom surface of the upper contact pattern is located between a top and a bottom of the lower contact pattern.

3. The semiconductor device according to claim 1, further comprising: A lower metal barrier layer surrounds a bottom surface and sidewalls of the lower contact pattern.

4. The semiconductor device according to claim 1, wherein: The upper contact pattern is located in the interlayer dielectric layer, and the second metal included in the upper contact pattern is in direct contact with the interlayer dielectric layer.

5. The semiconductor device according to claim 1, wherein The first metal includes one of cobalt, titanium, nickel, tungsten, molybdenum and tantalum.

6. The semiconductor device according to claim 1, wherein The second metal includes one of rhenium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum and gold.

7. The semiconductor device according to claim 1, wherein The third metal includes one of tungsten, molybdenum, manganese, indium, aluminum and nickel.

8. The semiconductor device according to claim 1, wherein The first metal includes cobalt and the second metal includes ruthenium.

9. The semiconductor device according to claim 1, wherein: The semiconductor layer includes a semiconductor substrate, and the semiconductor substrate includes an active pattern. The semiconductor device further comprises: a gate structure, the gate structure crossing the active pattern, and a plurality of source / drain patterns located in the active pattern at opposite sides of the gate structure, and The lower contact pattern is coupled to a corresponding source / drain pattern among the plurality of source / drain patterns.

10. The semiconductor device according to claim 9, wherein A top surface of the lower contact pattern is located at the same level as a top surface of the source / drain pattern.

11. The semiconductor device according to claim 9, further comprising: A metal silicide layer is located between the corresponding source / drain pattern and the lower contact pattern.

12. A semiconductor device, comprising: Semiconductor substrate; an interlayer dielectric layer, the interlayer dielectric layer being located on the semiconductor substrate; A conductive line, wherein the conductive line is located on the interlayer dielectric layer; an upper contact pattern, the upper contact pattern penetrating the interlayer dielectric layer, the upper contact pattern comprising a first metal; a lower contact pattern, the lower contact pattern surrounding a lower portion of the upper contact pattern, the lower contact pattern comprising a second metal, a second resistivity of the second metal being greater than a first resistivity of the first metal; as well as a metal barrier layer, the metal barrier layer being located between the lower contact pattern and the lower portion of the upper contact pattern, the metal barrier layer comprising a third metal different from the first metal and the second metal, wherein the lower contact pattern has a first upper width and a first lower width smaller than the first upper width, wherein the upper contact pattern has a second upper width and a second lower width, and both the second upper width and the second lower width are smaller than the first lower width, wherein the bottom surface of the upper contact pattern is located between the top and bottom of the lower contact pattern, wherein the lower contact pattern is located in the semiconductor substrate, wherein the upper contact pattern penetrates the interlayer dielectric layer and connects the conductive line to the lower contact pattern, and Wherein, a top surface of the metal barrier layer is coplanar with a top surface of the lower contact pattern.

13. The semiconductor device according to claim 12, wherein: The bottom surface of the upper contact pattern is lower than a bottom surface of the interlayer dielectric layer.

14. The semiconductor device according to claim 12, wherein: The first metal includes ruthenium and the second metal includes cobalt.

15. A semiconductor device, comprising: a semiconductor substrate, the semiconductor substrate comprising an active pattern; a gate structure, the gate structure crossing the active pattern and extending along a first direction; a plurality of source / drain patterns, the plurality of source / drain patterns being located on the active pattern, each of the plurality of source / drain patterns being located at an opposite side of the gate structure; as well as a contact structure coupled to a corresponding source / drain pattern among the plurality of source / drain patterns, Wherein, the contact structure comprises: a lower contact pattern, the lower contact pattern being located in the corresponding source / drain pattern, the lower contact pattern comprising a first metal, an upper contact pattern including a lower portion located in a recess defined by a top surface of the lower contact pattern, the upper contact pattern including a second metal having a first resistivity greater than a second resistivity of the second metal, and a metal barrier layer, the metal barrier layer being located between the lower contact pattern and the lower portion of the upper contact pattern, the metal barrier layer comprising a third metal, wherein the bottom of the upper contact pattern is lower than the top of the lower contact pattern, and Wherein, a top surface of the metal barrier layer is coplanar with a top surface of the lower contact pattern.

16. The semiconductor device according to claim 15, wherein: The first metal includes cobalt and the second metal includes ruthenium.

17. The semiconductor device according to claim 15, wherein: The third metal includes tungsten or molybdenum.

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