Semiconductor device including a gate structure having a skirt region

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: an active fin protruding upward from a substrate and extending in a first direction; and a gate structure extending in a second direction crossing the active fin, wherein a first width of a lower portion of the gate structure contacting the active fin is greater than a second width of a lower portion of the gate structure spaced apart from the active fin.

Description

[0001] This application is a divisional application based on the Chinese patent application filed on January 14, 2016, with application number 201610023864.4 and invention name “Semiconductor device including a gate structure with a skirt region”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority from Korean Patent Application No. 10-2015-0006772 filed in the Korean Intellectual Property Office on January 14, 2015, and U.S. Provisional Patent Application No. 62 / 104,539 filed in the U.S. Patent and Trademark Office on January 16, 2015, the contents of each of which are incorporated herein by reference. Technical Field

[0004] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0005] Multi-gate transistors have been proposed as a potential technology for increasing the density of integrated circuit devices. The multi-gate transistor has a fin-shaped or nanowire-shaped semiconductor body formed on a substrate and a gate subsequently formed on the surface of the semiconductor body. Since the multi-gate transistor uses a three-dimensional (3D) channel, it is easy to achieve the calibration of the multi-gate transistor. In addition, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, in the multi-gate transistor, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be suppressed. Summary of the invention

[0006] The inventive concept provides a semiconductor device having improved operating performance.

[0007] According to one aspect of the present invention, there is provided a semiconductor device, comprising: an active fin protruding from a substrate and extending in a first direction; a gate structure extending in a second direction intersecting the first direction, the gate structure being located on the active fin; and a field insulation layer located on the bottom of a long side of the active fin, wherein a top surface of the field insulation layer and an intersection portion of the active fin define at least one line segment, wherein the gate structure comprises a skirt extending outward in the first direction to cover a portion of the at least one line segment while exposing another portion of the at least one line segment.

[0008] According to another aspect of the present invention, a semiconductor device is provided, comprising: a first active fin and a second active fin protruding upward from a substrate and extending parallel to each other in a first direction; and a first gate structure extending in a second direction intersecting the first direction, the first gate structure being located on the active fin and on the second active fin, wherein the first gate structure comprises: a first skirt, in which a first side of the first gate structure extends outward in the first direction to contact a first side of the first active fin; a second skirt, in which a second side of the first gate structure extends outward in the first direction to contact a first side of the first active fin, the second side of the first gate structure being opposite to the first side of the first gate structure; a third skirt, in which the first side of the first gate structure extends outward in the first direction to contact a first side of a second active fin facing the first side of the first active fin; and a fourth skirt, in which the second side of the first gate structure extends outward in the first direction to contact the first side of the second active fin.

[0009] According to another aspect of the present invention, a semiconductor device is provided, comprising: an active fin protruding from a substrate and extending in a first direction; a gate structure extending in a second direction intersecting the first direction, the gate structure intersecting the active fin; and a dummy gate structure extending in the second direction to intersect the active fin, the active fin having an end portion located below the dummy gate structure, wherein the dummy gate structure comprises a first skirt, wherein a first side of the dummy gate structure extends outward in the first direction to contact a side surface of the active fin.

[0010] According to another aspect of the present invention, a semiconductor device is provided, comprising: a first active fin and a second active fin protruding from a substrate and extending parallel to each other in a first direction; a first gate structure extending in a second direction intersecting the first direction, the first gate structure being located on the first active fin and the second active fin; and a second gate structure extending parallel to the first gate structure, the second gate structure being located on the first active fin and the second active fin, wherein the first gate structure comprises: a first region adjacent to the first active fin and a second region spaced apart from the first active fin and the second active fin, the width of the first region being greater than the width of the second region, and the second gate structure comprises: a third region adjacent to the first active fin and a fourth region spaced apart from the first active fin and the second active fin, the width of the third region being greater than the width of the fourth region.

[0011] According to another aspect of the present invention, a semiconductor device is provided, comprising: an active fin protruding from a substrate and extending in a first direction; a field insulation layer adjacent to a long side of the active fin; a gate structure extending along a second direction on the field insulation layer to intersect the active fin; and a spacer located on at least one side of the gate structure and extending in the second direction, wherein the gate structure comprises: a first portion, in which the gate structure extends below the spacer; and a second portion, in which the gate structure does not extend below the spacer.

[0012] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate; an active fin protruding upward from the substrate and extending in a first direction; and a gate structure extending in a second direction to intersect the active fin, wherein a first width of a lower portion of the gate structure in contact with the active fin is greater than a second width of a lower portion of the gate structure spaced apart from the active fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a layout diagram showing a gate structure and active fins of a semiconductor device according to an embodiment of the inventive concept;

[0014] Figure 2 It is shown Figure 1 A perspective view of one of the gate structures and one of the active fins of the semiconductor device;

[0015] Figure 3 It is along Figure 1 A cross-sectional view taken along line AA';

[0016] Figure 4A It is along Figure 1 A cross-sectional view taken along line BB';

[0017] Figure 4B It is shown Figure 1 Area A1 along Figure 1 A cross-sectional view taken along line B1-B1';

[0018] Figure 4C It shows Figure 1 Area A2 along Figure 1 A cross-sectional view taken along line B2-B2';

[0019] Figure 5 is a layout diagram showing a gate structure and active fins of a semiconductor device according to another embodiment of the inventive concept;

[0020] Figure 6 It is along Figure 5 A cross-sectional view taken along line CC';

[0021] Figure 7 is a layout diagram showing a gate structure and active fins of a semiconductor device according to yet another embodiment of the inventive concept;

[0022] Figure 8 It is along Figure 7 A cross-sectional view taken along line D-D';

[0023] Fig.9A is a layout diagram showing a gate structure and active fins of a semiconductor device according to yet another embodiment of the inventive concept;

[0024] Fig. 9B It is along Fig.9A A cross-sectional view taken along line EE';

[0025] Fig.10 is a circuit diagram showing a semiconductor device according to yet another embodiment of the inventive concept;

[0026] Fig.11 yes Fig.10 A layout diagram of a semiconductor device;

[0027] Fig.12 is a system block diagram of a system on chip (SoC) including a semiconductor device according to some embodiments of the inventive concept;

[0028] Fig.13 is a block diagram of an electronic system including a semiconductor device according to some embodiments of the inventive concept;

[0029] Figures 14 to 16 An exemplary semiconductor system to which semiconductor devices according to some embodiments of the inventive concept may be applied is shown;

[0030] Figures 17 to 20 are diagrams illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0031] Embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. However, the inventive concept can be implemented in various forms and should not be construed as being limited to the embodiments shown. On the contrary, these embodiments are provided as examples so that this disclosure will be thorough and complete, and the inventive concept will be fully conveyed to those skilled in the art. Known processes, elements, and techniques for some embodiments of the inventive concept may not be described. Unless otherwise specified, the same reference numerals always indicate the same elements in the drawings and written descriptions, and therefore will not be repeated. In the drawings, the size and relative size of the layers and regions may be magnified for clarity.

[0032] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe multiple elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part.

[0033] For ease of description, spatially relative terms such as "under", "beneath", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to another element or feature. It should be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation shown in the figure. For example, if the device in the figure is inverted, the element described as "under other elements or features" or "below other elements or features" or "below other elements or features" will therefore be oriented as "above other elements or features". Therefore, the exemplary terms "under" and "below" can cover both "above" and "below". The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein will be interpreted accordingly. In addition, it should also be understood that when a layer is referred to as being "located between" two layers, it can be the only layer between the two layers, or one or more intermediate layers can also be present.

[0034] The terms used herein are intended only to describe specific embodiments and are not intended to limit the inventive concept. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are also intended to include plural forms. It should be understood that when the term "including" is used in this specification, it indicates the presence of listed features, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. In addition, the term "exemplary" is intended to represent an example or illustration.

[0035] It should be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it may be directly on, directly connected to, coupled to, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly adjacent to” another element or layer, there are no intervening elements or layers.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which the inventive concept belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted idealistically or overly formally.

[0037] In the following, reference will be made to Figures 1 to 4C Semiconductor devices according to embodiments of the inventive concept are described.

[0038] Figure 1 is a layout diagram showing a gate structure and active fins of a semiconductor device according to an embodiment of the inventive concept, Figure 2 It is shown Figure 1 A perspective view of one of the gate structures and one of the active fins of a semiconductor device, Figure 3 It is along Figure 1 A cross-sectional view taken along line AA' of Figure 4A It is along Figure 1 A cross-sectional view taken along line BB' of Figure 4B It is shown Figure 1 Area A1 along Figure 1 A cross-sectional view taken along line B1-B1', and Figure 4C It is shown Figure 1 Area A2 along Figure 1 The cross-sectional view is taken along the line B2-B2'. Note that Figure 1 and Figure 2 In order to more clearly illustrate the design of the gate structure, the spacers disposed on each side of the gate structure are not shown. Figure 3 , Figure 4B and Figure 4C These spacers are shown in FIG.

[0039] Reference Figures 1 to 4C , the semiconductor device 1 includes active fins F1 to F4, gate structures GS1 and GS2, and a field insulation layer 22. It should be understood that the semiconductor device may include more gate structures and active fins.

[0040] The active fins F1 to F4 may protrude from the substrate 10 , and may extend in the first direction X. As shown in FIG.

[0041] The substrate 10 may include a semiconductor material. For example, the semiconductor material may include one or more selected from Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. However, aspects of the present inventive concept are not limited thereto, and in other embodiments of the present inventive concept, for example, the substrate 10 may be an insulating substrate such as a silicon-on-insulator (SOI) substrate. When the substrate 10 is an SOI substrate, the response speed of the semiconductor device 1 may be improved.

[0042] like Figure 1 As shown, the active fins F1 to F4 may extend in, for example, a first direction X, and may be spaced apart from each other in, for example, a second direction Y.

[0043] Each of the active fins F1 to F4 may have a long side and a short side. Figure 1 , the long side direction of the active fins F1 to F4 is the first direction X, and the short side direction of the active fins F1 to F4 is the second direction Y, but aspects of the inventive concept are not limited thereto. For example, in other embodiments of the inventive concept, the long side direction of the active fins F1 to F4 may be the second direction Y, and the short side direction of the active fins F1 to F4 may be the first direction X.

[0044] The active fins F1 to F4 may be formed from corresponding portions of the substrate 10 , and may each include an epitaxial layer grown from the substrate 10 .

[0045] In some embodiments of the present inventive concept, the active fins F1 to F4 may include a semiconductor material. For example, the active fins F1 to F4 may include Si or SiGe.

[0046] In some embodiments of the present inventive concept, the active fins F1 to F4 may include the same material as that of the substrate 10. When the substrate 10 includes, for example, Si, the active fins F1 to F4 may include Si.

[0047] However, aspects of the inventive concept are not limited thereto, and the substrate 10 and the active fins F1 to F4 may include different materials.

[0048] When the substrate 10 includes, for example, Si, the active fins F1 to F4 may include a material different from Si. In this case, the active fins F1 to F4 may be formed on the substrate 10 by, for example, an epitaxial growth process.

[0049] The field insulation layer 22 may be formed on the substrate 10 , and may cover lower portions of sidewalls of the active fins F1 to F4 while exposing tops of the active fins F1 to F4 .

[0050] As shown, field insulation layer 22 may be adjacent to long sides of active fins F1 to F4 .

[0051] like Figure 2As shown, line segments LS are defined where the top surface of field insulation layer 22 contacts the respective long sides of active fins F1 to F4. Some portions of each line segment LS may be covered by gate structures GS1 and GS2, while other portions thereof are exposed, which will be described in detail later.

[0052] In some embodiments of the present inventive concepts, the field insulation layer 22 may include, for example, one selected from an oxide layer, a nitride layer, or an oxynitride layer, but aspects of the present inventive concepts are not limited thereto.

[0053] The gate structures GS1 and GS2 may extend along the second direction Y over the active fins F1 to F4 to cross the active fins F1 to F4 .

[0054] Although the gate structures GS1 and GS2 are Figure 1 2 and 3 as extending in the second direction Y, but aspects of the inventive concept are not limited thereto. In various embodiments, the gate structures GS1 and GS2 may intersect the first and second fins F1 to F4 at acute angles and / or obtuse angles.

[0055] As shown, the gate structure GS1 may be spaced apart from the gate structure GS2 in the first direction X.

[0056] The gate structure GS1 may include a gate insulating layer 112 , a work function control layer 113 , and a conductive layer 114 .

[0057] like Figure 3 As shown, the gate insulating layer 112 may be formed on the top surface of the active fin F2 , and may protrude upward from the substrate 10 along the sidewalls of the spacer 111 .

[0058] Since the gate structure GS1 according to the present embodiment is formed by, for example, a gate replacement process, the gate insulating layer 112 may have the above-described shape.

[0059] In addition, if Figure 4A As shown, the gate insulating layer 112 may extend in the second direction Y along the top surface of the field insulating layer 22 and the side surfaces and top surfaces of the active fins F2 .

[0060] The gate insulating layer 112 may include a high-k material having a higher dielectric constant than that of silicon dioxide. For example, the gate insulating layer 112 may include HfO 2 、ZrO 2 、LaO、Al 2 O 3 or 2 O 5 , but aspects of the present inventive concept are not limited thereto.

[0061] The work function control layer 113 and the conductive layer 114 may constitute a gate electrode. The work function control layer 113 may control the work function of the gate electrode, and the conductive layer 114 may fill a space formed by the work function control layer 113.

[0062] In some embodiments of the present inventive concept, the work function control layer 113 may include a first metal, and the conductive layer 114 may include a second metal different from the first metal.

[0063] The work function control layer 113 may include a portion extending upward along the top surface of the gate insulating layer 112 and the side surface of the conductive layer 114, such as Figure 3 Since the gate structure GS1 according to the present embodiment is formed by, for example, a gate replacement process, the work function control layer 113 may have the above-mentioned shape.

[0064] In addition, if Figure 4A As shown, the work function control layer 113 may extend in the second direction Y along the top of the field insulation layer 22 and the sidewalls and top of the active fin F2 .

[0065] The work function control layer 113 may include, for example, at least one of TiAl, TiAlC, TiAlN, HfSi, TiN, TaN, TiC, and TaC, and the conductive layer 114 may include, for example, W or Al, but aspects of the inventive concept are not limited thereto. In other embodiments, for example, the conductive layer 114 may include a non-metallic material such as Si or SiGe. The work function control layer 113 and the conductive layer 114 may be modified to have different configurations.

[0066] The spacer 111 may be formed along at least one side of the gate structure GS1. In some embodiments of the present inventive concept, the spacer 111 may be formed along both sides of the gate structure GS1.

[0067] In the illustrated embodiment, the spacer 111 has a columnar shape, but aspects of the inventive concept are not limited thereto. In other embodiments, the spacer 111 may be modified to have various other shapes. In the present embodiment, the spacer 111 may include, for example, a nitride layer (e.g., such as a silicon nitride layer).

[0068] However, aspects of the present inventive concept are not limited thereto, and other materials may be used to form the spacer 111. In some embodiments of the present inventive concept, the spacer 111 may include, for example, one of an oxide layer and an oxynitride layer.

[0069] Impurity epitaxial regions 42 may be formed on the active fins F1 to F4 located on opposite sides of the gate structure GS1 .

[0070] In some embodiments of the present inventive concept, the impurity epitaxial region 42 may be formed in the etched regions of the active fins F1 to F4. The impurity epitaxial region 42 may fill the corresponding recesses. The impurity epitaxial region 42 may be formed on the active fins F1 to F4 by, for example, an epitaxial growth process.

[0071] In some embodiments of the present inventive concept, the impurity epitaxial region 42 may be an elevated source region or drain region. A top surface of the impurity epitaxial region 42 may be higher than top surfaces of the active fins F1 to F4 above the substrate 10 .

[0072] The impurity epitaxial region 42 may include a semiconductor material. In some embodiments, the impurity epitaxial region 42 may include, for example, Si, but aspects of the inventive concept are not limited thereto.

[0073] When the semiconductor device 1 includes a PMOS transistor, the impurity epitaxial region 42 may include a compressive stress material. For example, the compressive stress material may include a material having a lattice constant greater than that of Si (e.g., SiGe). The compressive stress material may improve the mobility of carriers in the channel region defined in the active fins F1 to F4 by applying compressive stress to the channel region.

[0074] When the semiconductor device 1 includes an NMOS transistor, the impurity epitaxial region 42 may include the same material as that of the substrate 10 or a tensile stress material. For example, when the semiconductor device 1 includes Si, the impurity epitaxial region 42 may include a material having a lattice constant smaller than that of Si (e.g., SiC or SiP). The tensile stress material may improve the mobility of carriers in the channel region defined in the active fins F1 to F4 by applying tensile stress to the channel region.

[0075] Although not particularly shown, an interlayer dielectric layer covering the gate structure GS1 and the impurity epitaxial region 42 may be formed.

[0076] The gate structure GS2 may have a configuration substantially the same as that of the gate structure GS1. Specifically, the gate structure GS2 may include: a gate insulating layer 122, whose configuration is substantially the same as that of the gate insulating layer 112 included in the gate structure GS1; and a work function control layer 123 and a conductive layer 124, whose configuration is substantially the same as that of the work function control layer 113 and the conductive layer 114 included in the gate structure GS1.

[0077] The spacer 121 may be formed on at least one sidewall of the gate structure GS2. The configuration of the spacer 121 may be substantially the same as the configuration of the spacer 111 formed on at least one sidewall of the gate structure GS1.

[0078] In the present embodiment, each gate structure GS1 , GS2 may include a skirt S located in each region where a side of the gate structure GS1 , GS2 intersects a long side of one of the active fins F1 to F4 .

[0079] like Figure 1 and Figure 2 As shown, each skirt S is a portion of one of the gate structures GS1 and GS2 extending outward in a curved profile in the first direction X to cover a portion of each line segment LS defined by the intersection of the top surface of the field insulation layer 22 and the corresponding active fins F1 to F4 .

[0080] like Figure 2 As shown, each skirt S includes a lower portion of one side of the gate structure GS1 , GS2 , which extends outward more than the rest of the one side of the gate structure in the first direction X to contact the lower sidewall of a corresponding one of the active fins F1 to F4 .

[0081] For example, Figure 1 As shown, the first skirt S-1 extends outward from the left side surface of the gate structure GS1 in the first direction X to contact the first long side of the active fin F3, and the second skirt S-2 extends outward from the right side surface of the gate structure GS1 in the first direction X to also contact the first long side of the active fin F3.

[0082] In addition, if Figure 1 As shown, the third skirt S-3 extends outward from the left side surface of the gate structure GS1 in the first direction X to contact the first long side of the active fin F2, and the fourth skirt S-4 extends outward from the right side surface of the gate structure GS1 in the first direction X to contact the first long side of the active fin F2.

[0083] In addition, if Figure 1 As shown, the fifth skirt S-5 extends outward from the left side surface of the gate structure GS2 in the first direction X to contact the first long side of the active fin F3, and the sixth skirt S-6 extends outward from the right side surface of the gate structure GS2 in the first direction X to contact the first long side of the active fin F3.

[0084] In addition, if Figure 1 As shown, the seventh skirt S-7 extends outwardly from the left side surface of the gate structure GS2 in the first direction X to contact the first long side of the active fin F2, and the eighth skirt S-8 extends outwardly from the right side surface of the gate structure GS2 in the first direction X to contact the first long side of the active fin F2. The second skirt S-2 and the fifth skirt S-5 may be spaced apart from each other so that they are not connected to each other. Similarly, the fourth skirt S-4 and the seventh skirt S-7 may be spaced apart from each other so that they are not connected to each other.

[0085] Since the gate structure GS1 includes the skirt S discussed above, it may have the first and second regions A1 and A2 having different widths.

[0086] Specifically, the width W1 of the first region A1 of the gate structure GS1 adjacent to the active fins F1 to F4 may be greater than the width W2 of the second region A2 of the gate structure GS1 spaced apart from the active fins F1 to F4 (i.e., between two adjacent active fins among the active fins F1 to F4), and may be greater than the width W3 of the third region A3 of the gate structure GS1 on top of the active fins F1 to F4. The second width W2 may be equal to the third width W3.

[0087] Similarly, since the gate structure GS2 includes the skirt S discussed above, it may have a first region A1, a second region A2, and a third region A3. The width of each first region may be different from the width of the second region A2 and the third region A3. The second region A2 and the third region A3 may have the same width.

[0088] Specifically, a width W1 of a first region A1 of the gate structure GS2 adjacent to the active fins F1 to F4 may be greater than a width W2 of a second region A2 of the gate structure GS2 spaced apart from the active fins F1 to F4, and may be greater than a width W3 of a third region A3 of the gate structure GS2 at the top of the active fins F1 to F4.

[0089] In addition, since the gate structure GS2 includes the skirt S discussed above, Figure 4B As shown, the gate structure GS2 may extend below the lower portion of the spacer 121 in the first region A1, but not below the lower portion of the spacer 121 in the second region A2. Figure 4C shown.

[0090] Since the gate structure GS2 includes the skirt S discussed above, the width W1 of the first area A1 of the gate structure GS2 may be greater than the widths W2 and W3 of the second and third areas A2 and A3 of the gate structure GS2, respectively.

[0091] When the widths of the gate structures GS1 , GS2 are larger in a region adjacent to the active fins F1 to F4 (eg, the first region A1 ), the driving capability of the transistor may be improved, and thus, the operating performance of the semiconductor device may be improved.

[0092] Figure 5 is a layout diagram illustrating a gate structure and active fins of a semiconductor device 2 according to another embodiment of the inventive concept. Figure 6 It is along Figure 5 The following description will focus on the differences between this embodiment and the previously described embodiments.

[0093] Reference Figure 5 and Figure 6 The semiconductor device 2 includes active fins F5 and F6 , a gate structure GS3 , a dummy gate structure DGS1 , a field insulation layer 22 and a device isolation layer 24 .

[0094] The active fins F5 and F6 may protrude from the substrate 10 .

[0095] like Figure 5 and Figure 6 As shown, the active fins F5 and F6 may extend in, for example, a first direction X, and may be spaced apart from each other in a second direction Y. Each of the active fins F5 and F6 may have a long side and a short side.

[0096] The field insulating layer 22 may be formed on the substrate 10 and may cover lower portions of long sides of the active fins F5 and F6 while exposing top portions of the active fins F5 and F6. Figure 5 and Figure 6 As shown, field insulation layer 22 may be adjacent to long sides of active fins F5 and F6 .

[0097] Although not specifically shown, the line segment LS may be defined at a position where the top surface of the field insulating layer 22 contacts the long sides of the active fins F5 and F6, as shown in FIG. Figure 2 Some portions of the line segments LS may be covered by the gate structure GS3 and the dummy gate structure DGS1, while other portions of the line segments LS may be exposed.

[0098] The gate structure GS3 may extend in the second direction Y to cross the active fins F5 and F6 .

[0099] The gate structure GS3 can be configured with Figure 1 The configuration of the gate structure GS1 shown is substantially the same. Specifically, the configuration of the gate insulating layer 142 included in the gate structure GS3 may be substantially the same as the configuration of the gate insulating layer 112 included in the gate structure GS1, and the configuration of the work function control layer 143 and the conductive layer 144 included in the gate structure GS3 may be substantially the same as the configuration of the work function control layer 113 and the conductive layer 114 included in the gate structure GS1.

[0100] The configuration of the spacer 141 located on at least one side of the gate structure GS3 may be substantially the same as the configuration of the spacer 111 formed on at least one side of the gate structure GS1 .

[0101] Impurity epitaxial regions 42 may be formed on the active fins F5 and F6 located at opposite sides of the gate structure GS3 .

[0102] The device isolation layer 24 may be formed from at least one side (eg, Figure 52 and 3. The device isolation layer 24 may extend along the short sides of the active fins F5 and F6 in the second direction Y. The device isolation layer 24 and the field insulation layer 22 may intersect each other in a region where the long sides and the short sides of the active fins F5 and F6 intersect each other.

[0103] The dummy gate structure DGS1 may be spaced apart from the gate structure GS3 in the first direction X, and may extend in the second direction Y. The dummy gate structure DGS1 may overlap the active fins F5 and F6 and the device isolation layer 24 to then extend in the second direction Y. That is, as shown, ends of the active fins F5 and F6 may be located below the dummy gate structure DGS1.

[0104] The configuration of the dummy gate structure DGS1 may be substantially the same as the configuration of the gate structure GS3. Specifically, the configuration of the gate insulating layer 132 included in the dummy gate structure DGS1 may be substantially the same as the configuration of the gate insulating layer 142 included in the gate structure GS3, and the configuration of the work function control layer 133 and the conductive layer 134 included in the dummy gate structure DGS1 may be substantially the same as the configuration of the work function control layer 143 and the conductive layer 144 included in the gate structure GS3.

[0105] The configuration of the spacer 131 formed on at least one side of the dummy gate structure DGS1 may be substantially the same as the configuration of the spacer 141 formed on at least one side of the gate structure GS3 .

[0106] The impurity epitaxial layer 42 may be formed on the active fins F5 and F6 located at one side of the dummy gate structure DGS1 .

[0107] In the present embodiment, each gate structure GS3 , DGS1 may include a skirt S located in each region where one side of the gate structure DGS1 , GS3 intersects with a long side of one of the active fins F5 and F6 .

[0108] The skirt S may extend outward from the dummy gate structures DGS1 and GS3 in the first direction X to cover portions of each line segment LS defined by intersections of the top surface of the field insulation layer 22 and the active fins F5 and F6 while exposing other portions of the line segment LS.

[0109] For example, Figure 5As shown, the ninth skirt S-9 extends outward from the right side surface of the dummy gate structure DGS1 in the first direction X to contact the first long side of the active fin F5, the tenth skirt S-10 extends outward from the left side surface of the gate structure GS3 in the first direction X to contact the first long side of the active fin F5, and the eleventh skirt S-11 extends outward from the right side surface of the gate structure GS3 in the first direction X to contact the first long side of the active fin F5.

[0110] The ninth skirt S-9 extending outward from the right side surface of the dummy gate structure DGS1 in the first direction X to contact the first long side of the active fin F5 and the tenth skirt S-10 extending outward from the left side surface of the gate structure GS3 in the first direction X to contact the first long side of the active fin F5 may not be connected to each other but may be separated from each other as shown.

[0111] As shown, since the left side surface of the dummy gate structure DGS1 does not cross the active fins F5 and F6 , any skirt S may not be formed on the left side surface of the dummy gate structure DGS1 .

[0112] Figure 7 is a layout diagram illustrating a gate structure and active fins of a semiconductor device according to yet another embodiment of the inventive concept. Figure 8 It is along Figure 7 The following description will focus on the differences between this embodiment and the previously described embodiments.

[0113] Reference Figure 7 and Figure 8 , the semiconductor device 3 according to the present embodiment is different from the semiconductor device 2 in that it has a different dummy gate structure configuration.

[0114] Specifically, while the dummy gate structure DGS1 of the semiconductor device 2 includes the gate insulating layer 132 , the work function control layer 133 , and the conductive layer 134 , the dummy gate structure DGS2 of the semiconductor device 3 may include only a conductive layer including, for example, Si or poly-Si.

[0115] like Figure 8 As shown, the spacer 151 may be formed on at least one side of the dummy gate structure DGS2 .

[0116] Fig.9A is a layout diagram illustrating a gate structure and active fins of a semiconductor device according to yet another embodiment of the inventive concept. Fig. 9B It is along Fig.9A The following description will focus on the differences between this embodiment and the previously described embodiments.

[0117] Reference Fig.9A and Fig. 9B The semiconductor device 4 according to the present embodiment is different from the semiconductor device 2 according to the previous embodiment in the configuration of the device isolation layer.

[0118] Specifically, unlike the situation in which the top surface of the device isolation layer 24 and the top surfaces of the active fins F5 and the active fins F6 are located at substantially the same height in the semiconductor device 2 according to the previous embodiment, in the semiconductor device 4 according to the present embodiment, the top surface of the device isolation layer 26 can be lower than the top surfaces of the active fins F5 and the active fins F6.

[0119] Therefore, if Fig.9A and Fig. 9B As shown, a portion of the dummy gate structure DGS3 may extend below the top surfaces of the active fins F5 and F6 , and other portions of the dummy gate structure DGS3 may be higher than the top surfaces of the active fins F5 and F6 .

[0120] In addition to the difference in configuration, the dummy gate structure DGS3 can be used with Figure 5 and Figure 6 The dummy gate structures DGS1 of the illustrated semiconductor devices 2 have substantially the same configuration.

[0121] That is, the configuration of the gate insulation layer 162 included in the dummy gate structure DGS3 may be substantially the same as the configuration of the gate insulation layer 132 included in the dummy gate structure DGS1, and the configuration of the work function control layer 163 and the conductive layer 164 included in the dummy gate structure DGS3 may be substantially the same as the configuration of the work function control layer 133 and the conductive layer 134 included in the dummy gate structure DGS1.

[0122] The configuration of the spacer 161 formed on at least one side of the dummy gate structure DGS3 may be substantially the same as the configuration of the spacer 131 formed on at least one side of the dummy gate structure DGS1 .

[0123] Fig.10 is a circuit diagram illustrating a semiconductor device according to still another embodiment of the inventive concept. Fig.11 yes Fig.10 A layout diagram of a semiconductor device.

[0124] Reference Fig.10, the semiconductor device may include: a pair of inverters INV1 and INV2, which are electrically connected in parallel between a power node VCC and a ground node VSS; and a first transfer transistor PS1 and a second transfer transistor PS2, which are connected to respective output nodes of the inverters INV1 and INV2. The first transfer transistor PS1 and the second transfer transistor PS2 may be connected to a bit line BL and a complementary bit line BLb, respectively. The gates of the first transfer transistor PS1 and the second transfer transistor PS2 may be connected to a word line WL.

[0125] The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 electrically connected to each other in series, and the second inverter INV2 includes a second pull-up transistor PU2 and a second pull-down transistor PD2 electrically connected to each other in series. The first pull-up transistor PU1 and the second pull-up transistor PU2 may be PFET transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NFET transistors.

[0126] In addition, in order to constitute a latch circuit, the input node of the first inverter INV1 is connected to the output node of the second inverter INV2, and the input node of the second inverter INV2 is connected to the output node of the first inverter INV1.

[0127] Reference Fig.10 and Fig.11 The first active fin 210, the second active fin 220, the third active fin 230, and the fourth active fin 240 that are spaced apart from each other may be arranged in one direction (eg, in Fig.11 Here, the lengths of the second active fin 220 and the third active fin 230 may be shorter than the lengths of the first active fin 210 and the fourth active fin 240 .

[0128] In addition, the first gate electrode 251, the second gate electrode 252, the third gate electrode 253, and the fourth gate electrode 254 are formed in another direction (for example, in Fig.11 Each of the first to fourth gate electrodes 251 to 254 may cross one or more of the first to fourth active fins 210 to 240 .

[0129] Specifically, the first gate electrode 251 completely crosses the first active fin 210 and the second active fin 220, and partially overlaps the terminal of the third active fin 230. The third gate electrode 253 completely crosses the fourth active fin 240 and the third active fin 230, and partially overlaps the terminal of the second active fin 220. The second gate electrode 252 and the fourth gate electrode 254 are formed to cross the first active fin 210 and the fourth active fin 240, respectively.

[0130] As shown, the first pull-up transistor PU1 is defined near the intersection of the first gate electrode 251 and the second active fin 220, the first pull-down transistor PD1 is defined near the intersection of the first gate electrode 251 and the first active fin 210, and the first pass transistor PS1 is defined near the intersection of the second gate electrode 252 and the first active fin 210. The second pull-up transistor PU2 is defined near the intersection of the third gate electrode 253 and the third active fin 230, the second pull-down transistor PD2 is defined near the intersection of the third gate electrode 253 and the fourth active fin 240, and the second pass transistor PS2 is defined near the intersection of the fourth gate electrode 254 and the fourth active fin 240.

[0131] Although not specifically shown, sources and drains may be formed on opposite sides of portions where the first to fourth gate electrodes 251 to 254 respectively cross the first to fourth active fins ( 210 , 220 , 230 , and 240 ), and a plurality of contacts 250 may be formed.

[0132] In addition, the first shared contact 261 may connect the second active fin 220, the third gate electrode 253, and the wiring 271 to one another. The second shared contact 262 may connect the third active fin 230, the first gate electrode 251, and the wiring 272 to one another.

[0133] At least one of the semiconductor devices according to some embodiments of the inventive concept may be employed as the illustrated layout of an SRAM.

[0134] Fig.12 is a block diagram of a system of a system on chip (SoC) including a semiconductor device according to an embodiment of the inventive concept.

[0135] Reference Fig.12 , the SoC system 1000 may include an application processor 1001 and a DRAM 1060 .

[0136] The application processor 1001 may include a central processing unit 1010 , a multimedia system 1020 , a bus 1030 , a memory system 1040 , and a peripheral circuit 1050 .

[0137] The central processing unit 1010 may perform algorithmic operations required to operate the SoC system 1000. In some embodiments of the inventive concept, the central processing unit 1010 may be configured in a multi-core environment including a plurality of cores.

[0138] The multimedia system 1020 may be used to perform various multimedia functions in the SoC system 1000. The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, and a post-processor.

[0139] The bus 1030 may be used to perform data communication between the central processing unit 1010, the multimedia system 1020, the memory system 1040, and the peripheral circuit 1050. In some embodiments of the inventive concept, the bus 1030 may have a multi-layer structure. Examples of the bus 1030 may include a multi-layer advanced high-performance bus (AHB) or a multi-layer advanced eXtensible Interface (AXI), but aspects of the inventive concept are not limited thereto.

[0140] The memory system 1040 may provide an environment required for high-speed operation by connecting the AP 1001 to an external memory (e.g., DRAM 1060). In some embodiments of the inventive concept, the memory system 1040 may include a separate controller (e.g., DRAM controller) for controlling the external memory (e.g., DRAM 1060).

[0141] The peripheral circuit 1050 may provide an environment required for smoothly connecting the SoC system 1000 to an external device (eg, a main board). Therefore, the peripheral circuit 1050 may include various interfaces capable of compatibly using an external device connected to the SoC system 1000.

[0142] The DRAM 1060 may be used as a working memory of the AP 1001. In some embodiments of the inventive concept, as shown, the DRAM 1060 may be disposed outside the AP 1001. Specifically, the DRAM 1060 may be packaged together with the AP 1001 in a package-on-package (PoP) form.

[0143] At least one component of the SoC system 1000 may employ one of the above-described semiconductor devices according to an embodiment of the inventive concept.

[0144] Fig.13 is a block diagram of an electronic system including a semiconductor device according to an embodiment of the inventive concept.

[0145] Reference Fig.13 , the electronic system 1100 may include a controller 1110, an input / output device (I / O) 1120, a memory device 1130, an interface 1140, and a bus 1150. The controller 1110, the I / O 1120, the memory device 1130, and / or the interface 1140 may be connected to each other through the bus 1150. The bus 1150 corresponds to a path through which data moves.

[0146] The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and a logic element capable of having functions similar to those of a microprocessor, a digital signal processor, and a microcontroller. The I / O device 1120 may include a keypad, a keyboard, a display device, etc. The memory 1130 may store data and / or commands. The interface 1140 may perform a function of sending data to a communication network or receiving data from a communication network. The interface 1140 may be wired or wireless. For example, the interface 1140 may include an antenna or a wired / wireless transceiver, etc.

[0147] Although not shown, the electronic system 1100 may further include a high-speed DRAM and / or SRAM as a working memory for improving the operation of the controller 1110. A semiconductor device according to an embodiment of the inventive concept may be employed as a working memory.

[0148] In addition, the semiconductor device according to the embodiment of the inventive concept may be provided in the memory device 1130 , or may be provided in some components of the controller 1110 or the I / O 1120 .

[0149] The electronic system 1100 may be applied to a personal digital assistant (PDA), a portable computer, an internet tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any type of electronic device capable of transmitting and / or receiving information in a wireless environment.

[0150] Figures 14 to 16 An exemplary semiconductor system to which semiconductor devices according to some embodiments of the inventive concept may be applied is shown.

[0151] Fig.14 An example is shown in which a semiconductor device according to an embodiment of the inventive concept is applied to a tablet PC (1200), Fig.15 An example in which a semiconductor device according to an embodiment of the inventive concept is applied to a notebook computer (1300) is shown, and Fig.16 An example is shown in which the semiconductor device according to the embodiments of the inventive concept is applied to a smart phone (1400). At least one of the semiconductor devices according to some embodiments of the inventive concept may be employed for a tablet PC 1200, a notebook computer 1300, a smart phone 1400, and the like.

[0152] Additionally, the semiconductor device according to some embodiments of the inventive concept may also be applied to other integrated circuit devices not shown herein.

[0153] That is, in the above-described embodiments, only the tablet PC 1200 , the notebook computer 1300 , and the smart phone 1400 are exemplified as semiconductor devices including embodiments of the inventive concept, but aspects of the inventive concept are not limited thereto.

[0154] In some embodiments of the present invention, the semiconductor device may be implemented as a computer, an ultra mobile personal computer (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, an internet tablet, a wireless phone, a mobile phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3-dimensional (3D) television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, etc.

[0155] Figures 17 to 20 are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0156] Reference Fig.17 , the active fin F2 is formed to protrude upward from the substrate 10. The active fin F2 may extend in the first direction X.

[0157] Specifically, in some embodiments of the present inventive concept, the active fin F2 may be formed by etching the substrate 10. In other embodiments, the active fin F2 may be formed by forming an epitaxial layer including a semiconductor material on the substrate 10 and patterning the epitaxial layer.

[0158] Next, a field insulating layer 22 covering the bottom of the active fin F2 is formed on the substrate 10. Then, a conductive layer 72 is formed on the field insulating layer 22 and the active fin F2. Here, the conductive layer 72 may include, for example, polycrystalline silicon (poly-Si).

[0159] Next, refer to Fig.18 The conductive layer 72 is patterned so as to intersect the active fins F2. The conductive layer 72 may be patterned to form a skirt S in a region where the conductive layer 72 and the active fins F2 are adjacent to each other.

[0160] Reference Fig.19 , spacers 74 may be formed on opposite sides of the conductive layer 72. The spacers 74 may include, for example, an insulating material such as, for example, a silicon nitride layer or a silicon oxynitride layer.

[0161] Reference Fig. 20 , remove the conductive layer ( Fig.19 72). As a conductive layer ( Fig.19 As a result of 72), a skirt hole SH can be formed below the spacer 74.

[0162] Then, a gate insulating layer (eg, Figure 3 112), a work function control layer (eg, Figure 3 113) and a conductive layer (eg, Figure 3 The gate structure GS1 of 114) can be formed, and the gate structures GS1 to GS3 of the semiconductor devices 1 to 4 can be formed in substantially the same manner.

[0163] In addition, the device isolation layer (e.g. Figure 6 24. Fig. 9B 26) may be formed on one side of the active fin F2, and the dummy gate structures DGS1 and DGS3 of the semiconductor device 2 and the semiconductor device 4 may be formed in substantially the same manner.

[0164] Ultimately, if it is allowed to remain and not be removed Fig.19 The conductive layer 72 shown can also form the dummy gate structure DGS2 of the semiconductor device 3 .

[0165] Although the present invention has been specifically shown and described with reference to the exemplary embodiments of the present invention, it should be understood by those skilled in the art that various changes in form and detail may be made thereto without departing from the spirit and scope of the present invention as defined by the claims. Therefore, it is expected that the present embodiment is to be regarded as illustrative and not restrictive in all respects, and reference should be made to the claims rather than the above description to indicate the scope of the present invention.

Claims

1. A semiconductor device, comprising: an active fin protruding from the substrate and extending in a first direction; as well as a dummy gate structure extending in a second direction intersecting the first direction to intersect the active fin, the active fin having an end portion located below the dummy gate structure, The dummy gate structure includes a first skirt, in which a first side of the dummy gate structure extends outward in the first direction to contact a side surface of the active fin, The outer surface of the first skirt has a concave profile in a vertical plane, so that the width of the first skirt in the first direction continuously decreases as it moves away from the substrate in the vertical plane.

2. The semiconductor device according to claim 1, wherein The outer surface of the first skirt has a concave profile in a horizontal plane.

3. The semiconductor device according to claim 1 , further comprising a gate structure extending in the second direction, the gate structure intersecting the active fin, in, The gate structure includes a second skirt and a third skirt, wherein in the second skirt, a first side of the gate structure extends outward in the first direction to contact a side surface of the active fin, and in the third skirt, a second side of the gate structure opposite to the first side of the gate structure extends outward in the first direction to contact a side surface of the active fin.

4. The semiconductor device according to claim 3, wherein: A second side of the dummy gate structure opposite to the first side of the dummy gate structure is a flat side surface that does not include any skirt.

5. The semiconductor device according to claim 3, wherein: Each of the dummy gate structure and the gate structure includes: a gate insulating layer; a work function control layer on the gate insulating layer and including a first metal; and a conductive layer on the work function control layer and including a second metal different from the first metal.

6. The semiconductor device according to claim 3, in, The active fin has a first long side and a second long side opposite to each other in the second direction, wherein the first skirt portion contacts the surface of the first long side, The dummy gate structure includes a fourth skirt portion, in which a first side of the dummy gate structure extends outward in the first direction to contact a surface of the second long side.

7. The semiconductor device according to claim 6, wherein: The gate structure includes a fifth skirt portion in which the second side of the gate structure extends outward in the first direction to contact a surface of the second long side.

8. The semiconductor device according to claim 1 , further comprising a device isolation layer extending in the second direction and contacting an end portion of the active fin, in, The dummy gate structure is located on the active fin and the device isolation layer.

9. A semiconductor device comprising: a first active fin protruding from the substrate and extending in a first direction; a second active fin protruding from the substrate, extending in the first direction, and spaced apart from the first active fin in a second direction intersecting the first direction; a gate structure extending in the second direction to cross the first active fin and the second active fin; as well as a dummy gate structure extending in the second direction to intersect the first active fin and the second active fin, the first active fin and the second active fin having respective ends below the dummy gate structure, Wherein, in a region between the first active fin and the second active fin, a first distance between the gate structure and the dummy gate structure gradually increases to a maximum value along a direction from the first active fin to the second active fin and then gradually decreases, and Wherein, at a position intersecting with the first active fin, a second distance between the gate structure and the dummy gate structure gradually increases with increasing height, and The dummy gate structure has a portion extending outward in the first direction to contact a side surface of the first active fin, an outer surface of the portion having a concave profile in a vertical plane so that a width of the portion in the first direction continuously decreases as it moves away from the substrate in the vertical plane.

10. The semiconductor device according to claim 9, further comprising a device isolation layer extending in the second direction and contacting respective ends of the first active fin and the second active fin, in, The gate structure and the dummy gate structure are located on the first active fin, the second active fin, and the device isolation layer.

11. The semiconductor device according to claim 9, in, The dummy gate structure has a first side and a second side, wherein the first side faces the gate structure in the first direction, and the second side faces away from the first side in the first direction, Wherein, the first side has a concave profile in a horizontal plane and the second side has a flat profile in the horizontal plane.

12. The semiconductor device according to claim 11, wherein The gate structure has a third side and a fourth side, wherein the third side faces the dummy gate structure in the first direction, and the fourth side faces away from the third side in the first direction, Wherein, the third side and the fourth side have respective concave profiles in the horizontal plane.

13. The semiconductor device according to claim 9, wherein: The width of the dummy gate structure is smallest along the region.

14. The semiconductor device according to claim 13, wherein: In a region between the first active fin and the second active fin, a width of the dummy gate structure gradually decreases to a minimum value along a direction from the first active fin to the second active fin and then gradually increases.

15. The semiconductor device according to claim 9, wherein: The width of the gate structure is smallest in a region where the width has a maximum value along the first distance.

16. The semiconductor device according to claim 15, in, In a region between the first active fin and the second active fin, a width of the gate structure gradually decreases to a minimum value along a direction from the first active fin to the second active fin and then gradually increases.

17. A semiconductor device comprising: an active fin protruding from the substrate; an insulating layer in contact with a side surface of the active fin; as well as a gate structure on the active fin and the insulating layer, the gate structure having a first side and a second side opposite the first side, wherein the first side of the gate structure comprises a skirt extending outwardly along one of the side surfaces of the active fin, wherein the second side of the gate structure does not include any skirt portion, and The outer surface of the skirt has a concave profile in a vertical plane, so that the width of the skirt decreases continuously with increasing height.

18. The semiconductor device according to claim 17, wherein: The outer surface of the skirt has a concave profile in a horizontal plane.

19. The semiconductor device according to claim 17, wherein: A width of the first side of the gate structure is greater than a width of the second side of the gate structure.

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