Balanced multi-level dc-dc converter device

Abstract

A balanced multi-level DC-DC converter apparatus is disclosed, comprising: a capacitor string comprising at least two capacitors coupled in series; a switching circuit comprising a first port having first and second terminals connected to first and second end nodes of the capacitor string, respectively, and a second port configured to be coupled to an energy storage device. The switching circuit is configured to selectively connect the first and second terminals of the second port to the first and second end nodes and at least one interconnection node of the capacitor string. The apparatus further comprises: at least one inductor configured to be coupled in series with the second port of the switching circuit and the energy storage device; and a charging switch configured to directly connect the first terminal of the second port to the second terminal of the second port. The apparatus further comprises a control circuit for charging the inductor from the energy storage device and selectively charging the capacitor from the inductor.

Description

Background Technology

[0001] The subject matter of this invention relates to power equipment and methods, and more specifically, to DC-DC converter devices.

[0002] Multilevel converters are used in a variety of applications, such as motor drives, photovoltaic (PV) inverters, uninterruptible power supply (UPS) systems, and other power conversion applications. Multilevel converters can offer several advantages, such as improved output quality of the transistors or other switching devices used to implement the converter, reduced electromagnetic interference (EMI), and lower rated voltage.

[0003] In many systems, such as UPS systems, multilevel inverters used to generate AC output can be connected to DC energy storage devices such as batteries, supercapacitor banks, and fuel cells via DC-DC converters. For applications with higher load density, multiple multilevel inverters can be connected in parallel to meet load demands. In such parallel applications, it is generally desirable to regulate the DC voltages on the DC links connected to the DC-DC converters so that they are substantially uniform to reduce or eliminate circulating current. A common technique for balancing DC links is to use balancing circuits that balance the voltages on the individual levels of the inverter. Examples of various types of balancing circuits are described in U.S. Patent 6,819,576 to Johnson, Jr., U.S. Patent Application Publication 2018 / 0275699 to Oughton, Jr., and U.S. Patent Application Publication 2018 / 01278074 to Oughton, Jr. Summary of the Invention

[0004] Some embodiments of the present invention provide an apparatus comprising: a capacitor string including at least two capacitors coupled in series; and a switching circuit including a first port and a second port, the first port having a first terminal and a second terminal respectively connected to a first node and a second end node of the capacitor string, the second port being configured to be coupled to an energy storage device. The switching circuit is configured to selectively connect the first terminal and the second terminal of the second port to the first end node, the second end node, and at least one interconnecting node of the capacitor string. The apparatus further includes: at least one inductor configured to be coupled in series with the second port of the switching circuit and the energy storage device; and a charging switch configured to directly connect the first terminal of the second port to the second terminal of the second port. The apparatus further includes a control circuit configured to close the charging switch in a first interval to charge the inductor from the energy storage device and to selectively close at least two switches of the switching circuit in a second interval to selectively charge the capacitors in the capacitor string from the at least one inductor being charged.

[0005] In some embodiments, the switching circuit may include: at least one first switch configured to connect a first terminal of the first port to a first terminal of the second port; at least one second switch configured to connect a second terminal of the first port to a second terminal of the second port; and at least two third switches configured to connect the first terminal and the second terminal of the second port to the at least one interconnecting node. The control circuit may be configured to selectively close the at least two third switches during the second interval to selectively charge the capacitors in the capacitor string from the at least one charged inductor.

[0006] In some embodiments, the at least two third switches may include corresponding switches configured to connect the first terminal and a corresponding terminal of the second terminal of the second port to a midpoint interconnect node of the capacitor string. In other embodiments, the at least two third switches may include: a first plurality of switches configured to connect the first terminal of the second port to a first set of interconnect nodes of the capacitor string; and a second plurality of switches configured to connect the second terminal of the second port to a second set of interconnect nodes of the capacitor string. The first set of interconnect nodes and the second set of interconnect nodes may each include a midpoint interconnect node.

[0007] According to another aspect, the control circuit may be configured to sense at least one voltage across at least one capacitor in the capacitor string and selectively close the at least two third switches in the second interval in response to the sensed at least one voltage. For example, the control circuit may be configured to selectively close the at least two third switches in the second interval in response to the sensed at least one voltage to balance the voltages across the capacitors in the capacitor string.

[0008] According to another aspect, the at least two third switches may include a first transistor having a first rated voltage, and wherein the charging switch includes a second transistor having a second rated voltage greater than the first rated voltage. The device may also include an inverter coupled to the first port of the switching circuit.

[0009] In another embodiment of the subject matter of the invention, the device includes a capacitor string comprising at least two capacitors coupled in series. The device also includes a switching circuit comprising a first port and a second port, the first port having a first terminal and a second terminal connected to respective first and second end nodes of the capacitor string, the second port being configured to be coupled to an energy storage device. The switching circuit further includes: at least one first switch configured to connect the first terminal of the first port to the first terminal of the second port; at least one second switch configured to connect the second terminal of the first port to the second terminal of the second port; at least one third switch configured to connect the first terminal of the second port to a first interconnect node of the capacitor string; at least one fourth switch configured to connect the second terminal of the second port to a second interconnect node of the capacitor string; at least one fifth switch configured to connect the first terminal of the second port to a midpoint interconnect node of the capacitor string; and at least one sixth switch configured to connect the second terminal of the second port to the midpoint interconnect node. The device further includes: at least one inductor configured to be coupled in series with the second port of the switching circuit and the energy storage device; and a control circuit configured to cause the switching circuit to charge the at least one inductor in a first interval and to selectively close the at least one third switch, the at least one fourth switch, the at least one fifth switch and the at least one sixth switch in a second interval to selectively charge the capacitors in the capacitor string from the at least one inductor being charged.

[0010] In some embodiments, the control circuit may be configured to close the at least one third switch and the at least one fourth switch to charge the internal capacitors in the capacitor string, close the at least one fifth switch to charge the first external capacitor in the capacitor string, and close the at least one sixth switch to charge the second external capacitor in the capacitor string. In some embodiments, the control circuit may be configured to close the at least one fifth switch and the at least one sixth switch during the first interval to charge the at least one inductor. In another embodiment, the switching circuit may further include at least one seventh switch, which is configured to directly connect the first terminal of the second port to the second terminal of the second port, and the control circuit may be configured to close the at least one seventh switch during the first interval to charge the at least one inductor.

[0011] A further embodiment provides an apparatus comprising: a capacitor string including at least two capacitors coupled in series; and a switching circuit including a first port and a second port, the first port having a first terminal and a second terminal connected to respective first and second end nodes of the capacitor string, the second port being configured to be coupled to an energy storage device. The switching circuit may include: at least one first switch configured to connect the first terminal of the first port to the first terminal of the second port; at least one second switch configured to connect the second terminal of the first port to the second terminal of the second port; at least one third switch configured to connect the first terminal of the second port to a first interconnect node of the capacitor string; at least one fourth switch configured to connect the second terminal of the second port to a second interconnect node of the capacitor string; at least one fifth switch configured to connect the at least one third switch to a midpoint interconnect node of the capacitor string; and at least one sixth switch configured to connect the at least one fourth switch to the midpoint interconnect node. The device further includes at least one inductor configured to be coupled in series with the second port of the switching circuit and the energy storage device; and a control circuit configured to cause the switching circuit to charge the inductor in a first interval and selectively close the at least one third switch, the at least one fourth switch, the at least one fifth switch and the at least one sixth switch in a second interval to selectively charge the capacitors in the capacitor string from the at least one charged inductor.

[0012] In some embodiments, the at least one third switch may be configured to connect the first terminal of the second port to the first interconnect node via a first diode, and the at least one fourth switch may be configured to connect the second terminal of the second port to the second interconnect node via a second diode. The control circuit may be configured to close the at least one third switch, the at least one fourth switch, the at least one fifth switch, and the at least one sixth switch during the first interval to charge the at least one inductor. In another embodiment, the switching circuit may include at least one seventh switch configured to directly connect the first terminal of the second port to the second terminal of the second port, and the control circuit may be configured to close the at least one seventh switch during the first interval to charge the at least one inductor. Attached Figure Description

[0013] Figures 1-3 A 3-level DC-DC converter device and its operation are shown according to some embodiments.

[0014] Figures 4-6 A 5-level DC-DC converter device and its operation according to an alternative embodiment are shown.

[0015] Figures 7-9 A 5-level DC-DC converter device and its operation according to an additional embodiment are shown.

[0016] Figures 10-12 A 5-level DC-DC converter device and its operation according to an alternative embodiment are shown.

[0017] Figures 13-15 A 5-level DC-DC converter device and its operation according to a further embodiment are shown.

[0018] Figures 16-18 A 5-level DC-DC converter according to some implementation schemes is shown.

[0019] Figure 19 An uninterruptible power supply (UPS) system according to some implementation schemes is shown. Detailed Implementation

[0020] Specific exemplary embodiments of the subject matter of the invention will now be described with reference to the accompanying drawings. However, the subject matter of the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of the subject matter to those skilled in the art. In the drawings, similar reference numerals denote similar items. It should be understood that when an item is referred to as “connected” or “coupled” to another item, the item may be directly connected to or directly coupled to the other item, or there may be an intermediary item. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the subject matter of the invention. Unless otherwise expressly stated, the singular forms “a,” “an,” and “the” are intended to include the plural forms as used herein. It should also be understood that the terms “comprising” and / or “including” as used in this specification indicate the presence of the stated features, integers, steps, operations, items, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, items, components, and / or combinations thereof.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of this invention pertains. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant field, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0023] Some embodiments of the subject matter of this invention can provide improved DC link balancing in applications using multilevel inverters, such as UPS applications. In some embodiments, improved link balancing can be provided by a multilevel DC-DC converter that includes switching circuitry operable to provide selective charging of DC link capacitors for the purpose of balancing DC link voltages.

[0024] Figure 1 A three-level DC-DC converter device 100 according to some embodiments is shown. Device 100 includes a series connection of a first capacitor C1 and a second capacitor C2. A switching circuit 110 has a first port 111 with a first terminal 111a and a second terminal 111b coupled to corresponding first end nodes N1 and N3 of the capacitor strings C1 and C2. A second port 112 of the switching circuit 110 is configured to be coupled in series with a first inductor L1, a second inductor L2, and an energy storage device shown herein as a battery 10.

[0025] The switching circuit 110 includes a plurality of switches, shown herein as first to seventh insulated-gate bipolar transistors (IGBTs) Q1-Q5 with associated first to seventh parallel-connected diodes D1-D5. Transistors Q1-Q5 are configured to selectively couple the first terminal 112a and the second terminal 112b of the second port 112 to the end nodes N1, N3 and the midpoint interconnect node N2 of the capacitor strings C1, C2. Specifically, the first transistor Q1 is configured to connect the first terminal 111a of the first port 111 to the first terminal 112a of the second port 112. The second transistor Q2 is configured to connect the first terminal 112a of the second port 112 to the second terminal 112b of the second port 112. The third transistor Q3 is configured to connect the second terminal 111b of the first port 111 to the second terminal 112b of the second port 112. The fourth transistor Q4 is configured to connect the first terminal 112a of the second port 112 to the midpoint interconnect node N2. The fifth transistor Q5 is configured to connect the second terminal 112b of the second port 112 to the midpoint interconnect node N2. The control circuit 120 controls transistors Q1-Q5 in response to the voltages v1 and v2 across the respective capacitors in capacitors C1 and C2.

[0026] Figure 2 and Figure 3 The following are illustrated according to some implementation schemes. Figure 1 The operation of the converter device 100. In boost mode, device 110 transfers power from battery 10 by charging inductors L1 and L2 and selectively discharging inductors L1 and L2 into first capacitor C1 and second capacitor C2 to regulate capacitor voltages v1 and v2. In a first interval, control circuit 120 turns on (closes) second transistor Q2, while first transistor Q1, third transistor Q3, fourth transistor Q4, and fifth transistor Q5 are turned off. This causes a first current 101 to flow through first inductor L1 and second inductor L2, thereby charging inductors L1 and L2.

[0027] In the second interval following the corresponding interval in the first interval, after the second transistor Q2 is turned off, the fourth transistor Q4 and the fifth transistor Q5 can be selectively turned on to provide additional current to selectively charge the first capacitor C1 and the second capacitor C2 from the charged first inductor L1 and the second inductor L2. When the capacitor voltages v1 and v2 are at the desired levels (in this case, substantially the same), the first capacitor C1 and the second capacitor C2 can be charged simultaneously by the second current 102 through the first diode D1 and the third diode D3. However, if the voltage v1 across the first capacitor C1 is lower than the voltage v2 across the second capacitor C2 (e.g., due to an unbalanced or half-wave rectified load), the first capacitor C1 can be selectively (preferably) charged by turning on the fifth transistor Q5 to enable an additional third current 103 that charges the first capacitor C1 more than the second capacitor C2. Similarly, if the voltage v2 across the second capacitor C2 is lower than the voltage v1 across the first capacitor C1, the second capacitor C2 can be selectively charged by turning on the fourth transistor Q4 to enable an additional fourth current 104 that charges the second capacitor C2 more than the first capacitor C1.

[0028] See Figure 3 In the first interval of the buck mode that transmits power to the battery 10, the first transistor Q1 and the third transistor Q3 are turned on to provide a fifth current 105 to charge the first inductor L1 and the second inductor L2. In the second interval, a sixth current 106 from the discharge of inductors L1 and L2 flows freely through the second diode D2, thereby charging the battery 10.

[0029] According to another aspect, the configuration of device 100 allows for the use of different rated voltages among transistors Q1-Q5. Specifically, the fourth transistor Q4 and the fifth transistor Q5 may have rated voltages lower than those of the first transistor Q1, the second transistor Q2, and the third transistor Q3.

[0030] In 5-level inverter applications, the DC link may be prone to imbalance. Different types of imbalance can occur, including imbalance between the "positive" and "negative" capacitors, which can happen when a half-wave rectified load is applied to the inverter. Another type of imbalance is an imbalance between internal capacitors and external capacitors, which can occur due to high crest factor loads on the inverter.

[0031] Figure 4 A five-stage DC-DC converter device 400 according to an alternative embodiment is shown, which can be used to provide link balancing for such applications. Device 400 includes a series connection of a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. A switching circuit 410 has a first port 411 with first terminals 411a and second terminals 411b coupled to corresponding first end nodes N1 and second end nodes N5 of the capacitor C1-C4 series. A second port 412 of the switching circuit 410 is configured to be coupled in series with a first inductor L1, a second inductor L2, and an energy storage device shown herein as a battery 10.

[0032] The switching circuit 410 includes a plurality of switches, shown herein as including first to seventh IGBTs Q1-Q7 with associated first to seventh parallel connections of diodes D1-D7. A first transistor Q1 is configured to connect a first terminal 411a of a first port 411 to a first terminal 412a of a second port 412. A second transistor Q2 is configured to connect a first terminal 412a of a second port 412 to a second terminal 412b of a second port 412. A third transistor Q3 is configured to connect a second terminal 411b of a first port 411 to a second terminal 412b of a second port 412. A fourth transistor Q4 and a fifth transistor Q5 act as bidirectional switches, configured to connect a first terminal 412a of a second port 412 to an interconnect node N2. A sixth transistor Q5 and a seventh transistor Q7 act as bidirectional switches, configured to connect a second terminal 412b of a second port 412 to a midpoint interconnect node N4. The control circuit 420 controls transistors Q1-Q7 in response to the voltage v across the second capacitor C2 and the third capacitor C3. The fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 may have a lower rated voltage than the first transistor Q1, the second transistor Q2, and the third transistor Q3.

[0033] Figure 5 and Figure 6 The following are examples of methods for balancing capacitor voltages according to some embodiments. Figure 4 The operation of the converter device 400 is described. In the first interval of the boost mode, the control circuit 120 turns on the second transistor Q2 to allow a first current 401 to flow through the first inductor L1 and the second inductor L2, thereby charging the inductors L1 and L2. In the second interval following the corresponding interval in the first interval, the second transistor Q2 is turned off, and the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are selectively turned on to selectively charge capacitors C1-C4 from the charged first inductor L1 and the second inductor L2. When voltages v1, v2, and v3 are at desired relative levels (e.g., such that the corresponding voltages across capacitors C1-C4 are substantially the same), capacitors C1-C4 can be simultaneously charged by a second current 402 flowing through the first diode D1 and the third diode D3, wherein all transistors Q1-Q7 are turned off. To boost the internal capacitor voltage v2, the second capacitor C2 and the third capacitor C3 can be selectively charged by turning on the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7, thereby causing a third current 403 to boost the voltage v2 across the second capacitor C2 and the third capacitor C3. Figure 6 In the first interval of the buck mode shown, the first transistor Q1 and the third transistor Q3 are turned on to conduct a fourth current 404 to charge the first inductor L1 and the second inductor L2. In the second interval, transistors Q1-Q7 are turned off and a fifth current 405 flows freely through the second diode D2, thereby charging the battery 10.

[0034] Figure 7 A five-level DC-DC converter device 700 according to an alternative embodiment is shown, which provides enhanced balancing capability. Device 700 includes a series connection of a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. A switching circuit 710 has a first port 711 with first terminals 711a and second terminals 711b coupled to corresponding first end nodes N1 and N5 of the capacitor C1-C4 series. A second port 712 of the switching circuit 710 is configured to be coupled in series with a first inductor L1, a second inductor L2, and an energy storage device shown herein as a battery 10.

[0035] The switching circuit 710 includes a plurality of switches, shown herein as including first to seventh insulated-gate bipolar transistors (IGBTs) Q1-Q7 and associated first to seventh diodes D1-D7 connected in parallel, as well as additional eighth diode D8 and ninth diode D9. The first transistor Q1 is configured to connect the first terminal 711a of the first port 711 to the first terminal 712a of the second port 712. The second transistor Q2 is configured to connect the first terminal 712a of the second port 712 to the second terminal 712b of the second port 712. The third transistor Q3 is configured to connect the second terminal 711b of the first port 711 to the second terminal 712b of the second port 712. The fourth transistor Q4 is configured to couple the first terminal 712a of the second port 712 to the first interconnect node N2 via the eighth diode D8. The fifth transistor Q5 is configured to connect the emitter terminal of the fourth transistor Q4 to the midpoint interconnect node N3. The seventh transistor Q7 is configured to connect the second terminal 712b of the second port 712 to the interconnect node N4. The sixth transistor Q6 is configured to connect the collector terminal of the seventh transistor Q7 to the midpoint interconnect node N3. The control circuit 720 controls transistors Q1-Q7 in response to the voltage v1 across the first capacitor C1 and the second capacitor C2, the voltage v2 across the third capacitor C3 and the fourth capacitor C4, and the voltage v3 across the second capacitor C2 and the third capacitor C3. In the device 700, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 may have voltages lower than the rated voltages of the first transistor Q1, the second transistor Q2, and the third transistor Q3.

[0036] Figure 8 and Figure 9Operation of a converter device 700 according to some embodiments is illustrated. In a first interval of boost mode, control circuitry 720 turns on second transistor Q2 to conduct a first current 701 flowing through first inductor L1 and second inductor L2, thereby charging inductors L1 and L2. In a second interval following a corresponding interval in the first interval, second transistor Q2 is turned off, and fourth transistor Q4, fifth transistor Q5, sixth transistor Q6, and seventh transistor Q7 are selectively turned on to selectively charge capacitors C1-C4 from the charged first inductor L1 and second inductor L2. When the voltages v1, v2, v3 across all capacitors C1-C4 are at desired relative levels (e.g., such that the corresponding voltages across capacitors C1-C4 are substantially the same), capacitors C1-C4 can be simultaneously charged by a second current 702 flowing through first diode D1 and third diode D3. If voltage v3 is low, capacitors C2 and C3 can be charged by conducting the third current 703, which charges capacitors C2 and C3, through the conduction of transistors Q4, Q5, Q6, and Q7. If voltage v1 is low, capacitors C1 and C2 can be charged by conducting the fourth current 704, which charges capacitors C1 and C2. Similarly, if voltage v2 is low, capacitors C3 and C4 can be charged by conducting the fifth current 705, through the conduction of transistors Q4 and Q5. See also Figure 9 In the first interval of the buck mode, device 700 turns on the first transistor Q1 and the third transistor Q3 to conduct a sixth current 706 to charge the first inductor L1 and the second inductor L2. In the subsequent second interval, these transistors are turned off and a seventh current 707 flows freely through the second diode D2, thereby charging the battery 10.

[0037] Figure 10 A five-level DC-DC converter device 1000 according to another embodiment is shown. Device 1000 includes a series connection of a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. A switching circuit 1010 has a first port 1011 with a first terminal 1011a and a second terminal 1011b coupled to corresponding first end nodes N1 and N5 of the capacitor C1-C4 series. A second port 1012 of the switching circuit 1010 is configured to be series coupled to a first inductor L1, a second inductor L2, and an energy storage device shown herein as a battery 10.

[0038] The switching circuit 1010 includes a plurality of switches, shown herein as including first to eighth IGBTs Q1-Q8 with associated first to eighth diodes D1-D8 connected in parallel. A first transistor Q1 is configured to connect a first terminal 1011a of a first port 1011 to a first terminal 1012a of a second port 1012. A second transistor Q2 is configured to connect a first terminal 1012a of a second port 1012 to a midpoint interconnect node N3. A third transistor Q3 is configured to connect a second terminal 1012b of a second port 1012 to the midpoint interconnect node N3. A fourth transistor Q4 is configured to connect a second terminal 1011b of a first port 1011 to a second terminal 1012b of a second port 1012. A fifth transistor Q5 and a sixth transistor Q6 act as bidirectional switches, configured to connect a first terminal 1012a of a second port 1012 to an interconnect node N2. The seventh transistor Q7 and the eighth transistor Q8 act as bidirectional switches configured to connect the second terminal 1012b of the second port to the interconnect node N4. The control circuit 1020 controls transistors Q1-Q7 in response to the voltage v1 across the first capacitor C1 and the second capacitor C2, the voltage v2 across the third capacitor C3 and the fourth capacitor C4, and the voltage v3 across the second capacitor C2 and the third capacitor C3. In the device 1000, the second transistor Q2, the third transistor Q3, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 may have voltages lower than the rated voltages of the first transistor Q1 and the fourth transistor Q4.

[0039] Figure 11 and Figure 12The operation of a converter device 1000 according to some embodiments is illustrated. In a first interval of boost mode, control circuit 1020 turns on second transistor Q2 and third transistor Q3 to conduct a first current 1001 through first inductor L1 and second inductor L2, thereby charging inductors L1 and L2. In a second interval following a corresponding interval in the first interval, second transistor Q2, third transistor Q3, fifth transistor Q5, sixth transistor Q6, seventh transistor Q7, and eighth transistor Q8 are selectively turned on to selectively charge capacitors C1-C4 from the charged first inductor L1 and second inductor L2. When the voltages v1, v2, v3 across all capacitors C1-C4 are at desired relative levels (e.g., such that the voltages across each of capacitors C1-C4 are substantially the same), capacitors C1-C4 can be simultaneously charged by a second current 1002 passing through first diode D1 and fourth diode D4. If voltage v3 needs to be boosted, the second capacitor C2 and the third capacitor C3 can be charged by conducting the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 to conduct the third current 1003. If voltage v1 needs to be boosted, the first capacitor C1 and the second capacitor C2 can be charged by conducting the third transistor Q3 to conduct the fourth current 1004. Similarly, if voltage v2 needs to be boosted, the third capacitor C3 and the fourth capacitor C4 can be charged by conducting the second transistor Q2 to conduct the fifth current 1005. See also Figure 12 In the first interval of the buck mode, the device 1000 turns on the first transistor Q1 and the fourth transistor Q4 to conduct a sixth current 1006 to charge the first inductor L1 and the second inductor L2. Then these transistors are turned off and the seventh current 1007 flows freely through the second diode D2 and the third diode D3, thereby charging the battery 10.

[0040] Figure 13 A five-level DC-DC converter device 1300 according to a further embodiment is shown. Device 1300 includes a series connection of a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. A switching circuit 1310 has a first port 1311 with first terminals 1311a and second terminals 1311b coupled to corresponding first end nodes N1 and second end nodes N5 of the capacitor C1-C4 series. A second port 1312 of the switching circuit 1310 is configured to be coupled in series with a first inductor L1, a second inductor L2, and an energy storage device shown herein as a battery 10.

[0041] The switching circuit 1310 includes a plurality of switches, shown herein as including first to sixth IGBTs Q1-Q6 with associated first to sixth diodes D1-D6 connected in parallel, and additional seventh diode D7 and eighth diode D8. A first transistor Q1 is configured to connect a first terminal 1311a of a first port 1311 to a first terminal 1312a of a second port 1312. A sixth transistor Q6 is configured to connect a second terminal 1311b of the first port 1311 to a second terminal 1312b of the second port 1312. A second transistor Q2 is configured to couple the first terminal 1312a of the second port 1312 to a first interconnect node N2 via the seventh diode D7. A third transistor Q3 is configured to connect the emitter terminal of the second transistor Q2 to a midpoint interconnect node N3. A fifth transistor Q5 is configured to connect the second terminal 1312b of the second port 1312 to an interconnect node N4 via the eighth diode D8. A fourth transistor Q4 is configured to connect the collector terminal of the fifth transistor Q5 to the midpoint interconnect node N3. Control circuit 1320 controls transistors Q1-Q6 in response to voltages v1 across the first capacitor C1 and the second capacitor C2, voltages v2 across the third capacitor C3 and the fourth capacitor C4, and voltages v3 across the second capacitor C2 and the third capacitor C3. In device 1300, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 may have voltages lower than the rated voltages of the first transistor Q1 and the sixth transistor Q6.

[0042] Figure 14 and Figure 15Operation of a converter device 1300 according to some embodiments is illustrated. In a first interval of boost mode, control circuitry 1320 turns on second transistor Q2, third transistor Q3, fourth transistor Q4, and fifth transistor Q5 to conduct a first current 1301 charging first inductor L1 and second inductor L2. In a second interval following a corresponding interval in the first interval, transistors Q1-Q6 are selectively turned on to selectively charge capacitors C1-C4 from the charged first inductor L1 and second inductor L2. When the voltages v1, v2, v3 across all capacitors C1-C4 are at desired relative levels (e.g., such that the voltages across each of capacitors C1-C4 are substantially the same), capacitors C1-C4 can be simultaneously charged by a second current 1302 passing through first diode D1 and sixth diode D6. If voltage v3 requires a boost, second capacitor C2 and third capacitor C3 can be charged by turning on second transistor Q2 and fifth transistor Q5 to conduct a third current 1303. If voltage v1 needs to be boosted, the first capacitor C1 and the second capacitor C2 can be charged by conducting the fourth current 1304 through the fourth transistor Q4 and the fifth transistor Q5. Similarly, if voltage v2 needs to be boosted, the third capacitor C3 and the fourth capacitor C4 can be charged by conducting the fifth current 1305 through the second transistor Q2 and the third transistor Q3. See also Figure 15 In the first interval of the buck mode, device 1300 turns on the first transistor Q1 and the sixth transistor Q6 to conduct a sixth current 1306 to charge the first inductor L1 and the second inductor L2. In the subsequent second interval, transistors Q1-Q6 are turned off, and a seventh current 1307 flows freely through the second diode D2, the third diode D3, the fourth diode D4, and the fifth diode D5 to charge the battery 10.

[0043] Figure 16 A five-level DC-DC converter device 1600 according to another embodiment is shown. Device 1600 includes a series connection of a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. A switching circuit 1610 has a first port 1611 with a first terminal 1611a and a second terminal 1611b coupled to corresponding first end nodes N1 and N5 of the capacitor C1-C4 series. A second port 1612 of the switching circuit 1610 is configured to be coupled in series with a first inductor L1, a second inductor L2, and an energy storage device shown herein as a battery 10.

[0044] The switching circuit 1610 includes a plurality of switches, shown herein as including first to ninth IGBTs Q1 to Q8 with associated first to ninth diodes D1-D9 connected in parallel. A first transistor Q1 is configured to connect a first terminal 1611a of a first port 1611 to a first terminal 1612a of a second port 1612. A second transistor Q2 is configured to connect a first terminal 1612a of a second port 1612 to a midpoint interconnect node N3. A third transistor Q3 is configured to connect a second terminal 1612b of a second port 1612 to the midpoint interconnect node N3. A fourth transistor Q4 is configured to connect a second terminal 1611b of a first port 1611 to a second terminal 1612b of a second port 1612. A fifth transistor Q5 and a sixth transistor Q6 act as bidirectional switches, configured to connect a first terminal 1612a of a second port 1612 to an interconnect node N2. The seventh transistor Q7 and the eighth transistor Q8 act as bidirectional switches, configured to connect the second terminal 1612b of the second port to the interconnect node N4. The ninth transistor Q9 directly connects the first terminal 1612a of the second port 1612 to the second terminal 1612b of the second port 1612. The control circuit 1620 controls transistors Q1-Q9 in response to the voltage v1 across the first capacitor C1 and the second capacitor C2, the voltage v2 across the third capacitor C3 and the fourth capacitor C4, and the voltage v3 across the second capacitor C2 and the third capacitor C3. In the device 1600, the second transistor Q2, the third transistor Q3, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 may have a lower rated voltage than the first transistor Q1, the fourth transistor Q4, and the ninth transistor Q9.

[0045] Figure 17 and Figure 18The operation of a converter device 1600 according to some embodiments is illustrated. In a first interval of boost mode, control circuit 1620 turns on a ninth transistor Q9 to conduct a first current 1601 through a first inductor L1 and a second inductor L2, thereby charging inductors L1 and L2. In a second interval following a corresponding interval in the first interval, a second transistor Q2, a third transistor Q3, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8 are selectively turned on to selectively charge capacitors C1-C4 from the charged first inductor L1 and second inductor L2. When the voltages v1, v2, and v3 across all capacitors C1-C4 are balanced, capacitors C1-C4 can be simultaneously charged by a second current 1602 passing through a first diode D1 and a fourth diode D4. If voltage v3 needs to be boosted, the second capacitor C2 and the third capacitor C3 can be charged by conducting a third current 1603 through the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8. If voltage v1 needs to be boosted, the first capacitor C1 and the second capacitor C2 can be charged by turning on the third transistor Q3 to conduct the fourth current 1604. Similarly, if voltage v2 needs to be boosted, the third capacitor C3 and the fourth capacitor C4 can be charged by turning on the second transistor Q2 to conduct the fifth current 1605. See also Figure 12 In the first interval of the buck mode, device 1600 turns on the first transistor Q1 and the fourth transistor Q4 to conduct a sixth current 1606 to charge the first inductor L1 and the second inductor L2. Then these transistors are turned off and a seventh current 1607 flows freely through the ninth diode D9, thereby charging the battery 10.

[0046] As described above, DC-DC converter devices according to some embodiments can be advantageously used in parallel multilevel inverter applications. For example, in Figure 19 In the example application shown, the parallel-connected UPS 1900s may each include a multilevel inverter 1920 commonly connected to load 20. A corresponding balanced multilevel DC-DC converter 1910 along the aforementioned line may couple the multilevel inverter 1920 to a corresponding DC source 10, such as a battery, capacitor bank, and / or fuel cell. This arrangement can be used to reduce or eliminate circulating current between the UPS 1900s because the balanced multilevel DC-DC converter 1910 can equalize the DC voltage applied to the multilevel inverter 1920. Similar arrangements can be used in other inverter parallel applications, such as in grid-connected energy storage applications, motor drives, etc.

[0047] Exemplary embodiments of the subject matter of this invention have been disclosed in the accompanying drawings and description. Although specific terminology has been used, it is used in a general and descriptive sense only and not for limiting purposes, and the scope of the subject matter of this invention is defined by the following claims.

Claims

1. An apparatus comprising: A capacitor string, the capacitor string comprising at least two capacitors coupled in series; A switching circuit includes a first port and a second port. The first port has a first terminal and a second terminal respectively connected to a first end node and a second end node of the capacitor string. The second port is configured to be coupled to an energy storage device. The switching circuit is configured to selectively connect the first terminal and the second terminal of the second port to a first end node, a second end node, and at least one interconnect node of the capacitor string. The switching circuit also includes a first diode coupled between the first terminal of the first port and the first terminal of the second port, and a second diode coupled between the second terminal of the first port and the second terminal of the second port. At least one inductor, the at least one inductor being configured to be coupled in series with the second port of the switching circuit and the energy storage device; A charging switch configured to directly connect the first terminal of the second port to the second terminal of the second port; as well as A control circuit configured to close the charging switch in a first interval to charge the at least one inductor from the energy storage device and sense the voltage across the respective capacitors in the capacitor string, and to operate the switching circuit in a second interval in response to the sensed voltage, such that the capacitors in the capacitor string are jointly charged from the at least one inductor being charged via the first diode and the second diode, and the capacitors in the capacitor string are selectively charged from the at least one inductor being charged via selectively closing at least two switches of the switching circuit.

2. The device according to claim 1: The switching circuit mentioned above includes: At least one first switch, the at least one first switch being configured to connect the first terminal of the first port to the first terminal of the second port; At least one second switch, the at least one second switch being configured to connect the second terminal of the first port to the second terminal of the second port; and at least two third switches, the at least two third switches being configured to connect the first terminal and the second terminal of the second port to the at least one interconnecting node; as well as The control circuit is configured to selectively close the at least two third switches during the second interval to selectively charge the capacitors in the capacitor string from the at least one inductor being charged.

3. The device of claim 2, wherein the at least two third switches include corresponding switches configured to connect the first terminal and the corresponding terminal of the second port to the midpoint interconnect node of the capacitor string.

4. The device according to claim 2, wherein the at least two third switches comprise: A plurality of switches are configured to connect the first terminal of the second port to a first set of interconnect nodes of the capacitor string; as well as The second plurality of switches are configured to connect the second terminal of the second port to a second set of interconnect nodes of the capacitor string.

5. The device according to claim 4, wherein the first group of interconnect nodes and the second group of interconnect nodes each include a midpoint interconnect node.

6. The device of claim 2, wherein the control circuitry is configured to selectively close the at least two third switches in the second interval in response to a sensed voltage to balance the voltage across the capacitors in the capacitor string.

7. The device of claim 2, wherein the at least two third switches include a first transistor having a first rated voltage, and wherein the charging switch includes a second transistor having a second rated voltage greater than the first rated voltage.

8. The device according to claim 1, further comprising an inverter coupled to the first port of the switching circuit.

9. An apparatus comprising: A capacitor string, the capacitor string comprising at least two capacitors coupled in series; The switching circuit includes: A first port, the first port having a first terminal and a second terminal connected to a corresponding first end node and a second end node of the capacitor string; The second port is configured to be coupled to the energy storage device; At least one first switch, the at least one first switch being configured to connect the first terminal of the first port to the first terminal of the second port; At least one second switch, the at least one second switch being configured to connect the second terminal of the first port to the second terminal of the second port; At least one third switch, the at least one third switch being configured to connect the first terminal of the second port to a first interconnect node of the capacitor string; At least one fourth switch, the at least one fourth switch being configured to connect the second terminal of the second port to the second interconnect node of the capacitor string; At least one fifth switch, the at least one fifth switch being configured to connect the first terminal of the second port to the midpoint interconnect node of the capacitor string; At least one sixth switch, the at least one sixth switch being configured to connect the second terminal of the second port to the midpoint interconnect node; A first diode, the first diode being coupled between a first terminal of the first port and a first terminal of the second port; and A second diode is coupled between the second terminal of the first port and the second terminal of the second port; At least one inductor, the at least one inductor being configured to be coupled in series with the second port of the switching circuit and the energy storage device; and A control circuit configured to cause the switching circuit to charge the at least one inductor in a first interval and sense the voltage across the respective capacitors in the capacitor string, and to operate the switching circuit in a second interval in response to the sensed voltage, such that the capacitors in the capacitor string are jointly charged from the at least one inductor being charged via the first diode and the second diode, and that the capacitors in the capacitor string are selectively charged from the at least one inductor being charged via selectively closing the at least one third switch, the at least one fourth switch, the at least one fifth switch and the at least one sixth switch.

10. The device of claim 9, wherein the control circuit is configured to close the at least one third switch and the at least one fourth switch to charge the internal capacitor in the capacitor string, close the at least one fifth switch to charge the first external capacitor in the capacitor string, and close the at least one sixth switch to charge the second external capacitor in the capacitor string.

11. The device of claim 9, wherein the control circuit is configured to close the at least one fifth switch and the at least one sixth switch during the first interval to charge the at least one inductor.

12. The device of claim 9, wherein the switching circuit further comprises at least one seventh switch configured to directly connect the first terminal of the second port to the second terminal of the second port, and wherein the control circuit is configured to close the at least one seventh switch during the first interval to charge the at least one inductor.

13. The device of claim 9, wherein the at least one third switch comprises two transistors connected in series, and wherein the at least one fourth switch comprises two transistors connected in series.

14. An apparatus comprising: A capacitor string, the capacitor string comprising at least two capacitors coupled in series; The switching circuit includes: A first port, the first port having a first terminal and a second terminal connected to a corresponding first end node and a second end node of the capacitor string; The second port is configured to be coupled to the energy storage device; At least one first switch, the at least one first switch being configured to connect the first terminal of the first port to the first terminal of the second port; At least one second switch, the at least one second switch being configured to connect the second terminal of the first port to the second terminal of the second port; At least one third switch, the at least one third switch being configured to connect the first terminal of the second port to a first interconnect node of the capacitor string; At least one fourth switch, the at least one fourth switch being configured to connect the second terminal of the second port to the second interconnect node of the capacitor string; At least one fifth switch, the at least one fifth switch being configured to connect the at least one third switch to the midpoint interconnect node of the capacitor string; At least one sixth switch, the at least one sixth switch being configured to connect the at least one fourth switch to the midpoint interconnect node; A first diode, the first diode being coupled between a first terminal of the first port and a first terminal of the second port; and A second diode is coupled between the second terminal of the first port and the second terminal of the second port; At least one inductor, the at least one inductor being configured to be coupled in series with the second port of the switching circuit and the energy storage device; and A control circuit configured to cause the switching circuit to charge the at least one inductor and sense the voltage across the respective capacitors in the capacitor string during a first interval, and to operate the switching circuit during a second interval in response to the sensed voltage such that the capacitors in the capacitor string are jointly charged from the at least one inductor being charged via the first diode and the second diode, and that the capacitors in the capacitor string are selectively charged from the at least one inductor being charged via selectively closing the at least one third switch, the at least one fourth switch, the at least one fifth switch, and the at least one sixth switch.

15. The device of claim 14, wherein the at least one third switch is configured to connect the first terminal of the second port to the first interconnect node via a first diode, and wherein the at least one fourth switch is configured to connect the second terminal of the second port to the second interconnect node via a second diode.

16. The device of claim 14, wherein the control circuit is configured to close the at least one third switch, the at least one fourth switch, the at least one fifth switch and the at least one sixth switch during the first interval to charge the at least one inductor.

17. The device of claim 14, wherein the switching circuit includes at least one seventh switch configured to directly connect the first terminal of the second port to the second terminal of the second port, and wherein the control circuit is configured to close the at least one seventh switch during the first interval to charge the at least one inductor.

18. The device of claim 14, wherein the control circuitry is configured to sense at least one voltage across at least one of the capacitors in the capacitor string and, in response to the sensed at least one voltage, selectively close the at least one third switch, the at least one fourth switch, the at least one fifth switch, and the at least one sixth switch in the second interval.

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