Crosstalk cancellation circuit, transmitting device and transceiver system

Abstract

The present invention provides a crosstalk cancellation circuit, a transmission device, and a transceiver system. The XTC circuit (10) includes delay circuits (12ab, 12cb), differential signal generation circuits (13ab, 13cb), and an amplitude adjustment addition circuit (14b). A signal (Da) serving as an interfering signal is applied with a delay by the delay circuit (12ab) and then input to the differential signal generation circuit (13ab). The differential signal generation circuit (13ab) generates a differential signal having a differential waveform of the signal (Da). In the amplitude adjustment addition circuit (14b), the amplitude of the differential signal generated by the differential signal generation circuit (13ab) is adjusted to obtain a current signal, and the amplitude-adjusted differential signal is added to the signal (Db) in terms of current.

Description

Technical Field

[0001] The present invention relates to a crosstalk cancellation circuit, a transmission device, and a transceiver system. Background Art

[0002] In a transceiver system having a transmission device and a reception device, there are sometimes multiple signal lines arranged in parallel between the transmission device and the reception device. For example, an FFC (Flexible Flat Cable) is formed by arranging multiple signal lines side by side at a certain interval and is often used inside devices such as television receivers. When multiple signal lines are arranged in parallel, due to crosstalk occurring between adjacent signal lines, noise caused by the signal transmitted by an adjacent signal line is superimposed on the signal transmitted by each signal line. The magnitude (noise amplitude) of far-end crosstalk (FEXT) at the time of reaching the reception device depends on the length of the signal line and the interval of the parallel arrangement. The longer the signal line, the larger the noise amplitude of FEXT. In addition, the narrower the parallel arrangement interval of the signal lines, the larger the noise amplitude of FEXT.

[0003] A signal in which noise is superimposed due to the influence of crosstalk among the signals transmitted through adjacent signal lines is called a victim signal, and a signal that exerts the influence of this crosstalk on the victim signal is called an aggressor signal. In addition, since crosstalk is generated bidirectionally between the signals transmitted through adjacent signal lines, each signal may become either a victim signal or an aggressor signal.

[0004] The aggressor signal and the noise superimposed on the victim signal due to the crosstalk from this aggressor signal travel in parallel at the same speed and reach the reception device at the same time. Therefore, the amplitude of the noise superimposed on the victim signal increases as it advances in the signal line. However, the noise width is substantially the same as the rise time or fall time of the aggressor signal, and the noise width does not change substantially during the period of advancing in the signal line. The waveform of the noise superimposed on the victim signal can be approximated by a waveform obtained by adjusting the amplitude and delay of the differential waveform of the aggressor signal.

[0005] With the high-speedization of signal transmission in the transceiver system, the problem of crosstalk becomes more serious. For example, inside a television receiver, a serial signal is transmitted between a controller and a display driver, and due to high resolution such as 4K or 8K, the signal transmission inside the television receiver becomes high-speed. The FFC often used inside a television receiver has the characteristic that the greater the speed, the greater the attenuation of the signal, and the signal voltage at the receiving end and the noise voltage of FEXT become approximately the same magnitude. As a result, the margin for signal transmission decreases and the cost increases. Thus, as the signal transmission becomes high-speed, crosstalk cancellation becomes important.

[0006] As a technique for crosstalk cancellation (XTC), Document 1 "Cosimo Aprile, et al, An Eight-Lane 7-Gb / s / pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels," JSSC, vol. 53, No. 3, Mar 2018." and Document 2 "Specification of U.S. Patent No. 9,166,650" are known. Summary of the Invention

[0007] Study a crosstalk cancellation circuit (XTC circuit) capable of performing appropriate crosstalk cancellation (XTC).

[0008] First, as the first technique of XTC as in Document 1, consider a technique for removing noise superimposed on a victim signal in a receiving device. In the first technique, a high-pass filter is used to generate a differential signal having a differential waveform of an intrusion signal reaching the receiving device, and by adjusting the amplitude of this differential signal, noise superimposed on the intrusion signal reaching the receiving device is generated analogously. Then, using the analogously generated noise, the noise superimposed on the victim signal is canceled. By providing such an XTC circuit in the receiving device, the measured value of the bit error rate of the victim signal after the XTC circuit is minimized, and thus the setting (amplitude adjustment) of XTC can be optimized according to the magnitude of crosstalk (length and spacing of signal lines).

[0009] In this first technique, in order to perform XTC with higher precision, it is necessary to make the phase of the noise superimposed on the victim signal consistent with the phase of the noise analogously generated based on the intrusion signal. However, it is difficult to implement a delay circuit for adjusting the phase of the noise as an analog signal. A method of using a gain equalizer to adjust the phase of the noise can be considered, but it is not preferred because of high power consumption.

[0010] Next, as the second technique of XTC as in Document 2, consider a technique for pre-applying to a victim signal in a transmitting device the noise that will be superimposed on the victim signal at the moment it reaches the receiving device. In the second technique, in the transmitting device, after delaying the intrusion signal by a delay circuit, a high-pass filter is used to generate a differential signal having a differential waveform of the intrusion signal, and by adjusting the amplitude of this differential signal, analog noise is generated. Then, this analog noise is applied to the victim signal, and the subsequent victim signal is transmitted from the transmitting device. It is easy to implement a delay circuit for delaying the intrusion signal as a digital signal.

[0011] In this second technique, it is necessary to grasp the waveform of the noise superimposed on the victim signal at the moment of reaching the receiving device, and determine the delay amount and amplitude adjustment amount when generating the noise analogously according to the intrusion signal in the transmitting device. In the case of a closed system such as a television receiver, the delay amount and amplitude adjustment amount can be determined when designing the system. When performing high-speed signal transmission in a closed device, the second technique is effective.

[0012] In an XTC circuit, a capacitive coupling driver having a capacitive element serially provided at the output terminal of the driver is used, and the intrusion signal is input to the driver. It is also possible to consider a method in which the output impedance of the driver and the capacitive element serially connected thereto form a high-pass filter to generate a differential signal having a differential waveform of the intrusion signal. In addition, by making the capacitance value of the capacitive element variable, the amplitude adjustment of the differential signal can be performed. Moreover, the amplitude-adjusted analog noise can be applied to the victim signal through capacitive coupling.

[0013] Compared with the first technique of performing XTC on the receiving device side, the second technique of performing XTC on the transmitting device side is preferable in that the phase adjustment of the analog noise can be easily performed. However, in the case where a T coil is provided at the output terminal of the transmitting device, in the second technique, the T coil is required as described below.

[0014] The T coil provided at the output terminal of the transmitting device can eliminate the load capacitance (such as the capacitance of an ESD protection diode, etc.) added to its output terminal, improve the return loss and insertion loss of the output of the transmitting device, and can improve the output signal band of the transmitting device. In high-speed signal transmission exceeding about 10 Gbps, if an XTC circuit is provided in the transmitting device, the output signal band deteriorates. Therefore, in order to prevent this situation, it is necessary to provide a T coil. The XTC circuit of the second technique described above has a large load capacitance at the output terminal, so a T coil is provided for high-speed signal transmission.

[0015] The inductance of the T coil is designed to an optimal value according to the magnitude of the load capacitance to be eliminated. However, in the XTC circuit of the second technique described above, if the capacitance value of the capacitive element is changed for amplitude adjustment, the inductance of the T coil becomes non-optimal, and sometimes the normal signal characteristics of the T coil cannot be sufficiently improved. Thus, it is difficult to simultaneously achieve the improvement of the normal signal characteristics of the T coil and the improvement of the XTC characteristics.

[0016] The present disclosure shows a crosstalk cancellation circuit (XTC circuit) that can perform appropriate crosstalk cancellation (XTC) even when a T coil is provided at the output terminal. In addition, the present disclosure shows a transmitting device having an XTC circuit, and a transceiver system including such a transmitting device and a receiving device.

[0017] The crosstalk cancellation circuit (XTC circuit) is an XTC circuit provided in a transmitting device that transmits multiple signals to a receiving device via a plurality of signal lines. The XTC circuit includes: (1) a delay circuit that adjusts the phase of a first signal (invasive signal) among the multiple signals; (2) a differential signal generation circuit that generates a differential signal having a differential waveform of the first signal whose phase has been adjusted by the delay circuit; and (3) an amplitude adjustment summing circuit that adjusts the amplitude of the differential signal generated by the differential signal generation circuit, uses the differentially adjusted differential signal as a current signal, performs current addition of the amplitude-adjusted differential signal and a second signal (victim signal) among the multiple signals, and outputs the added second signal. Additionally, the multiple signals can each be a single-ended signal or a differential signal.

[0018] Preferably, the amplitude adjustment summing circuit includes a plurality of amplifiers, each of which has: an input terminal for inputting a voltage signal; and an output terminal that outputs a current signal corresponding to the voltage signal when set to conducting and does not output a current signal when set to non-conducting. The differential signal generated by the differential signal generation circuit is input to the input terminals of the plurality of amplifiers, the sum of the current signals output from the output terminals of the plurality of amplifiers is current-added to the second signal, and the amplitude adjustment amount of the differential signal is set by the conduction / non-conduction setting of each of the plurality of amplifiers.

[0019] Each of the plurality of amplifiers can have: a current source provided between a first potential terminal and the output terminal; a MOS transistor provided between a second potential terminal and the output terminal; and a capacitive element provided between the gate of the MOS transistor and the input terminal. Alternatively, each of the plurality of amplifiers can have: a PMOS transistor provided between a power supply potential terminal and the output terminal; an NMOS transistor provided between a ground potential terminal and the output terminal; a first capacitive element provided between the gate of the PMOS transistor and the input terminal; and a second capacitive element provided between the gate of the NMOS transistor and the input terminal. Additionally, one of the first potential terminal and the second potential terminal is a power supply potential terminal, and the other is a ground potential terminal. Additionally, in the case where the input / output signal is a differential signal, the circuit structure can be provided in pairs.

[0020] In the case where the input voltage signal is a differential signal composed of a first voltage signal and a second voltage signal, and the output current signal is a differential signal composed of a first current signal and a second current signal, each of the plurality of amplifiers may have the following circuit structures. Each of the plurality of amplifiers includes: a first current source provided between a first potential terminal and a first output terminal that outputs a first current signal; a second current source provided between the first potential terminal and a second output terminal that outputs a second current signal; a third current source connected to a second potential terminal; a first MOS transistor having a gate connected to a first input terminal to which the first voltage signal is input, and provided between the third current source and the first output terminal; and a second MOS transistor having a gate connected to a second input terminal to which the second voltage signal is input, and provided between the third current source and the second output terminal. Further, one of the first potential terminal and the second potential terminal is a power supply potential terminal, and the other is a ground potential terminal.

[0021] Alternatively, each of the plurality of amplifiers may also have the following circuit structures in the case where the input voltage signal is a differential signal composed of a first voltage signal and a second voltage signal, and the output current signal is a differential signal composed of a first current signal and a second current signal. Each of the plurality of amplifiers has: a first current source connected to a power supply potential terminal; a second current source connected to a ground potential terminal; a first PMOS transistor having a gate connected to a first input terminal to which the first voltage signal is input, and provided between the first current source and a first output terminal that outputs a first current signal; a second PMOS transistor having a gate connected to a second input terminal to which the second voltage signal is input, and provided between the first current source and a second output terminal that outputs a second current signal; a first NMOS transistor having a gate connected to the first input terminal, and provided between the second current source and the first output terminal; and a second NMOS transistor having a gate connected to the second input terminal, and provided between the second current source and the second output terminal.

[0022] The transmission device of the present disclosure has the crosstalk cancellation circuit of the present invention described above. The transceiver system of the present disclosure has the above-described transmission device and a reception device that receives a plurality of signals from the transmission device.

[0023] According to the present invention, appropriate crosstalk cancellation can be performed even when a T coil is provided at the output terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The structure of the transceiver system 1 is shown.

[0025] Figure 2 It is a diagram showing the structure of the XTC circuit 10.

[0026] Figure 3It is a diagram showing an example of the circuit configurations of the delay circuit 12 and the differential signal generation circuit 13.

[0027] Figure 4 It is a diagram showing the configuration of the amplitude adjustment adder circuit 14.

[0028] Figure 5 It is a diagram showing the configuration of the variable gain amplifier 21.

[0029] Figure 6 It is a diagram showing an example of the circuit configurations of the amplifier 31 and the on / off setting circuit 41.

[0030] Figure 7 It is a graph showing the result obtained by simulating the relationship between the amplitude adjustment amount and the signal transmission speed in the variable gain amplifier 21.

[0031] Figure 8A 、 Figure 8B 、 Figure 8C They are diagrams respectively showing the results obtained by simulating the operation of the XTC circuit 10, Figure 8A showing the case without crosstalk, Figure 8B showing the case with crosstalk but without performing XTC, Figure 8C showing the case with crosstalk and performing XTC.

[0032] Figure 9 It is a diagram showing the configuration of the XTC circuit 10A.

[0033] Figure 10 It is a diagram showing another example of the circuit configuration of the amplifier.

[0034] Figure 11 It is a diagram showing another example of the circuit configuration of the amplifier.

[0035] Figure 12 It is a diagram showing another example of the circuit configuration of the amplifier.

[0036] Figure 13 It is a diagram showing another example of the circuit configuration of the amplifier.

[0037] Figure 14 It is a diagram showing another example of the circuit configuration of the amplifier. Detailed Description of the Preferred Embodiments

[0038] Hereinafter, modes for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted. The present invention is not limited to these examples, as indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0039] Figure 1The structure of the transceiver system 1 is shown. The transceiver system 1 includes a transmitting device 2 and a receiving device 3. A plurality of signal lines 4 are arranged in parallel between the transmitting device 2 and the receiving device 3. The transceiver system 1 transmits a plurality of signals from the transmitting device 2 to the receiving device 3 through the plurality of signal lines 4. The plurality of signal lines 4 are arranged in parallel at a certain interval, for example, an FFC (Flexible Flat Cable).

[0040] Such a transceiver system exists, for example, in devices such as a television receiver. In this example, in the controller (transmitting device), a parallel signal (video signal) is converted into a serial signal, and this serial signal is transmitted from the controller to the driver (receiving device) of the display via the signal line. Then, in the driver, it is converted from the serial signal into a parallel signal, and an image is displayed on the display according to this parallel signal.

[0041] The transmitter 2 is equipped with an XTC circuit (crosstalk cancellation circuit) 10. The XTC circuit 10 cancels the crosstalk between the plurality of signals transmitted by the plurality of signal lines 4 (especially the signals transmitted by adjacent signal lines). The XTC circuit 10 generates noise that is superimposed on the victim signal at the moment of reaching the receiving device 3 according to the interfering signal, and pre-applies the generated noise to the victim signal.

[0042] The victim signal is a signal that has been affected by crosstalk and has noise superimposed on it. The interfering signal is a signal that imposes the influence of this crosstalk on the victim signal. Each signal can be either the victim signal or the interfering signal.

[0043] Figure 2 It is a diagram showing the structure of the XTC circuit 10. In this diagram, the case of performing XTC among three signals Da, Db, and Dc is shown. Assume that three signal lines for transmitting three signals Da, Db, and Dc are arranged in sequence, and the crosstalk between adjacent signal lines is eliminated.

[0044] When the signal Db transmitted through the central signal line among the three signal lines is set as the victim signal, the signals Da and Dc transmitted by the adjacent two signal lines become interfering signals. At this time, the signal Da, which is one of the interfering signals, is input to the differential signal generation circuit 13ab after being given a delay (phase adjustment) by the delay circuit 12ab, and a differential signal having the differential waveform of the signal Da is generated by the differential signal generation circuit 13ab. The signal Dc, which is the other interfering signal, is input to the differential signal generation circuit 13cb after being given a delay (phase adjustment) by the delay circuit 12cb, and a differential signal having the differential waveform of the signal Dc is generated by the differential signal generation circuit 13cb.

[0045] The signal Db as the victim signal is input to the amplitude adjustment adder circuit 14b after passing through the buffer 11b. In the amplitude adjustment adder circuit 14b, the amplitude of the differential signal generated by the differential signal generation circuit 13ab is adjusted to become a current signal, and the amplitude of the differential signal generated by the differential signal generation circuit 13cb is adjusted as a current signal, and these two amplitude-adjusted differential signals are added to the signal Db in current.

[0046] When the signal Da is the victim signal, the signal Db becomes the intrusion signal. The signal Db as the intrusion signal is applied with a delay (phase adjustment) by the delay circuit 12ba and then input to the differential signal generation circuit 13ba, and the differential signal generation circuit 13ba generates a differential signal having the differential waveform of the signal Db. The signal Da as the victim signal is input to the amplitude adjustment adder circuit 14a after passing through the buffer 11a. In the amplitude adjustment adder circuit 14a, the amplitude of the differential signal generated by the differential signal generation circuit 13ba is adjusted and then used as a current signal, and the amplitude-adjusted differential signal is added to the signal Da in current.

[0047] When the signal Dc is the victim signal, the signal Db becomes the intrusion signal. The signal Db as the intrusion signal is applied with a delay (phase adjustment) by the delay circuit 12bc and then input to the differential signal generation circuit 13bc, and the differential signal generation circuit 13bc generates a differential signal having the differential waveform of the signal Db. The signal Dc as the victim signal is input to the amplitude adjustment adder circuit 14c after passing through the buffer 11c. In the amplitude adjustment adder circuit 14c, the amplitude of the differential signal generated by the differential signal generation circuit 13bc is adjusted and then used as a current signal, and the amplitude-adjusted differential signal is added to the signal Dc in current.

[0048] The buffers 11a, 11b, and 11c may have a common structure. The delay circuits 12ab, 12ba, 12bc, and 12cb may have a common structure, hereinafter referred to as the delay circuit 12. The differential signal generation circuits 13ab, 13ba, 13bc, and 13cb may have a common structure, hereinafter referred to as the differential signal generation circuit 13. The amplitude adjustment adder circuits 14a and 14c may have a common structure. The common structure means a substantially identical structure. Compared with the amplitude adjustment adder circuits 14a and 14c, although the number of differential signals for current addition in the amplitude adjustment adder circuit 14b is different, the same structure can be adopted, hereinafter referred to as the amplitude adjustment adder circuit 14. Hereinafter, specific circuit structure examples of the delay circuit 12, the differential signal generation circuit 13, and the amplitude adjustment adder circuit 14 will be described.

[0049] Figure 3FIG. 0 is a diagram showing an example of the circuit configurations of the delay circuit 12 and the differential signal generation circuit 13 (differentiating circuit). The delay circuit 12 includes six inverters Inv1 to Inv6 and four switches Sw1 to Sw4. The six inverters Inv1 to Inv6 are connected in series. The switch Sw1 is provided between the input terminal of the delay circuit 12 and the output terminal of the delay circuit 12. The switch Sw2 is provided between the output terminal of the second-stage inverter Inv2 and the output terminal of the delay circuit 12. The switch Sw3 is provided between the output terminal of the fourth-stage inverter Inv4 and the output terminal of the delay circuit 12. The switch Sw4 is provided between the output terminal of the last-stage inverter Inv6 and the output terminal of the delay circuit 12. When any one of the switches Sw1 to Sw4 is in the conductive state, the other switches are in the non-conductive state. Depending on which of the switches Sw1 to Sw4 is made conductive, the number of inverters through which the signal passes from the input terminal to the output terminal of the delay circuit 12 can be made different, and the delay applied to the intrusion signal can be made variable.

[0050] The differential signal generation circuit 13 includes a capacitor element C and a resistor R. The capacitor element C is provided between the input terminal and the output terminal of the differential signal generation circuit 13. The resistor R is provided between the output terminal of the differential signal generation circuit 13 and the ground potential terminal. The differential signal generation circuit 13 configured in this way operates as a high-pass filter and can generate a signal (differential signal) having a waveform obtained by approximating the differential waveform of the input signal. As an example, the capacitance value of the capacitor element C is 37 fF, and the resistance value of the resistor R is 300 Ω.

[0051] Figure 4 FIG. 7 is a diagram showing the configuration of the amplitude adjustment adder circuit 14. The amplitude adjustment adder circuit 14 includes variable-gain amplifiers 21a, 21c, and an adder 22. The variable-gain amplifier 21a adjusts the amplitude of the differential signal generated by the differential signal generation circuit 13ab and outputs the amplitude-adjusted differential signal as a current signal. The variable-gain amplifier 21c adjusts the amplitude of the differential signal generated by the differential signal generation circuit 13cb and outputs the amplitude-adjusted differential signal as a current signal. The amount of amplitude adjustment (gain) in the variable-gain amplifiers 21a, 21c is variable, and there are cases where it is greater than 1, cases where it is 1 or less, and cases where it is negative. The adder 22 adds the differential signals (current signals) output after amplitude adjustment from the variable-gain amplifiers 21a, 21c and the victim signal in current and outputs the added victim signal.

[0052] Also shown in the figure are ESD protection diodes 23, 24 and inductors 25, 26. The ESD protection diode 23 is provided between the output terminal of the adder 22 and the power supply potential terminal. The ESD protection diode 24 is provided between the output terminal of the adder 22 and the ground potential terminal. The inductor 25 is provided on the path of the victim signal input to the adder 22. The inductor 26 is provided on the path of the victim signal output from the adder 22. The inductors 25, 26 form a T coil, which can eliminate the load capacitance (capacitance of the ESD protection diodes 23, 24, etc.) added to the output terminal of the adder 22 (i.e., the output terminal of the XTC circuit 10), improve the output return loss and insertion loss, and improve the output signal frequency band.

[0053] The gain variable amplifiers 21a, 21c may have a common structure, which is hereinafter referred to as the gain variable amplifier 21. Figure 5 It is a diagram showing the structure of the gain variable amplifier 21. The gain variable amplifier 21 includes eight amplifiers 31 to 38 and eight conduction cutoff setting circuits 41 to 48. The eight amplifiers 31 to 38 may have a common structure, and the eight conduction cutoff setting circuits 41 to 48 may also have a common structure. The eight conduction cutoff setting circuits 41 to 48 may also share a part of the partial circuit.

[0054] The input terminals of the amplifiers 31 to 38 are respectively connected to the input terminal of the gain variable amplifier 21, and a differential input signal (voltage signal V) is input. The output terminals of the amplifiers 31 to 38 are respectively connected to the output terminal of the gain variable amplifier 21. The amplifiers 31 to 38 can respectively perform conduction / cutoff setting through the corresponding conduction cutoff setting circuits in the conduction cutoff setting circuits 41 to 48. When the conduction is set, the amplifiers 31 to 38 respectively output a current signal I corresponding to the input voltage signal V from the output terminal, and when the cutoff is set, no current signal is output from the output terminal. If the number of amplifiers among the amplifiers 31 to 38 set to be conductive is set to n, the current signal output from the output terminal of the gain variable amplifier 21 becomes nI. The gain variable amplifier 21 can set the amplitude adjustment amount of the differential signal through the conduction / cutoff setting of each of the amplifiers 31 to 38.

[0055] Figure 6 It is a diagram showing an example of the circuit structure of the amplifier 31 and the conduction cutoff setting circuit 41. Here, it is assumed that the intrusion signal and the victim signal are differential signals, and each signal generated from these signals is also a differential signal.

[0056] The amplifier 31 includes current sources I1 and I2, NMOS transistors MN11 and MN12, capacitive elements C1 and C2, and resistors R1 and R2. The current source I1 is provided between the power supply potential terminal and the drain of the NMOS transistor MN11. The current source I2 is provided between the power supply potential terminal and the drain of the NMOS transistor MN12. The current sources I1 and I2 can each include a PMOS transistor to be implemented. The sources of the NMOS transistors MN11 and MN12 are each connected to the ground potential terminal.

[0057] The magnitudes of the currents flowing through the current sources I1 and I2 are controlled by the bias voltages provided by the conduction cutoff setting circuit 41. The conduction cutoff setting circuit 41 applies a bias voltage to the gate of the NMOS transistor MN11 via the resistor R1. The conduction cutoff setting circuit 41 applies a bias voltage to the gate of the NMOS transistor MN12 via the resistor R2.

[0058] The capacitive element C1 is provided between the input terminal of one signal (+V) in the input differential signal and the gate of the NMOS transistor MN11. The capacitive element C2 is provided between the input terminal of the other signal (-V) in the input differential signal and the gate of the NMOS transistor MN12. The drain of the NMOS transistor MN11 is connected to the output terminal of one signal (+I) of the output differential signal. The drain of the NMOS transistor MN12 is connected to the output terminal of the other signal (-I) of the output differential signal.

[0059] The conduction cutoff setting circuit 41 includes an inverter Inv, a current source I20, PMOS transistors MP20, MP21, MP22, NMOS transistors MN21, MN22, and switches Sw11, Sw12, Sw21, Sw22, Sw31, Sw32. Among them, the current source I20 and the PMOS transistor MP20 can be shared by eight conduction cutoff setting circuits 41 to 48.

[0060] The sources of the PMOS transistors MP20, MP21, and MP22 are each connected to the power supply potential terminal. The sources of the NMOS transistors MN21 and MN22 are each connected to the ground potential terminal.

[0061] The drain of the PMOS transistor MP20 is connected to the gates of the PMOS transistors MP20, MP21, and MP22, and is connected to the switch Sw31. The switch Sw32 is provided between the switch Sw31 and the power supply potential terminal. The current source I20 is provided between the drain of the PMOS transistor MP20 and the ground potential terminal.

[0062] The drain of NMOS transistor MN 21 is connected to the drain of PMOS transistor MP 21, the gate of NMOS transistor MN 21, and switch Sw 11. Switch Sw 12 is provided between switch Sw 11 and the ground potential terminal.

[0063] The drain of NMOS transistor MN 22 is connected to the drain of PMOS transistor MP 22, the gate of NMOS transistor MN 22, and switch Sw 21. Switch Sw 22 is provided between switch Sw 21 and the ground potential terminal.

[0064] Current source I 20, PMOS transistors MP 20 and MP 21, and NMOS transistor MN 21 form a current mirror circuit. Current source I 20, PMOS transistors MP 20 and MP 22, and NMOS transistor MN 22 form a current mirror circuit.

[0065] Inverter Inv generates a signal obtained by logically inverting the conduction cutoff setting signal EN. Switches Sw 11, Sw 12, Sw 21, Sw 22, Sw 31, and Sw 32 are each in either a conduction or cutoff state according to the level of the conduction cutoff setting signal EN. When the conduction cutoff setting signal EN is at a high level, switches Sw 11, Sw 21, and Sw 31 become conductive. When the conduction cutoff setting signal EN is at a low level (i.e., when the signal provided from inverter Inv is at a high level), switches Sw 11, Sw 21, and Sw 31 become conductive.

[0066] The relationship between amplifier 31 and the conduction cutoff setting circuit 41 is as follows. The connection point between switches Sw 11 and Sw 12 is connected to the gate of NMOS transistor MN 11 via resistor R1 of amplifier 31. The connection point between switches Sw 21 and Sw 22 is connected to the gate of NMOS transistor MN 12 via resistor R2 of amplifier 31. The connection point between switches Sw 31 and Sw 32 is connected to current sources I1 and I2 of amplifier 31.

[0067] When the conduction cutoff setting signal EN is at a low level, switches Sw 11, Sw 21, and Sw 31 become cutoff states, and switches Sw 12, Sw 22, and Sw 32 become conductive states. At this time, in amplifier 31, a ground potential is provided to the gates of NMOS transistors MN 11 and MN 12, respectively. In addition, a power supply potential is provided to the gates of the PMOS transistors constituting current sources I1 and I2. Therefore, amplifier 31 is set to a cutoff state, and even when an input signal (±V) is applied to the input terminal, the level ΔI of the signal output from the output terminal is 0.

[0068] When the conduction cutoff setting signal EN is at a high level, the switches Sw 11, Sw 21, and Sw 31 are in the conducting state, and the switches Sw 12, Sw 22, and Sw 32 are in the cutoff state. At this time, in the amplifier 31, the same potential as the gate potential of each of the NMOS transistors MN 21 and MN 22 is provided as a bias to the gates of the NMOS transistors MN 11 and MN 12 respectively. The same potential as the gate potential of each of the PMOS transistors MP 20, MP 21, and MP 22 is provided to the gates of the PMOS transistors constituting the current sources I1 and I2. Therefore, when the amplifier 31 is set to the conducting state and a signal (±V) is input to the input terminal, a signal (±I) corresponding to the input signal is output from the output terminal.

[0069] If the conduction cutoff setting signal EN input to n of the eight conduction cutoff setting circuits 41 to 48 is set to a high level and the conduction cutoff setting signal EN input to the other conduction cutoff setting circuits is set to a low level, the current signal output from the output terminal of the variable gain amplifier 21 becomes the sum nI of the current signals respectively output from the amplifiers set to conduction. Therefore, by changing the value of n, the amplitude adjustment amount of the differential signal in the variable gain amplifier 21 can be set.

[0070] Figure 7 It is a graph showing the result obtained by simulating the relationship between the amplitude adjustment amount and the signal transmission speed in the variable gain amplifier 21. The variable gain amplifier 21 has Figure 5 and Figure 6 the circuit structure shown. Let the magnitude of the current flowing through the current source I 20 of the conduction cutoff setting circuit be 100 μA, and let the magnitudes of the currents flowing through the current sources I1 and I2 of the amplifier at the time of conduction setting be 0.5 mA. The output current signal is observed as a voltage signal through the termination resistor in the subsequent output buffer, and the ratio of the observed voltage signal to the input voltage signal is taken as the amplitude adjustment amount (gain). In this graph, the horizontal axis is set as the signal transmission speed, the vertical axis is set as the amplitude adjustment amount, and the relationship between the amplitude adjustment amount and the signal transmission speed is shown for each value of n = 1 to 8. As shown in this graph, the larger the number n of the amplifiers set to conduction, the larger the amplitude adjustment amount. For example, when the signal transmission speed is 8 Gbps, the amplitude adjustment amount is 0.078 times when n = 1, and 0.53 times when n = 8.

[0071] Figure 8A 、 Figure 8B 、 Figure 8C are respectively graphs showing the results obtained by simulating the operation of the XTC circuit 10. Figure 8AShows the eye pattern of the signal after gain equalization in the receiving device in the absence of crosstalk. Figure 8B and Figure 8C Shows the eye pattern of the signal on the central signal line in the receiving device when there is crosstalk between three signal lines arranged in parallel. Figure 8B Represents the eye pattern when XTC is not performed. Figure 8C Represents the eye pattern when XTC of this embodiment is performed. Compared with Figure 8B the eye pattern of Figure 8C the eye pattern of

[0072] The XTC circuit 10 of this embodiment can perform appropriate XTC even when T coils (inductors 25, 26) are provided at the output end. That is, in the gain variable amplifier 21, even if the number n of the amplifiers 31 to 38 included in the gain variable amplifier 21 that are set to be turned on is changed in order to appropriately set the amplitude adjustment amount of the differential signal of the invading signal, the load capacitance attached to the output end does not change. Therefore, it is possible to take into account the improvement of the normal signal characteristics of the T coil and the improvement of the XTC characteristics. The XTC circuit 10 can be appropriately provided in the transmitting device 2. The transceiver system 1 having the transmitting device 2 and the receiving device 3 can be appropriately provided in a device such as a TV receiver.

[0073] The present invention is not limited to the above embodiments and can be variously modified. Hereinafter, modification examples of this embodiment will be described.

[0074] Figure 9 Is a diagram showing the structure of the XTC circuit 10A. Compared with Figure 2 the structure of the XTC circuit 10 shown in Figure 9 the difference of the XTC circuit 10A shown in Figure 2 is that it further has an adding circuit 15 that adds the differential signals output from the differential signal generation circuit 13ab and the differential signal generation circuit 13cb respectively. The adding circuit 15 can add the two differential signals by capacitive coupling. In the amplitude adjustment adding circuit 14b, the amplitude of the differential signal added and output by the adding circuit 15 is adjusted as a current signal, and the amplitude-adjusted differential signal is added to the signal Db in current. The amplitude adjustment adding circuit 14b can have the same structure as the amplitude adjustment adding circuits 14a and 14c. Figure 9 The amplitude adjustment adding circuit 14b of the XTC circuit 10A shown in

[0075] Figures 10 to 14 This is a diagram showing another circuit configuration example of amplifiers 31 to 38. Additionally, Figure 10 The circuit configuration example of the amplifier shown is equivalent to reversing the conductivity type with respect to Figure 6 the circuit configuration example of the amplifier shown in Figure 13 The circuit configuration example of the amplifier shown is equivalent to reversing the conductivity type with respect to Figure 12 the circuit configuration example of the amplifier shown in

[0076] Figure 10 The amplifier of the circuit configuration example shown includes current sources I3, I4, PMOS transistors MP11, MP12, capacitor elements C3, C4, and resistors R3, R4. The current source I3 is provided between the ground potential terminal and the drain of the PMOS transistor MP11. The current source I4 is provided between the ground potential terminal and the drain of the PMOS transistor MP12. The current sources I3, I4 can be respectively implemented by including NMOS transistors. The sources of the PMOS transistors MP11, MP12 are each connected to the power supply potential terminal.

[0077] The magnitudes of the currents flowing through the current sources I3, I4 are controlled by the bias voltages provided from the on-off setting circuit. The on-off setting circuit applies a bias voltage to the gate of the PMOS transistor MP11 via the resistor R3. The on-off setting circuit applies a bias voltage to the gate of the PMOS transistor MP12 via the resistor R4.

[0078] The capacitor element C3 is provided between the input terminal of one signal (+V) in the input differential signal and the gate of the PMOS transistor MP11. The capacitor element C4 is provided between the input terminal of the other signal (-V) in the input differential signal and the gate of the PMOS transistor MP12. The drain of the PMOS transistor MP11 is connected to the output terminal of one signal (+I) in the output differential signal. The drain of the PMOS transistor MP12 is connected to the output terminal of the other signal (-I) in the output differential signal.

[0079] Figure 11 The amplifier of the circuit configuration example shown includes NMOS transistors MN11, MN12, PMOS transistors MP11, MP12, capacitor elements C1 to C4, and resistors R1 to R4. The PMOS transistor MP11 and the NMOS transistor MN11 are serially provided between the power supply potential terminal and the ground potential terminal, and the PMOS transistor MP12 and the NMOS transistor MN12 are serially provided.

[0080] A bias voltage is applied to the gate of NMOS transistor MN11 via resistor R1 from the on / off setting circuit. A bias voltage is applied to the gate of NMOS transistor MN12 via resistor R2 from the on / off setting circuit. A bias voltage is applied to the gate of PMOS transistor MP11 via resistor R3 from the on / off setting circuit. A bias voltage is applied to the gate of PMOS transistor MP12 via resistor R4 from the on / off setting circuit.

[0081] Capacitor element C1 is provided between the input terminal of one of the input differential signals (+V) and the gate of NMOS transistor MN11. Capacitor element C2 is provided between the input terminal of the other input differential signal (-V) and the gate of NMOS transistor MN12. Capacitor element C3 is provided between the input terminal of one of the input differential signals (+V) and the gate of PMOS transistor MP11. Capacitor element C4 is provided between the input terminal of the other input differential signal (-V) and the gate of PMOS transistor MP12.

[0082] The drains of NMOS transistor MN11 and PMOS transistor MP11 are each connected to the output terminal of one of the output differential signals (+I). The drains of NMOS transistor MN12 and PMOS transistor MP12 are each connected to the output terminal of the other output differential signal (-I).

[0083] Figure 12 The amplifier of the illustrated circuit structure example includes current sources I1, I2, I5 and NMOS transistors MN11, MN12. Current source I1 is provided between the power supply potential terminal and the drain of NMOS transistor MN11. Current source I2 is provided between the power supply potential terminal and the drain of NMOS transistor MN12. Current source I5 is provided between the ground potential terminal and the sources of NMOS transistors MN11 and MN12. The gate of NMOS transistor MN11 is connected to the input terminal of one of the input differential signals (+V). The gate of NMOS transistor MN12 is connected to the input terminal of the other input differential signal (-V). The drain of NMOS transistor MN11 is connected to the output terminal of one of the output differential signals (+I). The drain of NMOS transistor MN12 is connected to the output terminal of the other output differential signal (-I). The on / off setting of this amplifier is performed by the on / off setting of current sources I1, I2, I5.

[0084] Figure 13The amplifier of the illustrated circuit structure example includes current sources I3, I4, I6, and PMOS transistors MP11 and MP12. The current source I3 is provided between the ground potential terminal and the drain of the PMOS transistor MP11. The current source I4 is provided between the ground potential terminal and the drain of the PMOS transistor MP12. The current source I6 is provided between the sources of the PMOS transistors MP11 and MP12 and the power supply potential terminal. The gate of the PMOS transistor MP11 is connected to the input terminal of one signal (+V) in the input differential signal. The gate of the PMOS transistor MP12 is connected to the input terminal of the other signal (-V) in the input differential signal. The drain of the PMOS transistor MP11 is connected to the output terminal of one signal (+I) in the output differential signal. The drain of the PMOS transistor MP12 is connected to the output terminal of the other signal (-I) in the output differential signal. The on / off setting of this amplifier is performed by the on / off setting of the current sources I3, I4, and I6.

[0085] Figure 14 The amplifier of the circuit structure example shown in includes current sources I5 and I6, NMOS transistors MN11 and MN12, and PMOS transistors MP11 and MP12. The current source I5 is provided between the ground potential terminal and the sources of the NMOS transistors MN11 and MN12. The current source I6 is provided between the power supply potential terminal and the sources of the PMOS transistors MP11 and MP12. The gates of the PMOS transistor MP11 and the NMOS transistor MN11 are connected to the input terminal of one signal (+V) in the input differential signal. The gates of the PMOS transistor MP12 and the NMOS transistor MN12 are connected to the input terminal of the other signal (-V) in the input differential signal. The drains of the PMOS transistor MP11 and the NMOS transistor MN11 are connected to each other and to the output terminal of one signal (+I) in the output differential signal. The drains of the PMOS transistor MP12 and the NMOS transistor MN12 are connected to each other and to the output terminal of the other signal (-I) in the output differential signal. The on / off setting of this amplifier is performed by the on / off setting of the current sources I5 and I6.

[0086] In Figures 12 to 14In the example of the circuit structure of the amplifier shown, since the current source includes MOS transistors, three or four MOS transistors are serially provided between the power supply potential terminal and the ground potential terminal. Considering the voltage between the source and the drain in each MOS transistor, when the amplitude of the victim signal is small, it is sometimes difficult to operate the MOS transistors constituting the input differential pair in the saturation region. If the MOS transistors do not operate in the saturation region, the output impedance becomes small, the output differential signal (current signal) is inconsistent between the upper and lower parts, or the gain decreases. On the other hand, in Figure 6 , Figure 10 , Figure 11 In the example of the circuit structure of the amplifier shown, two MOS transistors are serially provided between the power supply potential terminal and the ground potential terminal. Therefore, even when the amplitude of the victim signal is small, it is easy to operate the input differential pair in the saturation region, so it is preferable.

[0087] The above transceiver system 1 includes: a transmission device 2, a reception device 3, a signal line 4, crosstalk cancellation circuits (XTC circuits) 10, 10A, buffers 11a, 11b, 11c, delay circuits 12, 12ab, 12ba, 12bc, 12cb, differential signal generation circuits 13, 13ab, 13ba, 13bc, 13cb, amplitude adjustment addition circuits 14, 14a, 14b, 14c, addition circuits 15, gain variable amplifiers 21, 21a, 21c, adders 22, ESD protection diodes 23, 24, inductors 25, 26, amplifiers 31 to 38, and conduction cutoff setting circuits 41 to 48.

[0088] In addition, the connection of the above elements is an electrical connection, the terminals on the input side of each element are input terminals, and the terminals on the output side are output terminals. As described above, the crosstalk cancellation circuit includes: a first signal line (for example, a transmission line of signal Db); a second signal line (for example, a transmission line of signal Dc) disposed adjacent to the first signal line; a delay circuit (for example, 12cb) electrically connected to the second signal line (for example, a transmission line of signal Dc); a differential circuit (for example, 13cb) electrically connected to the output terminal of the delay circuit 12cb; a gain variable amplifier (for example, 21c) electrically connected to the output terminal of the differential circuit 13cb; and an adder 22, which includes a first input terminal electrically connected to the first signal line (transmission line of signal Db) and a second input terminal electrically connected to the output terminal of the gain variable amplifier (21c).

[0089] In addition, the above crosstalk cancellation circuit further includes a first coil 25 serially connected to the first input terminal of the adder 22 and a second coil 26 serially connected to the output terminal of the adder 22.

[0090] In addition, the above crosstalk cancellation circuit further includes a first diode 23 electrically connected between the output terminal of the adder 22 and the power supply potential, and a second diode 24 electrically connected between the output terminal of the adder 22 and the ground potential. The cathode of the first diode 23 is connected to the power supply potential, and the anode of the first diode 23 is connected to the output terminal of the adder 22. The anode of the second diode 24 is connected to the ground potential, and the cathode of the second diode 24 is connected to the output terminal of the adder 22. The first diode 23 and the second diode 24 are connected such that current flows in the same direction.

Claims

1. A crosstalk cancellation circuit is provided in a transmitting device that transmits a plurality of signals to a receiving device via a plurality of signal lines. The crosstalk cancellation circuit includes: a delay circuit that adjusts the phase of a first signal among the plurality of signals; a differential signal generation circuit that generates a differential signal having a differential waveform of the first signal whose phase has been adjusted by the delay circuit; and an amplitude adjustment adder circuit that adjusts the amplitude of the differential signal generated by the differential signal generation circuit, uses the amplitude-adjusted differential signal as a current signal, and performs current addition of the amplitude-adjusted differential signal and a second signal among the plurality of signals, and outputs the added second signal.

2. The crosstalk cancellation circuit according to claim 1, wherein the amplitude adjustment adder circuit includes a plurality of amplifiers, each of the plurality of amplifiers having: an input terminal for inputting a voltage signal; and an output terminal that outputs a current signal corresponding to the voltage signal when set to be conductive and does not output a current signal when set to be non-conductive, inputs the differential signal generated by the differential signal generation circuit to the input terminals of the plurality of amplifiers respectively, performs current addition of the sum of the current signals output from the output terminals of the plurality of amplifiers and the second signal, and sets the amplitude adjustment amount of the differential signal by setting the conduction / non-conduction of the plurality of amplifiers respectively.

3. The crosstalk cancellation circuit according to claim 2, wherein, Each of the plurality of amplifiers has: a current source provided between a first potential terminal and the output terminal; a MOS transistor provided between a second potential terminal and the output terminal; and a capacitive element provided between the gate of the MOS transistor and the input terminal.

4. The crosstalk cancellation circuit according to claim 2, wherein each of the plurality of amplifiers has: a PMOS transistor provided between a power supply potential terminal and the output terminal; an NMOS transistor provided between a ground potential terminal and the output terminal; a first capacitive element provided between the gate of the PMOS transistor and the input terminal; and a second capacitive element provided between the gate of the NMOS transistor and the input terminal.

5. The crosstalk cancellation circuit according to claim 2, wherein the voltage signals respectively input to the plurality of amplifiers are differential signals composed of a first voltage signal and a second voltage signal, and the current signals output are differential signals composed of a first current signal and a second current signal, each of the plurality of amplifiers has: a first current source provided between a first potential terminal and a first output terminal that outputs the first current signal; a second current source provided between the first potential terminal and a second output terminal that outputs the second current signal; a third current source connected to a second potential terminal; a first MOS transistor having a gate connected to a first input terminal to which the first voltage signal is input and provided between the third current source and the first output terminal; and a second MOS transistor having a gate connected to a second input terminal to which the second voltage signal is input and provided between the third current source and the second output terminal.

6. The crosstalk cancellation circuit according to claim 2, wherein the voltage signals respectively input to the plurality of amplifiers are differential signals composed of a first voltage signal and a second voltage signal, and the current signals output are differential signals composed of a first current signal and a second current signal. The plurality of amplifiers each have: a first current source connected to the power supply potential terminal; a second current source connected to the ground potential terminal; a first PMOS transistor having a gate connected to a first input terminal to which the first voltage signal is input, and disposed between the first current source and a first output terminal for outputting the first current signal; a second PMOS transistor having a gate connected to a second input terminal to which the second voltage signal is input, and disposed between the first current source and a second output terminal for outputting the second current signal; a first NMOS transistor having a gate connected to the first input terminal, and disposed between the second current source and the first output terminal; and a second NMOS transistor having a gate connected to the second input terminal, and disposed between the second current source and the second output terminal.

7. A transmitting device comprising the crosstalk cancellation circuit according to claim 1.

8. A transceiver system comprising: the transmitting device according to claim 7; and a receiving device configured to receive a plurality of signals from the transmitting device.

9. A crosstalk cancellation circuit disposed in a transmitting device, the crosstalk cancellation circuit comprising: a first signal line; a second signal line disposed adjacent to the first signal line; a delay circuit electrically connected to the second signal line; a differentiating circuit electrically connected to an output terminal of the delay circuit; a variable gain amplifier electrically connected to an output terminal of the differentiating circuit; and an adder having: a first input terminal electrically connected to the first signal line; and a second input terminal electrically connected to an output terminal of the variable gain amplifier, the adder adding the input current signals.

10. The crosstalk cancellation circuit according to claim 9, wherein the crosstalk cancellation circuit further comprises: a first coil connected in series to the first input terminal of the adder; and a second coil connected in series to an output terminal of the adder.

11. The crosstalk cancellation circuit according to claim 10, wherein the crosstalk cancellation circuit further comprises: a first diode electrically connected between the output terminal of the adder and the power supply potential; and a second diode electrically connected between the output terminal of the adder and the ground potential.

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