KWP protocol communication bus high impedance circuit and equipment

Abstract

The embodiment of the present invention discloses a KWP protocol communication bus high impedance circuit and device, the circuit comprising: a positive logic pull-up circuit, a negative logic pull-down circuit, a pull-up switch control circuit and a pull-down switch control circuit. By setting a KWP protocol communication bus high impedance circuit comprising a positive logic pull-up circuit, a negative logic pull-down circuit, a pull-up switch control circuit and a pull-down switch control circuit, the effect of the KWP protocol signal output end of the KWP protocol communication bus high impedance circuit being in a high impedance state is achieved when the input enable control signal is at a low level.

Description

Technical Field

[0001] The present invention relates to the technical field of automobile equipment, and in particular to a KWP protocol communication bus high-impedance circuit and equipment. Background Art

[0002] Since the 1980s, when cars entered the era of electronic control unit (ECU), car manufacturers have begun to use ECU to monitor car control systems. However, the ECU and fault diagnosis equipment of each manufacturer are developed by each car manufacturer, and the diagnostic interface and communication method are different and cannot be used interchangeably. As a result, the automotive aftermarket has developed various comprehensive diagnostic equipment, which performs protocol scanning on the communication pins of the on-board diagnostic system (On-Board Diagnostic-16, OBD-16) of the car, analyzes and determines the protocol type of the car's electronic control system, and then realizes self-service diagnosis of various electronic control systems of multiple car series, which puts forward the need to realize multiple communication protocols on the same communication line. The current mainstream solution for switching multiple communication protocols is to use relays or analog switches. However, the problems of the above methods include: the relay solution has a large device size and a high price, which brings obstacles to the miniaturization of the equipment; in addition to the high price of the signal analog switch integrated circuit solution, the analog switch also has certain impedance and resistance and capacitance distribution parameters, which have a certain impact on the quality of the communication signal. Summary of the invention

[0003] Based on this, it is necessary to propose a KWP protocol communication bus high-impedance circuit and device to address the above problems. The purpose of the present invention is to achieve the effect that the KWP protocol signal output end of the KWP protocol communication bus high-impedance circuit is in a high-impedance state when the input enable control signal is at a low level by setting a KWP protocol communication bus high-impedance circuit including a positive logic pull-up circuit, a negative logic pull-down circuit, a pull-up switch control circuit and a pull-down switch control circuit.

[0004] In a first aspect, the present application provides a KWP protocol communication bus high-impedance circuit, the circuit comprising: a positive logic pull-up circuit, a negative logic pull-down circuit, a pull-up switch control circuit, and a pull-down switch control circuit;

[0005] One end of the positive logic pull-up circuit, one end of the negative logic pull-down circuit, and one end of the pull-up switch control circuit are all electrically connected to one end of the pull-down switch control circuit, and one end of the positive logic pull-up circuit, one end of the negative logic pull-down circuit, one end of the pull-up switch control circuit, and one end of the pull-down switch control circuit are all enable control signal input ends, the other end of the positive logic pull-up circuit is electrically connected to the other end of the negative logic pull-down circuit, and the other end of the positive logic pull-up circuit and the other end of the negative logic pull-down circuit are both KWP protocol signal output ends;

[0006] The other end of the pull-up switch control circuit is electrically connected to the third end of the positive logic pull-up circuit, and the other end of the pull-down switch control circuit is electrically connected to the third end of the negative logic pull-down circuit; the third end of the positive logic pull-up circuit is a pull-up end, and the third end of the negative logic pull-down circuit is a pull-down end;

[0007] When the preset enable control signal input to the enable control signal input terminal of the positive logic pull-up circuit and the enable control signal input terminal of the pull-up switch control circuit is at a low level and / or the preset enable control signal input to the enable control signal input terminal of the negative logic pull-down circuit and the enable control signal input terminal of the pull-down switch control circuit is at a low level, the KWP protocol signal output terminal of the positive logic pull-up circuit and / or the KWP protocol signal output terminal of the negative logic pull-down circuit is in a high impedance state.

[0008] Optionally, the positive logic pull-up circuit comprises: a first KWP protocol signal processing circuit and a positive logic pull-up control circuit;

[0009] One end of the first KWP protocol signal processing circuit is the enable control signal input end, the other end of the first KWP protocol signal processing circuit is electrically connected to one end of the positive logic pull-up control circuit, the other end of the positive logic pull-up control circuit is the KWP protocol signal output end, and the positive logic pull-up control circuit also includes the pull-up end.

[0010] Optionally, the first KWP protocol signal processing circuit includes: a first NOR gate, a second NOR gate and a first resistor;

[0011] The first input terminal of the first NOR gate is the enable control signal input terminal, and the first input terminal of the first NOR gate is also electrically connected to the second input terminal of the first NOR gate;

[0012] The first input end of the second NOR gate is electrically connected to the output end of the first NOR gate, the second input end of the second NOR gate is the KWP protocol signal input end, the second input end of the second NOR gate is also electrically connected to one end of the first resistor, the other end of the first resistor is the first preset voltage input end, and the output end of the second NOR gate is electrically connected to one end of the positive logic pull-up control circuit.

[0013] Optionally, the positive logic pull-up control circuit includes: a first triode, a second triode, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a first capacitor;

[0014] One end of the second resistor is grounded, the other end of the second resistor is electrically connected to one end of the third resistor and the output end of the second NOR gate, and the other end of the third resistor is electrically connected to the base of the first transistor and the collector of the second transistor;

[0015] The collector of the first transistor is electrically connected to one end of the fourth resistor and one end of the first capacitor at the same time, the collector of the first transistor is also the KWP protocol signal output end, the other end of the fourth resistor is the pull-up end, the other end of the first capacitor is grounded, the emitter of the first transistor is electrically connected to one end of the fifth resistor and the base of the second transistor at the same time, and the other end of the fifth resistor is electrically connected to the emitter of the second transistor and grounded.

[0016] Optionally, the pull-up switch control circuit includes: a sixth transistor, a field effect transistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third capacitor and a fourth capacitor;

[0017] One end of the twelfth resistor is electrically connected to one end of the thirteenth resistor, the other end of the twelfth resistor is grounded, one end of the thirteenth resistor electrically connected to the twelfth resistor is also the enable control signal input end, the other end of the thirteenth resistor is electrically connected to the base of the sixth transistor, and the emitter of the sixth transistor is grounded;

[0018] The collector of the sixth transistor is electrically connected to one end of the fourteenth resistor, and the other end of the fourteenth resistor is electrically connected to one end of the fifteenth resistor and the gate of the field effect transistor at the same time;

[0019] The other end of the fifteenth resistor is electrically connected to one end of the third capacitor, one end of the fourth capacitor and the source of the field effect transistor at the same time, and the other end of the fifteenth resistor is also a fourth preset voltage input end;

[0020] The other end of the third capacitor is electrically connected to the other end of the fourth capacitor and is grounded;

[0021] The drain of the field effect tube is electrically connected to the pull-up end of the positive logic pull-up circuit.

[0022] Optionally, the negative logic pull-down circuit includes: a second KWP protocol signal processing circuit and a negative logic pull-down control circuit;

[0023] One end of the second KWP protocol signal processing circuit is the enable control signal input end, the other end of the second KWP protocol signal processing circuit is electrically connected to one end of the negative logic pull-down control circuit, the other end of the negative logic pull-down control circuit is the KWP protocol signal output end, and the negative logic pull-down control circuit also includes the pull-down end and a third preset voltage input end.

[0024] Optionally, the second KWP protocol signal processing circuit includes: a third NOR gate, a fourth NOR gate and a second capacitor;

[0025] The first input terminal of the third NOR gate is the enable control signal input terminal, the first input terminal of the third NOR gate is also electrically connected to the second input terminal of the third NOR gate, the third NOR gate further comprises: a second preset voltage input terminal and a ground terminal, one terminal of the second capacitor is electrically connected to the second preset voltage input terminal of the third NOR gate, and the other terminal of the second capacitor is grounded;

[0026] The first input end of the fourth NOR gate is electrically connected to the output end of the third NOR gate, the second input end of the fourth NOR gate is the KWP protocol signal input end, and the output end of the fourth NOR gate is electrically connected to one end of the negative logic pull-down control circuit.

[0027] Optionally, the negative logic pull-down control circuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor;

[0028] One end of the sixth resistor is grounded, the other end of the sixth resistor is electrically connected to the output end of the fourth NOR gate and one end of the seventh resistor at the same time, the other end of the seventh resistor is electrically connected to the base of the third triode, the emitter of the third triode is grounded, and the collector of the third triode is electrically connected to one end of the eighth resistor;

[0029] The other end of the eighth resistor is electrically connected to one end of the ninth resistor, the collector of the fourth transistor and the base of the fifth transistor at the same time, the other end of the ninth resistor is electrically connected to the emitter of the fourth transistor and one end of the tenth resistor at the same time, one end of the tenth resistor is also the third preset voltage input end, the other end of the tenth resistor is electrically connected to the base of the fourth transistor and the emitter of the fifth transistor at the same time, the collector of the fifth transistor is electrically connected to one end of the eleventh resistor, one end of the eleventh resistor is also the KWP protocol signal output end, and the other end of the eleventh resistor is the pull-down end.

[0030] Optionally, the pull-down switch control circuit includes: a seventh transistor and a sixteenth resistor;

[0031] One end of the sixteenth resistor is the enable control signal input end, the other end of the sixteenth resistor is electrically connected to the base of the seventh transistor, the emitter of the seventh transistor is grounded, and the collector of the seventh transistor is electrically connected to the pull-down end of the negative logic pull-down circuit.

[0032] In a second aspect, the present application provides a KWP protocol communication bus high-impedance device, characterized in that the device includes any one of the KWP protocol communication bus high-impedance circuits in the first aspect embodiment.

[0033] The embodiments of the present invention have the following beneficial effects:

[0034] A KWP protocol communication bus high-impedance circuit and device of the present invention are adopted, and the circuit comprises: a positive logic pull-up circuit, a negative logic pull-down circuit, a pull-up switch control circuit and a pull-down switch control circuit; one end of the positive logic pull-up circuit, one end of the negative logic pull-down circuit, and one end of the pull-up switch control circuit are all electrically connected to one end of the pull-down switch control circuit, and one end of the positive logic pull-up circuit, one end of the negative logic pull-down circuit, one end of the pull-up switch control circuit and one end of the pull-down switch control circuit are all enable control signal input ends, the other end of the positive logic pull-up circuit is electrically connected to the other end of the negative logic pull-down circuit, and the other end of the positive logic pull-up circuit and the other end of the negative logic pull-down circuit are both KWP protocol signal output ends; the pull-up circuit The other end of the switch control circuit is electrically connected to the third end of the positive logic pull-up circuit, and the other end of the pull-down switch control circuit is electrically connected to the third end of the negative logic pull-down circuit; the third end of the positive logic pull-up circuit is a pull-up end, and the third end of the negative logic pull-down circuit is a pull-down end; when the preset enable control signal inputted into the enable control signal input end of the positive logic pull-up circuit and the enable control signal input end of the pull-up switch control circuit is low level and / or the preset enable control signal inputted into the enable control signal input end of the negative logic pull-down circuit and the enable control signal input end of the pull-down switch control circuit is low level, the KWP protocol signal output end of the positive logic pull-up circuit and / or the KWP protocol signal output end of the negative logic pull-down circuit is in a high impedance state. By setting a KWP protocol communication bus high impedance circuit including a positive logic pull-up circuit, a negative logic pull-down circuit, a pull-up switch control circuit and a pull-down switch control circuit, the effect of the KWP protocol signal output end of the KWP protocol communication bus high impedance circuit being in a high impedance state when the input enable control signal is low level is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] in:

[0037] Figure 1 This is a structural block diagram of a high-impedance circuit of a KWP protocol communication bus in an embodiment of the present application;

[0038] Figure 2 This is a structural block diagram of a positive logic pull-up circuit in an embodiment of the present application;

[0039] Figure 3 A circuit diagram of a first KWP protocol signal processing circuit in an embodiment of the present application;

[0040] Figure 4 A circuit diagram of a positive logic pull-up control circuit in an embodiment of the present application;

[0041] Figure 5 is a circuit diagram of a pull-up switch control circuit in an embodiment of the present application;

[0042] Figure 6 This is a structural block diagram of a negative logic pull-down circuit in an embodiment of the present application;

[0043] Figure 7 A circuit diagram of a second KWP protocol signal processing circuit in an embodiment of the present application;

[0044] Figure 8 A circuit diagram of a negative logic pull-down control circuit in an embodiment of the present application;

[0045] Fig. 9 is a circuit diagram of a pull-down switch control circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] See also Figure 1, is a structural block diagram of a high-impedance circuit of a KWP protocol communication bus in an embodiment of the present application, the circuit comprising: a positive logic pull-up circuit 102, a negative logic pull-down circuit 103, a pull-up switch control circuit 101 and a pull-down switch control circuit 104; one end of the positive logic pull-up circuit 102, one end of the negative logic pull-down circuit 103, and one end of the pull-up switch control circuit 101 are all electrically connected to one end of the pull-down switch control circuit 104 and one end of the positive logic pull-up circuit 102, one end of the negative logic pull-down circuit 103, one end of the pull-up switch control circuit 101 and one end of the pull-down switch control circuit 104 One end is the enable control signal input terminal LOGIC+EN / LOGIC-EN, the other end of the positive logic pull-up circuit 102 is electrically connected to the other end of the negative logic pull-down circuit 103, and the other end of the positive logic pull-up circuit 102 and the other end of the negative logic pull-down circuit 103 are both KWP protocol signal output terminals K; the other end of the pull-up switch control circuit 101 is electrically connected to the third end of the positive logic pull-up circuit 102, and the other end of the pull-down switch control circuit 104 is electrically connected to the third end of the negative logic pull-down circuit 103; the third end of the positive logic pull-up circuit 102 is the pull-up terminal K_PULL UP, the third end of the negative logic pull-down circuit 103 is the pull-down end K_PULL DOWN; when the preset enable control signal input terminal LOGIC+EN / LOGIC-EN of the positive logic pull-up circuit 102 and the enable control signal input terminal LOGIC+EN / LOGIC-EN of the pull-up switch control circuit 101 is low and / or the preset enable control signal input terminal LOGIC+EN / LOGIC-EN of the negative logic pull-down circuit 103 and the enable control signal input terminal LOGIC+EN / LOGIC-EN of the pull-down switch control circuit 104 is low, the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 and / or the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 is in a high impedance state.

[0048] In the embodiment of the present application, the types of enable control signals that can be independently input to the enable control signal input terminal LOGIC+EN / LOGIC-EN include two types: a positive logic enable control signal LOGIC+EN and a negative logic enable control signal LOGIC-EN. When the enable control signal input terminal LOGIC+EN / LOGIC-EN inputs the positive logic enable control signal LOGIC+EN, the circuit that the positive logic enable control signal LOGIC+EN enters is the positive logic pull-up circuit 102 and the pull-up switch control circuit 101, and the negative logic pull-down circuit 103 and the pull-down switch control circuit 104 are in an unused state, and when the positive logic enable control signal LOGIC+EN inputted at the enable control signal input terminal LOGIC+EN / LOGIC-EN is at a high level, the positive logic pull-up circuit 102 and the pull-up switch control circuit 101 are turned on, so that the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 has a KWP protocol signal output, while the negative logic pull-down circuit 103 and the pull-down switch control circuit 104 are both in a non-conducting state, then at this time, the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 is in a high impedance state, that is, the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 has no KWP protocol signal output Output; Since the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit is a KWP protocol signal output terminal K composed of the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 and the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 directly and electrically connected together, the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit outputs the KWP protocol signal transmitted from the positive logic pull-up circuit 102 at this time; when the positive logic enable control signal LOGIC+EN input by the enable control signal input terminal LOGIC+EN / LOGIC-EN is at a low level, the positive logic pull-up circuit 102 and the pull-up switch control circuit 101 are in a cut-off state, that is, the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 is in a high-impedance state, and the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 is also in a high-impedance state, therefore, the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit is in a high-impedance state.

[0049] When the negative logic enable control signal LOGIC-EN is input to the enable control signal input terminal LOGIC+EN / LOGIC-EN, the circuit into which the negative logic enable control signal LOGIC-EN enters is the negative logic pull-down circuit 103 and the pull-down switch control circuit 104, and the positive logic pull-up circuit 102 and the pull-up switch control circuit 101 are in an unused state, and when the negative logic enable control signal LOGIC-EN input to the enable control signal input terminal LOGIC+EN / LOGIC-EN is at a high level, the negative logic pull-down circuit 103 and the pull-down switch control circuit 104 are turned on, so that the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 has a KWP protocol signal output, while the positive logic pull-up circuit 102 and the pull-up switch control circuit 101 are both in a non-conducting state, then at this time, the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 is in a high impedance state, that is, the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 has no KWP protocol signal output Output; Since the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit is a KWP protocol signal output terminal K composed of the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 and the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 directly and electrically connected together, the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit outputs the KWP protocol signal transmitted from the negative logic pull-down circuit 103 at this time; when the negative logic enable control signal LOGIC-EN input by the enable control signal input terminal LOGIC+EN / LOGIC-EN is at a low level, the negative logic pull-down circuit 103 and the pull-down switch control circuit 104 are in a cut-off state, that is, the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 is in a high-impedance state, and the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 is also in a high-impedance state, therefore, the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit is in a high-impedance state.

[0050] In the embodiment of the present application, by setting a KWP protocol communication bus high-impedance circuit including a positive logic pull-up circuit 102, a negative logic pull-down circuit 103, a pull-up switch control circuit 101, and a pull-down switch control circuit 104, when different enable control signals are input to the enable control signal input terminal LOGIC+EN / LOGIC-EN, the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 or the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 outputs a corresponding KWP protocol signal, or the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 and the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 are both in a high-impedance state, and the KWP protocol of the positive logic pull-up circuit 102 will not be in a high-impedance state. The purpose is to achieve the situation where the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 and the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 simultaneously output the corresponding KWP protocol signal, thereby achieving the effect that even if the KWP protocol signal output terminal K of the positive logic pull-up circuit 102 and the KWP protocol signal output terminal K of the negative logic pull-down circuit 103 are directly connected together, there will be no signal confusion output by the KWP protocol signal output terminal K of the high-impedance circuit of the KWP protocol communication bus, and at the same time, the effect is achieved by inputting different enable control signals at the enable control signal input terminal LOGIC+EN / LOGIC-EN, so that the KWP protocol signal output terminal K of the high-impedance circuit of the KWP protocol communication bus can output the corresponding KWP protocol signal as needed or be in a high-impedance state.

[0051] In order to more clearly understand the technical solution of this application, Figure 2 As shown, it is a structural block diagram of the positive logic pull-up circuit in an embodiment of the present application, and the positive logic pull-up circuit 102 includes: a first KWP protocol signal processing circuit 201 and a positive logic pull-up control circuit 202; one end of the first KWP protocol signal processing circuit 201 is an enable control signal input terminal LOGIC+EN / LOGIC-EN, and the other end of the first KWP protocol signal processing circuit 201 is electrically connected to one end of the positive logic pull-up control circuit 202, and the other end of the positive logic pull-up control circuit 202 is a KWP protocol signal output terminal K, and the positive logic pull-up control circuit 202 also includes a pull-up terminal K_PULL UP.

[0052] Specifically, Figure 3As shown, it is a circuit diagram of the first KWP protocol signal processing circuit in an embodiment of the present application, and the first KWP protocol signal processing circuit 201 includes: a first NOR gate U11C, a second NOR gate U11B and a first resistor R12; the first input terminal 9 of the first NOR gate U11C is an enable control signal input terminal LOGIC+EN / LOGIC-EN, and the first input terminal 9 of the first NOR gate U11C is also electrically connected to the second input terminal 8 of the first NOR gate U11C; the first input terminal 6 of the second NOR gate U11B is electrically connected to the output terminal 10 of the first NOR gate U11C, the second input terminal 5 of the second NOR gate U11B is the KWP protocol signal input terminal KTXD3, the second input terminal 5 of the second NOR gate U11B is also electrically connected to one end of the first resistor R12, the other end of the first resistor R12 is a first preset voltage input terminal +3.3V, and the output terminal 4 of the second NOR gate U11B is electrically connected to one end of the positive logic pull-up control circuit 202.

[0053] In the embodiment of the present application, when the enable control signal input terminal LOGIC+EN / LOGIC-EN inputs the positive logic enable control signal LOGIC+EN, the positive logic enable control signal LOGIC+EN will enter the first input terminal 9 of the first NOR gate U11C of the first KWP protocol signal processing circuit 201. It can be understood that the first input terminal 9 of the first NOR gate U11C and the second input terminal 8 of the first NOR gate U11C are electrically connected together. Therefore, the positive logic enable control signal LOGIC+EN input to the second input terminal 8 of the first NOR gate U11C is the same as the positive logic enable control signal LOGIC+EN input to the first input terminal 9 of the first NOR gate U11C; when the positive logic enable control signal LOGIC+EN is at a high level , the enable control signal outputted from the output terminal 10 of the first NOR gate U11C is the positive logic enable control signal -LOGIC+EN which is the inverted positive logic enable control signal LOGIC+EN, and the inverted positive logic enable control signal -LOGIC+EN is a low level; since the first input terminal 6 of the second NOR gate U11B is electrically connected to the output terminal 10 of the first NOR gate U11C, the enable control signal inputted to the first input terminal 6 of the second NOR gate U11B is the inverted positive logic enable control signal -LOGIC+EN which is a low level, then at this time, the output terminal 4 of the second NOR gate U11B will output the KWP protocol signal inputted from the second input terminal 5 of the second NOR gate U11B and the KWP protocol signal will be inputted into the positive logic pull-up control circuit 202.

[0054] When the positive logic enable control signal LOGIC+EN is at a low level, the inverted positive logic enable control signal -LOGIC+EN outputted from the output terminal 10 of the first NOR gate U11C is at a high level, and the enable control signal inputted from the first input terminal 6 of the second NOR gate U11B is the inverted positive logic enable control signal -LOGIC+EN and is at a high level. At this time, regardless of the level of the KWP protocol signal inputted from the second input terminal 5 of the second NOR gate U11B, the output terminal 4 of the second NOR gate U11B will output a low level. Therefore, the input of the end of the positive logic pull-up control circuit 202 electrically connected to the output terminal 4 of the second NOR gate U11B is at a low level.

[0055] In the embodiment of the present application, by setting the first KWP protocol signal processing circuit 201 including the first NOR gate U11C and the second NOR gate U11B, when the positive logic enable control signal LOGIC+EN inputted at the enable control signal input terminal LOGIC+EN / LOGIC-EN is at a high level, the output end of the first KWP protocol signal processing circuit 201 outputs the KWP protocol signal, and when the positive logic enable control signal LOGIC+EN inputted at the enable control signal input terminal LOGIC+EN / LOGIC-EN is at a low level, the output end of the first KWP protocol signal processing circuit 201 outputs a low level.

[0056] Specifically, Figure 4 As shown, it is a circuit diagram of the positive logic pull-up control circuit in the embodiment of the present application, and the positive logic pull-up control circuit 202 includes: a first transistor Q7, a second transistor Q8, a second resistor R55, a third resistor R99, a fourth resistor R79, a fifth resistor R113 and a first capacitor C91; one end of the second resistor R55 is grounded, and the other end of the second resistor R55 is electrically connected to one end of the third resistor R99 and the output end 4 of the second NOR gate U11B at the same time, and the other end of the third resistor R99 is electrically connected to the base of the first transistor Q7 and the collector of the second transistor Q8 at the same time; the collector of the first transistor Q7 is electrically connected to one end of the fourth resistor R79 and one end of the first capacitor C91 at the same time, and the collector of the first transistor Q7 is also electrically connected to the KWP protocol signal output end K, and the other end of the fourth resistor R79 is the pull-up end K_PULL UP, the other end of the first capacitor C91 is grounded, the emitter of the first transistor Q7 is electrically connected to one end of the fifth resistor R113 and the base of the second transistor Q8, and the other end of the fifth resistor R113 is electrically connected to the emitter of the second transistor Q8 and grounded.

[0057] In the embodiment of the present application, when the output terminal 4 of the second NOR gate U11B outputs the KWP protocol signal, the first transistor Q7 in the positive logic pull-up control circuit 202 is in the on state, that is, the positive logic pull-up control circuit 202 is in the on state; when the output terminal 4 of the second NOR gate U11B outputs a low level, the first transistor Q7 in the positive logic pull-up control circuit 202 is in the off state, that is, the positive logic pull-up control circuit 202 is in the off state.

[0058] In the embodiment of the present application, by setting the first transistor Q7 in the positive logic pull-up control circuit 202, when a KWP protocol signal is input into the positive logic pull-up control circuit 202, the first transistor Q7 is in an on state, and when a low level signal is input into the positive logic pull-up control circuit 202, the first transistor Q7 is in an off state, thereby achieving the effect that the positive logic pull-up control circuit 202 can switch between the on and off states when there are different inputs.

[0059] Furthermore, if Figure 5 As shown, it is a circuit diagram of the pull-up switch control circuit in the embodiment of the present application, and the pull-up switch control circuit 101 includes: a sixth transistor Q4, a field effect transistor Q27, a twelfth resistor R11, a thirteenth resistor R10, a fourteenth resistor R53, a fifteenth resistor R52, a third capacitor C9 and a fourth capacitor C74; one end of the twelfth resistor R11 is electrically connected to one end of the thirteenth resistor R10, and the other end of the twelfth resistor R11 is grounded, and one end of the thirteenth resistor R10 electrically connected to the twelfth resistor R11 is also an enable control signal input terminal LOGIC+EN / LOGIC-EN, and the other end of the thirteenth resistor R10 is connected to the base of the sixth transistor Q4. The collector of the sixth triode Q4 is electrically connected to one end of the fourteenth resistor R53, and the other end of the fourteenth resistor R53 is electrically connected to one end of the fifteenth resistor R52 and the gate of the field effect transistor Q27; the other end of the fifteenth resistor R52 is electrically connected to one end of the third capacitor C9, one end of the fourth capacitor C74 and the source of the field effect transistor Q27, and the other end of the fifteenth resistor R52 is also the fourth preset voltage input terminal VO; the other end of the third capacitor C9 is electrically connected to the other end of the fourth capacitor C74 and is grounded; the drain of the field effect transistor Q27 is electrically connected to the pull-up terminal K_PULL UP of the positive logic pull-up circuit 102.

[0060] In the embodiment of the present application, when the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the positive logic enable control signal LOGIC+EN and is at a high level, the sixth transistor Q4 is in the on state. At this time, the pull-up switch control circuit 101 is in the on state, and the drain of the field effect transistor Q27 and the pull-up terminal K_PULL UP of the positive logic pull-up circuit 102 are also in the on state. At the same time, it can be seen from the above that when the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the positive logic enable control signal LOGIC+EN and is at a high level, the positive logic pull-up circuit 102 is also in the on state. Therefore, when the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the positive logic enable control signal LOGIC+EN and is at a high level, the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit has a KWP protocol signal output.

[0061] When the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the positive logic enable control signal LOGIC+EN and is at a low level, the sixth transistor Q4 is in a cut-off state. At this time, the pull-up switch control circuit 101 is in a cut-off state, and the drain of the field effect transistor Q27 and the pull-up terminal K_PULL UP of the positive logic pull-up circuit 102 are also in a cut-off state. At the same time, it can be seen from the above that when the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the positive logic enable control signal LOGIC+EN and is at a low level, the positive logic pull-up circuit 102 is also in a cut-off state. Therefore, when the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the positive logic enable control signal LOGIC+EN and is at a low level, the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit is in a high-impedance state.

[0062] In the embodiment of the present application, by setting the first KWP protocol signal processing circuit 201, the positive logic pull-up control circuit 202 and the pull-up switch control circuit 101, when the enable control signal input to the enable control signal input terminal LOGIC+EN / LOGIC-EN of the KWP protocol communication bus high-impedance circuit is the positive logic enable control signal LOGIC+EN and is at a low level, the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit is in a high-impedance state.

[0063] In order to more clearly understand the technical solution of this application, Figure 6As shown, it is a structural block diagram of the negative logic pull-down circuit in an embodiment of the present application. The negative logic pull-down circuit 103 includes: a second KWP protocol signal processing circuit 601 and a negative logic pull-down control circuit 602; one end of the second KWP protocol signal processing circuit 601 is an enable control signal input terminal LOGIC+EN / LOGIC-EN, and the other end of the second KWP protocol signal processing circuit 601 is electrically connected to one end of the negative logic pull-down control circuit 602, and the other end of the negative logic pull-down control circuit 602 is a KWP protocol signal output terminal K. The negative logic pull-down control circuit 602 also includes a pull-down terminal K_PULL DOWN and a third preset voltage input terminal VO.

[0064] Specifically, Figure 7 As shown, it is a circuit diagram of the second KWP protocol signal processing circuit in an embodiment of the present application. The second KWP protocol signal processing circuit 601 includes: a third NOR gate U11A, a fourth NOR gate U11D and a second capacitor C75; the first input terminal 2 of the third NOR gate U11A is an enable control signal input terminal LOGIC+EN / LOGIC-EN, the first input terminal 2 of the third NOR gate U11A is also electrically connected to the second input terminal 3 of the third NOR gate U11A, and the third NOR gate U11A also includes: a second The preset voltage input terminal +5.0V and the ground terminal, one end of the second capacitor C75 is electrically connected to the second preset voltage input terminal +5.0V of the third NOR gate U11A, and the other end of the second capacitor C75 is grounded; the first input terminal 12 of the fourth NOR gate U11D is electrically connected to the output terminal 1 of the third NOR gate U11A, the second input terminal 11 of the fourth NOR gate U11D is the KWP protocol signal input terminal KTXD3, and the output terminal 13 of the fourth NOR gate U11D is electrically connected to one end of the negative logic pull-down control circuit 602.

[0065] In the embodiment of the present application, when the enable control signal input terminal LOGIC+EN / LOGIC-EN inputs the negative logic enable control signal LOGIC-EN, the negative logic enable control signal LOGIC-EN will enter the first input terminal 2 of the third NOR gate U11A of the second KWP protocol signal processing circuit 601. It can be understood that the first input terminal 2 of the third NOR gate U11A and the second input terminal 3 of the third NOR gate U11A are electrically connected together. Therefore, the negative logic enable control signal LOGIC-EN input to the second input terminal 3 of the third NOR gate U11A is the same as the negative logic enable control signal LOGIC-EN input to the first input terminal 2 of the third NOR gate U11A; when the negative logic enable control signal LOGIC-EN is at a high level, The enable control signal output from the output terminal 1 of the third NOR gate U11A is the negative logic enable control signal -LOGIC-EN after the negative logic enable control signal LOGIC-EN is inverted, and the inverted negative logic enable control signal -LOGIC-EN is a low level; since the first input terminal 12 of the fourth NOR gate U11D is electrically connected to the output terminal 1 of the third NOR gate U11A, the enable control signal input to the first input terminal 12 of the fourth NOR gate U11D is the inverted negative logic enable control signal -LOGIC-EN and is a low level, then at this time, the output terminal 13 of the fourth NOR gate U11D will output the KWP protocol signal input from the second input terminal 11 of the fourth NOR gate U11D and the KWP protocol signal will be input to the negative logic pull-down control circuit 602.

[0066] When the negative logic enable control signal LOGIC-EN is at a low level, the inverted negative logic enable control signal -LOGIC-EN output from the output terminal 1 of the third NOR gate U11A is at a high level, and the enable control signal input to the first input terminal 12 of the fourth NOR gate U11D is the inverted negative logic enable control signal -LOGIC-EN and is at a high level. At this time, no matter how high or low the level of the KWP protocol signal input to the second input terminal 11 of the fourth NOR gate U11D is, the output terminal 13 of the fourth NOR gate U11D will output a low level. Therefore, the input of the end of the negative logic pull-down control circuit 602 electrically connected to the output terminal 13 of the fourth NOR gate U11D is at a low level.

[0067] In the embodiment of the present application, by setting the second KWP protocol signal processing circuit 601 including the third NOR gate U11A and the fourth NOR gate U11D, when the negative logic enable control signal LOGIC-EN inputted at the enable control signal input terminal LOGIC+EN / LOGIC-EN is at a high level, the output end of the second KWP protocol signal processing circuit 601 outputs the KWP protocol signal, and when the negative logic enable control signal LOGIC-EN inputted at the enable control signal input terminal LOGIC+EN / LOGIC-EN is at a low level, the output end of the second KWP protocol signal processing circuit 601 outputs a low level.

[0068] Specifically, Figure 8 As shown, it is a circuit diagram of the negative logic pull-down control circuit in the embodiment of the present application, and the negative logic pull-down control circuit 602 includes: a third transistor Q9, a fourth transistor Q20, a fifth transistor Q21, a sixth resistor R121, a seventh resistor R120, an eighth resistor R119, a ninth resistor R115, a tenth resistor R116, and an eleventh resistor R122; one end of the sixth resistor R121 is grounded, and the other end of the sixth resistor R121 is electrically connected to the output end 13 of the fourth NOR gate U11D and one end of the seventh resistor R120 at the same time, and the other end of the seventh resistor R120 is electrically connected to the base of the third transistor Q9, the emitter of the third transistor Q9 is grounded, and the collector of the third transistor Q9 is electrically connected to one end of the eighth resistor R119. The other end of the eighth resistor R119 is electrically connected to one end of the ninth resistor R115, the collector of the fourth triode Q20 and the base of the fifth triode Q21, the other end of the ninth resistor R115 is electrically connected to the emitter of the fourth triode Q20 and one end of the tenth resistor R116, one end of the tenth resistor R116 is also the third preset voltage input terminal VO, the other end of the tenth resistor R116 is electrically connected to the base of the fourth triode Q20 and the emitter of the fifth triode Q21, the collector of the fifth triode Q21 is electrically connected to one end of the eleventh resistor R122, one end of the eleventh resistor R122 is also the KWP protocol signal output terminal K, and the other end of the eleventh resistor R122 is the pull-down terminal K_PULL DOWN.

[0069] In the embodiment of the present application, when the output terminal 13 of the fourth NOR gate U11D outputs the KWP protocol signal, the third transistor Q9 in the negative logic pull-down control circuit 602 is in the on state, that is, the negative logic pull-down control circuit 602 is in the on state; when the output terminal 13 of the fourth NOR gate U11D outputs a low level, the third transistor Q9 in the negative logic pull-down control circuit 602 is in the off state, that is, the negative logic pull-down control circuit 602 is in the off state.

[0070] In the embodiment of the present application, by setting the third transistor Q9 in the negative logic pull-down control circuit 602, when a KWP protocol signal is input into the negative logic pull-down control circuit 602, the third transistor Q9 is in an on state, and when a low level is input into the negative logic pull-down control circuit 602, the third transistor Q9 is in an off state, thereby achieving the effect that the negative logic pull-down control circuit 602 can switch between the on and off states when there are different inputs.

[0071] Furthermore, if Fig. 9 As shown, it is a circuit diagram of the pull-down switch control circuit in the embodiment of the present application, and the pull-down switch control circuit 104 includes: a seventh transistor Q3 and a sixteenth resistor R111; one end of the sixteenth resistor R111 is an enable control signal input terminal LOGIC+EN / LOGIC-EN, the other end of the sixteenth resistor R111 is electrically connected to the base of the seventh transistor Q3, the emitter of the seventh transistor Q3 is grounded, and the collector of the seventh transistor Q3 is electrically connected to the pull-down terminal K_PULL DOWN of the negative logic pull-down circuit 103.

[0072] In the embodiment of the present application, when the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the negative logic enable control signal LOGIC-EN and is at a high level, the seventh transistor Q3 is in an on state. At this time, the pull-down switch control circuit 104 is in an on state, and the collector of the seventh transistor Q3 and the pull-down terminal K_PULL DOWN of the negative logic pull-down circuit 103 are also in an on state at the electrical connection point. At the same time, it can be seen from the above that when the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the negative logic enable control signal LOGIC-EN and is at a high level, the negative logic pull-down circuit 103 is also in an on state. Therefore, when the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the negative logic enable control signal LOGIC-EN and is at a high level, the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit has a KWP protocol signal output.

[0073] When the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the negative logic enable control signal LOGIC-EN and is at a low level, the seventh transistor Q3 is in a cut-off state. At this time, the pull-down switch control circuit 104 is in a cut-off state, and the collector of the seventh transistor Q3 and the pull-down terminal K_PULLDOWN of the negative logic pull-down circuit 103 are also in a cut-off state. At the same time, it can be seen from the above that when the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the negative logic enable control signal LOGIC-EN and is at a low level, the negative logic pull-down circuit 103 is also in a cut-off state. Therefore, when the enable control signal inputted by the enable control signal input terminal LOGIC+EN / LOGIC-EN is the negative logic enable control signal LOGIC-EN and is at a low level, the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit is in a high-impedance state.

[0074] In the embodiment of the present application, by setting the second KWP protocol signal processing circuit 601, the negative logic pull-down control circuit 602 and the pull-down switch control circuit 104, when the enable control signal input to the enable control signal input terminal LOGIC+EN / LOGIC-EN of the KWP protocol communication bus high-impedance circuit is the negative logic enable control signal LOGIC-EN and is at a low level, the KWP protocol signal output terminal K of the KWP protocol communication bus high-impedance circuit is in a high-impedance state.

[0075] In one embodiment, the present application provides a KWP protocol communication bus high impedance device, the device comprising: Figures 1 to 9 The KWP protocol communication bus high-impedance circuit in any one of the embodiments.

[0076] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A KWP protocol communication bus high impedance circuit, characterized in that: The circuit comprises: a positive logic pull-up circuit, a negative logic pull-down circuit, a pull-up switch control circuit and a pull-down switch control circuit; One end of the positive logic pull-up circuit, one end of the negative logic pull-down circuit, and one end of the pull-up switch control circuit are all electrically connected to one end of the pull-down switch control circuit, and one end of the positive logic pull-up circuit, one end of the negative logic pull-down circuit, one end of the pull-up switch control circuit, and one end of the pull-down switch control circuit are all enable control signal input ends, the other end of the positive logic pull-up circuit is electrically connected to the other end of the negative logic pull-down circuit, and the other end of the positive logic pull-up circuit and the other end of the negative logic pull-down circuit are both KWP protocol signal output ends; The other end of the pull-up switch control circuit is electrically connected to the third end of the positive logic pull-up circuit, and the other end of the pull-down switch control circuit is electrically connected to the third end of the negative logic pull-down circuit; the third end of the positive logic pull-up circuit is a pull-up end, and the third end of the negative logic pull-down circuit is a pull-down end; When the preset enable control signal input to the enable control signal input terminal of the positive logic pull-up circuit and the enable control signal input terminal of the pull-up switch control circuit is at a low level and / or the preset enable control signal input to the enable control signal input terminal of the negative logic pull-down circuit and the enable control signal input terminal of the pull-down switch control circuit is at a low level, the KWP protocol signal output terminal of the positive logic pull-up circuit and / or the KWP protocol signal output terminal of the negative logic pull-down circuit is in a high impedance state, wherein the preset enable control signal is a positive logic enable control signal or a negative logic enable control signal.

2. The KWP protocol communication bus high impedance circuit according to claim 1, characterized in that: The positive logic pull-up circuit comprises: a first KWP protocol signal processing circuit and a positive logic pull-up control circuit; One end of the first KWP protocol signal processing circuit is the enable control signal input end, the other end of the first KWP protocol signal processing circuit is electrically connected to one end of the positive logic pull-up control circuit, the other end of the positive logic pull-up control circuit is the KWP protocol signal output end, and the positive logic pull-up control circuit also includes the pull-up end.

3. The KWP protocol communication bus high impedance circuit according to claim 2, characterized in that: The first KWP protocol signal processing circuit includes: a first NOR gate, a second NOR gate and a first resistor; The first input terminal of the first NOR gate is the enable control signal input terminal, and the first input terminal of the first NOR gate is also electrically connected to the second input terminal of the first NOR gate; The first input end of the second NOR gate is electrically connected to the output end of the first NOR gate, the second input end of the second NOR gate is the KWP protocol signal input end, the second input end of the second NOR gate is also electrically connected to one end of the first resistor, the other end of the first resistor is the first preset voltage input end, and the output end of the second NOR gate is electrically connected to one end of the positive logic pull-up control circuit.

4. The KWP protocol communication bus high impedance circuit according to claim 3, characterized in that: The positive logic pull-up control circuit comprises: a first triode, a second triode, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a first capacitor; One end of the second resistor is grounded, the other end of the second resistor is electrically connected to one end of the third resistor and the output end of the second NOR gate, and the other end of the third resistor is electrically connected to the base of the first transistor and the collector of the second transistor; The collector of the first transistor is electrically connected to one end of the fourth resistor and one end of the first capacitor at the same time, the collector of the first transistor is also the KWP protocol signal output end, the other end of the fourth resistor is the pull-up end, the other end of the first capacitor is grounded, the emitter of the first transistor is electrically connected to one end of the fifth resistor and the base of the second transistor at the same time, and the other end of the fifth resistor is electrically connected to the emitter of the second transistor and grounded.

5. The KWP protocol communication bus high impedance circuit according to claim 4, characterized in that: The pull-up switch control circuit includes: a sixth transistor, a field effect transistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third capacitor and a fourth capacitor; One end of the twelfth resistor is electrically connected to one end of the thirteenth resistor, the other end of the twelfth resistor is grounded, one end of the thirteenth resistor electrically connected to the twelfth resistor is also the enable control signal input end, the other end of the thirteenth resistor is electrically connected to the base of the sixth transistor, and the emitter of the sixth transistor is grounded; The collector of the sixth transistor is electrically connected to one end of the fourteenth resistor, and the other end of the fourteenth resistor is electrically connected to one end of the fifteenth resistor and the gate of the field effect transistor at the same time; The other end of the fifteenth resistor is electrically connected to one end of the third capacitor, one end of the fourth capacitor and the source of the field effect transistor at the same time, and the other end of the fifteenth resistor is also a fourth preset voltage input end; The other end of the third capacitor is electrically connected to the other end of the fourth capacitor and is grounded; The drain of the field effect tube is electrically connected to the pull-up end of the positive logic pull-up circuit.

6. The KWP protocol communication bus high impedance circuit according to claim 1, characterized in that: The negative logic pull-down circuit comprises: a second KWP protocol signal processing circuit and a negative logic pull-down control circuit; One end of the second KWP protocol signal processing circuit is the enable control signal input end, the other end of the second KWP protocol signal processing circuit is electrically connected to one end of the negative logic pull-down control circuit, the other end of the negative logic pull-down control circuit is the KWP protocol signal output end, and the negative logic pull-down control circuit also includes the pull-down end and a third preset voltage input end.

7. The KWP protocol communication bus high impedance circuit according to claim 6, characterized in that: The second KWP protocol signal processing circuit includes: a third NOR gate, a fourth NOR gate and a second capacitor; The first input terminal of the third NOR gate is the enable control signal input terminal, the first input terminal of the third NOR gate is also electrically connected to the second input terminal of the third NOR gate, the third NOR gate further comprises: a second preset voltage input terminal and a ground terminal, one terminal of the second capacitor is electrically connected to the second preset voltage input terminal of the third NOR gate, and the other terminal of the second capacitor is grounded; The first input end of the fourth NOR gate is electrically connected to the output end of the third NOR gate, the second input end of the fourth NOR gate is the KWP protocol signal input end, and the output end of the fourth NOR gate is electrically connected to one end of the negative logic pull-down control circuit.

8. The KWP protocol communication bus high impedance circuit according to claim 7, characterized in that: The negative logic pull-down control circuit comprises: a third transistor, a fourth transistor, a fifth transistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor; One end of the sixth resistor is grounded, the other end of the sixth resistor is electrically connected to the output end of the fourth NOR gate and one end of the seventh resistor at the same time, the other end of the seventh resistor is electrically connected to the base of the third triode, the emitter of the third triode is grounded, and the collector of the third triode is electrically connected to one end of the eighth resistor; The other end of the eighth resistor is electrically connected to one end of the ninth resistor, the collector of the fourth transistor and the base of the fifth transistor at the same time, the other end of the ninth resistor is electrically connected to the emitter of the fourth transistor and one end of the tenth resistor at the same time, one end of the tenth resistor is also the third preset voltage input end, the other end of the tenth resistor is electrically connected to the base of the fourth transistor and the emitter of the fifth transistor at the same time, the collector of the fifth transistor is electrically connected to one end of the eleventh resistor, one end of the eleventh resistor is also the KWP protocol signal output end, and the other end of the eleventh resistor is the pull-down end.

9. The KWP protocol communication bus high impedance circuit according to claim 8, characterized in that: The pull-down switch control circuit comprises: a seventh transistor and a sixteenth resistor; One end of the sixteenth resistor is the enable control signal input end, the other end of the sixteenth resistor is electrically connected to the base of the seventh transistor, the emitter of the seventh transistor is grounded, and the collector of the seventh transistor is electrically connected to the pull-down end of the negative logic pull-down circuit.

10. A KWP protocol communication bus high impedance device, characterized in that: The device comprises the KWP protocol communication bus high impedance circuit as claimed in any one of claims 1 to 9.

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