In-memory computing, high-density arrays

Abstract

The present disclosure relates to in-memory computing, high-density arrays. A memory cell to perform in-memory computing operations includes a pair of cross-coupled inverters and a pair of transistors to selectively perform read / write / hold operations associated with a logic state of the pair of cross-coupled inverters. The memory cell further includes a set of transistors coupled to the pair of cross-coupled inverters and symmetrically arranged with respect to the pair of cross-coupled inverters. An output node of the memory cell is at a terminal of the set of transistors and provides an output based on logic states of the pair of cross-coupled inverters and an input node disposed between pairs of the set of transistors. An array of memory cells can be generated with high-density arrangements of memory cells capable of performing in-memory computing operations. The memory cells can be arranged as a neural network including a set of networks of memory cells to provide a logic output operation based on logic states of respective memory cells.

Description

Technical Field

[0001] This disclosure relates to the field of static random access memory (SRAM), and more specifically to SRAM for performing in-memory computation. Background Technology

[0002] Machine learning and other computing applications involve performing systematic computations on stored or streaming data. Multiply-accumulate (MAC) cells have been used to perform large-scale computations on diverse datasets. MAC cells can be systematically organized to reduce interconnect lengths and achieve higher-density arrays. In the context of SRAM, some previously implemented techniques involved adding MAC computation slices within the SRAM array structure to aid processing. However, these solutions remain digital and involve full-swing signal switching, which can consume significant amounts of power. While analog computing circuitry can be implemented to reduce power consumption, this circuitry would interrupt the SRAM array structure, thus reducing array density.

[0003] One proposed solution uses an eight-transistor SRAM cell to implement in-memory computation. This solution encounters low-voltage battery instability and other operational issues associated with the two-port architecture. To date, designing a stable, low-power architecture for SRAM to enable in-memory computation has proven to be a difficult challenge. Summary of the Invention

[0004] This disclosure includes embodiments of a memory cell with in-memory computing capabilities. The memory cell includes ten transistors arranged to facilitate data storage and logical operations. A first set of transistors in the memory cell stores a first logic state and a complementary first logic state, and a second set of transistors is gate-coupled to the first set of transistors. A second logic state and a complementary second logic state are provided at nodes between adjacent pairs of the second set of transistors. The second set of transistors is coupled to an output node that provides a set of outputs for the memory cell. Each output provided at the output node corresponds to a logical operation involving two or more logic states selected from the first logic state, the complementary first logic state, the second logic state, and the complementary second logic state. This memory cell further helps to reduce vulnerability to data corruption.

[0005] This disclosure also includes embodiments of memory cell layouts. The memory cell layout includes a set of active regions and a set of gate regions extending in a direction tangential to each other. The memory cell layout enables the construction of high-density memory cell arrays. This disclosure also includes embodiments of neural networks comprising multiple memory cell networks, each including a set of memory cells with in-memory computing capabilities and a sense amplifier for generating an output based on a small-swing signal detected at the output of the set of memory cells. The outputs of the memory cells can be coupled together for various combinations of logical operations. Attached Figure Description

[0006] Figure 1 A schematic diagram of a memory cell according to one or more embodiments is shown;

[0007] Figure 2 An illustration is provided according to one or more embodiments. Figure 1 The first layout of the memory cells;

[0008] Figure 3 An illustration is provided according to one or more embodiments. Figure 1 The second layout of the memory cells;

[0009] Figure 4 An illustration is provided according to one or more embodiments. Figure 3 The connection diagram of the second layout;

[0010] Figure 5 A second schematic diagram of a memory cell according to one or more embodiments is shown;

[0011] Figure 6 An illustration is provided according to one or more embodiments. Figure 5 The first layout of the memory cells;

[0012] Figure 7 An illustration is provided according to one or more embodiments. Figure 5 The interconnection of memory cells; and

[0013] Figure 8 A neural network comprising a plurality of memory cell networks, each memory cell network including memory cells, is illustrated according to one or more embodiments. Detailed Implementation

[0014] The following description and accompanying drawings set forth certain specific details in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that the disclosed embodiments may be practiced without one or more of these specific details, or in different combinations with other methods, components, devices, materials, etc. In other instances, well-known structures or components associated with the environment of this disclosure (including, but not limited to, communication systems and networks and their surroundings) are not shown or described to avoid unnecessarily obscuring the description of the embodiments. Furthermore, the various embodiments may be methods, systems, or devices. Thus, the various embodiments may be entirely hardware embodiments.

[0015] Throughout the specification, claims, and drawings, the following terms take on their explicitly associated meanings unless the context clearly indicates otherwise. The term “ herein” refers to the specification, claims, and drawings associated with this application. The phrases “in one embodiment,” “in another embodiment,” “in various embodiments,” “in some embodiments,” “in other embodiments,” and their variations refer to one or more features, structures, functions, limitations, or characteristics of this disclosure and are not limited to the same or different embodiments unless the context clearly indicates otherwise. As used herein, the term “or” is an inclusive “or” operator and is equivalent to the phrases “A or B or both” or “A or B or C, or any combination thereof,” and similarly treats lists with additional elements. The term “based on” is not exclusive and allows for reliance on additional features, functions, aspects, or undescribed limitations unless the context clearly indicates otherwise. Furthermore, throughout the specification, the meanings of “an” and “the” include both singular and plural references.

[0016] Unless otherwise indicated or contradicted by the context, references to the term “group” (e.g., “a set of items”) as used herein should be interpreted as a non-empty collection comprising one or more components or instances.

[0017] As used herein, the term "node" refers to a point in a circuit where the terminals of two or more circuit elements are connected or can be connected. Unless otherwise indicated or contradicted by the context, a node is understood to refer to a point in the circuit outside the circuit elements.

[0018] Figure 1A schematic diagram of an SRAM cell 100 with in-memory computing capability according to one or more embodiments is shown. The SRAM cell 100 includes ten transistors (10T) arranged to facilitate data storage and in-memory computing capability. The memory cell 100 includes a first inverter 102 and a second inverter 104 cross-coupled to each other. Specifically, the output of the first inverter 102 is coupled to the input of the second inverter 104 at a first node 106 of the SRAM cell 100, and the output of the second inverter 104 is coupled to the input of the first inverter 102 at a second node 108 of the cell 100.

[0019] The first inverter 102 and the second inverter 104 may each be a complementary metal-oxide-semiconductor field-effect transistor (CMOS) inverter comprising a pair of complementary transistors (e.g., one p-type and one n-type), the pair of complementary transistors having a common coupled gate as an input node, and an output node with source-to-drain terminal connections between the transistor pairs. Therefore, the first inverter 102 includes a first transistor and a second transistor of the memory cell 100, and the second inverter 104 includes a third transistor and a fourth transistor of the memory cell 100. The first inverter 102 and the second inverter 104 may be implemented using other inverter topologies, such as transistor-to-transistor logic or other logic gate architectures, which may employ different types of transistors or more transistors.

[0020] The first inverter 102 and the second inverter 104 form a logic state D and a complementary logic state for storing the memory cell 100. The storage element. Logic state D and complementary logic state. These correspond together to the data bits stored in memory cell 100. Memory cell 100 also includes a fifth transistor 110 and a sixth transistor 112 for processing logic state D and complementary logic state D. Data is selectively read from or written to. The fifth transistor 110 has a first terminal coupled to the second node 108, a second terminal coupled to bit line BL, and a gate terminal coupled to word line WL. The sixth transistor 112 has a first terminal coupled to the first node 106, a second terminal coupled to the complementary bit line BLB, and a gate terminal coupled to word line WL. The logic state of the data on the complementary bit line BLB is inverted relative to the logic state of the data on bit line BL.

[0021] Memory cell 100 includes a set of internally gate-coupled transistors symmetrically positioned around a first inverter 102, a second inverter 104, a fifth transistor 110, and a sixth transistor 112. Specifically, memory cell 100 includes a seventh transistor 114 and an eighth transistor 116 coupled in series between a first output node 122 and a second output node 124 of memory cell 100. Memory cell 100 also includes a ninth transistor 118 and a tenth transistor 120 coupled in series between a third output node 126 and a fourth output node 128 of memory cell 100. Memory cell 100 may provide different logic outputs at each of the output nodes 122, 124, 126, and 128 based on the logic state of the other nodes in memory cell 100, as described in more detail below.

[0022] The seventh transistor 114 has a first terminal 130 coupled to the first output node 122, a second terminal 132 coupled to the third node 134 of the memory cell 100, and a gate terminal 136 coupled to the second node 108. The eighth transistor has a first node 138 coupled to the third node 134, a second terminal 140 coupled to the second output node 124, and a gate terminal 142 coupled to the first node 106. The third node 134 defines a node between the second terminal 132 of the co-coupled seventh transistor 114 and the first terminal 138 of the eighth transistor 116. A second logic state A is provided at the third node 134, which can be independent of logic state D and complementary logic states.

[0023] The ninth transistor 118 has a first terminal 144 coupled to the third output node 126, a second terminal coupled to the fourth node 148, and a gate terminal 150 coupled to the second node 108. The tenth transistor 120 has a first terminal 152 coupled to the fourth node 148, a second terminal 154 coupled to the fourth output node 128, and a gate terminal 156 coupled to the first node 106. Complementary second logic state It is provided at the fourth node 148 and has a logic state opposite to the second logic state A.

[0024] The seventh transistor 114, the eighth transistor 116, the ninth transistor 118, and the tenth transistor 120 are gate-coupled, which provides several benefits. Specifically, the gate terminals 136 and 150 of the seventh transistor 114 and the ninth transistor 118 are jointly coupled to the second node 108 of the memory cell 100. The gate terminals 142 and 156 of the eighth transistor 116 and the tenth transistor 120 are jointly coupled to the first node 106 of the memory cell 100. Coupling the gate terminals of the transistors to internal nodes of the memory cell 100, rather than exposing the gate terminals for external access, improves the robustness of the memory cell 100 by promoting reduced vulnerability to data corruption.

[0025] The logic state of the second logic state (and the complementary second logic state as a result) can be selectively controlled by input to memory cell 100. In some embodiments, the memory unit 100 may include controls for a second logic state A and a complementary second logic state. One or more inputs to the logic state. Third node 134 and fourth node 148 may be coupled to one or more lines, through which voltage signals are provided to drive the second logic state A and the complementary second logic state. The logic level. In some embodiments, the second logic state A and the complementary second logic state... It can be controlled by an associated system (such as a neural network or machine learning system). In some embodiments, the second logical state A and the complementary second logical state... This can correspond to a logic state stored in another memory cell within a memory cell array including memory cell 100. For example, a second logic state A and a complementary second logic state. It can correspond to the logical state of the adjacent memory cell of memory cell 100.

[0026] The first output node 122, the second output node 124, the third output node 126, and the fourth output node 128 are each based on logic state D and complementary logic state. Second logical state A and complementary second logical state A combination of one or more logical states in the memory cell 100 is used to provide a logical output. The output of memory cell 100 at the first output node 122 can be... It has the following truth table, where Q is the output at the first output node 122:

[0027] A D Q 0 0 1 0 1 0 1 0 1 1 1 1

[0028] The output of memory cell 100 at the second output node 124 can be A+D, and it has the following truth table, where Q is the output of the second output node 124:

[0029] A D Q 0 0 0 0 1 1 1 0 1 1 1 1

[0030] The output of memory cell 100 at the third output node 126 can be It has the following truth table, where Q is the output at the third output node 126:

[0031] A D Q 0 0 1 0 1 1 1 0 1 1 1 0

[0032] The output of memory cell 100 at the fourth output node 128 can be It has the following truth table, where Q is the output at the fourth output node 128:

[0033] A D Q 0 0 1 0 1 1 1 0 0 1 1 1

[0034] The aforementioned logic outputs are non-limiting examples of numerous logic operations that can be implemented via the structure of memory cell 100. The logic operations performed by memory cell 100 can be modified by changing the transistor types of the seventh transistor 114, the eighth transistor 116, the ninth transistor 118, or the tenth transistor 120. Different nodes of memory cell 100 can be connected together to perform other logic operations. For example, the first output node 122 and the fourth output node 128 can be connected together to perform an XOR or XNOR operation involving logic state D and the second logic state A. The XOR operation has the following truth table provided by the output nodes directly coupled together from the first output node 122 and the fourth output node 128:

[0035] A D Q 0 0 0 0 1 1 1 0 1 1 1 0

[0036] As another example, the second output node 124 and the third output node 126 can be connected together to perform an XNOR operation involving logic state D and the second logic state A. The XNOR operation has the following truth table provided by the output nodes where the second output node 124 and the third output node 126 are directly coupled together:

[0037] A D Q 0 0 1 0 1 0 1 0 0 1 1 1

[0038] Those skilled in the art will understand that other logical operations (e.g., NAND operations) can be implemented by coupling three or more of the output nodes (e.g., the first output node 122, the second output node 124, and the fourth output node 128).

[0039] The structure of memory cell 100 also facilitates low power consumption while enabling various types of in-memory computational logic operations. For example, a small voltage swing can be used to perform in-memory computational logic operations in memory cell 100, which reduces power consumption compared to other SRAM architectures.

[0040] In some embodiments, all transistors in memory cell 100 are MOSFET transistors. In this embodiment, all MOSFET transistors may be of the same type (e.g., N-type MOSFETs, P-type MOSFETs), or some may be different. For example, the first transistor of the first inverter 102 may be a P-type transistor, and the second transistor of the first inverter 102 may be an N-type transistor. The third transistor of the second inverter 104 may be a P-type transistor, and the fourth transistor of the second inverter 104 may be an N-type transistor. Assuming that the word lines WL connected to each transistor correspond to the same lines (i.e., providing the same logic state), then the fifth transistor 110 and the sixth transistor 112 are of the same type (e.g., both N-type and both P-type).

[0041] The types of the seventh transistor 114, the eighth transistor 116, the ninth transistor 118, and the tenth transistor 120 may vary depending on the desired logic outputs from the first to the fourth output nodes 122, 124, 126, and 128. As a non-limiting example, the seventh transistor 114 and the ninth transistor 118 may be of the same MOSFET type (e.g., both N-type and both P-type), and the eighth transistor 116 and the tenth transistor 120 may be of the same type but different from the transistor types of the seventh transistor 114 and the ninth transistor 118. Those skilled in the art will understand that different types of transistors may be implemented to achieve different in-memory computing functions (e.g., NAND, XNOR, XOR) without departing from the scope of this disclosure.

[0042] Figure 2 A first memory cell layout 200 corresponding to memory cell 100 is shown according to one or more embodiments. The first memory cell layout 200 includes a direction parallel to a first axis (in... Figure 2 Multiple active regions extending linearly vertically and in a direction tangential to the first axis (in Figure 2Multiple gate regions extend linearly on a horizontal plane. Each gate region may be a polysilicon layer or a combination of polysilicon and other materials such as silicides (e.g., cobalt silicide, tantalum silicide, tungsten silicide). Active regions are p-type or n-type diffused layers having p-type or n-type characteristics depending on the desired operation of the memory cell 100. Each of the active regions intersects with and covers one or more of the gate regions to form a transistor constituting the memory cell 100. Some active regions and / or some gate regions may vary in width and / or thickness along their length.

[0043] As used herein, the term "cover" refers to an arrangement of at least a first member and a second member, wherein an axis intersects a portion of the first member and a portion of the second member. The portions of the first member and the second member that are covered may be spaced apart from each other along the axis. For example, the first member and the second member may be considered covered without contact.

[0044] The gate region includes a region along a first direction (e.g., with). Figure 2 A first group of gate regions extends (parallel to the x-axis). The first group of gate regions includes a first gate region 202, a second gate region 204, and a third gate region 206 extending along a first direction and spaced apart from each other along the first direction. The gate regions also include regions extending along the first direction (e.g., parallel to the x-axis). Figure 2 The second group of gate regions extends parallel to the x-axis. The second group of gate regions includes a fourth gate region 208, a fifth gate region 210, and a sixth gate region 212 extending along the first direction and spaced apart from each other along the first direction. The first group of gate regions and the second group of gate regions are connected in a second direction (e.g., parallel to the x-axis). Figure 2 The gate regions are spaced apart on the y-axis (parallel to the y-axis). Although the gate regions are shown as coaxial with each other, some gate regions may not be aligned with other gate regions without departing from the scope of this disclosure.

[0045] The active regions include a first group of active regions extending in a second direction within a first region 214 of the first memory cell layout 200. The first group of active regions includes a first active region 220 and a second active region 222 spaced apart from the first active region 220 in a first direction. This group of active regions also includes a second group of active regions extending in a second direction within a second region 216, which is adjacent to the first region 214 in the first direction. The second group of active regions includes a third active region 224 and a fourth active region 226 spaced apart from the third active region 224 in a first direction. This group of active regions also includes a third group of active regions extending in a second direction within a third region 218, which is adjacent to the second region 216 in the first direction. The third group of active regions includes a fifth active region 228 and a sixth active region 230 spaced apart from the fifth active region 228 in a first direction.

[0046] Transistors are formed in the first memory cell layout 200 at locations where the gate region and the active region overlap. The first transistor of the first inverter 102 is formed in the overlap between the third active region 224 and the first gate region 202. The second transistor of the first inverter 102 is formed in the overlap between the second active region 222 and the first gate region 202. The third transistor of the second inverter 104 is formed in the overlap between the fourth active region 226 and the sixth gate region 212. The fourth transistor of the second inverter 104 is formed in the overlap between the fifth active region 228 and the sixth gate region 212. The fifth transistor 110 is formed in the overlap between the second gate region 204 and the fifth active region 228. The sixth transistor 112 is formed in the overlap between the fifth gate region 210 and the second active region 222.

[0047] The first set of active regions (i.e., in the first region 214) extends entirely between the first set of gate regions and the second set of gate regions. Specifically, the first active region 220 extends entirely between and covers the first gate region 202 and the fourth gate region 208, and the second active region 222 extends entirely between and covers the first gate region 202 and the fifth gate region 210. The third set of active regions (i.e., in the third region 218) also extends entirely between the first set of gate regions and the second set of gate regions. The fifth active region 228 extends entirely between and covers the second gate region 204 and the sixth gate region 212, and the sixth active region 230 extends entirely between and covers the third gate region 206 and the sixth gate region 212.

[0048] The second set of active regions (i.e., in the second region 216) extends partially between the first set of gate regions and the second set of gate regions. Specifically, the third active region 224 extends from the first gate region 202 toward the sixth gate region 212, but does not cover the sixth gate region 212. The fourth active region 208 extends from the sixth gate region 212 toward the first gate region 202, but does not cover the first gate region 202. The first metal region 232 is electrically coupled to the end of the third active region 224 and to the end of the sixth gate region 212. The second metal region 234 is electrically coupled to the end of the fourth active region 226 and to the end of the first gate region 202. The first metal region 232 and the second metal region 234 are used for cross-coupling the first inverter 102 and the second inverter 104. The first metal region 232 and the second metal region 234 may be formed on a different layer than the active regions and the gate regions. The first metal region 232 and the second metal region 234 may be electrically coupled through vias extending through one or more layers of the first memory cell layout 200.

[0049] The seventh transistor 114 is formed in the coverage area between the first gate region 202 and the first active region 220. The eighth transistor 116 is formed in the coverage area between the fourth gate region 208 and the first active region 220. The ninth transistor is formed in the coverage area between the third gate region 206 and the sixth active region 230. The tenth transistor 120 is formed in the coverage area between the sixth gate region 212 and the sixth active region 230.

[0050] End 236 of the second gate region 204 and end 238 of the fifth gate region 210 are electrically coupled to word lines for controlling the read / write / hold state of a pair of cross-coupled inverters. End 240 of the third gate region is electrically coupled to the intermediate portion 242 of the fifth active region 228 between the second gate region 204 and the sixth gate region 212. End 244 of the fourth gate region 208 is electrically coupled to the intermediate portion 246 of the second active region 222 located between the first gate region 202 and the fifth gate region 210. The third metal region 248 can connect the end 240 of the third gate region 206 to the intermediate portion 242 of the fifth active region 228 in a layer other than the active regions in the gate regions. The fourth metal region 250 can connect the end 244 of the fourth gate region 208 to the intermediate portion 246 of the second gate region 204 in a layer other than the active regions in the gate regions. The third metal region 248 and the fourth metal region 250 may have curved shapes extending in a first direction and a second direction.

[0051] The middle part 252 of the first active region 220 corresponds to the above-mentioned... Figure 1 The third node 134 is described. The middle portion 254 of the sixth active region 230 corresponds to the information about... Figure 1 The fourth node 148 is described. Contact points may be provided at the intermediate portion 252 for electrically coupling a signal corresponding to the second logic state A, and contact points may be provided at the intermediate portion 254 for electrically coupling a complementary second logic state. The signal.

[0052] The ends of the active regions can be connected according to the structure described with respect to memory cell 100. An example scheme for connecting the ends of the active regions will now be provided; however, this scheme can be adjusted according to transistor type, desired output logic, etc. The first end 256 of the first active region 220 corresponds to the first output node 122, and the second end 258 of the first active region 220 corresponds to the second output node 124. The first end 260 of the second active region 222 corresponds to a voltage potential connection (e.g., VDD, GND), and the second end 262 of the second active region corresponds to a bit line input connection (e.g., bit line BL, complementary bit line BLB). The first end 264 of the third active region 224 corresponds to a voltage potential connection (e.g., VDD, GND). The second end 266 of the fourth active region 226 also corresponds to a voltage potential connection (e.g., VDD, GND). The first end 268 of the fifth active region 228 corresponds to a bit line input connection (e.g., bit line BL, complementary bit line BLB), and the second end 270 of the fifth active region 228 corresponds to a voltage potential connection (e.g., VDD, GND). The first end 272 of the sixth active region 230 corresponds to the third output node 126, and the second end 274 of the sixth active region 230 corresponds to the fourth output node 128.

[0053] Figure 3 A second memory cell layout 300 corresponding to memory cell 100 according to one or more embodiments is shown. The second memory cell layout 300 operates in the same manner as described with respect to memory cell 100, but has a denser layout than the first memory cell layout 200. Specifically, in the second memory cell layout 300, the active and gate regions of the first region 214 are transposed about the y-axis relative to the first memory cell layout 200, and the active and gate regions of the third region 218 are transposed about the y-axis relative to the first memory cell layout 200 (see [link to documentation]). Figure 2 As a result, the space between gate regions in adjacent regions can be eliminated, allowing for a reduction in the number of different gate regions and a compression of the cell layout in the first direction. Therefore, the overall size of the memory cell layout is reduced, and the density of memory cell arrays with in-memory computing capabilities can be increased.

[0054] In the second memory cell layout 300, there is a first gate region 302 extending in a first direction (in a direction parallel to the x-axis) and a second gate region 304 extending in the first direction and spaced apart from the first gate region 302 in the first direction. A third gate region 306 and a fourth gate region 308 extend in the first direction and are spaced apart from the first gate region 302 and the second gate region 304 in a second direction (in a direction parallel to the y-axis). The third gate region 306 and the fourth gate region 308 are spaced apart from each other in the second direction. As a result, the gate region corresponding to the ninth transistor 118 is a part of the same gate region as the gate region of the first transistor corresponding to the first inverter 102. Furthermore, the gate region corresponding to the eighth transistor 116 is a part of the same gate region as the gate region of the third transistor corresponding to the second inverter 104.

[0055] The second memory cell layout 300 also has connection points located at its ends in the first direction to facilitate the sharing of line connections between adjacent memory cells. The second gate region 304 and the third gate region 306 correspond to the fifth transistor 110 and the sixth transistor 112 discussed with respect to memory cell 100, respectively. The second gate region 304 has an end 310 for connecting word lines WL to control write / read / hold operations of the fifth transistor 110. The third gate region 306 has an end 312 for connecting word lines WL to control write / read / hold operations of the sixth transistor 112. By facilitating connections between adjacent cells via shareable word lines WL at the ends of the second gate region 304 and the third gate region 306, rather than via internal nodes of the cells, the total area of ​​the memory array can be reduced by decreasing the distance between adjacent memory cells.

[0056] Apart from the active region of the transposed second memory cell layout 300 compared to the first memory cell layout 200, the remaining layout of the second memory cell 300 is basically similar to the first memory cell layout 200, so further description of it is omitted for the sake of brevity.

[0057] Figure 4 A connection diagram 400 of a second memory cell layout 300 according to one or more embodiments is shown. Connection diagram 400 includes the same features described above with respect to the second memory cell layout 300, as well as a detailed description of how active and gate regions can be connected to specific signals. Connection diagram 400 is intended as an example of how the second memory cell layout 300 can be connected, and is not intended to be limiting.

[0058] The end 310 of the second gate region 304 may be coupled to a shareable word line contact 402 of the second memory cell layout 300. The shareable word line contact 402 is coupled to a word line WL for controlling write / read / hold operations of the memory cell 100. The shareable word line contact 402 may be coupled to or jointly connected to shareable word line contacts of adjacent memory cells having the second memory cell layout 300. The word line WL to which the shareable word line contact 402 is connected extends in a layer of the memory cell layout (not shown).

[0059] The end 312 of the third gate region 306 may be coupled to a shareable word line contact 404 of the second memory cell layout 300. The shareable word line contact 404 is also coupled to a word line WL for controlling write / read / hold operations of the memory cell 100. The shareable word line contact 404 may be coupled to or commonly connected to shareable word line contacts of adjacent memory cells, as described above. Commonly coupled shareable word lines between adjacent memory cells facilitate a denser array layout of memory cells.

[0060] The ends 406 and 408 of the first gate region 302 and the fourth gate region 308 are spaced apart from the gate regions of adjacent memory cells in the first direction in the first direction.

[0061] The second active region 222 extends in a second direction below the first gate region 302 and above the third gate region 306. The second gate region 222 extends above the third gate region 306 to be coupled to the complementary bit line BLB via the first bit line connection 410. The second gate region 222 extends in a second direction below the first gate region 302 to be connected to the first ground connection 412, which is coupled to the ground terminal GND of the memory cell 100.

[0062] The first active region 220 extends in a second direction below the first gate region 302 and above the fourth gate region 308. The portion of the first active region 220 extending below the first gate region 302 is coupled to a first output connection 414 corresponding to a first output node 122 of the memory cell 100. The portion of the first active region 220 extending in the second direction above the fourth gate region 308 is coupled to a second output connection 416 corresponding to a second output node 124 of the memory cell 100. The intermediate portion 252 of the first active region 220 is coupled to a first input connection 418 corresponding to a third node 134 of the memory cell 100. In at least some embodiments, the first input connection 418 is coupled to a line in a layer different from the first active region 220.

[0063] The third active region 224 shown in Figure 400 extends in a second direction below the first gate region 302 and is coupled to a first power supply voltage connection 420 for receiving the power supply voltage of the memory cell 100. The fourth active region 226 shown in Figure 400 extends in a second direction above the fourth gate region 308 and is coupled to a second power supply voltage connection 422 for receiving the power supply voltage.

[0064] The sixth active region 230 extends in a second direction above the fourth gate region 308 and below the first gate region 302. The portion of the sixth active region 230 extending below the first gate region 302 is coupled to the third output connection 424 corresponding to the third output node 126. The portion of the sixth active region 230 extending above the fourth gate region 308 is coupled to the fourth output connection 426 corresponding to the fourth output node 128. The middle portion 254 of the sixth active region 230 is coupled to the second input connection 428 corresponding to the fourth node 148 of the memory cell 100.

[0065] The fifth active region 228 extends in a second direction above the fourth gate region 308 and below the second gate region 304. The portion of the fifth active region 228 extending below the second gate region 304 is coupled to the second bit line connection 430. The portion of the fifth active region 220 extending above the fourth gate region 308 is coupled to the second ground connection 432.

[0066] The second output connection 416 and the third output connection 424 can be coupled together (e.g., short-circuited) to generate an XOR output, as described above. A differential XOR output can be generated by connecting the second output connection 416 and the third output connection 424 to the differential input of the sense amplifier. The first output connection 414 and the fourth output connection 426 can be coupled together to generate an XNOR output, as described above. A differential XNOR output can be generated by connecting the first output connection 414 and the fourth output connection 426 to the differential input of the sense amplifier. The different output connections can be coupled together via metal lines extending in another layer of the memory cell layout.

[0067] Figure 5 A schematic diagram of an SRAM with in-memory computing capability according to one or more embodiments is shown. SRAM cell 500 includes eight transistors (18) arranged to facilitate data storage and in-memory computing capability. Memory cell 500 includes a first inverter 502 and a second inverter 504 cross-coupled to each other as described above with respect to memory cell 100. The first inverter 502 includes a first transistor and a second transistor of memory cell 500 coupled in series with each other. The second inverter 504 includes a third transistor and a fourth transistor of memory cell 500 coupled in series with each other.

[0068] Memory cell 500 includes a first node 506 located between the output of the first inverter 502 and the input of the second inverter 504, and also includes a second node 508 located between the input of the first inverter 502 and the output of the second inverter 504, as described above with respect to memory cell 100. The second node 508 stores data bits corresponding to the first logic state D, and the first node 506 stores data bits corresponding to the complementary first logic state D. The corresponding data bits, as also described regarding memory cell 100.

[0069] SRAM cell 500 further includes a fifth transistor 510 and a sixth transistor 512 coupled to a second node 508 and a first node 506, respectively. The fifth transistor 510 has a first terminal coupled to the right bit line WBAL and a gate terminal coupled to the right word line WWL. The sixth transistor 512 has a first terminal coupled to the complementary write bit line WBLB and a gate terminal coupled to the right word line WWL.

[0070] SRAM cell 500 further includes a seventh transistor 514 with its gate coupled to a first node 506, and an eighth transistor 516 with its gate coupled to a second node 508. A first terminal 518 of the seventh transistor is coupled to a third node 520 of the memory cell 500, which provides an input corresponding to a second logic state A of the memory cell 500. The eighth transistor 516 has a first terminal 522 coupled to a fourth node 524 of the memory cell 500, which provides an input corresponding to a complementary second logic state. The third node 520 can be coupled to the first input line 526 to drive the logic state of the third node 520. The fourth node 524 can be coupled to the second input line 528 to drive the logic state of the fourth node 524.

[0071] The seventh transistor 514 further includes a second terminal 530 coupled to a first output node 532 of the SRAM cell 500, and the eighth transistor 516 further includes a second terminal 534 coupled to a second output node 536 of the SRAM cell 500. The first output node 532 may be coupled to a first output line 538 to provide an output from the first output node 532, and the second output node 536 may be coupled to a second output line 540. The first output node 532 and the second output node 536 may each be based on logic state D and complementary logic states. Second logical state A and complementary second logical state A combination of one or more logical states is used to provide a logical output. For example, the output of memory cell 500 at the first output node 532 can be A+D, which has the following truth table, where Q is the output at the first output node 532:

[0072] A D Q 0 0 0 0 1 1 1 0 1 1 1 1

[0073] The output of memory cell 500 at the second output node 536 can be It has the following truth table, where Q is the output at the second output node 536:

[0074] A D Q 0 0 1 0 1 1 1 0 1 1 1 0

[0075] As described above with respect to memory cell 100, the aforementioned logic outputs are a non-limiting example of numerous logic operations that can be implemented via the structure of SRAM cell 500. Those skilled in the art will understand that different logic operations involving a first logic state and a second logic state (or their complements) can be performed based on various aspects of SRAM cell 500. The outputs of SRAM cell 500 can be coupled together to perform other logic operations; for example, first output node 532 and second output node 536 can be coupled together to perform XOR or XNOR operations involving first logic state D and second logic state A. The XNOR operation has the following truth table provided from an output node where first output node 532 and second output node 536 are directly coupled together:

[0076] A D Q 0 0 1 0 1 0 1 0 0 1 1 1

[0077] Figure 6 A memory cell layout 600 of an SRAM cell 500 according to one or more embodiments is shown. The memory cell layout 600 includes components parallel to a first axis (parallel to...). Figure 6 Multiple active regions extending linearly in the direction of the Y-axis and in the direction transverse to the first axis (parallel to the Y-axis). Figure 6 Multiple gate regions extending linearly along the X-axis (as described above). Each gate region can be multiple layers of polysilicon or a combination of polysilicon and other materials, as described above. Figure 2 As described, an active region is a P-type or N-type diffused layer having a shape that depends on the desired operation of the SRAM cell 500. Some active regions and / or some gate regions may vary in width and / or thickness along their length.

[0078] The gate region includes a first group of gate regions extending along a first direction, including a first gate region 602 and a second gate region 604 extending along the first direction and spaced apart from each other along the first direction. The gate region also includes a second group of gate regions extending along the first direction and spaced apart from each other along the first direction. The second group of gate regions includes a third gate region 606 and a fourth gate region 608 spaced apart from the third gate region 606. Although the gate regions are shown as coaxial with each other, some gate regions may not be aligned with other gate regions without departing from the scope of this disclosure.

[0079] The active regions include: a first group of active regions, each extending in a second direction within a first region 610 of the memory cell layout 600; a second group of active regions, each extending in a second direction within a second region 612 of the memory cell layout 600 adjacent to the first region 610; and a third group of active regions, each extending in a second direction within a third region 614 of the memory cell layout 600 adjacent to the second region 612. The first group of active regions includes a first active region 616 and a second active region 618 extending in the first direction, with the second active region 618 spaced apart from the first active region in the second direction. The second group of active regions includes a third active region 620 and a fourth active region 622 spaced apart from the third active region 620 in the second direction. The third group of active regions includes a fifth active region 624 and a sixth active region 626 spaced apart from the fifth active region 624 in the second direction.

[0080] Transistors are formed in the first memory cell layout 600 at locations where the gate region covers the active region. The first transistor of the first inverter 502 is formed in the area covering the third active region 620 and the first gate region 602. The second transistor of the first inverter 502 is formed in the area covering the second active region 618 and the first gate region 602. The third transistor of the second inverter 504 is formed in the area covering the fourth active region 622 and the fourth gate region 608. The fourth transistor of the second inverter 104 is formed in the area covering the fifth active region 624 and the fourth gate region 608. The fifth transistor 610 is formed in the area covering the second gate region 604 and the fifth active region 624. The sixth transistor 112 is formed in the area covering the third gate region 606 and the second active region 618. The seventh transistor 514 is formed in the area covering the first gate region 602 and the first active region 616. The eighth transistor 516 is formed in the area covering the fourth gate region 608 and the sixth active region 626.

[0081] The active region and gate region can be coupled to different inputs and outputs described with respect to SRAM cell 500. The first active region 616 includes a first end of a connection 628 corresponding to a first output node 532 of SRAM cell 500, and a second end of a connection 630 corresponding to a third node 520. The first active region 616 can provide a signal corresponding to a first output at the first output node 532 via connection 628. The first active region 616 can receive a signal corresponding to a second logic state A via connection 630.

[0082] The second active region 618 includes a first end provided with a connection 632 for connection to ground GND of memory cell 500; however, in some embodiments, connection 632 may be connected to a voltage source (e.g., +5V). The second active region 618 further includes a second end provided with a connection 634 for connection to bit line BL (or complementary bit line BLB in some embodiments).

[0083] The third active region 620 includes a first end having a connection 636 for connection to a voltage source VDD and a second end having a connection 638 for coupling to a fourth gate region 608. The fourth active region 622 includes a first end having a connection 640 coupled to a first gate region 602 and a second end having a connection 638 for connection to a voltage source VDD.

[0084] The fifth active region 624 includes a first end having a connection 644 for connection to a complementary bit line BLB (or bit line BL in some embodiments). The fifth active region 624 also includes a second end having a connection 646 for connection to ground GND (or voltage source VDD in some embodiments) of the memory cell 500.

[0085] The sixth active region 626 includes a first end of a connection 648 corresponding to the fourth node 524, and a second end of a connection 650 corresponding to the second output node 536 of the SRAM cell 500. The sixth active region 626 can provide a signal corresponding to a second output at the second output node 536 via the connection 650. The sixth active region 626 can receive a signal corresponding to a complementary second logic state via the connection 648. The signal.

[0086] The first gate region 602 has a first end with a connection 652, which is coupled to a connection 640 of the fourth active region 622 via a metal portion 654. The fourth gate region 608 has a first end with a connection 656, which is coupled to a connection 638 of the third active region 620 via a metal portion 658. As described above with respect to the layout of the memory cell 100, the metal portions 654 and 658 may be located on a different layer than the active and gate regions.

[0087] The second gate region 604 includes a first end having a connection 664 connected to the word write line WWL. The third gate region 606 includes a connection 662 at its first end for connection to the word write line WWL.

[0088] Layout 600 has a boundary 664 defining the outermost edge of SRAM cell 500. Boundary 664 has an asymmetrical shape, wherein each end has an L-shape that is transposed perpendicularly to the other end. Specifically, a first region 610 defines a first end of layout 600 and has a first recessed portion 666 recessed inward from the left and bottom sides of layout 600. A third region 614 defines a second end of layout 600 and has a second recessed portion 668 recessed inward from the right and top sides of layout 600. The first region 610 and the third region 614 are separated from each other by a second region 612 of layout 600.

[0089] The connection 630 of the first active region and the connection 662 of the third gate region 606 are adjacent to the first recessed portion 666 for connection with corresponding connection interfaces of adjacent memory cell layouts, as follows: Figure 7 As described, connections 630 and 662 may be exposed at a boundary 664 within the first recess 666 for connection with signal lines having corresponding adjacent connections.

[0090] Connection 648 of the sixth active region 626 and connection 660 of the second gate region 604 are adjacent to the second recess 668 for connection to corresponding connection interfaces of adjacent memory cell layouts. Connections 648 and 660 may be exposed at the boundary 664 within the second recess 668 for common connection to signal lines with corresponding adjacent connections. It should be noted that the ends of some regions may be... Figure 6 The positions shown are transposed to provide different interconnections for the nodes of the SRAM cell 500. For example, the first end of the first active region 616 may be transposed with its second end such that the connection 628 for providing the first output from the SRAM cell 500 may be located in or adjacent to the first recess 666.

[0091] The shape of the boundary 664 of the SRAM cell layout 600 enables connection with adjacent memory cell layouts to facilitate sequential connection of memory cells, which increases the density of memory cells compared to at least some prior embodiments. Figure 7 The illustrations show that each of them has the characteristics mentioned above. Figure 6 Figure 700 shows the interconnection of a plurality of SRAM cells 500 in the described memory cell layout 600. The plurality of SRAM cells 500 includes a first memory cell 500a having a first recess 666a that engages with a first recess 666b of a second memory cell 500b. The second memory cell 500b has a second end 668b that engages with a second end 668c of a third memory cell 500c. The third memory cell 500c has a first end 666c that engages with a first end 666d of a fourth memory cell 500d, and so on. The plurality of memory cells 500a…500d may include more or fewer than four cells.

[0092] Multiple memory cells 500a…500d may be part of a neural network or other machine learning system, where data bits are combined to generate an output. For example, a first output node 532 of the multiple memory cells 500a…500d may be commonly coupled to a first input of a sense amplifier, and a second output node 536 of the multiple memory cells 500a…500d may be commonly coupled to a second input of the sense amplifier, subsequently providing an output based on the difference between the first and second inputs. As another example, the first output node 532 and the second output node 536 of each of the multiple memory cells 500a…500d may be coupled together and provided to a first input of a sense amplifier. The second input of the sense amplifier may be coupled to a reference voltage, wherein the sense amplifier may provide an output based on the difference between the commonly coupled output node and the reference voltage.

[0093] Figure 8 A diagram of a neural network 800 according to one or more embodiments is shown. The neural network 800 includes a plurality of memory cell networks 802a, 802b…802n. Each network 802 includes a set of memory cells 100a, 100b, 100c…100n arranged parallel to each other. Each cell 100 has a first cell output 804 connected to a first sensing line 808 coupled to a first input terminal of a sensing amplifier 812. Each cell 100 may also have a second cell output 806 connected to a second sensing line 810 coupled to a second input terminal of the sensing amplifier 812. Each of the memory cell networks 802a, 802b…800n provides an independent output 814 corresponding to a data bit of the neural network 800.

[0094] exist Figure 8 In the illustrated embodiment, the sensing amplifier 812 operates in differential mode. In an embodiment where the sensing amplifier operates in single-ended mode, a reference voltage may be connected to one of the input terminals of the sensing amplifier 812, and the first sensing line 808 may be connected to the other input terminal of the sensing amplifier 812.

[0095] The first unit output 804 of each memory cell 100 corresponds to a first set of outputs selected from the first output node 122, the second output node 124, the third output node 126, and the fourth output node 128. The second unit output 806 of each memory cell 100 corresponds to a second set of outputs selected from the first output node 122, the second output node 124, the third output node 126, and the fourth output node 120.

[0096] As a non-limiting example, the first unit output 804 may be the output corresponding to the co-coupled first output node 122 and fourth output node 128, to provide the result of the XOR operation performed by the memory unit 100 via in-memory computation. The second unit output 806 may be the output corresponding to the co-coupled second output node 124 and third output node 126, to provide the result of the XNOR operation performed by the memory unit 100 via in-memory computation.

[0097] As an example of differential XOR output, the first unit output 804 may be the output corresponding to the first output node 122, and the second unit output 806 may be the output corresponding to the fourth output node 124. As an example of differential XNOR output, the first unit output 804 may be the output corresponding to the second output node 124, and the second unit output 806 may be the output corresponding to the third output node 126.

[0098] The adaptability between the two differential single-ended modes and the different logical operations (e.g., XNOR, XOR, NAND) increase the dynamic range of the neural network 800's operations.

[0099] The sensing amplifier 812 can perform differential readout operations on the first sensing line 808 to determine the results of operations performed by a set of memory cells 100a, 100b, 100c...100n coupled thereto. The sensing amplifier 812 can also be configured to perform single-ended operation to determine the results of in-memory calculations performed by the set of memory cells 100a, 100b, 100c...100n coupled thereto. The sensing amplifier 812 is capable of detecting small-swing voltage differences in the signal supplied to it, which reduces the amount of power consumed by the associated in-memory calculation operations.

[0100] Each of the multiple memory cell networks 802a, 802b...802n can determine the data output 814 based on the first cell output 804 and the second cell output 806 of each memory cell 100. Each sense amplifier 812 can, for example, detect a small swing difference between the first sense line 808 and the second sense line 810 to determine the voltage change corresponding to the appropriate output to be provided. This determination may involve taking into account the signals provided on the word lines WL of the set of memory cells 100a, 100b, 100c...100n.

[0101] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which these claims relate. Therefore, the claims are not limited to this disclosure.

Claims

1. A circuit for a neural network, comprising: Multiple memory cell networks, each memory cell network including: A group of memory cells coupled in parallel, wherein the memory cells of the group of memory cells each include: The first inverter has a first input and a first output; The second inverter has a second input coupled to the first output at a first node of the memory cell, and a second output coupled to the first input at a second node of the memory cell; The first transistor has a first terminal coupled to the first node and a gate coupled to the word line node; The second transistor has a first terminal coupled to the second node and a gate coupled to the word line node; The third transistor has a first terminal coupled to a first output node of the memory cell, a second terminal coupled to a third node of the memory cell, and a gate coupled to the first node; The fourth transistor has a first terminal coupled to a second output node of the memory cell, a second terminal coupled to a fourth node of the memory cell, and a gate coupled to the second node; The fifth transistor has a first terminal coupled to the third node, a second terminal coupled to the third output node of the memory cell, and a gate coupled to the second node; and The sixth transistor has a first terminal coupled to the fourth node, a second terminal coupled to the fourth output node of the memory cell, and a gate coupled to the first node; and An amplifier circuit provides data output from the memory cell network based on a set of signals received from the output nodes of the set of memory cells, the output nodes corresponding to one or more of the first output node, the second output node, the third output node, and the fourth output node, wherein, in operation, the data output of the memory cell network corresponds to one bit of data of the neural network.

2. The circuit of claim 1, wherein the first output node, the second output node, the third output node, and the fourth output node each provide different logic outputs, the different logic outputs relating to the logic states of two or more nodes selected from the first node, the second node, the third node, and the fourth node.

3. The circuit according to claim 1, wherein, The first output node is coupled to the fourth output node to provide a first logic output, and the second output node is coupled to the third output node to provide a second logic output.

4. The circuit according to claim 3, wherein the first logic output is the result of a first logic operation, and the second logic output is the result of a second logic operation different from the first logic operation.

5. The circuit according to claim 1, wherein the first node constitutes a first logic state of the memory cell, the second node constitutes an inverted first logic state of the memory cell, the third node constitutes a second logic state of the memory cell, and the fourth node constitutes an inverted second logic state of the memory cell.

6. The circuit of claim 1, wherein the first output node and the second output node each provide different logic outputs, the different logic outputs relating to the logic states of two or more nodes selected from the first node, the second node, the third node, and the fourth node.

7. The circuit of claim 6, wherein the first output node is coupled to the second output node to provide the result of an XOR operation.

8. The circuit of claim 6, wherein the first output node is coupled to the second output node to provide the result of an XOR operation.

9. A memory cell, comprising: The first set of gate regions extends along the first direction; The second group of gate regions extends along the first direction and is spaced apart from the first group of gate regions in a second direction that is transverse to the first direction; The first pair of active regions extends in the second direction between the first group of gate regions and the second group of gate regions in the first region in the first direction; The second pair of active regions extends in the second direction between the first group of gate regions and the second group of gate regions in the second region in the first direction; as well as A third pair of active regions extends in the second direction from the third region in the first direction. The first active region in the third pair of active regions covers the first gate region in the first group of gate regions. The second active region in the third pair of active regions covers the first gate region in the second group of gate regions. The third region is located between the first region and the second region in the first direction. The first end of the first group of gate regions located between the first pair of active regions in the first direction is coupled to the middle portion of one of the first pair of active regions via a first conductor. The second end of the second group of gate regions located between the second pair of active regions in the first direction is coupled to the middle portion of one of the second pair of active regions via a second conductor.

10. The memory cell of claim 9, wherein the first conductor has a curved shape, and the second conductor has a curved shape.

11. The memory cell of claim 9, wherein the third end of the first set of gate regions is coupled to a first contact point for connecting a first word line, and the fourth end of the second set of gate regions is coupled to a second contact point for connecting a second word line.

12. The memory cell of claim 9, wherein a first end of the first set of gate regions is located at a first end of the memory cell in the first direction, and a second end of the second set of gate regions is located at a second end of the memory cell in the second direction.

13. The memory cell of claim 9, wherein a first intermediate portion of the first active region of the first pair of active regions is coupled to a contact point for connecting a first input line, and a second intermediate portion of the first active region of the second pair of active regions is coupled to a second contact point for connecting a second input line.

14. The memory cell of claim 13, wherein the second active region of the first pair of active regions has a first end input for connecting a first bit line to the memory cell, and the second active region of the second pair of active regions has a second end for connecting a second bit line to the memory cell.

15. The memory cell of claim 13, wherein the first active region of the first pair of active regions has a first end for providing a first logic output of the memory cell and a second end for providing a second logic output of the memory cell.

16. The memory cell of claim 15, wherein the first active region in the second pair of active regions has a first end for providing a third logic output of the memory cell and a fourth end for providing a fourth logic output of the memory cell.

17. The memory cell of claim 9, wherein the first active region of the first pair of active regions has a shorter length in the second direction than the length of the second active region of the first pair of active regions.

18. The memory cell of claim 9, wherein the first active region of the second pair of active regions has a shorter length in the second direction than the length of the second active region of the second pair of active regions.

19. The memory cell of claim 9, wherein the boundary defining the first region has a recessed portion on a first side in the second direction, and the boundary defining the second region has a recessed portion on a second side in the second direction opposite to the first side.

20. The memory cell of claim 9, wherein the first active region of the first pair of active regions is not electrically coupled to the active region of the second pair of active regions or the active region of the third pair of active regions within the memory cell, and the first active region of the second pair of active regions is not electrically coupled to the active region of the first pair of active regions or the active region of the third pair of active regions within the memory cell.

21. A memory cell, comprising: The first set of gate regions extends along the first direction; The second group of gate regions extends along the first direction and is spaced apart from the first group of gate regions in a second direction that is transverse to the first direction; The first pair of active regions extends in the second direction between the first group of gate regions and the second group of gate regions in the first region in the first direction; The second pair of active regions extends in the second direction between the first group of gate regions and the second group of gate regions in the second region in the first direction; as well as A third pair of active regions extends in the second direction from the third region in the first direction. The first active region in the third pair of active regions covers the first gate region in the first group of gate regions, and the second active region in the third pair of active regions covers the first gate region in the second group of gate regions. The third region is located between the first region and the second region in the first direction. The first group of gate regions, the second group of gate regions, the first pair of active regions, the second pair of active regions, and the third pair of active regions together form a ten-transistor memory cell. The first end of the first set of gate regions located between the first pair of active regions in the first direction is coupled to the middle portion of one of the first pair of active regions via a first conductor, and the second end of the second set of gate regions located between the second pair of active regions in the first direction is coupled to the middle portion of one of the second pair of active regions via a second conductor.

22. The memory cell of claim 21, wherein a first intermediate portion of the first active region of the first pair of active regions is coupled to a contact point for connecting a first input line, and a second intermediate portion of the first active region of the second pair of active regions is coupled to a second contact point for connecting a second input line.

23. The memory cell of claim 22, wherein the second active region of the first pair of active regions has a first end input for connecting a first bit line to the memory cell, and the second active region of the second pair of active regions has a second end for connecting a second bit line to the memory cell.

24. The memory cell of claim 22, wherein the first active region of the first pair of active regions has a first end for providing a first logic output of the memory cell and a second end for providing a second logic output of the memory cell.

25. The memory cell of claim 24, wherein the first active region in the second pair of active regions has a first end for providing a third logic output of the memory cell and a fourth end for providing a fourth logic output of the memory cell.

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