Display device and printed circuit board

Abstract

A display device and a printed circuit board are provided. The display device includes, among other aspects, a pad region having a pattern that reduces gaps between signal lines caused by variations in signal line profiles. A corresponding printed circuit board may also include a similar pattern to reduce gaps between leads. The pad and printed circuit board may be in contact via an anisotropic conductive film.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0104703, filed on August 26, 2019, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments / implementations of the invention generally relate to a display device. Background Art

[0003] A display device is a device for displaying data. The display device includes a display area and a non-display area. In the display area, a plurality of pixels are provided on a substrate, and in the non-display area, a plurality of pads are provided on the substrate. A flexible film (e.g., a chip on film (COF)) with a drive circuit mounted thereon can be bonded to the pads and can transmit drive signals to the pixels.

[0004] The flexible film may include a plurality of leads bonded to the pads, and the leads may be bonded to different pads. The leads may be bonded to the pads via an anisotropic conductive film (ACF) disposed between the pads.

[0005] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the Invention

[0006] A device constructed according to an exemplary embodiment / example of the invention / a method according to an exemplary embodiment / example of the invention can provide a display device that can reduce bubbles in an anisotropic conductive film (ACF) during thermal extrusion of the ACF, which bonds a printed circuit board and a display panel.

[0007] However, the embodiments of the present disclosure are not limited to those described herein. The above and other embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one or more exemplary embodiments / embodiments of the invention, a display device includes: a base substrate; a plurality of signal lines disposed on the base substrate to extend from an end portion of the base substrate in a first direction and to be spaced apart from each other in a second direction intersecting the first direction; and an insulating pattern disposed between the signal lines on the end portion of the base substrate.

[0009] The base substrate may have a display area defined thereon and a pad area disposed on a periphery of the display area, the display device may further include an insulating layer exposing the signal line in the pad area, and the insulating layer may be disposed in the same layer as the insulating pattern.

[0010] The display device may further include a printed circuit board attached to the pad area, wherein the printed circuit board includes: a driving integrated circuit (IC); and a plurality of leads connected to the driving IC and spaced apart from each other in the second direction, and the leads are arranged to overlap with the signal lines in the thickness direction.

[0011] The display device may further include an ACF disposed between the lead line and the signal line, wherein the lead line and the signal line are electrically connected through the ACF.

[0012] An insulating pattern may be provided between the leads.

[0013] Each of the leads may include a first lead portion having a first width; and a second lead portion having a second width smaller than the first width and disposed between the first lead portion and the driving IC.

[0014] The insulation pattern may be provided between the second lead portions of the lead wires.

[0015] A distance between first lead portions of the leads may be smaller than a distance between second lead portions of the leads.

[0016] The sum of the distance between the left side of the second lead portion of the lead and the adjacent insulating pattern on the left and the distance between the right side of the second lead portion of the lead and the adjacent insulating pattern on the right can be 0.8 to 1.2 times the distance between the first lead portions of the lead.

[0017] The ACF may be in contact with a side surface of each of the first lead portions of the leads, a side surface of each of the second lead portions of the leads, and a side surface of each of the insulation patterns.

[0018] Each of the leads may further include a third lead portion disposed between the first lead portion and the second lead portion, and a width of the third lead portion may gradually increase from the second lead portion to the first lead portion.

[0019] An insulating pattern may also be provided between the third lead portions of the leads.

[0020] The distance between the first lead portions of the leads may be smaller than the distance between the third lead portions of the leads, and the distance between the first lead portions of the leads may be the same as the sum of the distance between the left side of the third lead portion of the lead and the adjacent insulating pattern on the left and the distance between the right side of the third lead portion of the lead and the adjacent insulating pattern on the right.

[0021] The ACF may also be in contact with a side surface of each of the third lead portions of the leads and a side surface of each of the insulation patterns.

[0022] Each of the insulating patterns may include a plurality of patterns spaced apart from each other in the second direction.

[0023] According to yet another exemplary embodiment / example of the invention, a display device includes: a base substrate defining a display area and a pad area disposed on a periphery of the display area; a plurality of signal lines disposed on the base substrate to extend from an end portion of the base substrate in a first direction and to be spaced apart from one another in a second direction intersecting the first direction; a printed circuit board including a driver IC, a plurality of leads connected to the driver IC and spaced apart from one another in a second direction, and an insulating layer exposing the leads in the pad area; and an ACF disposed between the leads and the signal lines, wherein the leads are disposed to overlap with the signal lines in a thickness direction, and the insulating layer includes a protrusion pattern protruding toward the signal lines.

[0024] Each of the leads may include: a first lead portion having a first width; and a second lead portion having a second width smaller than the first width and disposed between the first lead portion and the driving IC, and the protrusion pattern may be disposed between the second lead portions of the leads.

[0025] The distance between the first lead portions of the leads can be smaller than the distance between the second lead portions of the leads, and the sum of the distance between the left side of the second lead portion of the lead and the adjacent insulating pattern on the left and the distance between the right side of the second lead portion of the lead and the adjacent insulating pattern on the right can be 0.8 to 1.2 times the distance between the first lead portions of the leads.

[0026] The ACF may be in contact with a side surface of each of the first lead portions of the leads, a side surface of each of the second lead portions of the leads, and a side surface of each of the insulation patterns.

[0027] Each of the leads may further include a third lead portion disposed between the first and second lead portions, a width of the third lead portion may gradually increase from the second lead portion to the first lead portion, and a protruding pattern may be further disposed between the third lead portions of the leads.

[0028] According to the above and other embodiments of the present disclosure, generation of bubbles in an ACF, which bonds a printed circuit board and a display panel, may be reduced during thermal compression of the ACF.

[0029] Other features and embodiments may be apparent from the following description, drawings, and claims.

[0030] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0031] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 are plan / perspective views of a display device constructed according to an exemplary embodiment of the invention.

[0033] Figure 2 yes Figure 1 A cross-sectional view of a display device.

[0034] Figure 3 It shows Figure 1 A partial layout diagram of the pad area of a display device.

[0035] Figure 4 It shows Figure 1 A partial layout diagram of a printed circuit board (PCB) of a display device.

[0036] Figure 5 It shows Figure 1 A diagram of the display device's pad area and PCB layout.

[0037] Figure 6 It is along Figure 5 A cross-sectional view taken along line VI-VI'.

[0038] Figure 7 It is along Figure 5 A cross-sectional view taken along line VII-VII'.

[0039] Figure 8 It is along Figure 5 A sectional view taken along line VIII-VIII'.

[0040] Figure 9 It is along Figure 5 A sectional view taken along line IX-IX'.

[0041] Figure 10 It shows that Figure 1 A cross-sectional view of a process for bonding a display panel and a PCB of a display device.

[0042] Figure 11 It is shown in Figure 10 A plan view of how the first bonding member flows in the process shown in FIG.

[0043] Figure 12 is a partial layout diagram illustrating a pad area of a display device according to another embodiment of the present disclosure.

[0044] Figure 13 It shows Figure 12A partial layout diagram of the PCB of a display device.

[0045] Figure 14 It shows Figure 12 A diagram of the display device's pad area and PCB layout.

[0046] Figure 15 It is along Figure 14 A sectional view taken along line XV-XV'.

[0047] Figure 16 It is along Figure 14 A sectional view taken along line XVI-XVI'.

[0048] Figure 17 is a layout diagram illustrating a pad area and a PCB of a display device according to another embodiment of the present disclosure.

[0049] Figure 18 is a layout diagram illustrating a pad area and a PCB of a display device according to another embodiment of the present disclosure.

[0050] Figure 19 is a layout diagram illustrating a pad area and a PCB of a display device according to another embodiment of the present disclosure.

[0051] Figure 20 FIG. 1 is a partial layout diagram of a PCB of a display device according to another embodiment of the present disclosure.

[0052] Figure 21 FIG. 1 is a partial layout diagram of a PCB of a display device according to another embodiment of the present disclosure.

[0053] Figure 22 FIG. 1 is a partial layout diagram of a PCB of a display device according to another embodiment of the present disclosure.

[0054] Figure 23 is a layout diagram illustrating a pad area and a PCB of a display device according to another embodiment of the present disclosure.

[0055] Figure 24 is a layout diagram illustrating a pad area and a PCB of a display device according to another embodiment of the present disclosure.

[0056] Figure 25 FIG. 1 is a partial layout diagram of a PCB of a display device according to another embodiment of the present disclosure.

[0057] Figure 26 FIG. 1 is a partial layout diagram of a PCB of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words and are non-limiting examples of devices or methods employing one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, various exemplary embodiments may be different, but do not have to be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0059] Unless otherwise specified, the exemplary embodiments shown will be understood as providing exemplary features of various details that can actually implement some ways of implementing the inventive concept. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter, individually or collectively referred to as "elements") can be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0060] The use of cross hatching and / or shading is generally provided in the accompanying drawings to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed in a different order than described. For example, two continuously described processes can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0061] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bound to" another element or layer, the element or layer may be directly on, directly connected to or directly bound to the other element or layer, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bound to" another element or layer, there are no intermediate elements or intermediate layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intermediate element. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, the y-axis and the z-axis) and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0062] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below could be named the second element without departing from the disclosed teachings.

[0063] For descriptive purposes, spatially relative terms such as "under," "beneath," "beneath," "down," "over," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another(s) element(s) as shown in the accompanying drawings. Spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the drawings is turned over, an element described as "under" or "beneath" other elements or features would subsequently be positioned "over" the other elements or features. Thus, the exemplary term "under" can include both an above and a below orientation. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0064] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "one", and "the" are also intended to include plural forms. In addition, when the terms "comprise", "include" and / or their variations are used in this specification, the term descriptions include the features, integral bodies, steps, operations, elements, components and / or their groups stated, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than as terms of degree, and so they are used to explain the inherent deviations in measured values, calculated values and / or provided values that will be recognized by those of ordinary skill in the art.

[0065] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to the specific illustrated shapes of the regions, but rather are to include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device and, as such, are not necessarily intended to be limiting.

[0066] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0067] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments. As such, variations in the shapes of the diagrams, for example, due to manufacturing techniques and / or tolerances, are anticipated. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions shown herein, but will include deviations in shapes, for example, due to manufacturing. For example, regions shown or described as flat may typically have rough and / or nonlinear features. In addition, the acute angles (or "pointed corners") shown may be rounded (rounded). Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, and are not intended to limit the scope of the claims set forth.

[0068] Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings.

[0069] Figure 1 is a layout diagram of a display device according to an embodiment of the present disclosure, and Figure 2 yes Figure 1 A cross-sectional view of a display device.

[0070] The display device 1, which is a device for displaying moving images or still images, can be used not only as a display screen for mobile electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notepads, electronic book (e-book) readers, portable multimedia players (PMPs), navigation devices, or ultra-mobile PCs (UMPCs)), but also as a display screen for various other products (such as televisions (TVs), notebook computers, monitors, billboards, or Internet of Things (IoT) devices).

[0071] Reference Figure 1 and Figure 2 , the display device 1 may include a display panel 100 displaying an image, a printed circuit board (PCB) 300 connected to the display panel 100 , and a main circuit board 500 connected to the PCB 300 .

[0072] The display panel 100 may be, for example, an organic light emitting diode (OLED) display panel. The display panel 100 will be described below as, for example, an OLED display panel, but the present disclosure is not limited thereto. That is, various other display panels such as a liquid crystal display (LCD) panel, a quantum dot (QD)-OLED display panel, a QD-LCD panel, a quantum nano-light emitting diode (nanoLED) display panel, or a micro-light emitting diode (microLED) display panel may be used as the display panel 100.

[0073] The display panel 100 includes a display area DA and a non-display area NA, the display area DA including a plurality of pixel areas, and the non-display area NA being disposed on the periphery of the display area DA. The display area DA may have a rectangular shape with right or rounded corners in a plan view. The display area DA may have short sides and long sides. The short sides of the display area DA may extend in a first direction DR1. The long sides of the display area DA may extend in a second direction DR2. However, the planar shape of the display area DA is not particularly limited, and the display area DA may have various other shapes in a plan view, such as a circular shape or an elliptical shape. The non-display area NA may be disposed adjacent to two short sides and two long sides of the display area DA. In this case, the non-display area NA may surround all sides of the display area DA and may form an edge of the display area DA, but the present disclosure is not limited thereto. Alternatively, the non-display area NA may be disposed adjacent to only two short sides or only two long sides of the display area DA.

[0074] The non-display area NA of the display panel 100 may include a panel pad area P_PA. The panel pad area P_PA may be disposed adjacent to, for example, one of the short sides of the display area DA, but the present disclosure is not limited thereto. Alternatively, the panel pad area P_PA may be disposed adjacent to both short sides of the display area DA or adjacent to both short sides and both long sides of the display area DA.

[0075] The PCB 300 may include a printed base film 310 and a driving integrated circuit (IC) 390 disposed on the printed base film 310. The printed base film 310 may include an insulating material.

[0076] The PCB 300 may include a first circuit area CA1 attached to the panel pad area P_PA of the display panel 100; a second circuit area CA2 disposed on one side of the first circuit area CA1 in the second direction DR2; and a third circuit area CA3 disposed on one side of the second circuit area CA2 in the second direction DR2 and attached to the main circuit board 500. A driver IC 390 may be disposed on one surface of the second circuit area CA2 of the PCB 300. The driver IC 390 may be, for example, a data driver IC, and a chip on film (COF) implemented as the data driver IC may be applied to the driver IC 390.

[0077] The main circuit board 500 may include a circuit pad area attached to the third circuit area CA3 of the PCB 300. In the circuit pad area of the main circuit board 500, a plurality of circuit pads may be provided and may be connected to leads in the third circuit area CA3 of the PCB 300.

[0078] Reference Figure 2 , the display device 1 may further include a panel backsheet 200 disposed below the display panel 100. The panel backsheet 200 may be attached to the bottom surface of the display panel 100. The panel backsheet 200 may include one or more functional layers. The functional layer may be a layer that performs a heat dissipation function, an electromagnetic shielding function, a grounding function, a buffering function, a strength enhancement function, a support function and / or a digitization function. The functional layer may be a sheet layer, a film layer, a thin film layer, a coating, a panel or a board. The functional layer may have a single-layer structure or may have a stack of multiple thin films or coatings. The functional layer may be, for example, a supporting substrate, a heat dissipation layer, an electromagnetic shielding layer, an impact absorbing layer or a digitizer.

[0079] like Figure 2As shown in FIG, the PCB 300 may be bent downward in the third direction DR3. One side of the PCB 300 and the main circuit board 500 may be positioned below the panel bottom film 200. The bottom surface of the panel bottom film 200 may be bonded to the main circuit board 500 via an adhesive layer, but the present disclosure is not limited thereto.

[0080] The display panel 100 may include a base substrate 101 , a plurality of conductive layers, a plurality of insulating layers separating the conductive layers, and an organic layer EL.

[0081] The base substrate 101 may be disposed in the display area DA and the non-display area NA and may span the display area DA and the non-display area NA. The base substrate 101 may support various components disposed thereon. For example, the base substrate 101 may be a rigid substrate including a rigid material such as glass or quartz, but the present disclosure is not limited thereto. In another example, the base substrate 101 may be a flexible substrate including a flexible material such as polyimide (PI).

[0082] The buffer layer 102 may be disposed on the base substrate 101. The buffer layer 102 may prevent moisture and oxygen from penetrating through the base substrate 101. The buffer layer 102 may include silicon nitride (SiN x ) film, silicon oxide (SiO2) film and silicon oxynitride (SiO x N y ) membrane.

[0083] The semiconductor layer 105 may be disposed on the buffer layer 102. The semiconductor layer 105 may form a channel of a thin film transistor (TFT). The semiconductor layer 105 may be disposed in each pixel in the display area DA and may also be disposed in the non-display area NA. The semiconductor layer 105 may include a source / drain region and a channel region. The semiconductor layer 105 may include polycrystalline silicon.

[0084] The first insulating layer 111 may be provided on the semiconductor layer 105. The first insulating layer 111 may be provided over the entire surface of the base substrate 101. The first insulating layer 111 may be a gate insulating film having a gate insulating function. The first insulating layer 111 may include a silicon compound or a metal oxide. For example, the first insulating layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide, and these materials may be used alone or in combination.

[0085] The first conductive layer 120 may be disposed on the first insulating layer 111. The first conductive layer 120 may include a gate electrode GE of the TFT and a first electrode CE1 of the storage capacitor Cst. Although not specifically shown, the first conductive layer 120 may further include a gate signal line. The gate signal line may be arranged to pass through the display area DA and the panel pad area P_PA. The gate signal line may be connected to the signal line PAD of the third conductive layer 140. The first conductive layer 120 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 120 may be a single layer film or a stack of multiple films.

[0086] The second insulating layer 112 may be disposed on the first conductive layer 120. The second insulating layer 112 may isolate the first conductive layer 120 from the second conductive layer 130. The second insulating layer 112 may include one selected from the aforementioned examples of materials for the first insulating layer 111. In the panel pad area P_PA, the second insulating layer 112 may include a plurality of contact holes that partially expose the top surfaces of the gate signal lines. The signal lines PAD and the gate signal lines may be electrically connected through the contact holes.

[0087] The second conductive layer 130 may be disposed on the second insulating layer 112. The second conductive layer 130 may include a second electrode CE2 of the storage capacitor Cst. The second conductive layer 130 may include one selected from the aforementioned examples of the material of the first conductive layer 120. The first electrode CE1 and the second electrode CE2 of the storage capacitor Cst may form the storage capacitor Cst via the second insulating layer 112.

[0088] The third insulating layer 113 may be disposed on the second conductive layer 130. The third insulating layer 113 may include at least one selected from the aforementioned examples of materials for the first insulating layer 111. In some embodiments, the third insulating layer 113 may include an organic insulating material. The organic insulating material may be selected from the examples of materials for the first via layer VIA1.

[0089] The third conductive layer 140 may be disposed on the third insulating layer 113. The third conductive layer 140 may include a source electrode SE, a drain electrode DE, a high potential voltage electrode ELVDDE, and a signal line PAD. The third conductive layer 140 may include at least one metal selected from Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu. The third conductive layer 140 may be a single-layer film, but the present disclosure is not limited thereto. Alternatively, the third conductive layer 140 may be a stack of multiple films. For example, the third conductive layer 140 may include a stack of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu. For example, the third conductive layer 140 may include Ti / Al / Ti.

[0090] The signal line PAD of the third conductive layer 140 may be disposed to overlap the gate signal line of the first conductive layer 120 in the thickness direction and may be electrically coupled to the gate signal line of the first conductive layer 120 through contact holes of the second insulating layer 112 and the third insulating layer 113 .

[0091] A plurality of signal lines PAD may be provided. The plurality of signal lines PAD may be provided to be spaced apart from each other in one direction. The plurality of signal lines PAD may be provided to extend to the end of the panel pad area P_PA. The plurality of signal lines PAD may be connected to the gate signal lines and thus may be connected to the display area DA.

[0092] The first via layer VIA1 or the fourth insulating layer may be provided on the third conductive layer 140. The first via layer VIA1 or the fourth insulating layer may include an organic insulating material or an inorganic insulating material. The organic insulating material may include at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, and benzocyclobutene (BCB). The inorganic insulating material may include at least one of the aforementioned examples of the material of the first insulating layer 111.

[0093] like Figure 2 As shown in FIG, in the panel pad area P_PA, the first via layer VIA1 may expose the top surface of the signal line PAD. The portion of the top surface of the signal line PAD exposed by the first via layer VIA1 may be electrically connected to the PCB 300 via the first adhesive member AM1.

[0094] PCB 300 may also include a lead 320 disposed on one surface of the first circuit area CA1 of the printed base film 310; and a circuit lead 330 disposed on one surface of the third circuit area CA3 of the printed base film 310. The lead 320 may be electrically connected to the signal line PAD. For example, the lead 320 may be electrically connected to the exposed portion of the top surface of the signal line PAD via a first adhesive member AM1. The first adhesive member AM1 may be an anisotropic conductive film (ACF). The ACF may include a resin layer and conductive balls dispersed within the resin layer.

[0095] The lead 320 and the circuit lead 330 may include a metal material. The lead 320 and the circuit lead 330 may include at least one metal selected from Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu. For example, the lead 320 may include Cu and Au.

[0096] The fourth conductive layer 150 may be disposed on the first via layer VIA1. The fourth conductive layer 150 may include a data line DL, a connection electrode CNE, and a high-potential voltage line ELVDDL. The data line DL may be electrically coupled to the source electrode SE of the TFT via a contact hole penetrating the first via layer VIA1. The connection electrode CNE may be electrically coupled to the drain electrode DE of the TFT via another contact hole penetrating the first via layer VIA1. The high-potential voltage line ELVDDL may be electrically connected to the high-potential voltage electrode ELVDDE via yet another contact hole penetrating the first via layer VIA1. The fourth conductive layer 150 may include one selected from the aforementioned examples of the material of the third conductive layer 140.

[0097] The second via layer VIA2 may be disposed on the fourth conductive layer 150. The second via layer VIA2 may include at least one selected from among the aforementioned examples of the material of the first via layer VIA1.

[0098] The anode electrode ANO may be disposed on the second via layer VIA2 and may be electrically connected to the connection electrode CNE via a contact hole penetrating the second via layer VIA2.

[0099] The bank layer BANK may be disposed on the anode electrode ANO. The bank layer BANK may include an opening exposing the anode electrode ANO. The bank layer BANK may be formed of an organic insulating material or an inorganic insulating material. For example, the bank layer BANK may include at least one of a photoresist, a polyimide resin, an acrylic resin, a silicon compound, and a polyacrylic resin.

[0100] The organic layer EL may be disposed on the top surface of the anode electrode ANO and in the opening of the bank layer BANK. The cathode electrode CAT may be disposed on the organic layer EL and on the bank layer BANK. The cathode electrode CAT may be a common electrode provided for all pixels. The anode electrode ANO, the organic layer EL, and the cathode electrode CAT together constitute an OLED.

[0101] The thin film encapsulation layer 170 is disposed on the cathode electrode CAT. The thin film encapsulation layer 170 may cover the OLED. The thin film encapsulation layer 170 may be a layer in which inorganic films and organic films are alternately stacked. For example, the thin film encapsulation layer 170 may include a first inorganic encapsulation film 171, an organic encapsulation film 172, and a second inorganic encapsulation film 173 stacked in sequence.

[0102] Figure 3 It shows Figure 1 A partial layout diagram of the pad area of the display device, Figure 4 It shows Figure 1 A partial layout diagram of a printed circuit board of a display device, Figure 5 It shows Figure 1 The display device pad area and PCB layout diagram, Figure 6 It is along Figure 5 A cross-sectional view taken along line VI-VI', Figure 7 It is along Figure 5 A cross-sectional view taken along line VII-VII', Figure 8 It is along Figure 5 A sectional view taken along line VIII-VIII', Figure 9 It is along Figure 5 A sectional view taken along line IX-IX'.

[0103] Reference Figure 3 , a plurality of signal lines PAD may be provided and may be arranged along a first direction DR1. The plurality of signal lines PAD may include, for example, a power pad, a data pad, and a panel dummy pad. The second direction DR2 may be a direction from the panel pad area P_PA to the display area DA. The first direction DR1 may be a direction intersecting the second direction DR2. Figure 3 It is shown that the plurality of signal lines PAD have a uniform width and extend to the display area DA, but the present disclosure is not limited thereto.

[0104] The first adhesive member AM1 may be disposed in the panel pad area P_PA.The first adhesive member AM1 may be disposed on the plurality of signal lines PAD.

[0105] The display panel 100 of the display device 1 may further include an insulating pattern VIA3 disposed along the first direction DR1 at an end of the base substrate 101 along one of the short sides of the base substrate 101. The insulating pattern VIA3 may be disposed in the same layer as the first via layer VIA1 or the fourth insulating layer. The insulating pattern VIA3 may include the same material as the first via layer VIA1 or the fourth insulating layer. The insulating pattern VIA3 may be formed by the same process as the first via layer VIA1.

[0106] The insulating pattern VIA3 can be arranged between a plurality of signal lines PAD. Figure 3 It is shown as not overlapping with the plurality of signal lines PAD, but may slightly overlap with the plurality of signal lines PAD in the thickness direction.

[0107] The insulating pattern VIA3 may contact adjacent sides of corresponding adjacent signal lines PAD among the plurality of signal lines PAD, but the present disclosure is not limited thereto. Alternatively, the insulating pattern VIA3 may be disposed a predetermined distance away from adjacent sides of corresponding adjacent signal lines PAD among the plurality of signal lines PAD.

[0108] The insulating pattern VIA3 may be disposed on the end of the base substrate 101 to be aligned in a thickness direction with the end of the base substrate 101. That is, in a plan view, the insulating pattern VIA3 may protrude from the end of the base substrate 101 toward the display area DA.

[0109] like Figure 3 As shown in , the insulating pattern VIA3 may have a pentagonal shape in a plan view. That is, the first side of the insulating pattern VIA3 may be aligned with the end of the base substrate 101 in the thickness direction, the second side and the third side of the insulating pattern VIA3 connected to the first side of the insulating pattern VIA3 may respectively face the adjacent sides of corresponding adjacent signal lines PAD among the plurality of signal lines PAD, and the fourth side and the fifth side of the insulating pattern VIA3, respectively connected to the second side and the third side of the insulating pattern VIA3, may extend in a direction between the first direction DR1 and the second direction DR2. The fourth side and the fifth side of the insulating pattern VIA3 may form a corner protruding toward the display area DA.

[0110] In a plan view, the insulation pattern VIA3 and the plurality of signal lines PAD may be covered by the first adhesive member AM1 in the panel pad area P_PA.

[0111] Reference Figure 4, a plurality of leads 320 may be provided. The plurality of leads 320 of the PCB 300 may be electrically connected to the driver IC 390. The plurality of leads 320 may be arranged to be spaced apart from each other in the first direction DR1. Each of the plurality of leads 320 may include portions having different widths in the first direction DR1. Each of the plurality of leads 320 may include a first lead portion 321 disposed adjacent to an end of the first circuit region CA1, a second lead portion 322 connected to the driver IC 390, a third lead portion 323 disposed between the first lead portion 321 and a fifth lead portion 325, a fourth lead portion 324 disposed between the second lead portion 322 and the fifth lead portion 325, and a fifth lead portion 325 disposed between the third lead portion 323 and the fourth lead portion 324.

[0112] The second lead portion 322 may have a first width W1, the fourth lead portion 324 may have a second width W2, and the fifth lead portion 325 may have a third width W3. The first width W1, the second width W2, and the third width W3 may be widths measured in the first direction DR1. The first width W1 and the third width W3 may be uniform, while the second width W2 may be within a range between the first width W1 and the third width W3 and may gradually increase from the second lead portion 322 to the fifth lead portion 325.

[0113] Figure 4 The side of the fourth lead portion 324 may be straight in a plan view, but the present disclosure is not limited thereto. That is, the side of the fourth lead portion 324 may have a predetermined slope so that the second width W2 may gradually decrease from the second lead portion 322 to the fifth lead portion 325.

[0114] The first and third lead portions 321 and 323 may be symmetrical to the second and fourth lead portions 322 and 324 with respect to the fifth lead portion 325 .

[0115] Reference Figure 5 , the plurality of leads 320 may be respectively disposed on the plurality of signal line PADs. Each of the plurality of signal line PADs may be disposed under a plurality of portions of the corresponding lead 320. Each of the plurality of signal line PADs may be disposed so as to overlap the first to fifth lead portions 321 to 325 of the corresponding lead 320 in the thickness direction.

[0116] like Figure 5, each of the insulating patterns VIA3 of the display panel 100 may be disposed between the second lead portion 322 and the fourth lead portion 324 of one lead line 320 and the second lead portion 322 and the fourth lead portion 324 of another (adjacent) lead line 320. That is, the insulating pattern VIA3 may be disposed to overlap the second lead portion 322 and the fourth lead portion 324 of the lead line 320 in the first direction DR1.

[0117] The second and third sides of the insulating pattern VIA3 can extend in the same direction as the second lead portion 322 of the lead 320 and face the second lead portion 322 of the lead 320, the fourth side of the insulating pattern VIA3 can extend in the same direction as the left side of the fourth lead portion 324 of the lead 320 and face the left side of the fourth lead portion 324 of the lead 320, and the fifth side of the insulating pattern VIA3 can extend in the same direction as the right side of the fourth lead portion 324 of the lead 320 and face the right side of the fourth lead portion 324 of the lead 320.

[0118] Reference Figure 6 The PCB 300 may further include an insulating layer IL300 disposed under the printed base film 310 and exposing the surface of the leads 320 in the panel pad area P_PA or the first circuit area CA1. The insulating layer IL300 may include a flexible insulating material. For example, the insulating layer IL300 may include a flexible film containing solder resist or PI.

[0119] The portion of the surface of the lead 320 exposed by the insulating layer IL300 may be electrically connected to the signal line PAD. One side of the first adhesive member AM1 may be disposed a predetermined distance apart from the first via layer VIA1, and the other side of the first adhesive member AM1 may be aligned with the end of the base substrate 101 in the thickness direction.

[0120] The first adhesive member AM1 may be provided between the lead 320 and the signal line PAD. The first adhesive member AM1 may be interposed between the lead 320 and the signal line PAD to electrically couple the lead 320 and the signal line PAD. The first adhesive member AM1 may be provided to overlap with the first to fifth lead portions 321 to 325 of the lead 320 and may be in contact with the first to fifth lead portions 321 to 325 of the lead 320.

[0121] Reference Figure 7The insulating pattern VIA3 may be disposed on the surface of the third insulating layer 113 at an end of the base substrate 101. The first adhesive member AM1 may be disposed on the side and top surfaces of the insulating pattern VIA3 and in contact with the side and top surfaces of the insulating pattern VIA3. The first adhesive member AM1 may be disposed so as to overlap the insulating pattern VIA3. The portion of the first adhesive member AM1 overlapping the insulating pattern VIA3 may be thinner than the portion of the first adhesive member AM1 not overlapping the insulating pattern VIA3.

[0122] Reference Figure 8 , the fifth lead portions 325 of a pair of adjacent leads 320 spaced apart from each other in the first direction DR1 may be spaced apart by a fourth width W4. A pair of adjacent signal lines PAD spaced apart from each other in the first direction DR1 may also be spaced apart by the fourth width W4, but the present disclosure is not limited thereto. Alternatively, the pair of adjacent signal lines PAD may be spaced apart by a distance less than or greater than the fourth width W4.

[0123] The first adhesive member AM1 may be in contact with the side surfaces of the fifth lead portions 325 of a pair of adjacent leads 320 and with the side surfaces of a pair of adjacent signal lines PAD.

[0124] The first bonding member AM1 may be disposed so as to overlap the fifth lead portions 325 of the pair of adjacent leads 320 and the pair of adjacent signal lines PAD. The portion of the first bonding member AM1 overlapping the fifth lead portions 325 of the pair of adjacent leads 320 and the pair of adjacent signal lines PAD may be thinner than the portion of the first bonding member AM1 not overlapping the fifth lead portions 325 of the pair of adjacent leads 320 and the pair of adjacent signal lines PAD.

[0125] The first adhesive member AM1 may include a resin layer RL and a plurality of conductive balls CB dispersed in the resin layer RL. The lead 320 and the signal line PAD may be electrically coupled via the conductive balls CB.

[0126] Reference Figure 9 , the second lead portions 322 of a pair of adjacent leads 320 spaced apart from each other in the first direction DR1 may be arranged to be spaced apart from each other by a distance greater than the fourth width W4. In addition, the fourth lead portions 324 (see FIG. 3 ) of the pair of adjacent leads 320 Figure 5 ) may be set to be spaced apart from each other by a distance greater than the fourth width W4 but less than a distance between the second lead portions 322 of the pair of adjacent leads 320.

[0127] The height of the insulating pattern VIA3 from the third insulating layer 113 in the thickness direction may be greater than the height of a pair of adjacent signal lines PAD from the third insulating layer 113 in the thickness direction. That is, the top surface of the insulating pattern VIA3 may be higher than the top surfaces of the pair of adjacent signal lines PAD. The side surface of the insulating pattern VIA3 may be in direct contact with the pair of adjacent signal lines PAD, but the present disclosure is not limited to this.

[0128] The insulating pattern VIA3 may have a first side adjacent to the left second lead portion 322 and a second side adjacent to the right second lead portion 322. The first side of the insulating pattern VIA3 and the left second lead portion 322 may be separated from each other by a fifth width W5, and the second side of the insulating pattern VIA3 and the right second lead portion 322 may be separated from each other by a sixth width W6.

[0129] The sum of the fifth width W5 and the sixth width W6 may be substantially the same as the fourth width W4. For example, the sum of the fifth width W5 and the sixth width W6 may be about 0.8 to about 1.2 times the fourth width W4.

[0130] Refer again Figure 5 In a plan view, the sum of the distance between the left side of the fourth portion 324 of the lead 320 and the insulating pattern VIA3 and the distance between the right side of the fourth portion 324 of the lead 320 and the insulating pattern VIA3 may be substantially the same as the fourth width W4. For example, in a plan view, the sum of the distance between the left side of the fourth portion 324 of the lead 320 and the insulating pattern VIA3 and the distance between the right side of the fourth portion 324 of the lead 320 and the insulating pattern VIA3 may be approximately 0.8 to approximately 1.2 times the fourth width W4.

[0131] Refer again Figure 9 The first bonding member AM1 can be in direct contact with the top surface of the pair of adjacent signal lines PAD, the bottom surface of the second lead portion 322 of the pair of adjacent leads 320 facing the signal line PAD, the side of the second lead portion 322 of the pair of adjacent leads 320, the portion of the side of the insulating pattern VIA3 exposed by the pair of adjacent signal lines PAD, and the top surface of the insulating pattern VIA3.

[0132] Figure 10 It shows that Figure 1 A cross-sectional view of a process of bonding a display panel and a PCB of a display device, and Figure 11 It is shown in Figure 10 A plan view of how the first bonding member flows during the process shown in FIG.

[0133] Reference Figure 10 and 11, a bonding device (not shown) is placed on the PCB 300. The bonding device can bond the lead 320 to the signal line PAD via the first bonding member material AM1a by pressing the top surface of the PCB 300. The bonding device can partially melt the first bonding member material AM1a by providing heat. Figure 11 As shown in FIG, due to the influence of the downward pressure, the partially melted first adhesive member material AM1a may fill the spaces between the leads 320 and the signal lines PAD.

[0134] Figure 11 The downward flow of the first bonding member material AM1a in the second direction DR2 is shown when the first bonding member material AM1a partially melts and fills the spaces between the leads 320 and between the signal lines PAD under the influence of downward pressure.

[0135] The flow rate of the first adhesive member material AM1a is related to the area of the space in which the first adhesive member material AM1a can flow. As mentioned above, the fifth lead portions 325 of the leads 320 spaced apart from each other in the first direction DR1 may be spaced apart by a fourth width W4, the second lead portions 322 of the leads 320 may be spaced apart by a distance greater than the fourth width W4, and the fourth lead portions 324 of the leads 320 may also be spaced apart by a distance greater than the fourth width W4.

[0136] Therefore, when the first adhesive member material AM1a partially melts and flows downward in the second direction DR2, the flow rate of the first adhesive member material AM1a may decrease because the distance between the leads 320 in the first direction DR1 increases from the fifth lead portion 325 to the fourth lead portion 324 to the second lead portion 322. As a result, bubbles generated in the first adhesive member material AM1a may not be properly pushed away to the end of the display panel 100, but may remain around the fourth lead portion 324 and the second lead portion 322. The remaining bubbles may cause moisture to accumulate, resulting in bonding defects around the fourth lead portion 324 and the second lead portion 322.

[0137] The first side of the insulating pattern VIA3 and the second lead portion 322 located to the left of the insulating pattern VIA3 may be separated by a fifth width W5, and the second side of the insulating pattern VIA3 and the second lead portion 322 located to the right of the insulating pattern VIA3 may be separated by a sixth width W6, and the sum of the fifth width W5 and the sixth width W6 may be substantially the same as the fourth width W4. In addition, the sum of the distance between the left side of the fourth portion 324 of the lead 320 and the insulating pattern VIA3 and the distance between the right side of the fourth portion 324 of the lead 320 and the insulating pattern VIA3 may be substantially the same as the fourth width W4.

[0138] Therefore, when the first adhesive member material AM1a partially melts and flows downward in the second direction DR2 due to the influence of the downward pressure, even if the distance between the leads 320 increases from the fifth lead portion 325 to the fourth lead portion 324 to the second lead portion 322, any decrease in the flow rate of the first adhesive member material AM1a can be prevented. That is, the exemplary embodiment can prevent bubbles generated in the first adhesive member material AM1a from remaining around the fourth lead portion 324 and the second lead portion 322, and as a result, the penetration of external moisture or the occurrence of bonding defects due to bubbles can be prevented in advance.

[0139] The following describes display devices according to other embodiments of the present disclosure, focusing mainly on the Figure 1 The difference in display devices.

[0140] Figure 12 is a partial layout diagram showing a pad area of a display device according to another embodiment of the present disclosure, Figure 13 It shows Figure 12 Partial layout diagram of the PCB of the display device, Figure 14 It shows Figure 12 The display device pad area and PCB layout diagram, Figure 15 It is along Figure 14 A sectional view taken along line XV-XV', and Figure 16 It is along Figure 14 A sectional view taken along line XVI-XVI'.

[0141] according to Figures 12 to 16 A display device of an embodiment with Figure 1 The display device 1 is different in that the display panel 100_1 does not include an insulating pattern, and the PCB 300_1 includes a protrusion pattern PT.

[0142] Specifically, the insulating pattern may not be provided in the display panel 100_1 , but the protrusion pattern PT may be provided in the PCB 300_1 .

[0143] Reference Figure 13 and Figure 14 , the insulating layer IL300_1 of the PCB 300_1 may include a protrusion pattern PT protruding from an end portion of the main body portion MR of the insulating layer IL300_1. A plurality of protrusion patterns PT may be provided.

[0144] The protruding pattern PT may include the same material as the insulating layer IL300_1. In a plan view, the protruding pattern PT may be disposed between a plurality of adjacent signal lines PAD. Although not shown as overlapping the signal lines PAD, the protruding pattern PT may slightly overlap the signal lines PAD in the thickness direction.

[0145] The protrusion pattern PT may be provided on the end of the base substrate 101 to be aligned in a thickness direction with the end of the base substrate 101. That is, in a plan view, the protrusion pattern PT may protrude from the end of the base substrate 101 toward the display area DA.

[0146] The protruding pattern PT may have Figure 3 The insulating pattern VIA3 may have substantially the same shape as the protruding pattern PT. That is, the protruding pattern PT may have a pentagonal shape in a plan view. In other words, the first side of the protruding pattern PT may be aligned with the end of the base substrate 101 in the thickness direction, the second and third sides of the protruding pattern PT connected to the first side of the protruding pattern PT may respectively face the adjacent sides of the adjacent signal line PAD, and the fourth and fifth sides of the protruding pattern PT, respectively connected to the second and third sides of the protruding pattern PT, may extend in a direction between the first direction DR1 and the second direction DR2. The fourth and fifth sides of the protruding pattern PT may form a corner that protrudes toward the display area DA.

[0147] In a plan view, the protrusion pattern PT and the signal line PAD may be covered by the first adhesive member AM1 in the panel pad area P_PA.

[0148] Reference Figure 15 The protruding pattern PT may be disposed beneath the printed base film 310 and may be physically connected to the main portion MR of the insulating layer IL300_1. The first adhesive member AM1 may be disposed on and in contact with the side and bottom surfaces of the protruding pattern PT. The first adhesive member AM1 may be disposed so as to overlap the protruding pattern PT. The portion of the first adhesive member AM1 overlapping the protruding pattern PT may be thinner than the portion of the first adhesive member AM1 not overlapping the protruding pattern PT.

[0149] Reference Figure 16 , the second lead portions 322 of a pair of adjacent leads 320 spaced apart from each other in the first direction DR1 may be disposed to be spaced apart from each other by a distance greater than the fourth width W4. In addition, the fourth lead portions 324 of a pair of adjacent leads 320 may be disposed to be spaced apart from each other by a distance greater than the fourth width but less than the distance between the second lead portions 322 of the pair of adjacent leads 320.

[0150] The height of the protruding pattern PT from the printed base film 310 in the thickness direction may be greater than the height of the second lead portions 322 of a pair of adjacent leads 320 from the protruding pattern PT in the thickness direction. In other words, the bottom surface of the protruding pattern PT may be lower than the bottom surface of the second lead portions 322 of the pair of adjacent leads 320.

[0151] The protrusion pattern PT may have a first side adjacent to the left second lead portion 322 and a second side adjacent to the right second lead portion 322. The first side of the protrusion pattern PT and the left second lead portion 322 may be separated from each other by a fifth width W5, and the second side of the protrusion pattern PT and the right second lead portion 322 may be separated from each other by a sixth width W6.

[0152] The sum of the fifth width W5 and the sixth width W6 may be substantially the same as the fourth width W4. For example, the sum of the fifth width W5 and the sixth width W6 may be about 0.8 to about 1.2 times the fourth width W4.

[0153] In addition, refer again Figure 14 In a plan view, the sum of the distance between the left side of the fourth portion 324 of the lead 320 and the protrusion pattern PT and the distance between the right side of the fourth portion 324 of the lead 320 and the protrusion pattern PT may be substantially the same as the fourth width W4. For example, in a plan view, the sum of the distance between the left side of the fourth portion 324 of the lead 320 and the protrusion pattern PT and the distance between the right side of the fourth portion 324 of the lead 320 and the protrusion pattern PT may be approximately 0.8 times to approximately 1.2 times the fourth width W4.

[0154] The first side of the protruding pattern PT and the second lead portion 322 located to the left of the protruding pattern PT may be separated by a fifth width W5, and the second side of the protruding pattern PT and the second lead portion 322 located to the right of the protruding pattern PT may be separated by a sixth width W6, and the sum of the fifth width W5 and the sixth width W6 may be substantially the same as the fourth width W4. In addition, the sum of the distance between the left side of the fourth portion 324 of the lead 320 and the protruding pattern PT and the distance between the right side of the fourth portion 324 of the lead 320 and the protruding pattern PT may be substantially the same as the fourth width W4.

[0155] Therefore, when the first adhesive member material AM1a partially melts and flows downward in the second direction DR2 due to the influence of the downward pressure, even if the distance between the leads 320 increases from the fifth lead portion 325 to the fourth lead portion 324 to the second lead portion 322, any decrease in the flow rate of the first adhesive member material AM1a can be prevented. In other words, it is possible to prevent bubbles generated in the first adhesive member material AM1a from remaining around the fourth lead portion 324 and the second lead portion 322. As a result, it is possible to prevent the penetration of external moisture or the occurrence of bonding defects due to bubbles in advance.

[0156] Figure 17 is a layout diagram illustrating a pad area and a PCB of a display device according to another embodiment of the present disclosure.

[0157] Figure 17Display device and Figure 1 The display device 1 is different in that the insulating pattern VIA3_1 may have a curved side.

[0158] Specifically, Figure 3 The fourth side and the fifth side of the insulating pattern VIA3 may be curved, as shown in FIG. Figure 17 As shown in .

[0159] Figure 18 is a layout diagram illustrating a pad area and a PCB of a display device according to another embodiment of the present disclosure.

[0160] Figure 18 Display device and Figure 1 The display device 1 is different in that the insulating pattern VIA3_2 may have a triangular shape in a plan view.

[0161] Specifically, Figure 3 The second side and the fourth side of the insulating pattern VIA3 together form a sixth side, Figure 3 The third side and the fifth side of the insulating pattern VIA3 form a seventh side. Therefore, the first side, the sixth side, and the seventh side of the insulating pattern VIA3 may form a triangle shape.

[0162] Figure 19 is a layout diagram illustrating a pad area and a PCB of a display device according to another embodiment of the present disclosure.

[0163] Figure 19 Display device and Figure 1 The display device 1 is different only in that the insulating pattern VIA3_3 has a rectangular shape in a plan view, and thus, a detailed description thereof will be omitted.

[0164] Figure 20 FIG. 1 is a partial layout diagram of a PCB of a display device according to another embodiment of the present disclosure.

[0165] Figure 20 Display device and Figure 13 The difference between the display device is that the protruding pattern PT_1 is different from Figure 17 The insulating pattern VIA3_1 may have a curved side, and thus, a detailed description thereof will be omitted.

[0166] Figure 21 FIG. 1 is a partial layout diagram of a PCB of a display device according to another embodiment of the present disclosure.

[0167] Figure 21 Display device and Figure 13 The difference between the display device is that the protruding pattern PT_2 is different from Figure 18The insulating pattern VIA3_2 may have a triangular shape in a plan view, and thus, a detailed description thereof will be omitted.

[0168] Figure 22 FIG. 1 is a partial layout diagram of a PCB of a display device according to another embodiment of the present disclosure.

[0169] Figure 22 Display device and Figure 13 The difference between the display device is that the protruding pattern PT_3 is different from Figure 19 The insulating pattern VIA3_3 may have a rectangular shape in a plan view, and thus, a detailed description thereof will be omitted.

[0170] Figure 23 is a layout diagram illustrating a pad area and a PCB of a display device according to another embodiment of the present disclosure.

[0171] Figure 23 Display device and Figure 1 The display device 1 is different in that each of the insulating patterns V1A3_4 includes a plurality of individual patterns, ie, first to third patterns P1 to P3.

[0172] Specifically, refer to Figure 23 , the first pattern P1 to the third pattern P3 may be arranged to be spaced apart from each other in the first direction DR1. The third pattern P3 may be arranged between the first pattern P1 and the second pattern P2. Figure 10 and Figure 11 As described above, the first adhesive member material (not shown) may flow between the first pattern P1, the second pattern P2, and the third pattern P3. Each of the insulating patterns VIA3_4 is Figure 23 3. In the embodiment shown in FIG. 3, the insulating patterns VIA3_4 are shown as including three separate patterns, but the present disclosure is not limited thereto. Alternatively, each of the insulating patterns VIA3_4 may include two separate patterns or four or more separate patterns.

[0173] Figure 24 is a layout diagram illustrating a pad area and a PCB of a display device according to another embodiment of the present disclosure.

[0174] Figure 24 Display device and Figure 23 The display device of FIG. 5 is different in that each of the insulating patterns VIA3_5 includes a plurality of individual patterns, ie, first to third patterns P1_1 to P3_1.

[0175] Specifically, refer to Figure 24, the third pattern P3_1 may be disposed below the first pattern P1_1 and the second pattern P2_1 in the second direction DR2. The first pattern P1_1 and the second pattern P2_1 may be spaced apart from each other in the first direction DR1, and the first pattern P1_1 and the third pattern P3_1, or the second pattern P2_1 and the third pattern P3_1, may be spaced apart from each other in the second direction DR2. The first adhesive member material (not shown) may flow in two streams along the spaces between the first pattern P1_1 and the third pattern P3_1 and between the second pattern P2_1 and the third pattern P3_1.

[0176] Figure 25 FIG. 1 is a partial layout diagram of a PCB of a display device according to another embodiment of the present disclosure.

[0177] Figure 25 Display device and Figure 13 The display device of is different only in that each of the protruding patterns PT_4 includes a plurality of individual patterns, ie, fourth to sixth patterns P4 to P6, and thus, a detailed description thereof will be omitted.

[0178] Figure 26 FIG. 1 is a partial layout diagram of a PCB of a display device according to another embodiment of the present disclosure.

[0179] Figure 26 Display device and Figure 25 The display device of is different only in that each of the protruding patterns PT_5 includes a plurality of individual patterns, ie, fourth to sixth patterns P4_1 to P6_1 , and thus, a detailed description thereof will be omitted.

[0180] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concepts of the present disclosure are not limited to such embodiments, but rather to the broader scope of the claims set forth herein and various obvious modifications and equivalent arrangements.

Claims

1. A display device, comprising: a base substrate having a display area and a non-display area including a pad area; a plurality of signal lines provided on the base substrate to extend from an end portion of the base substrate in a first direction and to be spaced apart from each other in a second direction intersecting the first direction; a pattern disposed between the plurality of signal lines on an outermost portion of the base substrate to reduce a spatial difference between adjacent signal lines; as well as a printed circuit board attached to the pad area and comprising: a driver integrated circuit; and a plurality of leads connected to the driver integrated circuit and spaced apart from each other in the second direction, Wherein, each of the multiple leads includes: a first lead portion having a first width; a second lead portion having a second width narrower than the first width and arranged between the first lead portion and the driver integrated circuit; and a third lead portion arranged between the first lead portion and the second lead portion and having a third width, and the third width gradually increases from the second lead portion toward the first lead portion.

2. The display device according to claim 1, further comprising: an insulating layer exposing the plurality of signal lines in the pad region, Wherein, the pattern and the insulating layer are arranged in the same layer.

3. The display device according to claim 2, wherein: The plurality of lead lines are disposed to overlap with the plurality of signal lines.

4. The display device according to claim 3, further comprising: an anisotropic conductive film, provided between the plurality of signal lines and the plurality of lead lines, The plurality of signal lines and the plurality of lead lines are electrically connected through the anisotropic conductive film.

5. The display device according to claim 4, wherein The pattern is provided between the plurality of leads of the printed circuit board. The display device according to claim 1 , wherein: The pattern is provided between the second lead portions.

7. The display device according to claim 6, wherein: A distance between the first lead portions is smaller than a distance between the second lead portions.

8. A printed circuit board, comprising: Driver integrated circuit; a plurality of leads connected to the driver integrated circuit and separated from each other; as well as Insulation layer, exposing the leads, wherein the insulating layer includes a protruding pattern that reduces the distance gap between the plurality of leads, and Wherein, each of the multiple leads includes: a first lead portion having a first width; a second lead portion having a second width narrower than the first width and arranged between the first lead portion and the driver integrated circuit; and a third lead portion arranged between the first lead portion and the second lead portion and having a third width, and the third width gradually increases from the second lead portion toward the first lead portion.

9. The printed circuit board according to claim 8, wherein The protrusion pattern is provided between the second lead portions.

Images