Display device

Abstract

The display device includes a display panel and a display panel driver. The display panel includes pixels, and the pixels include a first type of switching element and a second type of switching element different from the first type. The display panel driver drives the display panel. The display panel driver drives the first type of switching element and the second type of switching element at a high driving frequency in a first mode. The display panel driver drives the first type of switching element at the high driving frequency in a second mode, and drives the second type of switching element at a low driving frequency lower than the high driving frequency. The display panel driver drives the first type of switching element and the second type of switching element at the low driving frequency in a third mode.

Description

Technical Field

[0001] Example embodiments of the inventive concepts relate to a display device, and more particularly, to a display device that reduces power consumption and improves display quality. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver, and a drive controller. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The emission driver outputs an emission signal to the emission line. The drive controller controls the gate driver, the data driver, and the emission driver.

[0003] When the image displayed on the display panel is a static image or the display panel operates in a normally-on mode, the driving frequency of the display panel may be reduced to reduce power consumption.

[0004] When the driving frequency of the display panel is reduced, flickering may be displayed to the user, and display defects may be generated due to a shift in a threshold voltage, so that the display quality of the display panel may be deteriorated. Summary of the invention

[0005] Technical Purpose

[0006] Example embodiments of the inventive concept provide a display device capable of reducing power consumption and improving display quality.

[0007] Technical Solution

[0008] In an example embodiment of a display device according to the concept of the present invention, the display device includes a display panel and a display panel driver. The display panel includes pixels, and the pixels include a first type of switching element and a second type of switching element different from the first type. The display panel driver drives the display panel. The display panel driver is configured to drive the first type of switching element at a high driving frequency in a first mode and drive the second type of switching element at the high driving frequency. The display panel driver is configured to drive the first type of switching element at the high driving frequency in a second mode, and drive the second type of switching element at a low driving frequency lower than the high driving frequency. The display panel driver is configured to drive the first type of switching element at the low driving frequency and drive the second type of switching element at the low driving frequency in a third mode.

[0009] In example embodiments, the first type of switching element may be a polysilicon thin film transistor. The second type of switching element may be an oxide thin film transistor.

[0010] In example embodiments, the first type of switching element may be a P-type transistor. The second type of switching element may be an N-type transistor.

[0011] In an example embodiment, the pixel may include a first pixel switching element, a second pixel switching element, a third pixel switching element, a fourth pixel switching element, a fifth pixel switching element, a sixth pixel switching element, a seventh pixel switching element, a storage capacitor, and an organic light emitting element, the first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node, the second pixel switching element including a control electrode to which a first data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node, the third pixel switching element including a control electrode to which a second data write gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the third node, the fourth pixel switching element including a control electrode to which a data voltage is applied The fifth pixel switching element includes a control electrode applied with an emission signal, an input electrode applied with an initialization voltage, and an output electrode connected to the first node; the sixth pixel switching element includes a control electrode applied with the emission signal, an input electrode connected with the third node, and an output electrode connected to the anode of the organic light-emitting element; the seventh pixel switching element includes a control electrode, an input electrode applied with the initialization voltage, and an output electrode connected to the anode of the organic light-emitting element; the storage capacitor includes a first electrode applied with the high power supply voltage and a second electrode connected to the first node; and the organic light-emitting element includes the anode and a cathode applied with a low power supply voltage.

[0012] In example embodiments, the first pixel switching element, the second pixel switching element, the fifth pixel switching element, and the sixth pixel switching element may be polysilicon thin film transistors. The third pixel switching element, the fourth pixel switching element, and the seventh pixel switching element may be oxide thin film transistors.

[0013] In example embodiments, the control electrode of the seventh pixel switching element may be connected to the control electrode of the sixth pixel switching element or receive an organic light emitting element initialization gate signal.

[0014] In example embodiments, the first pixel switching element, the second pixel switching element, the fifth pixel switching element, the sixth pixel switching element, and the seventh pixel switching element may be the polysilicon thin film transistor. The third pixel switching element and the fourth pixel switching element may be the oxide thin film transistor.

[0015] In an example embodiment, the first mode may be a high frequency driving mode. The second mode may be a low frequency hybrid driving mode. The third mode may be a low frequency driving mode. When an input image entering the display panel driver represents a moving image, the display panel may be driven in the first mode. When the input image represents a static image and the display device is in the hybrid driving mode, the display panel may be driven in the second mode. When the input image represents a static image and the display device is not in the hybrid driving mode, the display panel may be driven in the third mode.

[0016] In example embodiments, the display panel driver may be configured to determine a flicker value of the input image. The display panel driver may be configured to determine the low driving frequency according to the flicker value of the input image.

[0017] In example embodiments, when the input image represents a static image and the difference between the maximum brightness of the input image and the minimum brightness of the input image is equal to or less than a first reference value, the display panel driver may be configured to drive the display panel in the second mode. When the input image represents a static image and the difference between the maximum brightness of the input image and the minimum brightness of the input image is greater than the first reference value, the display panel driver may be configured to drive the display panel in the third mode.

[0018] In example embodiments, when the input image represents a static image and the size of the images having the same grayscale value in the input image is greater than a second reference value, the display panel driver may be configured to drive the display panel in the second mode. When the input image represents a static image and the size of the images having the same grayscale value in the input image is equal to or less than the second reference value, the display panel driver may be configured to drive the display panel in the third mode.

[0019] In an example embodiment, the display panel driver may be configured to divide the input image into a plurality of segments and to determine segment driving frequencies of the plurality of segments. When an absolute value of a difference between the number of the worst segment having the highest segment driving frequency among the plurality of segments and the number of the majority segment having the most frequently occurring segment driving frequency among the segments is greater than a third reference value, the display panel driver may be configured to drive the display panel at a compensation driving frequency that is smaller than the segment driving frequency of the worst segment.

[0020] In example embodiments, when an absolute value of the difference between the number of the worst segment and the number of the majority segment is greater than the third reference value, the display panel driver may be configured to compensate for data of the worst segment.

[0021] In example embodiments, a second data write gate signal and a data initialization gate signal applied to the display panel may have the low driving frequency in the second mode. A first data write gate signal, an emission signal, and an organic light emitting element initialization gate signal applied to the display panel may have the high driving frequency in the second mode.

[0022] In example embodiments, a first data write gate signal, a second data write gate signal, a data initialization gate signal, an emission signal, and an organic light emitting element initialization gate signal applied to the display panel may have the low driving frequency in the second mode. A low power supply voltage applied to a cathode of an organic light emitting element of the display panel may have the high driving frequency in the second mode.

[0023] In an example embodiment of a display device according to the concept of the present invention, the display device includes a display panel and a display panel driver. The display panel includes pixels, and the pixels include a first type of switching element and a second type of switching element different from the first type. The display panel driver is configured to drive the display panel. The display panel driver is configured to drive the first type of switching element and the second type of switching element at a high driving frequency in a first mode. The display panel driver is configured to drive at least one of the first type of switching element and the second type of switching element at a low driving frequency in a second mode. The display panel driver is configured to count the duration of the second mode. When the duration of the second mode is greater than a reference time, a drive signal applied to at least one of the first type of switching element and the second type of switching element is changed.

[0024] In example embodiments, when the duration of the second mode is greater than the reference time, the display panel driver may be configured to insert a compensation frame having a compensating driving frequency greater than the low driving frequency.

[0025] In example embodiments, a data write gate signal and a data initialization gate signal applied to the display panel may be generated based on a gate-on voltage and a gate-off voltage. When the duration of the second mode is greater than the reference time, the display panel driver may be configured to reduce a level of the gate-off voltage.

[0026] In example embodiments, a data write gate signal and a data initialization gate signal applied to the display panel may be generated based on a gate-on voltage and a gate-off voltage. When the duration of the second mode is greater than the reference time, the display panel driver may be configured to increase a level of the gate-on voltage.

[0027] In example embodiments, when the duration of the second mode is greater than the reference time, the display panel driver may be configured to lower a level of an initialization voltage applied to the display panel.

[0028] Effects of the Invention

[0029] According to the display device, the display panel is driven in the high frequency driving mode, the low frequency hybrid driving mode, and the low frequency driving mode, so that flickering of the display panel can be prevented.

[0030] In addition, an input image of the display panel is divided into a plurality of segments, and a driving frequency of a worst segment having a highest segment driving frequency is reduced, so that power consumption of the display device can be reduced.

[0031] In addition, when the display panel is driven in a low-frequency driving mode for a long time, the threshold voltage of the switching element can be prevented from shifting, thereby preventing display defects of the display panel caused by the shift of the threshold voltage.

[0032] Therefore, the display quality is prevented from being deteriorated in the low-frequency driving mode, so that the power consumption of the display device can be reduced and the display quality of the display panel can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a block diagram illustrating a display device according to an example embodiment of the inventive concept.

[0034] Figure 2 It is shown Figure 1 Circuit diagram of a pixel of a display panel.

[0035] Figure 3 is shown applied to Figure 2 Timing diagram of the pixel input signal.

[0036] Figure 4 It is shown Figure 1Flow chart of a driving mode of a display device.

[0037] Figure 5a is shown in low frequency drive mode applied to Figure 2 A timing diagram of the input signals to the pixels of the display panel.

[0038] Figure 5b is shown in the low frequency hybrid drive mode applied to Figure 2 A timing diagram of the input signals to the pixels of the display panel.

[0039] Figure 6 It is shown Figure 4 Flowchart of the detailed operation of the low frequency drive mode.

[0040] Figure 7 It is shown Figure 4 A flowchart of an example of the detailed operation of the low frequency hybrid drive mode.

[0041] Figure 8 is a flowchart illustrating an example of a detailed operation of a low frequency hybrid driving mode according to an example embodiment of the inventive concept.

[0042] Fig. 9 is a timing diagram illustrating input signals applied to pixels of a display panel according to an example embodiment of the inventive concept.

[0043] Fig.10 is a circuit diagram illustrating a pixel of a display panel according to an example embodiment of the inventive concept.

[0044] Fig.11 is a circuit diagram illustrating a pixel of a display panel according to an example embodiment of the inventive concept.

[0045] Fig.12 is shown applied to Fig.11 Timing diagram of the pixel input signal.

[0046] Fig.13 is a flowchart illustrating an operation of a low frequency driving mode according to an example embodiment of the inventive concept.

[0047] Fig.14 is a conceptual diagram showing a segment driving frequency of an input image of a display panel.

[0048] Fig.15 is a graph showing the segment driving frequency of an input image of a display panel.

[0049] Fig.16 is a flowchart illustrating an operation of a low frequency driving mode according to an example embodiment of the inventive concept.

[0050] Fig.17is a graph illustrating a threshold voltage according to time of a switching element of a display panel according to an example embodiment of the inventive concept.

[0051] Fig.18 is a flow chart illustrating the operation of the display panel in the low frequency driving mode.

[0052] Fig.19 is a timing diagram showing a gate signal applied to a display panel and a compensated gate signal.

[0053] Fig.20a is a table showing the frequency of compensation frames and the number of compensation frames.

[0054] Fig.20b is a table showing the frequency of compensation frames and the number of compensation frames.

[0055] Fig.20c is a table showing the frequency of compensation frames and the number of compensation frames.

[0056] Fig.21 is a flow chart illustrating the operation of the display panel in the low frequency hybrid driving mode.

[0057] Fig. 22 is a timing diagram illustrating a gate signal applied to a display panel and a compensated gate-off voltage according to an example embodiment of the inventive concept.

[0058] Fig.23 is a timing diagram illustrating a gate signal applied to a display panel and a compensated gate-on voltage according to an example embodiment of the inventive concept.

[0059] Fig.24 is a timing diagram illustrating a gate signal applied to a display panel and a compensated initialization voltage according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0060] Hereinafter, the inventive concept will be explained in detail with reference to the accompanying drawings.

[0061] Figure 1 is a block diagram illustrating a display device according to an example embodiment of the inventive concept.

[0062] Reference Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0063] The display panel 100 has a display area displaying an image and a peripheral area adjacent to the display area.

[0064] The display panel 100 includes a plurality of gate lines GWPL, GWNL, GIL, and GBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the gate lines GWPL, GWNL, GIL, and GBL, the data lines DL, and the emission lines EL. The gate lines GWPL, GWNL, GIL, and GBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EL may extend in the first direction D1.

[0065] The driving controller 200 receives input image data IMG and an input control signal CONT from an external device (not shown). For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0066] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0067] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0068] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0069] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0070] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0071] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600 .

[0072] The gate driver 300 generates a gate signal driving the gate lines GWPL, GWNL, GIL, and GBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may sequentially output the gate signal to the gate lines GWPL, GWNL, GIL, and GBL.

[0073] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0074] In example embodiments, the gamma reference voltage generator 400 may be disposed in the driving controller 200 or in the data driver 500 .

[0075] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200 and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into an analog type data voltage using the gamma reference voltage VGREF and outputs the data voltage to the data line DL.

[0076] The emission driver 600 generates an emission signal to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission line EL.

[0077] Figure 2 It is shown Figure 1 1 is a circuit diagram of a pixel of the display panel 100. Figure 3 is shown applied to Figure 2 Timing diagram of the pixel input signal.

[0078] Reference Figures 1 to 3 The display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0079] The pixel receives data write gate signals GWP and GWN, data initialization gate signal GI, organic light emitting element initialization gate signal GB, data voltage VDATA and emission signal EM, and the organic light emitting element OLED of the pixel emits light corresponding to the level of data voltage VDATA to display an image.

[0080] In this example embodiment, the pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin film transistor. For example, the first type of switching element may be a low temperature polysilicon (LTPS) thin film transistor. For example, the second type of switching element may be an oxide thin film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0081] For example, the data write gate signals GWP and GWN may include a first data write gate signal GWP and a second data write gate signal GWN. The first data write gate signal GWP may be applied to a P-type transistor so that the first data write gate signal GWP has a low-level activation signal corresponding to the data write timing. The second data write gate signal GWN may be applied to an N-type transistor so that the second data write gate signal GWN has a high-level activation signal corresponding to the data write timing.

[0082] At least one of the pixels may include first to seventh pixel switching elements T1 to T7 , a storage capacitor CST, and an organic light emitting element OLED.

[0083] The first pixel switching element T1 includes a control electrode connected to the first node N1, an input electrode connected to the second node N2, and an output electrode connected to the third node N3.

[0084] For example, the first pixel switch element T1 may be a polysilicon thin film transistor. For example, the first pixel switch element T1 may be a P-type thin film transistor. The control electrode of the first pixel switch element T1 may be a gate electrode, the input electrode of the first pixel switch element T1 may be a source electrode, and the output electrode of the first pixel switch element T1 may be a drain electrode.

[0085] The second pixel switching element T2 includes a control electrode to which the first data write gate signal GWP is applied, an input electrode to which the data voltage VDATA is applied, and an output electrode connected to the second node N2.

[0086] For example, the second pixel switch element T2 may be a polysilicon thin film transistor. For example, the second pixel switch element T2 may be a P-type thin film transistor. The control electrode of the second pixel switch element T2 may be a gate electrode, the input electrode of the second pixel switch element T2 may be a source electrode, and the output electrode of the second pixel switch element T2 may be a drain electrode.

[0087] The third pixel switching element T3 includes a control electrode to which the second data write gate signal GWN is applied, an input electrode connected to the first node N1, and an output electrode connected to the third node N3.

[0088] For example, the third pixel switch element T3 may be an oxide thin film transistor. For example, the third pixel switch element T3 may be an N-type thin film transistor. The control electrode of the third pixel switch element T3 may be a gate electrode, the input electrode of the third pixel switch element T3 may be a source electrode, and the output electrode of the third pixel switch element T3 may be a drain electrode.

[0089] The fourth pixel switching element T4 includes a control electrode to which the data initialization gate signal GI is applied, an input electrode to which the initialization voltage VI is applied, and an output electrode connected to the first node N1.

[0090] For example, the fourth pixel switch element T4 may be an oxide thin film transistor. For example, the fourth pixel switch element T4 may be an N-type thin film transistor. The control electrode of the fourth pixel switch element T4 may be a gate electrode, the input electrode of the fourth pixel switch element T4 may be a source electrode, and the output electrode of the fourth pixel switch element T4 may be a drain electrode.

[0091] The fifth pixel switching element T5 includes a control electrode to which the emission signal EM is applied, an input electrode to which the high power voltage ELVDD is applied, and an output electrode connected to the second node N2.

[0092] For example, the fifth pixel switch element T5 may be a polysilicon thin film transistor. For example, the fifth pixel switch element T5 may be a P-type thin film transistor. The control electrode of the fifth pixel switch element T5 may be a gate electrode, the input electrode of the fifth pixel switch element T5 may be a source electrode, and the output electrode of the fifth pixel switch element T5 may be a drain electrode.

[0093] The sixth pixel switching element T6 includes a control electrode to which the emission signal EM is applied, an input electrode connected to the third node N3, and an output electrode connected to the anode of the organic light emitting element OLED.

[0094] For example, the sixth pixel switch element T6 may be a polysilicon thin film transistor. For example, the sixth pixel switch element T6 may be a P-type thin film transistor. The control electrode of the sixth pixel switch element T6 may be a gate electrode, the input electrode of the sixth pixel switch element T6 may be a source electrode, and the output electrode of the sixth pixel switch element T6 may be a drain electrode.

[0095] The seventh pixel switching element T7 includes a control electrode to which the organic light emitting element initialization gate signal GB is applied, an input electrode to which the initialization voltage V1 is applied, and an output electrode connected to the anode of the organic light emitting element OLED.

[0096] For example, the seventh pixel switch element T7 may be an oxide thin film transistor. For example, the seventh pixel switch element T7 may be an N-type thin film transistor. The control electrode of the seventh pixel switch element T7 may be a gate electrode, the input electrode of the seventh pixel switch element T7 may be a source electrode, and the output electrode of the seventh pixel switch element T7 may be a drain electrode.

[0097] The storage capacitor CST includes a first electrode to which the high power voltage ELVDD is applied and a second electrode connected to the first node N1.

[0098] The organic light emitting element OLED includes an anode and a cathode to which a low power voltage ELVSS is applied.

[0099] exist Figure 3 During the first duration DU1, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI. During the second duration DU2, in response to the first data write gate signal GWP and the second data write gate signal GWN, the threshold voltage |VTH| of the first pixel switch element T1 is compensated, and the data voltage VDATA compensated for the threshold voltage |VTH| is written to the first node N1. During the third duration DU3, the anode of the organic light emitting element OLED is initialized in response to the organic light emitting element initialization gate signal GB. During the fourth duration DU4, the organic light emitting element OLED emits light in response to the emission signal EM so that the display panel 100 displays an image.

[0100] Although in the present example embodiment, the transmission cut-off duration of the transmission signal EM corresponds to the first duration DU1, the second duration DU2, and the third duration DU3, the inventive concept is not limited thereto. The transmission cut-off duration of the transmission signal EM may be set to include the second duration DU2. The transmission cut-off duration of the transmission signal EM may be longer than the sum of the first duration DU1, the second duration DU2, and the third duration DU3.

[0101] During the first duration DU1, the data initialization gate signal GI may have an activation level. For example, the activation level of the data initialization gate signal GI may be a high level. When the data initialization gate signal GI has the activation level, the fourth pixel switching element T4 is turned on so that the initialization voltage VI may be applied to the first node N1. The data initialization gate signal GI[N] of the current stage may be generated based on the scan signal SCAN[N-1] of the previous stage.

[0102] During the second duration DU2, the first data write gate signal GWP and the second data write gate signal GWN may have an activation level. For example, the activation level of the first data write gate signal GWP may be a low level, and the activation level of the second data write gate signal GWN may be a high level. When the first data write gate signal GWP and the second data write gate signal GWN have an activation level, the second pixel switch element T2 and the third pixel switch element T3 are turned on. In addition, the first pixel switch element T1 is turned on in response to the initialization voltage VI. The first data write gate signal GWP[N] of the current stage may be generated based on the scan signal SCAN[N] of the current stage. The second data write gate signal GWN[N] of the current stage may be generated based on the scan signal SCAN[N] of the current stage.

[0103] Along a path formed by the first, second, and third pixel switching elements T1 , T2 , and T3 , a voltage obtained by subtracting an absolute value |VTH| of a threshold voltage of the first pixel switching element T1 from the data voltage VDATA may be charged at the first node N1 .

[0104] During the third duration DU3, the organic light emitting element initialization gate signal GB may have an activation level. For example, the activation level of the organic light emitting element initialization gate signal GB may be a high level. When the organic light emitting element initialization gate signal GB has the activation level, the seventh pixel switch element T7 is turned on so that the initialization voltage V1 may be applied to the anode of the organic light emitting element OLED. The organic light emitting element initialization gate signal GB[N] of the current stage may be generated based on the scan signal SCAN[N+1] of the next stage.

[0105] During the fourth duration DU4, the emission signal EM may have an activation level. The activation level of the emission signal EM may be a low level. When the emission signal EM has the activation level, the fifth pixel switch element T5 and the sixth pixel switch element T6 are turned on. In addition, the first pixel switch element T1 is turned on by the data voltage VDATA.

[0106] The driving current flows through the fifth pixel switching element T5, the first pixel switching element T1, and the sixth pixel switching element T6 to drive the organic light emitting element OLED. The intensity of the driving current can be determined by the level of the data voltage VDATA. The brightness of the organic light emitting element OLED is determined by the intensity of the driving current. The driving current ISD flowing through the path from the input electrode to the output electrode of the first pixel switching element T1 is determined by the following equation 1.

[0107] [Equation 1]

[0108]

[0109] In Equation 1, μ is the mobility of the first pixel switch element T1. Cox is the capacitance per unit area of ​​the first pixel switch element T1. W / L is the ratio of the width and length of the first pixel switch element T1. VSG is the voltage between the input electrode of the first pixel switch element T1 and the control electrode of the first pixel switch element T1. |VTH| is the threshold voltage of the first pixel switch element T1.

[0110] The voltage VG of the first node N1 after compensating the threshold voltage |VTH| during the second duration DU2 may be expressed as Equation 2 below.

[0111] [Equation 2]

[0112] VG=VDATA-|VTH|

[0113] When the organic light emitting element OLED emits light during the fourth duration DU4, the driving voltage VOV and the driving current ISD may be expressed as the following Equation 3 and Equation 4. In Equation 3, VS is the voltage of the second node N2.

[0114] [Equation 3]

[0115] VOV=VS-VG-|VTH|=ELVDD-(VDATA-|VTH|)-|VTH|=ELVDD-VDATA

[0116] [Equation 4]

[0117]

[0118] The threshold voltage |VTH| is compensated during the second duration DU2 , so that when the organic light emitting element OLED emits light during the fourth duration DU4 , the driving current ISD may be determined regardless of the threshold voltage |VTH| of the first pixel switching element T1 .

[0119] In this example embodiment, when the image displayed on the display panel 100 is a static image or the display panel is operated in a normally open mode, the driving frequency of the display panel 100 can be reduced to reduce power consumption. When all the switching elements of the pixels of the display panel 100 are polysilicon thin film transistors, flickering may occur due to leakage current of the pixel switching elements in the low-frequency driving mode. Therefore, some of the pixel switching elements may be oxide thin film transistors. In this example embodiment, the third pixel switching element T3, the fourth pixel switching element T4, and the seventh pixel switching element T7 may be oxide thin film transistors. The first pixel switching element T1, the second pixel switching element T2, the fifth pixel switching element T5, and the sixth pixel switching element T6 may be polysilicon thin film transistors.

[0120] Figure 4 It is shown Figure 1 Flow chart of a driving mode of a display device. Figure 5a is shown in low frequency drive mode applied to Figure 2 A timing diagram of the input signals to the pixels of the display panel. Figure 5b is shown in the low frequency hybrid drive mode applied to Figure 2 A timing diagram of the input signals to the pixels of the display panel.

[0121] Reference Figures 1 to 5b , the display panel 100 is driven in a first mode, a second mode, and a third mode. In the first mode, the display panel driver may drive at least one of the first type of switching elements (e.g., T2, T5, and T6) and at least one of the second type of switching elements (e.g., T3 and T4) at a high driving frequency. In the second mode, the display panel driver may drive at least one of the first type of switching elements (e.g., T2, T5, and T6) at a high driving frequency, and drive at least one of the second type of switching elements (e.g., T3 and T4) at a low driving frequency lower than the high driving frequency. In the third mode, the display panel driver may drive at least one of the first type of switching elements (e.g., T2, T5, and T6) and at least one of the second type of switching elements (e.g., T3 and T4) at a low driving frequency.

[0122] However, in the second mode, not all of the second type switching elements may be driven at a low driving frequency. The second type switching element (e.g., T7) may be an element for initializing the organic light emitting element, so that the seventh pixel switching element T7 may be driven at a high driving frequency like the fifth pixel switching element T5 and the sixth pixel switching element T6 in the second mode.

[0123] The first mode may be a high frequency driving mode. The second mode may be a low frequency hybrid driving mode. The third mode may be a low frequency driving mode.

[0124] The display panel driver (eg, the driving controller 200 ) analyzes the input image (step S100 ). The display panel driver determines whether the input image represents a moving image or a still image (step S200 ).

[0125] When the input image represents a moving image, the display panel 100 is driven in the high-frequency driving mode (step S300). When the input image represents a static image and the display device is in the hybrid driving mode (step S400), the display panel 100 is driven in the low-frequency hybrid driving mode (step S600). When the input image represents a static image and the display device is not in the hybrid driving mode (step S400), the display panel 100 is driven in the low-frequency driving mode (step S500).

[0126] Figure 5a In the low frequency driving mode, the emission signal EM, the first data writing gate signal GWP, the data initialization gate signal GI, the second data writing gate signal GWN and the organic light emitting element initialization gate signal GB can be driven at a low driving frequency.

[0127] exist Figure 5a The high driving frequency may be 60 Hz, and the low driving frequency may be 1 Hz. Herein, in the low frequency driving mode, the write operation WRITE is performed in one frame within one second, and the hold operation HOLD is performed in fifty-nine frames.

[0128] Figure 5b In the low frequency hybrid driving mode, the emission signal EM, the first data write gate signal GWP and the organic light emitting element initialization gate signal GB can be driven at a high driving frequency, and the data initialization gate signal GI and the second data write gate signal GWN can be driven at a low driving frequency.

[0129] exist Figure 5b In the low-frequency driving mode, the high driving frequency may be 60 Hz, and the low driving frequency may be 1 Hz. Herein, in the low-frequency driving mode, a write operation WRITE is performed in one frame within one second, and a hold operation HOLD is performed in fifty-nine frames. In the hold operation HOLD, the organic light emitting element may be repeatedly turned on and off.

[0130] The low-frequency driving mode may be superior to the low-frequency hybrid driving mode in terms of power consumption reduction, but depending on the input image, the user may visually perceive flickering in the low-frequency driving mode. Therefore, the display panel 100 may be selectively driven in the low-frequency driving mode and the low-frequency hybrid driving mode by activating and deactivating the hybrid driving mode (step S400).

[0131] Figure 6 It is shown Figure 4 Flowchart of the detailed operation of the low frequency drive mode.

[0132] Reference Figures 1 to 6 In the low frequency driving mode, the input image may be analyzed so that a flicker value may be determined (step S510). The flicker value may represent the lowest frequency that does not generate flicker in the displayed image.

[0133] When the flicker value is greater than 15 Hz and less than or equal to 30 Hz (step S520 ), the display panel 100 may be driven at 30 Hz in the low frequency driving mode (step S530 ).

[0134] Although not shown in the drawing, when the flicker value is greater than 30 Hz, the display panel 100 may be driven in a high frequency driving mode (step S300 ).

[0135] When the flicker value is greater than 10 Hz and less than or equal to 15 Hz (step S540 ), the display panel 100 may be driven at 15 Hz in the low frequency driving mode (step S550 ).

[0136] When the flicker value is greater than 1 Hz and less than or equal to 10 Hz (step S560 ), the display panel 100 may be driven at 10 Hz in the low frequency driving mode (step S570 ).

[0137] When the flicker value is equal to or less than 1 Hz (step S560 ), the display panel 100 may be driven at 1 Hz in the low frequency driving mode (step S580 ).

[0138] Figure 7 It is shown Figure 4 A flowchart of an example of the detailed operation of the low frequency hybrid drive mode.

[0139] Reference Figures 1 to 7 , the operation steps of the low-frequency driving mode (step S500) can be applied to the operation of the low-frequency hybrid driving mode (step S600).

[0140] In the low frequency hybrid driving mode, an input image may be analyzed so that a flicker value may be determined (step S610 ).

[0141] When the flicker value is greater than 15 Hz and less than or equal to 30 Hz (step S620 ), the display panel 100 may be driven at 30 Hz in the low frequency hybrid driving mode (step S630 ).

[0142] Although not shown in the drawing, when the flicker value is greater than 30 Hz, the display panel 100 may be driven in a high frequency driving mode (step S300 ).

[0143] When the flicker value is greater than 10 Hz and less than or equal to 15 Hz (step S640 ), the display panel 100 may be driven at 15 Hz in the low frequency hybrid driving mode (step S650 ).

[0144] When the flicker value is greater than 1 Hz and less than or equal to 10 Hz (step S660 ), the display panel 100 may be driven at 10 Hz in the low frequency hybrid driving mode (step S670 ).

[0145] When the flicker value is equal to or less than 1 Hz (step S660 ), the display panel 100 may be driven at 1 Hz in the low frequency hybrid driving mode (step S680 ).

[0146] According to the present exemplary embodiment, the display panel 100 is driven in the high frequency driving mode, the low frequency hybrid driving mode, and the low frequency driving mode, so that power consumption of the display device can be reduced and flickering of the display panel can be effectively prevented.

[0147] Figure 8 is a flowchart illustrating an example of a detailed operation of a low frequency hybrid driving mode according to an example embodiment of the inventive concept.

[0148] In addition to the operation of the low frequency hybrid driving mode, the display device according to the present exemplary embodiment is different from the reference Figures 1 to 7 The display device of the previously explained exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 7 The same or similar parts as those described in the previous example embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0149] Reference Figures 1 to 6 and Figure 8 , in the low frequency hybrid driving mode, the input image may be analyzed so that the flicker value may be determined (step S610).

[0150] When the difference OPR|MAX-MIN| between the maximum brightness of the input image and the minimum brightness of the input image is equal to or less than the first reference value X (step S615), the display panel driver may drive the display panel 100 in the low frequency hybrid driving mode (steps S620 to S680).

[0151] In contrast, when the difference OPR|MAX-MIN| between the maximum brightness of the input image and the minimum brightness of the input image is greater than the first reference value X (step S615 ), the display panel driver may drive the display panel 100 in the low frequency driving mode (step S500 ).

[0152] When the difference OPR|MAX-MIN| between the maximum brightness of the input image and the minimum brightness of the input image is large enough, the possibility of flicker generation may be relatively low, so that the display panel 100 may be driven in a low-frequency driving mode to reduce power consumption.

[0153] In contrast, when the difference OPR|MAX-MIN| between the maximum brightness of the input image and the minimum brightness of the input image is not large enough, the possibility of generating flicker may be relatively high, so that the display panel 100 may be driven in the low frequency hybrid driving mode to prevent flicker.

[0154] When the size of the image having the same grayscale value is greater than the second reference value Y (step S615 ), the display panel driver may drive the display panel 100 in the low frequency hybrid driving mode (steps S620 to S680 ).

[0155] In contrast, when the size of the image having the same grayscale value is equal to or less than the second reference value Y (step S615 ), the display panel driver may drive the display panel 100 in the low frequency driving mode (step S500 ).

[0156] When the size of an image having the same grayscale value is small, the possibility of flickering may be relatively low, so that the display panel 100 may be driven in a low-frequency driving mode to reduce power consumption.

[0157] In contrast, when the size of an image having the same grayscale value is large, the possibility of generating a flicker may be relatively high, so that the display panel 100 may be driven in a low frequency hybrid driving mode to prevent the flicker.

[0158] According to the present exemplary embodiment, the display panel 100 is driven in the high frequency driving mode, the low frequency hybrid driving mode, and the low frequency driving mode, so that power consumption of the display device can be reduced and flickering of the display panel can be effectively prevented.

[0159] Fig. 9 is a timing diagram illustrating input signals applied to pixels of a display panel according to an example embodiment of the inventive concept.

[0160] In addition to the operation of the low frequency hybrid driving mode, the display device according to the present exemplary embodiment is different from the reference Figures 1 to 7 The display device of the previously explained exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 7 The same or similar parts as those described in the previous example embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0161] Reference Figures 1 to 5a , Figure 6 , Figure 7 and Fig. 9In the low-frequency hybrid driving mode, the emission signal EM, the first data writing gate signal GWP, the data initialization gate signal GI, the second data writing gate signal GWN and the organic light emitting element initialization gate signal GB can be driven at a low driving frequency.

[0162] On the contrary, the low power voltage ELVSS applied to the cathode of the organic light emitting element OLED of the display panel 100 may have a high driving frequency. For example, the low power voltage ELVSS may normally maintain a low level, and the low power voltage ELVSS may have a high level pulse at a high driving frequency. When the low power voltage ELVSS has a high level pulse, the organic light emitting element OLED may be turned off instantaneously so that the organic light emitting element OLED may be turned off as shown in FIG. Figure 5b Therefore, flickering of the display panel 100 can be prevented.

[0163] Fig.10 is a circuit diagram illustrating a pixel of a display panel according to an example embodiment of the inventive concept.

[0164] In addition to the pixel structure of the display panel, the display device according to the present exemplary embodiment is different from the reference Figures 1 to 7 The display device of the previously explained exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 7 The same or similar parts as those described in the previous example embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0165] Reference Figure 1 , Figures 3 to 7 and Fig.10 , at least one of the pixels may include first to seventh pixel switching elements T1 to T7 , a storage capacitor CST, and an organic light emitting element OLED.

[0166] The pixel structure of this exemplary embodiment is similar to that of the embodiment shown in FIG. 1 except that the control electrode of the seventh pixel switching element T7 is connected to the control electrode of the sixth pixel switching element T6. Figure 2 The pixel structure of the previous example embodiments is substantially the same.

[0167] The emission signal EM is applied to the control electrode of the seventh pixel switch element T7, and the seventh pixel switch element T7 is an N-type transistor. Figure 3 During the period DU1 to DU3 in FIG. 1 , the seventh pixel switching element T7 is turned on and the organic light emitting element OLED is initialized.

[0168] Fig.11 is a circuit diagram illustrating a pixel of a display panel according to an example embodiment of the inventive concept. Fig.12is shown applied to Fig.11 Timing diagram of the pixel input signal.

[0169] In addition to the pixel structure of the display panel, the display device according to the present exemplary embodiment is different from the reference Figures 1 to 7 The display device of the previously explained exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 7 The same or similar parts as those described in the previous example embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0170] Reference Figure 1 , Figures 3 to 7 , Fig.11 and Fig.12 , at least one of the pixels may include first to seventh pixel switching elements T1 to T7 , a storage capacitor CST, and an organic light emitting element OLED.

[0171] In the present example embodiment, the seventh pixel switching element T7 includes a control electrode to which the organic light emitting element initialization gate signal GB is applied, an input electrode to which the initialization voltage V1 is applied, and an output electrode connected to the anode of the organic light emitting element OLED.

[0172] For example, the seventh pixel switch element T7 may be a polysilicon thin film transistor. For example, the seventh pixel switch element T7 may be a P-type thin film transistor.

[0173] exist Fig.12 During the first duration DU1, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI. During the second duration DU2, in response to the first data write gate signal GWP and the second data write gate signal GWN, the threshold voltage |VTH| of the first pixel switch element T1 is compensated, and the data voltage VDATA compensated for the threshold voltage |VTH| is written to the first node N1. During the third duration DU3, the anode of the organic light emitting element OLED is initialized in response to the organic light emitting element initialization gate signal GB. During the fourth duration DU4, the organic light emitting element OLED emits light in response to the emission signal EM, so that the display panel 100 displays an image.

[0174] In the present example embodiment, the activation level of the organic light emitting element initialization gate signal GB may be a low level.

[0175] In this example embodiment, some of the pixel switching elements may be oxide thin film transistors. In this example embodiment, the third pixel switching element T3 and the fourth pixel switching element T4 may be oxide thin film transistors. The first pixel switching element T1, the second pixel switching element T2, the fifth pixel switching element T5, the sixth pixel switching element T6, and the seventh pixel switching element T7 may be polysilicon thin film transistors.

[0176] Fig.13 is a flowchart illustrating an operation of a low frequency driving mode according to an example embodiment of the inventive concept. Fig.14 is a conceptual diagram showing a segment driving frequency of an input image of a display panel. Fig.15 is a graph showing the segment driving frequency of an input image of a display panel.

[0177] In addition to the operation in the low-frequency driving mode, the display device according to the present exemplary embodiment is different from the reference Figures 1 to 7 The display device of the previously explained exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 7 The same or similar parts as those described in the previous example embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0178] Alternatively, the operation of the low-frequency driving mode of the display device of the present example embodiment may be additionally applied to the example embodiments explained above.

[0179] Reference Figures 1 to 5b and Figures 13 to 15 , the display panel driver may divide the input image into a plurality of segments SG1 to SG9. The display panel driver may determine segment flicker values ​​of the plurality of segments (step S700). The display panel driver may determine segment driving frequencies of the plurality of segments based on the segment flicker values.

[0180] The display panel driver may determine the worst segment having the highest segment driving frequency among the plurality of segments. In addition, the display panel driver may determine the majority segment having the segment driving frequency that occurs most frequently among the plurality of segments.

[0181] exist Fig.14 , the worst segment may be the fifth segment SG5 having a segment driving frequency of 30 Hz. The number of segments having a segment driving frequency of 1 Hz is 4, and the number of segments having a segment driving frequency of 2 Hz is 4, so that the majority of segments may be one of the segments having a segment driving frequency of 1 Hz or one of the segments having a segment driving frequency of 2 Hz.

[0182] The display panel driver may calculate the absolute value of the difference between the number of the worst segment and the number of the majority segment. Fig.15, the number of worst segments may be 1, and the number of majority segments may be 4, so that the absolute value of the difference between the number of worst segments and the number of majority segments may be 3.

[0183] When the absolute value of the difference between the number of the worst segment and the number of the majority segment is greater than the third reference value Z (step S710), the display panel driver may drive the display panel 100 at a compensation driving frequency (e.g., 10 Hz) smaller than the segment driving frequency (e.g., 30 Hz) of the worst segment (step S730).

[0184] When the absolute value of the difference between the number of the worst segment and the number of the majority segment is large, the ratio of the worst segment among all the segments may be small. In this case, when the entire display panel 100 is driven at the segment driving frequency of the worst segment, power consumption may be high.

[0185] Therefore, as explained above, when the ratio of the worst segment among all segments is small, the display panel 100 can be driven at a compensation driving frequency smaller than the segment driving frequency of the worst segment, thereby reducing power consumption while risking deteriorating the display quality of the worst segment.

[0186] On the contrary, when the absolute value of the difference between the number of the worst segment and the number of the majority segment is equal to or less than the third reference value Z (step S710), the display panel driver may drive the display panel 100 at the segment driving frequency of the worst segment (e.g., 30 Hz) (step S720).

[0187] When the absolute value of the difference between the number of the worst segment and the number of the majority segment is small, the ratio of the worst segment among all the segments may be large. In this case, the display panel 100 may be driven at the segment driving frequency of the worst segment to prevent degradation of display quality.

[0188] Fig.16 is a flowchart illustrating an operation of a low frequency driving mode according to an example embodiment of the inventive concept.

[0189] In addition to the operation in the low-frequency driving mode, the display device according to the present exemplary embodiment is different from the reference Figures 13 to 15 The display device of the previously explained exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 13 to 15 The same or similar parts as those described in the previous example embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0190] Reference Figures 1 to 5b and Figures 14 to 16 , the display panel driver may divide the input image into a plurality of segments SG1 to SG9. The display panel driver may determine segment flicker values ​​of the plurality of segments (step S700). The display panel driver may determine segment driving frequencies of the plurality of segments based on the segment flicker values.

[0191] When the absolute value of the difference between the number of the worst segment and the number of the majority segment is greater than the third reference value Z (step S710), the display panel driver may drive the display panel 100 at a compensation driving frequency (e.g., 10 Hz) smaller than the segment driving frequency (e.g., 30 Hz) of the worst segment (step S730).

[0192] In addition, when the absolute value of the difference between the number of the worst segment and the number of the majority segment is greater than the third reference value Z (step S710 ), the display panel driver may compensate the data of the worst segment (step S725 ).

[0193] When the display panel 100 is driven at a compensation driving frequency (e.g., 10 Hz) that is smaller than the segment driving frequency (e.g., 30 Hz) of the worst segment, flickering may be generated at the worst segment. Therefore, data of the worst segment may be compensated to prevent flickering. For example, when the grayscale of the data of the worst segment may be increased, the user may not easily recognize the flickering. In this case, interpolation may be applied to the worst segment and the segments adjacent to the worst segment, so that data compensation of the worst segment may not be easily recognized by the user.

[0194] When the absolute value of the difference between the number of the worst segment and the number of the majority segment is equal to or less than the third reference value Z (step S710), the display panel driver may drive the display panel 100 at the segment driving frequency (eg, 30 Hz) of the worst segment (step S720).

[0195] Fig.17 is a graph illustrating a threshold voltage according to time of a switching element of a display panel according to an example embodiment of the inventive concept. Fig.18 is a flow chart illustrating the operation of the display panel in the low frequency driving mode. Fig.19 is a timing diagram showing a gate signal applied to a display panel and a compensated gate signal. Fig.20a is a table showing the frequency of compensation frames and the number of compensation frames. Fig.20b is a table showing the frequency of compensation frames and the number of compensation frames. Fig.20c is a table showing the frequency of compensation frames and the number of compensation frames.

[0196] In addition to compensating the threshold voltage of the switching element in the low-frequency driving mode, the display device according to the present exemplary embodiment is different from the reference Figures 1 to 7 The display device of the previously explained exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 1 to 7 The same or similar parts as those described in the previous example embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0197] Alternatively, the operation of the low-frequency driving mode of the display device of the present example embodiment may be additionally applied to the example embodiments explained above.

[0198] Reference Figures 1 to 5b and Figure 17 to Figure 20c , as the duration of the low-frequency driving increases, the threshold voltage of the switching element of the pixel of the display panel 100 may shift in the negative direction.

[0199] For example, a shift in threshold voltage may occur at the third pixel switching element T3, the fourth pixel switching element T4, and the seventh pixel switching element T7, which are oxide thin film transistors. When the threshold voltage shifts, display defects such as horizontal line defects may occur on the display panel 100.

[0200] When the display panel 100 operates in the low frequency driving mode (step S500 ), the display panel driver may count the duration CNT of the low frequency driving mode.

[0201] When the duration CNT of the low-frequency driving mode is greater than the reference time THC (step S810), the driving signal applied to at least one of the first type of switching element (e.g., polysilicon thin film transistor) and the second type of switching element (e.g., oxide thin film transistor) can be adjusted (or changed) to prevent the threshold voltage from shifting.

[0202] In the present example embodiment, when the duration CNT of the low frequency driving mode is greater than the reference time THC (step S810), the display panel driver may insert a compensation frame CF having a compensating driving frequency greater than the low driving frequency (step S820).

[0203] For example, after the compensation frame CF is inserted, the duration CNT of the low-frequency driving mode may be initialized.

[0204] exist Fig.19 In the embodiment, the driving signal GS may be an uncompensated gate signal, and the compensated driving signal GSC may be a gate signal including an inserted compensation frame CF for compensating the threshold voltage. The compensated driving signal GSC may be Figure 5a At least one of the signals EM, GWP, GI, GWN and GB having a low driving frequency.

[0205] exist Fig.20a For example, the reference time THC and the compensation frame frequency (eg, 60 Hz) may be fixed.

[0206] like Fig.20aAs shown in, when the low driving frequency is 1 Hz and the duration of the low-frequency driving mode is greater than ten seconds, twenty or more compensation frames CF with a compensation frame frequency of 60 Hz may be inserted to prevent the shift of the threshold voltage of the switching element. When the low driving frequency is 2 Hz and the duration of the low-frequency driving mode is greater than ten seconds, ten or more compensation frames CF with a compensation frame frequency of 60 Hz may be inserted to prevent the shift of the threshold voltage of the switching element. When the low driving frequency is 15 Hz and the duration of the low-frequency driving mode is greater than ten seconds, two or more compensation frames CF with a compensation frame frequency of 60 Hz may be inserted to prevent the shift of the threshold voltage of the switching element. When the low driving frequency is 30 Hz and the duration of the low-frequency driving mode is greater than ten seconds, one or more compensation frames CF with a compensation frame frequency of 60 Hz may be inserted to prevent the shift of the threshold voltage of the switching element.

[0207] exist Fig.20b For example, the reference time THC may be changed and the compensation frame frequency (eg, 60 Hz) may be fixed.

[0208] like Fig.20b As shown in, when the low driving frequency is 1 Hz and the duration of the low frequency driving mode is greater than ten seconds, twenty or more compensation frames CF with a compensation frame frequency of 60 Hz may be inserted to prevent the shift of the threshold voltage of the switching element. When the low driving frequency is 2 Hz and the duration of the low frequency driving mode is greater than twenty seconds, ten or more compensation frames CF with a compensation frame frequency of 60 Hz may be inserted to prevent the shift of the threshold voltage of the switching element. When the low driving frequency is 15 Hz and the duration of the low frequency driving mode is greater than sixty seconds, two or more compensation frames CF with a compensation frame frequency of 60 Hz may be inserted to prevent the shift of the threshold voltage of the switching element. When the low driving frequency is 30 Hz and the duration of the low frequency driving mode is greater than one hundred and twenty seconds, one or more compensation frames CF with a compensation frame frequency of 60 Hz may be inserted to prevent the shift of the threshold voltage of the switching element.

[0209] exist Fig.20c For example, the reference time THC may be fixed and the compensation frame frequency may be varied.

[0210] like Fig.20cAs shown in, when the low driving frequency is 1 Hz and the duration of the low frequency driving mode is greater than ten seconds, twenty or more compensation frames CF having a compensation frame frequency greater than 1 Hz may be inserted to prevent the shift of the threshold voltage of the switching element. When the low driving frequency is 2 Hz and the duration of the low frequency driving mode is greater than ten seconds, ten or more compensation frames CF having a compensation frame frequency greater than 2 Hz may be inserted to prevent the shift of the threshold voltage of the switching element. When the low driving frequency is 15 Hz and the duration of the low frequency driving mode is greater than ten seconds, two or more compensation frames CF having a compensation frame frequency greater than 15 Hz may be inserted to prevent the shift of the threshold voltage of the switching element. When the low driving frequency is 30 Hz and the duration of the low frequency driving mode is greater than ten seconds, one or more compensation frames CF having a compensation frame frequency greater than 30 Hz may be inserted to prevent the shift of the threshold voltage of the switching element.

[0211] Fig.21 is a flow chart illustrating the operation of the display panel in the low frequency hybrid driving mode.

[0212] Reference Figures 17 to 21 , Fig.18 The operation of the low frequency driving mode can be similarly applied to the low frequency hybrid driving mode.

[0213] When the display panel 100 operates in the low frequency hybrid driving mode (step S600 ), the display panel driver may count the duration CNT of the low frequency hybrid driving mode.

[0214] When the duration CNT of the low-frequency hybrid driving mode is greater than the reference time THC (step S910), the driving signal applied to at least one of the first type of switching element (e.g., polysilicon thin film transistor) and the second type of switching element (e.g., oxide thin film transistor) can be adjusted to prevent the threshold voltage from shifting.

[0215] In the present example embodiment, when the duration CNT of the low frequency hybrid driving mode is greater than the reference time THC (step S910 ), the display panel driver may insert a compensation frame CF having a compensation driving frequency greater than the low driving frequency (step S920 ).

[0216] In the low-frequency hybrid driving mode, the compensated driving signal GSC can be Figure 5b At least one of the signals GI and GWN having a low driving frequency.

[0217] Fig. 22 is a timing diagram illustrating a gate signal applied to a display panel and a compensated gate-off voltage according to an example embodiment of the inventive concept.

[0218] In addition to the method of compensating the threshold voltage of the switching element of the display device, the display device according to the present exemplary embodiment is different from the reference Figures 17 to 21 The display device of the previously explained exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 17 to 21 The same or similar parts as those described in the previous example embodiments are described above, and any repeated explanation regarding the above elements will be omitted.

[0219] Reference Fig.17 , Fig.18 , Fig.21 and Fig. 22 When the display panel 100 operates in the low frequency driving mode (step S500), the display panel driver may count the duration CNT of the low frequency driving mode.

[0220] When the duration CNT of the low-frequency driving mode is greater than the reference time THC (step S810), the driving signal applied to at least one of the first type of switching element (e.g., polysilicon thin film transistor) and the second type of switching element (e.g., oxide thin film transistor) can be adjusted to prevent the threshold voltage from shifting.

[0221] The data write gate signals GWP and GWN and the data initialization gate signal GI applied to the display panel 100 are generated based on the gate-on voltage VGH and the gate-off voltage VGL.

[0222] In the present example embodiment, when the duration CNT of the low frequency driving mode is greater than the reference time THC, the display panel driver may reduce the level of the gate-off voltage VGL.

[0223] When the level of the gate-off voltage VGL decreases, the Figure 2 The amplitude of the data initialization gate signal GI of the fourth pixel switching element T4 increases, and the gate-source voltage of the fourth pixel switching element T4 increases, so that the shift of the threshold voltage of the fourth pixel switching element T4 can be compensated.

[0224] In addition, when the level of the gate-off voltage VGL decreases, the Figure 2 The amplitude of the second data write gate signal GWN of the third pixel switching element T3 increases, and the gate-source voltage of the third pixel switching element T3 increases, so that the shift of the threshold voltage of the third pixel switching element T3 can be compensated.

[0225] Fig.23 is a timing diagram illustrating a gate signal applied to a display panel and a compensated gate-on voltage according to an example embodiment of the inventive concept.

[0226] In addition to the method of compensating the threshold voltage of the switching element of the display device, the display device according to the present exemplary embodiment is different from the reference Figures 17 to 21 The display device of the previously explained exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 17 to 21 The same or similar parts as those described in the previous example embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0227] Reference Fig.17 , Fig.18 , Fig.21 and Fig.23 When the display panel 100 operates in the low frequency driving mode (step S500), the display panel driver may count the duration CNT of the low frequency driving mode.

[0228] When the duration CNT of the low-frequency driving mode is greater than the reference time THC (step S810), the driving signal applied to at least one of the first type of switching element (e.g., polysilicon thin film transistor) and the second type of switching element (e.g., oxide thin film transistor) can be adjusted to prevent the threshold voltage from shifting.

[0229] The data write gate signals GWP and GWN and the data initialization gate signal GI applied to the display panel 100 are generated based on the gate-on voltage VGH and the gate-off voltage VGL.

[0230] In the present example embodiment, when the duration CNT of the low frequency driving mode is greater than the reference time THC, the display panel driver may increase the level of the gate-on voltage VGH.

[0231] When the gate-on voltage VGH level increases, the Figure 2 The amplitude of the data initialization gate signal GI of the fourth pixel switching element T4 increases, and the gate-source voltage of the fourth pixel switching element T4 increases, so that the shift of the threshold voltage of the fourth pixel switching element T4 can be compensated.

[0232] In addition, when the level of the gate-on voltage VGH increases, the Figure 2 The amplitude of the second data write gate signal GWN of the third pixel switching element T3 increases, and the gate-source voltage of the third pixel switching element T3 increases, so that the shift of the threshold voltage of the third pixel switching element T3 can be compensated.

[0233] Fig.24 is a timing diagram illustrating a gate signal applied to a display panel and a compensated initialization voltage according to an example embodiment of the inventive concept.

[0234] In addition to the method of compensating the threshold voltage of the switching element of the display device, the display device according to the present exemplary embodiment is different from the reference Figures 17 to 21 The display device of the previously explained exemplary embodiment is substantially the same. Therefore, the same reference numerals will be used to indicate the same Figures 17 to 21 The same or similar parts as those described in the previous example embodiments are described herein, and any repeated explanation regarding the above elements will be omitted.

[0235] Reference Fig.17 , Fig.18 , Fig.21 and Fig.24 When the display panel 100 operates in the low frequency driving mode (step S500), the display panel driver may count the duration CNT of the low frequency driving mode.

[0236] When the duration CNT of the low-frequency driving mode is greater than the reference time THC (step S810), the driving signal applied to at least one of the first type of switching element (e.g., polysilicon thin film transistor) and the second type of switching element (e.g., oxide thin film transistor) can be adjusted to prevent the threshold voltage from shifting.

[0237] The data write gate signals GWP and GWN and the data initialization gate signal GI applied to the display panel 100 are generated based on the gate-on voltage VGH and the gate-off voltage VGL.

[0238] In the present example embodiment, when the duration CNT of the low frequency driving mode is greater than the reference time THC, the display panel driver may reduce the level of the initialization voltage V1 applied to the display panel 100 .

[0239] When the level of the initialization voltage V1 decreases, the gate-source voltage of the fourth pixel switching element T4 increases, so that the shift of the threshold voltage of the fourth pixel switching element T4 can be compensated.

[0240] According to the above explained example embodiments, the display panel 100 is driven in the high frequency driving mode, the low frequency hybrid driving mode, and the low frequency driving mode, so that flickering of the display panel 100 can be prevented.

[0241] In addition, an input image of the display panel 100 is divided into a plurality of segments, and a driving frequency of a worst segment having a highest segment driving frequency is reduced, so that power consumption of the display device can be reduced.

[0242] In addition, when the display panel 100 is driven for a long time in the low frequency driving mode, a shift in the threshold voltage of the switching element can be prevented. Therefore, a display defect of the display panel 100 due to the shift in the threshold voltage can be prevented.

[0243] Therefore, the display quality is prevented from being deteriorated in the low-frequency driving mode, so that the power consumption of the display device can be reduced and the display quality of the display panel 100 can be improved.

[0244] Industrial Availability

[0245] According to the inventive concept explained above, power consumption of a display device can be reduced and display quality of a display panel can be improved.

[0246] Although a few example embodiments of the inventive concept have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the inventive concept.

[0247] <Description of Reference Numerals>

[0248] 100: display panel 200: drive controller

[0249] 300: Gate driver 400: Gamma reference voltage generator

[0250] 500: data driver 600: transmission driver

Claims

1. A display device, comprising: a display panel comprising pixels, the pixels comprising switching elements of a first type and switching elements of a second type different from the first type; as well as a display panel driver, the display panel driver driving the display panel, wherein the display panel driver is configured to drive the first type of switching elements at a high driving frequency in a first mode and to drive the second type of switching elements at the high driving frequency, wherein the display panel driver is configured to drive the first type of switching elements at the high driving frequency in the second mode, and to drive the second type of switching elements at a low driving frequency lower than the high driving frequency during driving the first type of switching elements at the high driving frequency, and The display panel driver is configured to drive the first type of switching elements at the low driving frequency and drive the second type of switching elements at the low driving frequency in a third mode.

2. The display device according to claim 1, wherein: The first type of switching element is a polysilicon thin film transistor, and Wherein, the second type of switch element is an oxide thin film transistor.

3. The display device according to claim 2, wherein: The first type of switch element is a P-type transistor, and Wherein, the second type of switch element is an N-type transistor.

4. The display device according to claim 2, wherein: The pixels include: a first pixel switching element, the first pixel switching element comprising a control electrode connected to the first node, an input electrode connected to the second node, and an output electrode connected to the third node; a second pixel switching element, the second pixel switching element comprising a control electrode to which a first data writing gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third pixel switching element, the third pixel switching element comprising a control electrode to which a second data writing gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the third node; a fourth pixel switching element, the fourth pixel switching element comprising a control electrode to which a data initialization gate signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to the first node; a fifth pixel switching element, the fifth pixel switching element comprising a control electrode to which an emission signal is applied, an input electrode to which a high power supply voltage is applied, and an output electrode connected to the second node; a sixth pixel switching element, the sixth pixel switching element comprising a control electrode to which the emission signal is applied, an input electrode connected to the third node, and an output electrode connected to an anode of an organic light emitting element; a seventh pixel switching element, the seventh pixel switching element comprising a control electrode, an input electrode to which the initialization voltage is applied, and an output electrode connected to the anode of the organic light emitting element; a storage capacitor including a first electrode to which the high power supply voltage is applied and a second electrode connected to the first node; and The organic light emitting element includes the anode and a cathode to which a low power supply voltage is applied.

5. The display device according to claim 4, wherein: The first pixel switching element, the second pixel switching element, the fifth pixel switching element and the sixth pixel switching element are polysilicon thin film transistors, and Wherein, the third pixel switch element, the fourth pixel switch element and the seventh pixel switch element are oxide thin film transistors.

6. The display device according to claim 4, wherein: The control electrode of the seventh pixel switch element is connected to the control electrode of the sixth pixel switch element or receives an organic light emitting element initialization gate signal.

7. The display device according to claim 4, wherein: The first pixel switching element, the second pixel switching element, the fifth pixel switching element, the sixth pixel switching element and the seventh pixel switching element are polysilicon thin film transistors, and Wherein, the third pixel switching element and the fourth pixel switching element are the oxide thin film transistors.

8. The display device according to claim 1, wherein: The first mode is a high frequency driving mode, Wherein, the second mode is a low-frequency hybrid driving mode, Wherein, the third mode is a low-frequency driving mode, When the input image entering the display panel driver represents a moving image, the display panel is driven in the first mode, wherein when the input image represents a static image and the display device is in a hybrid driving mode, the display panel is driven in the second mode, and Wherein, when the input image represents a static image and the display device is not in the hybrid driving mode, the display panel is driven in the third mode.

9. The display device according to claim 8, wherein: The display panel driver is configured to determine a flicker value of the input image, and Wherein, the display panel driver is configured to determine the low driving frequency according to the flicker value of the input image.

10. The display device according to claim 8, wherein: When the input image represents a static image and a difference between a maximum brightness of the input image and a minimum brightness of the input image is equal to or less than a first reference value, the display panel driver is configured to drive the display panel in the second mode, and Wherein, when the input image represents a static image and the difference between the maximum brightness of the input image and the minimum brightness of the input image is greater than the first reference value, the display panel driver is configured to drive the display panel in the third mode.

11. The display device according to claim 8, wherein: When the input image represents a static image and the size of images having the same grayscale value in the input image is greater than a second reference value, the display panel driver is configured to drive the display panel in the second mode, and Wherein, when the input image represents a static image and the size of the images having the same grayscale value in the input image is equal to or smaller than the second reference value, the display panel driver is configured to drive the display panel in the third mode.

12. The display device according to claim 8, wherein: The display panel driver is configured to divide the input image into a plurality of segments and to determine segment driving frequencies of the plurality of segments, and Wherein, when the absolute value of the difference between the number of the worst segment having the highest segment driving frequency among the multiple segments and the number of the majority segment having the most frequently occurring segment driving frequency among the multiple segments is greater than a third reference value, the display panel driver is configured to drive the display panel at a compensation driving frequency that is smaller than the segment driving frequency of the worst segment.

13. The display device according to claim 12, wherein: When an absolute value of the difference between the number of the worst segment and the number of the majority segment is greater than the third reference value, the display panel driver is configured to compensate for data of the worst segment.

14. The display device according to claim 1, wherein: A second data writing gate signal and a data initializing gate signal applied to the display panel have the low driving frequency in the second mode, and Wherein, the first data writing gate signal, the emission signal and the organic light emitting element initialization gate signal applied to the display panel have the high driving frequency in the second mode.

15. The display device according to claim 1, wherein: A first data writing gate signal, a second data writing gate signal, a data initialization gate signal, an emission signal, and an organic light emitting element initialization gate signal applied to the display panel have the low driving frequency in the second mode, and Wherein, the low power supply voltage applied to the cathode of the organic light emitting element of the display panel has the high driving frequency in the second mode.

16. A display device, comprising: a display panel comprising pixels, the pixels comprising switching elements of a first type and switching elements of a second type different from the first type; as well as a display panel driver configured to drive the display panel, wherein the display panel driver is configured to drive the first type of switching elements and the second type of switching elements at a high driving frequency in a first mode, wherein the display panel driver is configured to drive at least one of the first type of switching element and the second type of switching element at a low driving frequency in a second mode, and wherein the display panel driver is configured to count the duration of the second mode and compare the duration of the second mode with a reference time, and Wherein, when the duration of the second mode is greater than the reference time, during the second mode, a driving signal including a compensation frame for compensating for a threshold voltage of the at least one switching element is applied to at least one switching element of the first type of switching element and the second type of switching element.

17. The display device according to claim 16, wherein: When the duration of the second mode is greater than the reference time, the display panel driver is configured to insert the compensation frame having a compensating driving frequency greater than the low driving frequency.

18. The display device according to claim 16, wherein: generating a data writing gate signal and a data initializing gate signal applied to the display panel based on the gate-on voltage and the gate-off voltage, and Wherein, when the duration of the second mode is greater than the reference time, the display panel driver is configured to reduce the level of the gate-off voltage.

19. The display device according to claim 16, wherein: generating a data writing gate signal and a data initializing gate signal applied to the display panel based on the gate-on voltage and the gate-off voltage, and Wherein, when the duration of the second mode is greater than the reference time, the display panel driver is configured to increase the level of the gate-on voltage.

20. The display device according to claim 16, wherein: When the duration of the second mode is greater than the reference time, the display panel driver is configured to reduce a level of an initialization voltage applied to the display panel.

Images