Display device

Abstract

A display device is disclosed. The display device includes: a display panel; and a panel driver configured to drive the display panel. In an active period of the frame period, the panel driver generates a data voltage based on the gamma voltage, supplies the data voltage to the plurality of pixels through the plurality of data lines, and supplies a scan signal having a gate-on voltage to the plurality of pixels through the plurality of scan lines. In a blanking period of the frame period, the panel driver outputs a black data voltage to the plurality of data lines and outputs a gate off voltage to the plurality of scan lines. In a display-off period, the panel driver outputs a gamma voltage to the plurality of data lines, outputs a gate-off voltage to the plurality of scan lines, and adjusts at least one of the gamma voltage and the gate-off voltage.

Description

Technical Field

[0001] Embodiments of the inventive concept relate to a display device, and more particularly, to a display device capable of preventing flickering in a display-off period and a method of operating the display device. Background Art

[0002] When static electricity is induced to the display panel of the display device, the threshold voltage of the transistor of each pixel of the display panel may shift (for example, positive shift), and leakage current through the transistor may be generated due to the threshold voltage shift. In addition, the brightness of the pixel may be distorted due to the leakage current.

[0003] For example, in a display-off period in which the display panel does not display an image, flickering (eg, green flickering) of the display panel may occur due to leakage current. Summary of the invention

[0004] Some embodiments provide a display device capable of preventing flickering in a display off period.

[0005] Some embodiments provide a method of operating a display device capable of preventing flickering in a display off period.

[0006] According to an embodiment, a display device is provided, the display device comprising: a display panel including a plurality of data lines, a plurality of scan lines, and a plurality of pixels connected to the plurality of data lines and the plurality of scan lines; and a panel driver configured to drive the display panel. In an effective period of a frame period, the panel driver generates a data voltage based on a gamma voltage, provides the data voltage to a plurality of pixels through a plurality of data lines, and provides a scan signal having a gate-on voltage to a plurality of pixels through a plurality of scan lines. In a blanking period of a frame period, the panel driver outputs a black data voltage to a plurality of data lines, and outputs a gate-off voltage to a plurality of scan lines. In a display-off period, the panel driver outputs a gamma voltage to a plurality of data lines, outputs a gate-off voltage to a plurality of scan lines, and adjusts at least one of the gamma voltage and the gate-off voltage.

[0007] In an embodiment, the display-off period is between the display-on period and the sleep state period.

[0008] In an embodiment, the display-off period is between the display-on period and the power-off period.

[0009] In an embodiment, in the display off period, the panel driver reduces the gamma voltage so that a difference between the gate-off voltage and the gamma voltage becomes greater than or equal to a predetermined voltage margin.

[0010] In an embodiment, the panel driver adjusts the gamma voltage to a predetermined low gamma voltage in the display off period.

[0011] In an embodiment, the panel driver adjusts the gamma voltage to the black data voltage in the display off period.

[0012] In an embodiment, in the display off period, the panel driver increases the gate-off voltage so that a difference between the gate-off voltage and the gamma voltage becomes greater than or equal to a predetermined voltage margin.

[0013] In an embodiment, the panel driver adjusts the gate-off voltage to a predetermined high-off voltage in the display-off period.

[0014] In an embodiment, the panel driver adjusts the gate-off voltage to a voltage obtained by adding a predetermined voltage margin to the gamma voltage in the display-off period.

[0015] In an embodiment, in the display off period, the panel driver decreases the gamma voltage and increases the gate-off voltage so that a difference between the gate-off voltage and the gamma voltage becomes greater than or equal to a predetermined voltage margin.

[0016] In an embodiment, in the display off period, the panel driver adjusts the gamma voltage to the black data voltage, and adjusts the gate-off voltage to a voltage obtained by adding a predetermined voltage margin to the adjusted gamma voltage.

[0017] In an embodiment, the black data voltage is set to a plurality of first voltage levels at a plurality of dimming levels, respectively. In a display off period, the gamma voltage is adjusted to a plurality of first voltage levels at a plurality of dimming levels, the gate-off voltage is adjusted to a plurality of second voltage levels at a plurality of dimming levels, and the plurality of second voltage levels are respectively higher than the plurality of first voltage levels by a predetermined voltage margin.

[0018] In an embodiment, the panel driver selectively performs an operation of adjusting at least one of the gamma voltage and the gate-off voltage in response to a command received from an external host processor.

[0019] According to an embodiment, a method for operating a display device is provided. In the method, a data voltage is generated based on a gamma voltage in an effective period of a frame period, the data voltage is provided to a plurality of pixels through a plurality of data lines in the effective period, a scan signal having a gate-on voltage is provided to a plurality of pixels through a plurality of scan lines in the effective period, a black data voltage is output to the plurality of data lines in a blanking period of the frame period, a gate-off voltage is output to the plurality of scan lines in the blanking period, a gamma voltage is output to the plurality of data lines in a display-off period, a gate-off voltage is output to the plurality of scan lines in a display-off period, and at least one of the gamma voltage and the gate-off voltage is adjusted in the display-off period.

[0020] In an embodiment, in order to adjust at least one of the gamma voltage and the gate-off voltage, the gamma voltage is reduced in the display-off period so that a difference between the gate-off voltage and the gamma voltage becomes greater than or equal to a predetermined voltage margin.

[0021] In an embodiment, in order to adjust at least one of the gamma voltage and the gate-off voltage, the gamma voltage is adjusted to a predetermined low gamma voltage in the display-off period.

[0022] In an embodiment, in order to adjust at least one of the gamma voltage and the gate-off voltage, the gamma voltage is adjusted to the black data voltage in the display-off period.

[0023] In an embodiment, to adjust at least one of the gamma voltage and the gate-off voltage, the gate-off voltage is increased in the display-off period so that a difference between the gate-off voltage and the gamma voltage becomes greater than or equal to a predetermined voltage margin.

[0024] In an embodiment, in order to adjust at least one of the gamma voltage and the gate-off voltage, the gamma voltage is reduced in the display-off period, and the gate-off voltage is increased in the display-off period.

[0025] In an embodiment, to adjust at least one of the gamma voltage and the gate-off voltage, the gamma voltage is adjusted to the black data voltage in the display-off period, and the gate-off voltage is adjusted to a voltage obtained by adding a predetermined voltage margin to the adjusted gamma voltage in the display-off period.

[0026] As described above, in the display device and the method for operating the display device according to the embodiment, in the display off period, at least one of the gamma voltage applied to the data line and the gate off voltage applied to the scan line can be adjusted. Therefore, in the display off period, leakage current in each pixel can be prevented, and flickering of the display panel caused by the leakage current can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present inventive concept will become more apparent by describing embodiments of the present inventive concept in detail with reference to the attached drawings.

[0028] Figure 1 is a block diagram showing a display device according to an embodiment.

[0029] Figure 2 is a circuit diagram showing an example of a pixel included in the display device according to the embodiment.

[0030] Figure 3: is a timing chart showing an example of voltages in a display-off period in a display device in which a gamma voltage and a gate-off voltage are not adjusted.

[0031] FIG. 4A to FIG. 4C is a diagram for describing an example of flicker caused by static electricity in a display-off period in a display device in which a gamma voltage and a gate-off voltage are not adjusted.

[0032] Figure 5 : is a timing chart showing an example of voltages in a display-off period in the display device according to the embodiment.

[0033] Figure 6 : is a circuit diagram for describing an example of a gate-source voltage of a second transistor in each pixel in a display off period in a display device according to an embodiment.

[0034] Figure 7 is a flowchart illustrating a method of operating a display device according to an embodiment.

[0035] FIG. 8A to FIG. 8D is a diagram for describing an example of a display OFF period.

[0036] Fig. 9 is a timing chart for describing an example in which the gamma voltage is reduced in the display-off period.

[0037] Fig. 10A is a timing diagram for describing an example in which the gamma voltage is reduced in the display off period, and Fig. 10B is a diagram for describing an example in which a gamma voltage is reduced to different voltage levels for different display devices in a display off period.

[0038] Fig.11 is a flowchart illustrating a method of operating a display device according to an embodiment.

[0039] Fig.12 is a timing chart for describing an example in which the gate-off voltage increases in the display-off period.

[0040] Fig.13 is a timing chart for describing an example in which the gate-off voltage increases in the display-off period.

[0041] Fig.14 is a flowchart illustrating a method of operating a display device according to an embodiment.

[0042] Fig.15A is a timing diagram for describing an example in which the gamma voltage decreases and the gate-off voltage increases in the display-off period, and Fig. 15Bis a diagram for describing an example of adjusting each of a gamma voltage and a gate-off voltage to a different voltage level for different display devices in a display-off period.

[0043] Fig.16 is a diagram for describing an example of adjusting each of a gamma voltage and a gate-off voltage to a different voltage level for different dimming levels in a display-off period.

[0044] Fig.17 is a block diagram showing an electronic device including a display device according to an embodiment. DETAILED DESCRIPTION

[0045] Embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings.Throughout the drawings, like reference numerals may refer to like elements.

[0046] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and these elements are not limited by these terms. Thus, the "first" element in an embodiment may be described as the "second" element in another embodiment.

[0047] It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly dictates otherwise.

[0048] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0049] The term "about" as used herein includes the stated value and means within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system). For example, as understood by a person of ordinary skill in the art, "about" may mean within one or more standard deviations. In addition, it will be understood that, although a parameter may be described herein as having "about" a certain value, depending on the embodiment, the parameter may be an exact certain value or an approximate certain value within the measurement error as will be understood by a person of ordinary skill in the art. Other uses of these terms and similar terms used to describe the relationship between components should be interpreted in a similar manner.

[0050] Figure 1 is a block diagram showing a display device according to an embodiment. Figure 2 is a circuit diagram showing an example of a pixel included in the display device according to the embodiment. Figure 3: is a timing chart showing an example of voltages in a display-off period in a display device in which a gamma voltage and a gate-off voltage are not adjusted. FIG. 4A to FIG. 4C is a diagram for describing an example of flicker caused by static electricity in a display-off period in a display device in which a gamma voltage and a gate-off voltage are not adjusted. Figure 5 : is a timing chart showing an example of voltages in a display-off period in the display device according to the embodiment. Figure 6 : is a circuit diagram for describing an example of a gate-source voltage of a second transistor in each pixel in a display off period in a display device according to an embodiment.

[0051] refer to Figures 1 to 6 According to an embodiment, the display device 100 may include: a display panel 110 including a plurality of pixels PX; and a panel driver 120 driving the display panel 110. In some embodiments, the panel driver 120 may include: a data driver 130 providing a data voltage VDAT to the plurality of pixels PX; a scan driver 140 providing a scan signal SS to the plurality of pixels PX; an emission driver 150 providing an emission signal EM to the plurality of pixels PX; a power management circuit 160 generating a voltage (e.g., an analog driving voltage AVDD) for operation of the display device 100; and a controller 170 controlling the operation of the display device 100.

[0052] The display panel 110 may include a plurality of data lines, a plurality of scan lines, a plurality of emission lines, and a plurality of pixels PX connected to the plurality of data lines, the plurality of scan lines, and the plurality of emission lines. Figure 2 As shown in , each pixel PX may include a storage capacitor CST, first, second, third, fourth, fifth, sixth, and seventh transistors T1, T2, T3, T4, T5, T6, and T7, and a light emitting element EL.

[0053] The storage capacitor CST can store the data voltage VDAT transmitted through the second transistor T2 and the first transistor T1 (connected in a diode manner). In some embodiments, the storage capacitor CST may include a first electrode connected to a line transmitting a first power supply voltage ELVDD (e.g., a high power supply voltage) and a second electrode connected to the gate of the first transistor T1.

[0054] The first transistor T1 may generate a driving current based on the data voltage VDAT stored in the storage capacitor CST. In some embodiments, the first transistor T1 may include a gate connected to the storage capacitor CST, a first terminal connected to the second transistor T2 and the fifth transistor T5, and a second terminal connected to the third transistor T3 and the sixth transistor T6.

[0055] The second transistor T2 may transmit the data voltage VDAT of the data line DL to the first terminal of the first transistor T1 in response to the scan signal SS (or the write signal GW). In some embodiments, the second transistor T2 may include a gate receiving the scan signal SS (or the write signal GW), a first terminal (e.g., a source) connected to the data line DL, and a second terminal connected to the first terminal of the first transistor T1.

[0056] The third transistor T3 may be diode-connected to the first transistor T1 in response to the scan signal SS (or the write signal GW). In some embodiments, the third transistor T3 may include a gate receiving the scan signal SS (or the write signal GW), a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to the gate of the first transistor T1.

[0057] The fourth transistor T4 may apply the initialization voltage VINIT to the storage capacitor CST and the gate of the first transistor T1 in response to the scan signal SS (or the initialization signal GI). In some embodiments, the fourth transistor T4 may include a gate receiving the scan signal SS (or the initialization signal GI), a first terminal connected to the storage capacitor CST and the gate of the first transistor T1, and a second terminal connected to a line transmitting the initialization voltage VINIT.

[0058] The fifth transistor T5 and the sixth transistor T6 may form a path of a driving current from a line transmitting a first power supply voltage ELVDD to a line transmitting a second power supply voltage ELVSS (e.g., a low power supply voltage) in response to an emission signal EM. In some embodiments, the fifth transistor T5 may include a gate receiving the emission signal EM, a first terminal connected to the line transmitting the first power supply voltage ELVDD, and a second terminal connected to the first terminal of the first transistor T1, and the sixth transistor T6 may include a gate receiving the emission signal EM, a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to the anode of the light emitting element EL.

[0059] The seventh transistor T7 may apply the initialization voltage VINIT to the anode of the light emitting element EL in response to the scan signal SS (or the write signal GW). In some embodiments, the seventh transistor T7 may include a gate receiving the scan signal SS (or the write signal GW), a first terminal connected to the anode of the light emitting element EL, and a second terminal connected to a line transmitting the initialization voltage VINIT.

[0060] The light emitting element EL may emit light based on the driving current generated by the first transistor T1. In some embodiments, the light emitting element EL may be an organic light emitting diode (OLED), but is not limited thereto. In some embodiments, the light emitting element EL may be any suitable light emitting element. For example, the light emitting element EL may be a micro light emitting diode, a nano light emitting diode (NED), a quantum dot (QD) light emitting diode, an inorganic light emitting diode, or any other suitable light emitting element. In some embodiments, the light emitting element EL may include an anode connected to the sixth transistor T6 and the seventh transistor T7 and a cathode connected to a line transmitting the second power supply voltage ELVSS.

[0061] although Figure 2 1 shows an example in which the scan signal SS applied to the second transistor T2, the third transistor T3, and the seventh transistor T7 is the same write signal GW, but in some embodiments, the scan signal SS applied to the second transistor T2, the third transistor T3, and the seventh transistor T7 may be different signals. Figure 2 As shown in , the first transistor T1 to the seventh transistor T7 may be implemented as a P-type metal oxide semiconductor (PMOS) transistor, but is not limited thereto. In some embodiments, at least one of the first transistor T1 to the seventh transistor T7 may be implemented as an N-type metal oxide semiconductor (NMOS) transistor. In addition, although Figure 2 An example in which each pixel PX has a 7T1C structure including seven transistors T1 to T7 and one capacitor CST is shown, but the structure of the pixel PX of the display device 100 according to the embodiment is not limited to Figure 2 The 7T1C structure shown in FIG.

[0062] The data driver 130 may generate a data voltage VDAT based on the output image data ODAT, the data control signal DCTRL and the gamma voltage VREG, and may provide the data voltage VDAT to a plurality of pixels PX. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal and a load signal. The data driver 130 may generate a data voltage VDAT based on the gamma voltage VREG. In some embodiments, the data driver 130 may generate data voltages VDAT corresponding to a plurality of gray levels by dividing the gamma voltage VREG, and may provide a plurality of pixels PX with a data voltage VDAT corresponding to a gray level indicated by the output image data ODAT. In addition, the data driver 130 may provide a plurality of pixels PX with a data voltage VDAT generated based on the gamma voltage VREG through a plurality of data lines in an effective period of each frame period of the display-on period, may output a black data voltage VBLACK to a plurality of data lines in a blanking period (e.g., a vertical blanking period or an edge period) of each frame period of the display-on period, and may output a gamma voltage VREG in a display-off period. Here, the black data voltage VBLACK may mean a data voltage VDAT for the lowest gray level (e.g., 0 gray level) or a highest data voltage. In some embodiments, the data driver 130 and the controller 170 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED) integrated circuit. In some embodiments, the data driver 130 and the controller 170 may be implemented as separate integrated circuits.

[0063] In some embodiments, the data driver 130 may include a voltage conversion block VCB that receives an analog driving voltage AVDD from the power management circuit 160 and generates a gamma voltage VREG, a gate-off voltage VGH, and a gate-on voltage VGL based on the analog driving voltage AVDD. The voltage conversion block VCB may convert the analog driving voltage AVDD into a gamma voltage VREG, a gate-off voltage VGH, and a gate-on voltage VGL. The data driver 130 may generate a data voltage VDAT based on the gamma voltage VREG, and may provide the gate-off voltage VGH and the gate-on voltage VGL to the scan driver 140. Although Figure 1 An example in which the voltage conversion block VCB is included in the data driver 130 is shown, but the location of the voltage conversion block VCB is not limited to Figure 1 In some embodiments, the voltage conversion block VCB may be included in the power management circuit 160 or the controller 170 .

[0064] The scan driver 140 may generate a scan signal SS having a gate-on voltage VGL based on a scan control signal SCTRL received from the controller 170. In some embodiments, the scan control signal SCTRL may include a scan start signal and a scan clock signal, but is not limited thereto. In addition, in an effective period of each frame period of the display-on period, the scan driver 140 may sequentially provide the scan signal SS to a plurality of pixels PX row by row. In some embodiments, the scan signal SS applied to each pixel PX may include, but is not limited to, Figure 2 110. In addition, in the blanking period of each frame period of the display-on period and the display-off period, the scan driver 140 may output the gate-off voltage VGH as the scan signal SS to the plurality of scan lines. In some embodiments, the scan driver 140 may be integrated or formed in the display panel 110. In some embodiments, the scan driver 140 may be implemented as one or more integrated circuits.

[0065] The emission driver 150 may generate an emission signal EM based on an emission control signal EMCTRL received from the controller 170, and may sequentially provide the emission signal EM to a plurality of pixels PX row by row. In some embodiments, the emission control signal EMCTRL may include an emission start signal and an emission clock signal, but is not limited thereto. In some embodiments, the emission driver 150 may be integrated or formed in the display panel 110. In some embodiments, the emission driver 150 may be implemented as one or more integrated circuits.

[0066] The power management circuit 160 may generate a voltage (e.g., an analog driving voltage AVDD) for operation of the display device 100 based on the power control signal PCTRL received from the controller 170. For example, the power management circuit 160 may generate an analog driving voltage AVDD provided to the data driver 130, and may further generate a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINIT provided to the display panel 110. In some embodiments, the power management circuit 160 may be implemented as an integrated circuit, and the integrated circuit may be referred to as a power management integrated circuit (PMIC). In some embodiments, the power management circuit 160 may be included in the data driver 130 or the controller 170.

[0067] The controller 170 (e.g., a timing controller (TCON)) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In some embodiments, the controller 170 may receive a command CMD (or a user command) instead of the input image data IDAT during a blanking period of a frame period. In addition, as Figure 1 As shown in , the control signal CTRL may include a display-on signal DISP_ON indicating a display-on period, a display-off signal DISP_OFF ​​indicating a display-off period, a sleep-in signal SLP_IN indicating the start of a sleep state period, a sleep-out signal SLP_OUT indicating the end of a sleep state period, a power-on signal PWR_ON indicating that the power of the display device 100 is turned on, and a power-off signal PWR_OFF indicating that the power of the display device 100 is turned off. In some embodiments, the control signal CTRL may further include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc., but is not limited thereto. The controller 170 may generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, an emission control signal EMCTRL, and a power control signal PCTRL based on the input image data IDAT and the control signal CTRL. The controller 170 may control the operation of the data driver 130 by providing the output image data ODAT and the data control signal DCTRL to the data driver 130, may control the operation of the scan driver 140 by providing the scan control signal SCTRL to the scan driver 140, may control the operation of the emission driver 150 by providing the emission control signal EMCTRL to the emission driver 150, and may control the operation of the power management circuit 160 by providing the power control signal PCTRL to the power management circuit 160.

[0068] like Figure 3As shown in, in the display off period DISP_OFF_P between the display on period DISP_ON_P and the sleep state period SLP_STA_P or between the display on period DISP_ON_P and the power off period, in the case where the gamma voltage VREG and the gate-off voltage VGH are not adjusted, the gate-source voltage VGS1 of the second transistor T2 of each pixel PX can be reduced. For example, when the display device 100 enters the display off period DISP_OFF_P in response to the display off signal DISP_OFF, the data driver 130 can output the gamma voltage VREG instead of the data voltage VDAT and the black data voltage VBLACK to the plurality of data lines. That is, in the display off period DISP_OFF_P, the voltage VDL of the data line DL connected to the first terminal (e.g., source) of the second transistor T2 can be increased from the black data voltage VBLACK (or the data voltage VDAT) to the gamma voltage VREG. Therefore, the gate-source voltage VGS1 of the second transistor T2 in the display-off period DISP_OFF_P may be less than the gate-source voltage of the second transistor T2 in the display-on period DISP_ON_P. For example, in the display-on period DISP_ON_P, the voltage difference between the gate-off voltage VGH of about 6.9V applied to the gate of the second transistor T2 and the black data voltage VBLACK of about 6.4V applied to the first terminal of the second transistor T2 may be about 0.5V. However, in the display-off period DISP_OFF_P, the voltage difference between the gate-off voltage VGH of about 6.9V applied to the gate of the second transistor T2 and the gamma voltage VREG of about 6.8V applied to the first terminal of the second transistor T2 may be about 0.1V (which is less than the voltage difference of about 0.5V in the display-on period DISP_ON_P). For ease of explanation, Figure 3 An example of the voltage VDL of the data line DL when the display device 100 displays a black image or a black pattern is shown. However, in the display on period DISP_ON_P, the voltage VDL of the data line DL may be the data voltage VDAT in the effective period of each frame period, and may be the black data voltage VBLACK in the blanking period of each frame period.

[0069] In addition, in the case where the gamma voltage VREG and the gate-off voltage VGH are not adjusted in the display off period DISP_OFF_P, the display panel 110 may flicker due to static electricity. Figure 4AAs shown in , when a user grasps the electronic device 200 including the display device 100, static electricity may be induced to the display panel 110. For example, static electricity may flow into the polyimide layer of the display panel 110. Due to the static electricity, the threshold voltage of each of the first transistor T1 to the seventh transistor T7 of each pixel PX may shift (for example, positive shift), and leakage current may be generated. For example, Figure 4B As shown in , in the display off period DISP_OFF_P, if the threshold voltage of the second transistor T2 is offset due to static electricity, and the gate-source voltage VGS1 of the second transistor T2 is reduced to a voltage difference of about 0.1V between the gate-off voltage VGH of about 6.9V and the gamma voltage VREG of about 6.8V, a leakage current ILEAK through the second transistor T2 may be generated. The leakage current ILEAK through the second transistor T2 may be provided to the light emitting element EL through the first transistor T1 and the sixth transistor T6, and the light emitting element EL may emit light based on the leakage current ILEAK. In this case, as Figure 4C As shown in , flickering of the display panel 110 of the electronic device 200 may occur. For example, a green light emitting element may have a higher light emitting efficiency than red and blue light emitting elements, and thus, green flickering may occur in the electronic device 200.

[0070] In order to prevent the display panel 110 from flickering in the display off period DISP_OFF_P, in the display device 100 according to the embodiment, the panel driver 120 may adjust at least one of the gamma voltage VREG and the gate off voltage VGH in the display off period DISP_OFF_P. In some embodiments, in the display off period DISP_OFF_P, the panel driver 120 may reduce the gamma voltage VREG so that the difference between the gate off voltage VGH and the gamma voltage VREG becomes greater than or equal to a predetermined voltage margin. For example, the predetermined voltage margin may be about 0.5V or about 0.6V, but is not limited thereto. In some embodiments, in the display off period DISP_OFF_P, the panel driver 120 may increase the gate off voltage VGH so that the difference between the gate off voltage VGH and the gamma voltage VREG becomes greater than or equal to a predetermined voltage margin. In some embodiments, in the display off period DISP_OFF_P, the panel driver 120 may reduce the gamma voltage VREG and may increase the gate off voltage VGH so that the difference between the gate off voltage VGH and the gamma voltage VREG becomes greater than or equal to a predetermined voltage margin.

[0071] For example, Figure 5As shown in FIG. 1 , in the display off period DISP_OFF_P, the panel driver 120 can generate a gamma voltage VREG' lower than the gamma voltage VREG in the display on period DISP_ON_P by reducing the gamma voltage VREG, and can output the reduced gamma voltage VREG' to a plurality of data lines. In addition, the panel driver 120 can generate a gate-off voltage VGH' higher than the gate-off voltage VGH in the display on period DISP_ON_P by increasing the gate-off voltage VGH, and can output the increased gate-off voltage VGH' to a plurality of scan lines. Therefore, as Figure 6 As shown in , the voltage difference between the gate-off voltage VGH' applied to the gate of the second transistor T2 and the gamma voltage VREG' applied to the first terminal (e.g., source) of the second transistor T2 or the gate-source voltage VGS2 of the second transistor T2 of each pixel PX may be greater than or equal to a predetermined voltage margin, the second transistor T2 may be turned off (e.g., completely turned off), and in some embodiments, no leakage current ILEAK through the second transistor T2 is generated. Therefore, in some embodiments, even if the threshold voltage of the second transistor T2 is shifted due to the static electricity of the display panel 110, in the display off period DISP_OFF_P, no leakage current ILEAK through the second transistor T2 is generated, and flickering of the display panel 110 can be prevented.

[0072] Furthermore, in some embodiments, the operation of adjusting at least one of the gamma voltage VREG and the gate-off voltage VGH may be selectively performed in response to a command CMD (eg, a user command) received from an external host processor. That is, the command CMD may enable or disable the operation.

[0073] As described above, in the display device 100 according to the embodiment, in the display off period DISP_OFF_P, at least one of the gamma voltage VREG applied to the data line and the gate off voltage VGH applied to the scan line can be adjusted. Therefore, in the display off period DISP_OFF_P, the leakage current ILEAK in each pixel PX can be prevented, and the flicker of the display panel 110 can be prevented.

[0074] Figure 7 is a flowchart illustrating a method of operating a display device according to an embodiment. FIG. 8A to FIG. 8D is a diagram for describing an example of a display OFF period. Fig. 9 is a timing chart for describing an example in which the gamma voltage is reduced in the display-off period. Fig. 10A is a timing diagram for describing an example in which the gamma voltage is reduced in the display off period, and Fig. 10Bis a diagram for describing an example in which a gamma voltage is reduced to different voltage levels for different display devices in a display off period.

[0075] refer to Figure 1 , Figure 2 and Figures 7 to 10B In the effective period of each frame period of the display on period DISP_ON_P, the panel driver 120 may generate a data voltage VDAT based on the gamma voltage VREG (S310), and may provide the data voltage VDAT and the scan signal SS having the gate-on voltage VGL to the plurality of pixels PX of the display panel 110 (S320 and S330). For example, the data driver 130 may generate the data voltage VDAT by dividing the gamma voltage VREG corresponding to the plurality of gray levels respectively (S310), and may provide the data voltage VDAT corresponding to the gray level indicated by the output image data ODAT to the plurality of pixels PX through the plurality of data lines (S320). In addition, the scan driver 140 may sequentially provide the scan signal SS having the gate-on voltage VGL to the plurality of pixels PX row by row through the plurality of scan lines (S330). The plurality of pixels PX may receive the data voltage VDAT in response to the scan signal SS, and may display an image based on the data voltage VDAT.

[0076] In a blanking period (e.g., a vertical blanking period or a porch period) of each frame period of the display on period DISP_ON_P, the panel driver 120 may output a black data voltage VBLACK to a plurality of data lines (S340), and may output a gate-off voltage VGH as a scan signal SS to a plurality of scan lines (S350). For example, the black data voltage VBLACK may be a data voltage VDAT for a lowest gray level (e.g., a gray level of 0) or a highest data voltage, and the gate-off voltage VGH may be a high gate voltage.

[0077] If the panel driver 120 does not receive the display off signal DISP_OFF ​​(S360: No), the panel driver 120 may repeat the above operations (S310 to S350). When the panel driver 120 receives the display off signal DISP_OFF ​​(S360: Yes), the display device 100 may enter the display off period DISP_OFF_P. Here, the display off period DISP_OFF_P may be a period in which the emission signal EM is maintained at the gate-off voltage VGH and the plurality of pixels PX do not emit light.

[0078] In some embodiments, Fig. 8A and Figure 8CAs shown in , the display off period DISP_OFF_P may be between the display on period DISP_ON_P and the sleep state period SLP_STA_P. In some embodiments, as Figure 8B and Fig.8D As shown in , the display off period DISP_OFF_P may be between the display on period DISP_ON_P and the power off period PWR_OFF_P. Fig. 8A As shown in, in an embodiment, when the display off signal DISP_OFF ​​is received in the display on period DISP_ON_P, the display device 100 may enter the display off period DISP_OFF_P. In addition, when the sleep entry signal SLP_IN is received in the display off period DISP_OFF_P, the display device 100 may enter the sleep state period SLP_STA_P. In the sleep state period SLP_STA_P, the panel driver 120 may stop generating the voltages VREG, VGH, and ELVDD. Figure 8B As shown in , in an embodiment, when a power-off signal PWR_OFF is received in the display-off period DISP_OFF_P, the display device 100 may enter the power-off period PWR_OFF_P. The power-off period PWR_OFF_P may refer to a period in which the display device 100 is powered off. Figure 8C As shown in , in an embodiment, when the sleep exit signal SLP_OUT is received in the sleep state period SLP_STA_P, the display device 100 may enter the display off period DISP_OFF_P. In addition, in an embodiment, when the display on signal DISP_ON is received in the display off period DISP_OFF_P, the display device 100 may enter the display on period DISP_ON_P in which the display panel 110 displays an image. Fig.8D As shown in , in an embodiment, when the power-on signal PWR_ON is received in the power-off period PWR_OFF_P, the display apparatus 100 may enter the display-off period DISP_OFF_P.

[0079] Reference again Figure 7In the method of operating the display device 100 according to the embodiment, in the display off period DISP_OFF_P, the panel driver 120 may output the gamma voltage VREG to the plurality of data lines (S370), may output the gate-off voltage VGH to the plurality of scan lines (S380), and may reduce the gamma voltage VREG so that the difference between the gate-off voltage VGH and the gamma voltage VREG becomes greater than or equal to a predetermined voltage margin (S390). In some embodiments, the predetermined voltage margin may be a voltage for turning off (e.g., completely turning off) the second transistor T2, and may be, but is not limited to, about 0.5V or about 0.6V.

[0080] In some embodiments, Fig. 9 As shown in FIG. 1 , in the display off period DISP_OFF_P, the panel driver 120 may generate a reduced gamma voltage VREG′ by reducing the gamma voltage VREG to a predetermined low gamma voltage VLREG. Fig. 9 An example in which the predetermined low gamma voltage VLREG is about 4.5 V is shown, but the predetermined low gamma voltage VLREG is not limited to about 4.5 V. The difference between the gate-off voltage VGH and the reduced gamma voltage VREG' may be greater than or equal to a predetermined voltage margin. Therefore, in an embodiment, in the display off period DISP_OFF_P, no leakage current through the second transistor T2 is generated, and flickering of the display panel 110 may be prevented.

[0081] In some embodiments, Fig. 10A As shown in the figure, in the display off period DISP_OFF_P, the panel driver 120 may generate a reduced gamma voltage VREG by reducing the gamma voltage VREG to the black data voltage VBLACK. Thus, the gate-source voltage of the second transistor T2 in the display off period DISP_OFF_P may be maintained at the gate-source voltage of the second transistor T2 in the display on period DISP_ON_P. Therefore, in an embodiment, in the display off period DISP_OFF_P, a leakage current through the second transistor T2 is not generated, and flickering of the display panel 110 may be prevented.

[0082] In addition, if Fig. 10BAs shown in , the black data voltage VBLACK may have different voltage levels for different display devices DEV1 and DEV2. For example, the black data voltage VBLACK of the first display device DEV1 may be set to about 6.4V by a multi-time programming (MTP) operation of the first display device DEV1, and the black data voltage VBLACK of the second display device DEV2 may be set to about 6.2V by an MTP operation of the second display device DEV2. In this case, in the display off period DISP_OFF_P, the first display device DEV1 may reduce the gamma voltage VREG from about 6.8V to about 6.4V, and the second display device DEV2 may reduce the gamma voltage VREG from about 6.8V to about 6.2V.

[0083] As described above, in the method of operating the display device 100 according to the embodiment, the gamma voltage VREG can be reduced in the display off period DISP_OFF_P. Therefore, in the display off period DISP_OFF_P, leakage current in each pixel PX can be prevented, and flickering of the display panel 110 due to leakage current can be prevented.

[0084] Fig.11 is a flowchart illustrating a method of operating a display device according to an embodiment. Fig.12 is a timing chart for describing an example in which the gate-off voltage increases in the display-off period. Fig.13 is a timing chart for describing an example in which the gate-off voltage increases in the display-off period.

[0085] In addition to the gate-off voltage VGH can be increased in the display off period DISP_OFF_P, Fig.11 The method shown in Figure 7 The methods shown in are substantially the same. Therefore, for ease of explanation, further description of previously described elements and technical aspects may be omitted.

[0086] refer to Figure 1 , Figure 2 and Figures 11 to 13In the effective period of each frame period of the display on period DISP_ON_P, the panel driver 120 may generate a data voltage VDAT based on the gamma voltage VREG (S310), and may provide the data voltage VDAT and the scan signal SS having the gate-on voltage VGL to the plurality of pixels PX of the display panel 110 (S320 and S330). In the blanking period of each frame period of the display on period DISP_ON_P, the panel driver 120 may output a black data voltage VBLACK to the plurality of data lines (S340), and may output the gate-off voltage VGH as the scan signal SS to the plurality of scan lines (S350). If the panel driver 120 does not receive the display off signal DISP_OFF ​​(S360: No), the panel driver 120 may repeat the above operations (S310 to S350). When the panel driver 120 receives the display off signal DISP_OFF ​​(S360: Yes), the display device 100 may enter the display off period DISP_OFF_P.

[0087] In the method of operating the display device 100 according to an embodiment, in the display off period DISP_OFF_P, the panel driver 120 can output the gamma voltage VREG to multiple data lines (S370), can output the gate off voltage VGH to multiple scan lines (S380), and can increase the gate off voltage VGH so that the difference between the gate off voltage VGH and the gamma voltage VREG becomes greater than or equal to a predetermined voltage margin (S395).

[0088] In some embodiments, Fig.12 As shown in FIG. 1 , in the display off period DISP_OFF_P, the panel driver 120 may generate an increased gate-off voltage VGH′ by increasing the gate-off voltage VGH to a predetermined high off voltage VOFFH. Fig.12 An example in which the predetermined high cut-off voltage VOFFH is about 7.4 V is shown, but the predetermined high cut-off voltage VOFFH is not limited to about 7.4 V. The difference between the increased gate cut-off voltage VGH' and the gamma voltage VREG may be greater than or equal to a predetermined voltage margin. Therefore, in an embodiment, in the display off period DISP_OFF_P, no leakage current through the second transistor T2 is generated, and flickering of the display panel 110 may be prevented.

[0089] In some embodiments, Fig.13As shown in, in the display off period DISP_OFF_P, the panel driver 120 can generate an increased gate-off voltage VGH” by increasing the gate-off voltage VGH to a voltage VMAR+VREG obtained by adding a predetermined voltage margin VMAR to the gamma voltage VREG. Thus, in the display off period DISP_OFF_P, even if the voltage applied to the first terminal (e.g., the source) of the second transistor T2 increases from the black data voltage VBLACK to the gamma voltage VREG, the difference between the increased gate-off voltage VGH” and the gamma voltage VREG may correspond to the predetermined voltage margin VMAR (e.g., the gate-source voltage VGS of the second transistor T2 of each pixel PX may correspond to the predetermined voltage margin VMAR). Therefore, in an embodiment, in the display off period DISP_OFF_P, no leakage current is generated through the second transistor T2, and flickering of the display panel 110 can be prevented. Although Fig.13 An example in which the predetermined voltage margin VMAR is about 0.6V is shown, but the predetermined voltage margin VMAR is not limited to about 0.6V.

[0090] As described above, in the method of operating the display device 100 according to the embodiment, the gate-off voltage VGH can be increased in the display off period DISP_OFF_P. Therefore, in the display off period DISP_OFF_P, leakage current in each pixel PX can be prevented, and flickering of the display panel 110 caused by leakage current can be prevented.

[0091] Fig.14 is a flowchart illustrating a method of operating a display device according to an embodiment. Fig.15A is a timing diagram for describing an example in which the gamma voltage decreases and the gate-off voltage increases in the display-off period, and Fig. 15B is a diagram for describing an example of adjusting each of a gamma voltage and a gate-off voltage to a different voltage level for different display devices in a display-off period. Fig.16 is a diagram for describing an example of adjusting each of a gamma voltage and a gate-off voltage to a different voltage level for different dimming levels in a display-off period.

[0092] In addition to reducing the gamma voltage VREG and increasing the gate-off voltage VGH in the display off period DISP_OFF_P, Fig.14 The method shown in Figure 7 or Fig.11 The methods shown in are substantially the same. Therefore, for ease of explanation, further description of previously described elements and technical aspects may be omitted.

[0093] refer to Figure 1 , Figure 2 and Figures 14 to 16 In the effective period of each frame period of the display on period DISP_ON_P, the panel driver 120 may generate a data voltage VDAT based on the gamma voltage VREG (S310), and may provide the data voltage VDAT and the scan signal SS having the gate-on voltage VGL to the plurality of pixels PX of the display panel 110 (S320 and S330). In the blanking period of each frame period of the display on period DISP_ON_P, the panel driver 120 may output a black data voltage VBLACK to the plurality of data lines (S340), and may output the gate-off voltage VGH as the scan signal SS to the plurality of scan lines (S350). If the panel driver 120 does not receive the display off signal DISP_OFF ​​(S360: No), the panel driver 120 may repeat the above operations (S310 to S350). When the panel driver 120 receives the display off signal DISP_OFF ​​(S360: Yes), the display device 100 may enter the display off period DISP_OFF_P.

[0094] In the method of operating the display device 100 according to the embodiment, in the display off period DISP_OFF_P, the panel driver 120 may output the gamma voltage VREG to the plurality of data lines (S370), and may output the gate off voltage VGH to the plurality of scan lines (S380). In addition, the panel driver 120 may reduce the gamma voltage VREG (S390), and may increase the gate off voltage VGH (S395) so that the difference between the gate off voltage VGH and the gamma voltage VREG becomes greater than or equal to the predetermined voltage margin VMAR. For example, the panel driver 120 may reduce the gamma voltage VREG to a predetermined low gamma voltage VLREG or a black data voltage VBLACK, and may increase the gate off voltage VGH to a predetermined high off voltage VOFFH or a voltage obtained by adding the predetermined voltage margin VMAR to the reduced gamma voltage.

[0095] In some embodiments, Fig.15AAs shown in, in the display off period DISP_OFF_P, the panel driver 120 may generate a reduced gamma voltage VREG'' by reducing the gamma voltage VREG to the black data voltage VBLACK, and may generate an increased gate-off voltage VGH''' by increasing the gate-off voltage VGH to a voltage obtained by adding a predetermined voltage margin VMAR to the black data voltage VBLACK. Thus, in the display off period DISP_OFF_P, the difference between the increased gate-off voltage VGH''' and the reduced gamma voltage VREG''' may correspond to the predetermined voltage margin VMAR (for example, the gate-source voltage VGS of the second transistor T2 of each pixel PX may correspond to the predetermined voltage margin VMAR). Therefore, in an embodiment, in the display off period DISP_OFF_P, no leakage current through the second transistor T2 is generated, and flickering of the display panel 110 may be prevented.

[0096] In addition, if Fig. 15B As shown in , the gamma voltage VREG and the gate-off voltage VGH may be adjusted to different voltage levels for different display devices DEV1 and DEV2. For example, the black data voltage VBLACK of the first display device DEV1 may be set to about 6.4V by the MTP operation of the first display device DEV1, and the black data voltage VBLACK of the second display device DEV2 may be set to about 6.6V by the MTP operation of the second display device DEV2. In this case, in the display off period DISP_OFF_P, the first display device DEV1 may adjust the gamma voltage VREG from about 6.8V to about 6.4V corresponding to the black data voltage VBLACK for the first display device DEV1, and may adjust the gate-off voltage VGH to about 7.0V corresponding to the black data voltage VBLACK for the first display device DEV1 plus a predetermined voltage margin VMAR. In addition, in the display off period DISP_OFF_P, the second display device DEV2 may adjust the gamma voltage VREG from approximately 6.8V to approximately 6.6V corresponding to the black data voltage VBLACK for the second display device DEV2, and may adjust the gate-off voltage VGH to approximately 7.2V corresponding to the black data voltage VBLACK for the second display device DEV2 plus a predetermined voltage margin VMAR.

[0097] Furthermore, in some embodiments, Fig.16As shown in , the gamma voltage VREG and the gate-off voltage VGH can be adjusted to different voltage levels at different dimming levels DBV1 to DBV6 (or different brightness values). That is, the black data voltage VBLACK can be set to multiple first voltage levels at different dimming levels DBV1 to DBV6. In the display off period DISP_OFF_P, the gamma voltage VREG can be adjusted to multiple first voltage levels at multiple dimming levels DBV1 to DBV6, and the gate-off voltage VGH can be adjusted to multiple second voltage levels at multiple dimming levels DBV1 to DBV6, and the multiple second voltage levels can be higher than the multiple first voltage levels by a predetermined voltage margin VMAR, respectively.

[0098] For example, the MTP operation may be performed at each of the first to sixth dimming levels DBV1 to DBV6, and as shown in FIG. Fig.16As shown in the figure, the black data voltage VBLACK can be set to about 6.4V at the first dimming level DBV1 corresponding to about 500 nits, the black data voltage VBLACK can be set to about 6.3V at the second dimming level DBV2 corresponding to about 250 nits, the black data voltage VBLACK can be set to about 6.2V at the third dimming level DBV3 corresponding to about 110 nits, the black data voltage VBLACK can be set to about 6.1V at the fourth dimming level DBV4 corresponding to about 80 nits, the black data voltage VBLACK can be set to about 6.0V at the fifth dimming level DBV5 corresponding to about 40 nits, and the black data voltage VBLACK can be set to about 5.9V at the sixth dimming level DBV6 corresponding to about 20 nits. In this case, when entering the display off period DISP_OFF_P at the first dimming level DBV1, the panel driver 120 may adjust the gamma voltage VREG to about 6.4V corresponding to the black data voltage VBLACK, and may adjust the gate-off voltage VGH to about 7.0V corresponding to the black data voltage VBLACK plus a predetermined voltage margin VMAR. In addition, when entering the display off period DISP_OFF_P at the second dimming level DBV2, the panel driver 120 may adjust the gamma voltage VREG to about 6.3V corresponding to the black data voltage VBLACK, and may adjust the gate-off voltage VGH to about 6.9V corresponding to the black data voltage VBLACK plus a predetermined voltage margin VMAR. In addition, when entering the display off period DISP_OFF_P at the third dimming level DBV3, the panel driver 120 may adjust the gamma voltage VREG to about 6.2V corresponding to the black data voltage VBLACK, and may adjust the gate-off voltage VGH to about 6.8V corresponding to the black data voltage VBLACK plus a predetermined voltage margin VMAR. In addition, when entering the display off period DISP_OFF_P at the fourth dimming level DBV4, the panel driver 120 may adjust the gamma voltage VREG to about 6.1 V corresponding to the black data voltage VBLACK, and may adjust the gate-off voltage VGH to about 6.7 V corresponding to the black data voltage VBLACK plus a predetermined voltage margin VMAR. In addition, when entering the display off period DISP_OFF_P at the fifth dimming level DBV5, the panel driver 120 may adjust the gamma voltage VREG to about 6.0 V corresponding to the black data voltage VBLACK, and may adjust the gate-off voltage VGH to about 6.6 V corresponding to the black data voltage VBLACK plus a predetermined voltage margin VMAR.Furthermore, when entering the display off period DISP_OFF_P at the sixth dimming level DBV6 , the panel driver 120 may adjust the gamma voltage VREG to about 5.9V corresponding to the black data voltage VBLACK and may adjust the gate-off voltage VGH to about 6.5V corresponding to the black data voltage VBLACK plus a predetermined voltage margin VMAR.

[0099] As described above, in the method of operating the display device 100 according to the embodiment, in the display off period DISP_OFF_P, the gamma voltage VREG can be reduced and the gate off voltage VGH can be increased. Therefore, in the display off period DISP_OFF_P, leakage current in each pixel PX can be prevented, and flickering of the display panel 110 caused by leakage current can be prevented.

[0100] Fig.17 is a block diagram showing an electronic device including a display device according to an embodiment.

[0101] refer to Fig.17 , the electronic device 1100 may include a host processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may further include a plurality of ports for communicating with, for example, a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0102] The host processor 1110 may perform various computing functions or tasks. The host processor 1110 may be, for example, an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The host processor 1110 may be coupled to other components via, for example, an address bus, a control bus, a data bus, etc. In addition, in some embodiments, the host processor 1110 may be further coupled to an expansion bus such as, for example, a peripheral component interconnect (PCI) bus.

[0103] The memory device 1120 may store data for operation of the electronic device 1100. For example, the memory device 1120 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc. and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0104] The storage device 1130 may be, for example, a solid state drive (SSD) device, a hard disk drive (HDD) device, a compact disk read only memory (CD-ROM) device, etc. The I / O device 1140 may be, for example, an input device such as a keyboard, a keypad, a mouse, a touch screen, etc. and an output device such as, for example, a printer, a speaker, etc. The power supply 1150 may supply power for the operation of the electronic device 1100. The display device 1160 may be coupled to other components via a bus or other communication link.

[0105] In the display device 1160, at least one of the gamma voltage applied to the data line and the gate-off voltage applied to the scan line can be adjusted during the display-off period. Therefore, during the display-off period, leakage current in each pixel can be prevented, and flickering of the display panel caused by the leakage current can be prevented.

[0106] Embodiments of the inventive concept may be applied to any electronic device 1100 including the display device 1160. For example, embodiments of the inventive concept may be applied to a television (TV), a digital TV, a 3D TV, a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, and the like.

[0107] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.

Claims

1. A display device, wherein: The display device comprises: A display panel comprising a plurality of data lines, a plurality of scan lines, and a plurality of pixels connected to the plurality of data lines and the plurality of scan lines; and a panel driver configured to drive the display panel, wherein, in an effective period of a frame period, the panel driver generates a data voltage based on a gamma voltage, supplies the data voltage to the plurality of pixels through the plurality of data lines, and supplies a scan signal having a gate-on voltage to the plurality of pixels through the plurality of scan lines, wherein, in a blanking period of the frame period, the panel driver outputs a black data voltage to the plurality of data lines and outputs a gate-off voltage to the plurality of scan lines, and In which, during a display off period, the panel driver outputs the gamma voltage to the plurality of data lines, outputs the gate-off voltage to the plurality of scan lines, and adjusts at least one of the gamma voltage and the gate-off voltage.

2. The display device according to claim 1, wherein: The display-off period is between the display-on period and the sleep state period.

3. The display device according to claim 1, wherein: The display-off period is between the display-on period and the power-off period.

4. The display device according to claim 1, wherein: In the display-off period, the panel driver reduces the gamma voltage so that a difference between the gate-off voltage and the gamma voltage becomes greater than or equal to a predetermined voltage margin.

5. The display device according to claim 1, wherein: The panel driver adjusts the gamma voltage to a predetermined low gamma voltage in the display off period.

6. The display device according to claim 1, wherein: The panel driver adjusts the gamma voltage to the black data voltage in the display off period.

7. The display device according to claim 1, wherein: In the display-off period, the panel driver increases the gate-off voltage so that a difference between the gate-off voltage and the gamma voltage becomes greater than or equal to a predetermined voltage margin.

8. The display device according to claim 1, wherein: The panel driver adjusts the gate-off voltage to a predetermined high-off voltage in the display-off period.

9. The display device according to claim 1, wherein: The panel driver adjusts the gate-off voltage to a voltage obtained by adding a predetermined voltage margin to the gamma voltage in the display-off period.

10. The display device according to claim 1, wherein: In the display-off period, the panel driver reduces the gamma voltage and increases the gate-off voltage so that a difference between the gate-off voltage and the gamma voltage becomes greater than or equal to a predetermined voltage margin.

11. The display device according to claim 1, wherein: In the display-off period, the panel driver adjusts the gamma voltage to the black data voltage, and adjusts the gate-off voltage to a voltage obtained by adding a predetermined voltage margin to the adjusted gamma voltage.

12. The display device according to claim 1, wherein: The black data voltage is set to a plurality of first voltage levels at a plurality of dimming levels, respectively, and In which, during the display off period, the gamma voltage is adjusted to the multiple first voltage levels at the multiple dimming levels, the gate-off voltage is adjusted to the multiple second voltage levels at the multiple dimming levels, and the multiple second voltage levels are respectively higher than the multiple first voltage levels by a predetermined voltage margin.

13. The display device according to claim 1, wherein: The panel driver selectively performs an operation of adjusting at least one of the gamma voltage and the gate-off voltage in response to a command received from an external host processor.

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