Liquid crystal display panel and display device

Abstract

The invention discloses a liquid crystal display panel and a display device, which are characterized in that a second electrode of a thin film transistor further comprises a first part, and the first part is at least partially overlapped with the orthographic projection of a grid line on a first substrate, so that parasitic capacitance formed between a grid electrode and the second electrode is equivalently compensated; under the condition of counterpoint fluctuation in the technological process, for example, a film layer where a grid electrode is located is equivalent to the overall left part under the ideal counterpoint condition, so that the overlapping capacitance between a third part of a left thin film transistor electrically connected with the same data line and the grid electrode is increased, and the overlapping capacitance between a first part and the grid electrode is decreased; the overlapping capacitance between the third part of the right thin film transistor electrically connected with the data line and the grid electrode is reduced, and the overlapping capacitance between the first part and the grid electrode is increased; the added first part can ensure that the Cgs of each sub-pixel on the left side and the right side of the same data line are roughly the same, the uniformity of Flickers is improved, and the problem of flicker of a display surface is avoided.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a liquid crystal display panel and display device. Background Technology

[0002] Liquid crystal display (LCD) panels are increasingly widely used due to their advantages such as low power consumption, miniaturization, and thinness.

[0003] A liquid crystal display panel typically includes an array substrate and a counter substrate arranged opposite each other, as well as a liquid crystal layer located between the array substrate and the counter substrate. The liquid crystal display panel can change the rotation direction of liquid crystal molecules in the liquid crystal layer by generating an electric field between the pixel electrodes and the common electrode in the array substrate, and achieves display in conjunction with a polarizer. Summary of the Invention

[0004] This invention provides a liquid crystal display panel and display device, which can achieve a liquid crystal display panel with long lifespan, high aperture ratio, low power consumption, and can improve low-frequency flicker and enhance product image quality. The specific solution is as follows:

[0005] An embodiment of the present invention provides a liquid crystal display panel, comprising: an array substrate and an opposing substrate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the opposing substrate; wherein,

[0006] The array substrate includes a first substrate and a plurality of gate lines and a plurality of data lines located on the side of the first substrate facing the opposing substrate. The plurality of gate lines are arranged along the column direction and the plurality of data lines are arranged along the row direction.

[0007] The multiple gate lines and the multiple data lines are insulated and intersected to define multiple sub-pixels. Each sub-pixel in the same row is electrically connected to at least one gate line. Each data line is electrically connected to a portion of the sub-pixels in each of two adjacent columns of sub-pixels, and the two adjacent columns of sub-pixels electrically connected by the data line are located on both sides of the data line.

[0008] The sub-pixel includes a pixel electrode and a thin-film transistor located on the side of the first substrate facing the opposing substrate. The gate of the thin-film transistor is electrically connected to the gate line. The first electrode of the thin-film transistor is electrically connected to the data line. The second electrode of the thin-film transistor includes a first part, a second part, and a third part arranged along the row direction and forming an integral structure. The second part is electrically connected to the pixel electrode. The first part at least partially overlaps with the orthographic projection of the gate line on the first substrate. The third part at least partially overlaps with the orthographic projection of the gate on the first substrate.

[0009] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, each row of sub-pixels is electrically connected to one of the gate lines;

[0010] A data line is provided on both sides of each column of sub-pixels. The (2n-1)th row and the 2nth row of sub-pixels in each column of sub-pixels are electrically connected to the data lines on both sides of the column of sub-pixels, where n is a positive integer.

[0011] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the orthographic projection shape of the first part and the third part on the first substrate is a line shape.

[0012] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the gate line and the gate are an integral structure, and the gate line between two adjacent gates along the row direction includes: a horizontal portion, a first inclined portion connecting one of the two gates to one end of the horizontal portion, and a second inclined portion connecting the other of the two gates to the other end of the horizontal portion; the angle between the first inclined portion and the horizontal portion is an obtuse angle, and the angle between the second inclined portion and the horizontal portion is an obtuse angle;

[0013] The gate line between two adjacent gates along the row direction also includes a vertical portion located on the side of the horizontal portion near the thin-film transistor electrically connected to the gate line, the first portion at least partially overlapping the orthographic projection of the vertical portion on the first substrate.

[0014] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the gate line and the gate are an integral structure, and the gate line between two adjacent gates along the row direction includes: an inclined portion, a first horizontal portion connecting one of the two adjacent gates to one end of the inclined portion, and a second horizontal portion connecting the other gate of the two adjacent gates to the other end of the inclined portion; the angle between the first horizontal portion and the inclined portion is an obtuse angle, and the angle between the inclined portion and the second horizontal portion is an obtuse angle;

[0015] The gate line between two adjacent gates along the row direction also includes a vertical portion located on the side of the inclined portion near the thin-film transistor electrically connected to the gate line, the first portion at least partially overlapping the orthographic projection of the vertical portion on the first substrate.

[0016] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the gate line and the gate are an integral structure, and the gate line between two adjacent gates along the row direction includes: a vertical portion, a first horizontal portion connecting one of the two adjacent gates to one end of the vertical portion, and a second horizontal portion connecting the other gate of the two adjacent gates to the other end of the vertical portion;

[0017] The first portion and the orthographic projection of the vertical portion on the first substrate overlap at least partially.

[0018] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the gate line is located between the first substrate and the pixel electrode, and the data line is located between the gate line and the pixel electrode;

[0019] The array substrate further includes: a first passivation layer located between the data line and the pixel electrode, a planarization layer located between the first passivation layer and the pixel electrode, a common electrode located between the planarization layer and the pixel electrode, and a second passivation layer located between the common electrode and the pixel electrode;

[0020] The second passivation layer, the planarization layer, and the first passivation layer correspond to the second part having a first via that sequentially penetrates the second passivation layer, the planarization layer, and the first passivation layer. The pixel electrode is electrically connected to the second part through a connection portion located in the first via. The ratio of the distance of the first via from the adjacent two data lines along the row direction is 1 to 3.

[0021] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the thickness of the second passivation layer is [missing information].

[0022] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the pixel electrode is a block electrode, and the pixel electrode includes a plurality of slits;

[0023] The common electrode has a planar structure and includes a second through hole corresponding to the first through hole. The connecting part does not contact the inner wall of the second through hole.

[0024] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the liquid crystal layer includes positive liquid crystal, and the liquid crystal elastic constant K of the positive liquid crystal is ≥11.2.

[0025] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the dielectric constant along the direction parallel to the long axis of the positive liquid crystal is the horizontal dielectric constant ε. ∥The dielectric constant along the direction perpendicular to the long axis of the positive liquid crystal is the perpendicular dielectric constant ε. ⊥ , Δε=(ε ∥ -ε ⊥ ) < 4.1.

[0026] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the thickness d of the liquid crystal layer is less than 2.8 μm.

[0027] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, a first alignment layer is disposed on the side of the array substrate facing the liquid crystal layer, and a second alignment layer is disposed on the side of the opposing substrate facing the liquid crystal layer. The impedance values ​​of the materials of the first alignment layer and the second alignment layer are both ≥1×10⁻⁶. 15 Ω.

[0028] Optionally, in the liquid crystal display panel provided in the embodiments of the present invention, the opposing substrate includes: a second substrate, and a black matrix and a color resist layer located on the side of the second substrate facing the array substrate; the black matrix includes a plurality of pixel openings, and the color resist layer includes color resist located in each of the pixel openings;

[0029] The minimum width of the black matrix covering the data line area is 4μm, and the minimum width of the black matrix covering the gate line area is 8.5μm.

[0030] Accordingly, this embodiment of the invention also provides a display device, including: the liquid crystal display panel provided in this embodiment of the invention, and a backlight module located on the light-incident side of the array substrate.

[0031] The beneficial effects of the embodiments of the present invention are as follows:

[0032] This invention discloses a liquid crystal display panel and display device. Since the second electrode of the thin-film transistor also includes a first part, and the first part at least partially overlaps with the orthographic projection of the gate line on the first substrate, this is equivalent to compensating for the parasitic capacitance formed between the gate and the second electrode. In the event of process alignment fluctuations, for example, if the film layer containing the gate is shifted to the left under ideal alignment, the overlap capacitance between the third part and the gate of the left-hand thin-film transistor connected to the same data line increases, while the overlap capacitance between the first part and the gate decreases; conversely, the overlap capacitance between the third part and the gate of the right-hand thin-film transistor connected to the same data line decreases, while the overlap capacitance between the first part and the gate increases. This added first part ensures that the Cgs of each sub-pixel on both sides of the same data line is approximately the same, thus the ΔV corresponding to each sub-pixel... P This consistency improves the uniformity of the flicker and avoids flickering issues on the display surface. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of a liquid crystal display panel provided in an embodiment of the present invention;

[0034] Figure 2 A schematic diagram of a pixel architecture for array substrate 1;

[0035] Figure 3 for Figure 2 The diagram shows a layout schematic of an array substrate;

[0036] Figure 4 for Figure 2 Another layout schematic diagram of the array substrate shown;

[0037] Figure 5 for Figure 4 A schematic diagram of the cross-section along the CC' direction;

[0038] Figure 6 The switching voltage (ΔV) corresponding to the pixel grayscale driving voltage of the positive and negative frames. P ) Schematic diagram;

[0039] Figure 7 for Figure 3 A magnified view of a portion of the image;

[0040] Figure 8 for Figure 4 A magnified view of a portion of the image;

[0041] Figure 9 For corresponding Figure 3 A partially enlarged schematic diagram of another type of gate line in the array substrate shown;

[0042] Figure 10 For different thicknesses (English: Thickness, unit: ΔV corresponding to PVX2) P A diagram illustrating the relationship between charging rate and charging rate;

[0043] Figure 11 This is a schematic diagram of liquid crystal jitter when the K value is relatively small;

[0044] Figure 12 for Figure 11 A schematic diagram showing the transmittance fluctuations caused by the vibration of liquid crystal molecules.

[0045] Figure 13 This is a schematic diagram of liquid crystal jitter when the K value is relatively large;

[0046] Figure 14 for Figure 13 A schematic diagram showing the transmittance fluctuations caused by the vibration of liquid crystal molecules.

[0047] Figure 15 This is a schematic diagram of the Flicker test points for the present invention and related technologies;

[0048] Figure 16 This is a cross-sectional structural diagram of a display device provided in an embodiment of the present invention;

[0049] Figure 17 This is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "comprising" or "including," and similar terms used in this invention, mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0052] As used in this invention, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0053] As used in this invention, "parallel," "perpendicular," and "equal" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, the difference between the two equals being less than or equal to 10% of either one.

[0054] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0055] This invention describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, for clarity, the thickness of layers and the area of ​​regions are enlarged. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0056] In this invention, circles, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate circles, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other deformations.

[0057] Currently, to reduce power consumption, TFT-LCD display panels are increasingly pursuing low-frequency or wide-frequency displays. For gaming monitors, the screen refresh rate is 144Hz and above. The higher the refresh rate, the more stable and smooth the picture, and the clearer the display effect, but the power consumption is higher, affecting the product's usage time. When the display screen is in standby mode, it automatically switches to a low refresh rate state to reduce power consumption and extend the product's usage time. However, the lower the refresh rate, the more severe the image flickering and jitter, which can easily cause visual fatigue, eye strain, dizziness, and other adverse experiences. The greater the difference between high and low refresh rates, the more severe the flickering is during the switching process, which is more likely to cause a poor user experience.

[0058] This invention provides a liquid crystal display panel, such as... Figure 1 As shown, it includes: an array substrate 1 and an opposing substrate 2 disposed opposite each other, and a liquid crystal layer 3 located between the array substrate 1 and the opposing substrate 2.

[0059] Specifically, such as Figures 2-5 As shown, Figure 2 This is a schematic diagram of a pixel architecture for array substrate 1. Figure 3 for Figure 2 The diagram shows a layout schematic of an array substrate. Figure 4 for Figure 2 The diagram shows another layout of the array substrate. Figure 5 for Figure 4 A cross-sectional schematic diagram along the CC' direction shows that the array substrate 1 includes a first substrate 11 and multiple gate lines (G1, G2, G3...) and multiple data lines (D1, D2, D3...) located on the side of the first substrate 11 facing the opposing substrate 2. The multiple gate lines (G1, G2, G3...) are arranged along the column direction Y, and the multiple data lines (D1, D2, D3...) are arranged along the row direction X.

[0060] Specifically, such as Figures 2-4As shown, multiple gate lines (G1, G2, G3...) and multiple data lines (D1, D2, D3...) intersect and define multiple sub-pixels (e.g., R, G, B). Sub-pixels in the same column have the same color resist, while sub-pixels in the same row have different colors resist (e.g., arranged in RGBRGBRGB...). Each sub-pixel in the same row is electrically connected to at least one gate line. Each data line is electrically connected to a portion of the sub-pixels in each of the two adjacent columns of sub-pixels, and the two adjacent columns of sub-pixels electrically connected by the data line are located on both sides of the data line. Optionally, each row of sub-pixels is electrically connected to a gate line, for example, the first row of sub-pixels is electrically connected to gate line G1, the second row of sub-pixels is electrically connected to gate line G2, the third row of sub-pixels is electrically connected to gate line G3, and so on; a data line is provided on both sides of each column of sub-pixels, and the (2n-1)th and (2n)th rows of sub-pixels in each column are electrically connected to the data lines on both sides of that column of sub-pixels, where n is a positive integer; for example, data lines D1 and D2 are provided on both sides of the first column of sub-pixels, and the (1st, 3rd, 5th...)th rows of sub-pixels in the first column are electrically connected to the data lines on both sides of the column of sub-pixels. Data line D1 is electrically connected, and the sub-pixels in rows 2, 4, 6... are electrically connected to data line D2; for example, data lines D2 and D3 are respectively set on both sides of the second column of sub-pixels, and the sub-pixels in rows 1, 3, 5... of the second column of sub-pixels are electrically connected to data line D2, and the sub-pixels in rows 2, 4, 6... are electrically connected to data line D3; for example, data lines D3 and D4 are respectively set on both sides of the third column of sub-pixels, and the sub-pixels in rows 1, 3, 5... of the third column of sub-pixels are electrically connected to data line D3, and the sub-pixels in rows 2, 4, 6... are electrically connected to data line D4; and so on.

[0061] Specifically, the pixel structure provided in the embodiments of the present invention can be driven using a Z-inversion method. Figure 2 In this driving method, sub-pixels in different rows electrically connected by the same data line have the same polarity, while sub-pixels in the same row connected by adjacent data lines have opposite polarities. This driving method allows positive and negative frames to alternately input signals of opposite polarities in both the row direction (X) and column direction (Y). The human eye will not perceive vertical stripes in the displayed image using this driving method. Therefore, the present invention... Figure 2 The Z-inverted pixel architecture shown can drive the display to avoid vertical stripe problems.

[0062] It should be noted that the pixel structure provided in the embodiments of the present invention is not limited to... Figure 2 The single-gate pixel architecture shown can also be a pixel architecture that uses a dual-gate to achieve Z-inversion, as long as sub-pixels are connected on both sides of the same data line.

[0063] Specifically, such as Figures 2-5As shown, a sub-pixel includes a pixel electrode 12 located on the side of the first substrate 11 facing the opposing substrate 2 and a thin-film transistor T. The gate G of the thin-film transistor T is electrically connected to the corresponding gate lines (G1, G2, G3...). The first electrode 13 of the thin-film transistor T is electrically connected to the corresponding data lines (D1, D2, D3...). The second electrode 14 of the thin-film transistor T includes a first part 141, a second part 142, and a third part 143 arranged along the row direction X and forming an integral structure. The second part 142 is electrically connected to the pixel electrode 12. The first part 141 (e.g., the first part 141 corresponding to the second electrode 14 of the first thin-film transistor T from the left of the first row of sub-pixels P) at least partially overlaps with the orthographic projection of the gate line (e.g., G1) on the first substrate 11. The third part 143 at least partially overlaps with the orthographic projection of the gate G on the first substrate 11.

[0064] Specifically, such as Figure 3 and Figure 4 As shown, since the thin-film transistors T connected to different rows of the same data line (e.g., D2) are located on the left and right sides of the data line D2, under the condition of process fluctuation, there is an alignment deviation between the gate G and the second electrode 14 (e.g., the source S). When the second electrode 14 of the thin-film transistor does not include the first part 141 that overlaps with the orthographic projection of the gate line (e.g., G1), it will cause the Cgs (parasitic capacitance between the gate G and the source S) of the sub-pixels on the left and right sides of the same data line (e.g., D2) to be different, resulting in a flicker problem in the display screen.

[0065] like Figure 6 As shown, Figure 6 The switching voltage (ΔV) corresponding to the pixel grayscale driving voltage of the positive and negative frames. P (Diagram) Flicker = brightness difference between two frames / average brightness of the panel. Flicker is caused by the difference in pixel voltage between positive and negative frames, resulting in alternating brightness levels. There are many reasons for flicker, including the voltage jump (ΔV) generated when pixels are powered on or off. P ) is one of the influencing factors, ΔV P By reducing ΔV, flicker can be improved. P It can be obtained from the following calculation formula:

[0066]

[0067] In this formula, Cgs is the parasitic capacitance between the gate (G) and the source (S), Cst is the storage capacitance, Clc is the liquid crystal capacitance, VGH is the high voltage applied to the gate G, and VGL is the low voltage applied to the gate G.

[0068] The liquid crystal display panel provided in this embodiment of the invention includes a first part on the second electrode of the thin-film transistor. This first part at least partially overlaps with the orthographic projection of the gate line onto the first substrate. This effectively compensates for the parasitic capacitance formed between the gate and the second electrode. In cases of process alignment fluctuations, such as when the film layer containing the gate is shifted to the left under ideal alignment, the overlap capacitance between the third part and the gate of the left thin-film transistor connected to the same data line (e.g., D2) increases, while the overlap capacitance between the first part and the gate decreases. Conversely, the overlap capacitance between the third part and the gate of the right thin-film transistor connected to the same data line D2 decreases, while the overlap capacitance between the first part and the gate increases. This added first part ensures that the Cgs of each sub-pixel on both sides of the same data line are approximately the same, thus the ΔV corresponding to each sub-pixel... P This consistency improves the uniformity of the flicker and avoids flickering issues on the display surface.

[0069] Alternatively, the pixel electrode material may include transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0070] Optionally, the material of the gate line may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate line may be a single-layer structure or a multilayer structure. For example, gate line 103 is a single-layer structure composed of a molybdenum metal layer.

[0071] Optionally, the material of the data cable may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The data cable may be a single-layer structure or a multilayer structure, for example, the data cable may be a multilayer structure composed of titanium metal layer / aluminum metal layer / titanium metal layer.

[0072] In some embodiments, in the liquid crystal display panel provided in the present disclosure, such as Figure 2 and Figure 3 As shown, the first portion 141 and the third portion 143 are both in the shape of a line when projected onto the first substrate 11. In this way, while ensuring the performance of the thin-film transistor T, the first portion 141 and the third portion 143 of the line structure will move towards the side closer to the adjacent gate line in the column direction Y, thereby reducing the area occupied by the thin-film transistor T in the sub-pixel, which can improve the pixel aperture ratio and reduce power consumption.

[0073] In some embodiments, in the liquid crystal display panel provided in the present disclosure, such as Figure 3 and Figure 7 As shown, Figure 7 for Figure 3The enlarged schematic diagram shows that the gate lines (G1, G2, G3...) and the gates G are an integral structure. The gate line G1 between two adjacent gates G (e.g., D2 and D3 are the two gates G corresponding to G1 respectively) along the row direction X includes: a horizontal portion 21, a first inclined portion 22 connecting one of the two gates G (the gate G corresponding to D2) to one end of the horizontal portion 21, and a second inclined portion 23 connecting the other gate G (the gate G corresponding to D3) to the other end of the horizontal portion 21; the angle between the first inclined portion 22 and the horizontal portion 21 is an obtuse angle, and the angle between the second inclined portion 23 and the horizontal portion 21 is an obtuse angle;

[0074] The gate line G1 between two adjacent gates G (e.g., D2 and D3 corresponding to G1 respectively) along the X direction also includes a vertical portion 24 located on the side of the horizontal portion 21 near the thin-film transistor T to which the gate line G1 is electrically connected. The first portion 141 and the orthographic projection of the vertical portion 24 on the first substrate 11 at least partially overlap. That is, in this embodiment of the invention, a vertical portion 24 is added to the horizontal portion 21 of the gate line so that the orthographic projection between the vertical portion 24 and the first portion 141 overlaps. In cases of process alignment fluctuations, such as when the film layer containing the gate G is shifted to the left under ideal alignment conditions, the overlap capacitance between the third part 143 of the left thin-film transistor T and the gate G increases, while the overlap capacitance between the first part 141 and the vertical part 24 decreases. Conversely, the overlap capacitance between the third part 143 of the right thin-film transistor 5 and the gate G decreases, while the overlap capacitance between the first part 141 and the vertical part 24 increases. This increase in the first part 141 and the vertical part 24 ensures that the Cgs of each sub-pixel on both sides of the same data line are approximately the same, thus ensuring that the ΔVP corresponding to each sub-pixel is the same. This improves the uniformity of the flicker and avoids flickering on the display surface.

[0075] In some embodiments, in the liquid crystal display panel provided in the present disclosure, such as Figure 4 and Figure 8 As shown, Figure 8 for Figure 4The enlarged schematic diagram shows that the gate lines (G1, G2, G3...) and the gates G are an integral structure. The gate line G1 between two adjacent gates G (e.g., D2 and D3 are the two gates G corresponding to G1 respectively) along the row direction X includes: an inclined portion 31, a first horizontal portion 32 connecting one of the two adjacent gates G (the gate G corresponding to D2) to one end of the inclined portion 31, and a second horizontal portion 33 connecting the other gate G (the gate G corresponding to D3) to the other end of the inclined portion 31; the angle between the first horizontal portion 32 and the inclined portion 31 is an obtuse angle, and the angle between the inclined portion 31 and the second horizontal portion 33 is an obtuse angle;

[0076] The gate line G1 between two adjacent gates G (e.g., gates G2 and D3 corresponding to G1 respectively) along the row direction X also includes a vertical portion 24 located on the side of the inclined portion 31 near the thin-film transistor T electrically connected to the gate line G1. The first portion 141 and the orthographic projection of the vertical portion 24 on the first substrate 11 at least partially overlap. That is, the embodiment of the present invention adds a vertical portion 24 to the inclined portion 31 of the gate line so that the orthographic projection between the vertical portion 24 and the first portion 141 overlaps. This embodiment can improve the uniformity of flicker and avoid flickering problems on the display surface. Figure 3 The same applies, so I will not go into details here.

[0077] In some embodiments, in the liquid crystal display panel provided in the present disclosure, such as Figure 9 As shown, Figure 9 For corresponding Figure 3 The diagram shows a partially enlarged view of another type of gate line in the array substrate. The gate line (G1, G2, G3...) and the gate G are an integral structure. The gate line G1 between two adjacent gates G (e.g., D2 and D3 are the two gates G corresponding to G1 respectively) along the row direction X includes: a vertical portion 24, a first horizontal portion 32 connecting one of the two adjacent gates G (the gate G corresponding to D2) to one end of the vertical portion 24, and a second horizontal portion 33 connecting the other gate G (the gate G corresponding to D3) to the other end of the vertical portion 24.

[0078] The first portion 141 and the vertical portion 24 at least partially overlap in their orthographic projections on the first substrate 11. That is, in this embodiment of the invention, the area of ​​the gate line adjacent to the first portion 141 is configured as a vertical portion 24, so that the orthographic projections of the vertical portion 24 and the first portion 141 overlap. This embodiment can improve the uniformity of the flicker and avoid flickering problems on the display surface. Figure 3 The same applies, so I will not go into details here.

[0079] In some embodiments, the thin-film transistor can be a P-type transistor or an N-type transistor, and can be a bottom-gate, top-gate, or dual-gate type, etc. This disclosure uses a bottom-gate thin-film transistor as an example. In this invention, the first electrode of the thin-film transistor can be the source and the second electrode can be the drain, or the first electrode can be the drain and the second electrode can be the source; no limitation is made here. The thin-film transistor may also include... Figures 2-5 The active layer Act shown can be made of IGZO, which is an amorphous oxide containing indium, gallium, and zinc. Its carrier mobility is 20-30 times that of amorphous silicon, which can greatly improve the charging and discharging rate of the pixel electrode of the thin film transistor, improve the response speed of the pixel, and achieve a faster refresh rate. At the same time, the faster response also greatly improves the line scanning rate of the pixel.

[0080] In some embodiments, in the liquid crystal display panel provided in the present disclosure, such as Figures 3-5 As shown, the gate lines (G1, G2, G3...) and the gate electrode G are located between the first substrate 11 and the pixel electrode 12, and the data lines (D1, D2, D3...) and the first electrode 13 and the second electrode 14 of the thin film transistor T are located between the gate lines (G1, G2, G3...) and the pixel electrode 12.

[0081] The array substrate also includes: a first passivation layer PVX1 located between the data lines (D1, D2, D3...) and the pixel electrode 12, a planarization layer PLN located between the first passivation layer PVX1 and the pixel electrode 12, a common electrode 15 located between the planarization layer PLB and the pixel electrode 12, and a second passivation layer PVX2 located between the common electrode 15 and the pixel electrode 12.

[0082] The second passivation layer PVX2, the planarization layer PLN, and the first passivation layer PVX1 correspond to the second part 142 and have a first via V1 that sequentially penetrates the second passivation layer PVX2, the planarization layer PLN, and the first passivation layer PVX1. The pixel electrode 12 is electrically connected to the second part 142 through a connection portion 16 located within the first via V1. The ratio of the distance of the first via V1 from two adjacent data lines (e.g., D2 and D3) along the row direction X is 1 to 3. In this way, the first via V1 and the thin-film transistor T are biased to be located at one of the corners of the sub-pixel, making the structure of the array substrate more compact, thereby increasing the light-transmitting area, improving the aperture ratio, increasing the transmittance, and reducing power consumption.

[0083] Specifically, such as Figure 5 As shown, a gate insulating layer (GI) can be disposed between the gate G layer of the thin film transistor T and the active layer Act. The material of the gate insulating layer can be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0084] In some embodiments, the materials of the first passivation layer and the second passivation layer may be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The material of the planarization layer may include at least one of organic insulating materials such as polymethyl methacrylate (also known as acrylic), polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and phenolic epoxy resin, and is not limited herein.

[0085] As mentioned above, ΔV P The formula and Figure 6 It can be seen that ΔV P When the gate G is off, the voltage difference caused by the pixel's storage capacitance Cst and parasitic capacitance Cgs is what needs to be reduced to decrease ΔV. P It can reduce not only Cgs but also ΔV P You can also increase the pixel's storage capacitance Cst to reduce ΔV. P To improve the problem of low-frequency flicker. Therefore, in some embodiments, in the liquid crystal display panel provided in the embodiments of this disclosure, such as Figure 5 As shown, the thickness of the second passivation layer PVX2 can be Specifically, such as Figure 10 As shown, Figure 10 For different thicknesses (English: Thickness, unit: ΔV corresponding to PVX2) P The diagram illustrates the relationship between PVX2 thickness and charging rate, where curve A represents the charging rate for PVX2 with different thicknesses, and curve B represents the ΔV for PVX2 with different thicknesses. P (Unit: V), the dashed line C represents the baseline of charging rate. In related technologies, the thickness of the second passivation layer PVX2 is generally greater than... As can be seen, compared with related technologies, in this invention, as PVX2 is thinned, Cst increases, and ΔV... P The rate decreases linearly, while the charging rate shows a trend of first decreasing slowly and then decreasing rapidly. As shown in Table 1 below, when PVX2 decreases from... At that time, ΔV P From 0.37 to 0.18, the charging rate only decreased by 1.5%, still meeting the product's charging specifications. Furthermore, when PVX2 drops to... At that time, the charging rate did not meet the specification of ≥95%, therefore, embodiments of the present invention require PVX2 to be thinned to... But need This allows for improvements to the flicker while maintaining product charging efficiency.

[0086] Table 1. ΔV corresponding to different thicknesses of PVX2P and charging rate

[0087]

[0088] In some embodiments, in the liquid crystal display panel provided in the present disclosure, such as Figure 4 and Figure 5 As shown, the pixel electrode 12 can be a block electrode, and the pixel electrode 12 includes multiple slits;

[0089] The common electrode 15 can be a planar structure. The common electrode 12 includes a second via V2 corresponding to the first via V1. The connecting part 16 does not contact the inner wall of the second via V2, so as to achieve the insulated arrangement of the pixel electrode 12 and the common electrode 15.

[0090] In some embodiments, in the liquid crystal display panel provided in the present disclosure, such as Figure 1 As shown, liquid crystal layer 3 includes a positive liquid crystal that enables fast response; the elastic constant Kave (K) of the liquid crystal is the average of K11, K22, and K33, and the value of K determines the magnitude of the restoring torque of the liquid crystal after deformation caused by electric field disturbance from equilibrium state. Figures 11-14 As shown, Figure 11 This is a schematic diagram of liquid crystal jitter when the K value is relatively small. Figure 12 for Figure 11 A schematic diagram showing the transmittance fluctuations caused by the vibration of liquid crystal molecules. Figure 13 This is a schematic diagram of liquid crystal jitter when the K value is relatively large. Figure 14 for Figure 13 The diagram shows the transmittance fluctuation caused by the jitter of liquid crystal molecules. It can be seen that when the elastic constant K of the liquid crystal increases, the rigidity of the liquid crystal increases, and the transmittance fluctuation / brightness difference caused by the jitter of liquid crystal molecules during the switching between positive and negative frames decreases, thereby improving the flicker.

[0091] The formula for calculating contrast ratio (CR) is as follows:

[0092]

[0093] Among them, S cell Δn is the liquid crystal scattering coefficient, Δn is the refractive index of the liquid crystal layer, and n is the refractive index of the liquid crystal layer. O n is the refractive index of ordinary light for a positive liquid crystal. e d is the refractive index of the non-normal light of the negative liquid crystal, and d is the thickness of the liquid crystal layer (i.e., cell thickness).

[0094] As the value of K increases, the liquid crystal scattering coefficient (S) cell As the K value decreases, the contrast ratio (CR) increases, and as the K value increases, the rotational viscosity coefficient γ1 of the liquid crystal also increases.

[0095] The formula for the response time of a liquid crystal display panel is as follows:

[0096] Descent time:

[0097] Ascent time:

[0098] Where γ1 is the rotational viscosity coefficient of the liquid crystal, K is the elastic constant of the liquid crystal, d is the thickness of the liquid crystal layer (i.e., the cell thickness of the liquid crystal display panel), ε0 is the vacuum dielectric constant, and Δε = (ε ∥ -ε ⊥ ), horizontal dielectric constant ε ∥ The dielectric constant is ε along the direction parallel to the long axis of the positive liquid crystal, and the perpendicular dielectric constant is ε. ⊥ V is the dielectric constant along the direction perpendicular to the long axis of the positive liquid crystal, and V is the driving voltage applied to the liquid crystal layer. th This is the threshold voltage of the liquid crystal.

[0099] As can be seen, the response time is directly proportional to γ1; therefore, as γ1 increases, the response time slows down. For high refresh rate products, the higher the refresh rate, the faster the required response time.

[0100] The formula for the driving voltage (V) is as follows:

[0101]

[0102] Therefore, the present invention can increase the driving voltage V of the liquid crystal layer by reducing the dielectric constant Δε of the liquid crystal and increasing the K value, and reduce the thickness d of the liquid crystal layer (according to the theory of continuous liquid crystal elastomer, the distance between the first liquid crystal layer near the pixel electrode and the last liquid crystal layer far from the pixel electrode is reduced, so the time required for the first liquid crystal layer to start rotating under voltage drive to be transferred to the last liquid crystal layer is reduced, and the response time is reduced), so that the liquid crystal display panel can improve flicker and increase CR while maintaining the original response time.

[0103] Optionally, the liquid crystal elastic constant K of the positive liquid crystal provided in the embodiments of the present invention is ≥11.2, and Δε=(ε ∥ -ε ⊥ The liquid crystal layer thickness (i.e., cell thickness) d < 2.8 μm is less than 4.1. Compared with the positive liquid crystal with K = 11.2 and Δε = 4.1 and the liquid crystal layer with d = 2.8 μm used in related technologies, the liquid crystal display panel provided by the present invention can maintain the original level while improving flicker and CR.

[0104] As shown in Tables 2 and 3 below, LC1 represents the liquid crystal provided in the related art, and LC2 represents the liquid crystal provided in the embodiments of the present invention. The value of the liquid crystal elastic constant K changes from 11.2 in the related art to 13.8 in the present invention, the thickness of the liquid crystal layer changes from 2.8 μm in the related art to 2.6 μm in the present invention, and the dielectric constant Δε of the liquid crystal changes from 4.1 in the related art to 3 in the present invention. It can be concluded that the liquid crystal scattering coefficient S cell The driving voltage V changes from 0.033 in the related technology to 0.026 in this invention, and from 5.7V in the related technology to 6.7V in this invention. The contrast ratio CR of this invention can be improved by 19% compared with the related technology, while the response time GTG remains unchanged. When the cell gap of the liquid crystal display panel is reduced, the transmittance Tr of the liquid crystal display panel only decreases by 2%, which does not affect the performance of the liquid crystal display panel.

[0105] Table 2 Parameters of different LCs

[0106] Item LC1 LC2 Δn 0.1168 0.1189 Δε 4.1 3 Kave(pN) 11.2 13.8 γ1(mPa·s) 44 60

[0107] Table 3 Optical performance of different LCs

[0108] Item LC1 LC2 CellGap (μm) 2.8 2.6 V(V) 5.7 6.7 <![CDATA[S cell ]]> 0.033 0.026 CR 100％ 119％ GTG 100％ 100％ Tr 100％ 98％

[0109] In some embodiments, in the liquid crystal display panel provided in the present disclosure, such as Figure 1 As shown, a first alignment layer 4 is disposed on the side of the array substrate 1 facing the liquid crystal layer 3, and a second alignment layer 5 is disposed on the side of the opposing substrate 2 facing the liquid crystal layer 3. The impedance values ​​of the materials of the first alignment layer 4 and the second alignment layer 5 are both ≥1×10⁻⁶. 15 Ω. Specifically, the impedance value of the material used in the alignment layer of the relevant technology is generally 10 Ω. 15 Ω, the impedance value of the alignment layer of the present invention is 100 times that of the related technology. When using an alignment layer with a high impedance value, the charge (+) accumulation rate on the material surface is slower. Before the voltage switch of the next frame, the high impedance alignment layer accumulates less charge than the low impedance alignment layer, resulting in a smaller voltage difference change. Therefore, the voltage change on the liquid crystal capacitor is smaller, which can reduce the brightness change caused by liquid crystal jitter and thus improve the flicker problem.

[0110] In some embodiments, such as Figure 4 and Figure 8As shown, the length X1 of the first via V1 in the row direction X satisfies: 10μm ≥ X1 ≥ 5μm, and the length X2 of the first via V1 in the column direction Y satisfies: 12μm ≥ X2 ≥ 5μm. Therefore, the minimum size of the first via V1 in actual use is when X1 is 5μm and X2 is 5μm. By reducing the size of the first via V1, the area of ​​the sub-pixel occupied by the first via V1 is reduced, increasing the proportion of the sub-pixel area used for display, thereby improving the aperture ratio.

[0111] In some embodiments, such as Figure 4 and Figure 8 As shown, the width-to-length ratio (W / L) of the T-channel in a thin-film transistor can be 3.5 / 5. Since the effective channel of the thin-film transistor T is trapezoidal based on the orthogonal projection of the substrate 11, the effective length of W is the length of the median line of the trapezoid in the column direction Y. When W is 3.5 μm, the effective length of the median line of the trapezoid is approximately 5.4 μm. By increasing the ratio of the length of the channel in the column direction Y to the length of the channel in the row direction X, the width-to-length ratio of the channel is increased, thereby improving the aperture ratio of the sub-pixel.

[0112] In some embodiments, such as Figure 3 , Figure 4 , Figures 7-9 As shown, the side of the gate G near the second electrode 14 is recessed towards the first electrode 13 relative to the side of the active layer Act near the second electrode 14, so that the orthogonal projection of the active layer Act on the substrate 11 exists outside the orthogonal projection of the gate G on the substrate 11. This reduces the overlap area between the gate G and the second electrode 14, reduces the parasitic capacitance Cgs between the gate G and the second electrode 14 (e.g., the source S), thereby reducing ΔVP and improving flicker.

[0113] In some embodiments, such as Figure 4 and Figure 8 As shown, the distance W1 between the adjacent sides of the active layer Act and the gate G in the column direction Y can be 3μm. This reduces the overlap area between the gate G and the data line, thereby reducing the load on the data line and thus reducing the logic power consumption.

[0114] In some embodiments, such as Figure 3 , Figure 4 and Figure 8 As shown, the width W3 of the data line crossing region above the gate G can be 3.75 μm, and the width W2 of the data line excluding the crossing region can be 3.5 μm. This results in a smaller overlap area between the gate G and the data line, reducing the load on the data line, decreasing Cdc coupling, reducing Vcom delay, and thus reducing logic power consumption. The reason W3 is wider than W2 is that the data line is prone to breakage at the crossing position above the gate, hence W3 is increased to 3.75 μm.

[0115] In some embodiments, such as Figure 3 , Figure 4 and Figure 8 As shown, the minimum distance W4 between the gate line G1 and the adjacent side of the second part 142 in the column direction Y can be 3.5μm, and the minimum distance W5 between the gate G and the adjacent side of the second part 142 in the row direction X can be 3.5μm. In this way, the distances between the gate G, the gate line G1 and the second part 142 are relatively large, which can reduce the lateral parasitic capacitance Cgs, further reduce ΔVP and improve the flicker problem.

[0116] In some embodiments, such as Figure 1 , Figure 4 and Figure 9 As shown, the opposing substrate 2 includes: a second substrate 21, and a black matrix BM and a color resist layer 22 located on the side of the second substrate 21 facing the array substrate 1; the black matrix BM includes a plurality of pixel openings, and the color resist layer 22 includes color resists located in each pixel opening. The color resists may include red color resist (R), green color resist (G) and blue color resist (B). The orthographic projection of each color resist on the second substrate 21 covers the orthographic projection of the corresponding pixel opening on the second substrate 21.

[0117] In some embodiments, such as Figure 4 As shown, the black matrix material used in related technologies may result in insufficient exposure or partial development loss. However, the present invention uses a black matrix material that can improve sensitivity and linearity, enabling the minimum width d1 of the black matrix BM covering the data line area to be 4μm. In addition, by adjusting the structure and position of the thin-film transistor T and reducing the size of the first via V1, the present invention can achieve a minimum width d2 of 8.5μm for the black matrix BM covering the gate line area. The inventors of this case have found through testing that the pixel aperture ratio of the liquid crystal display panel provided by the embodiments of the present invention can be increased to 78.4%. Compared with the solutions in related technologies, the transmittance of the present invention can be improved by 10%, providing a basis for achieving ultra-low backlight power consumption and enhancing the competitiveness of the product.

[0118] In some embodiments, in the liquid crystal display panel provided in the present disclosure, such as Figure 1 As shown, the opposing substrate 2 also includes an organic layer (OC) 23 located between the black matrix BM, the color resist layer 22 and the second alignment layer 5, and the organic layer 23 serves to planarize the substrate.

[0119] In some embodiments, in the liquid crystal display panel provided in the present disclosure, such as Figure 1 As shown, it also includes an encapsulating adhesive layer 6 located between the first alignment layer 4 and the second alignment layer 5 for sealing the liquid crystal layer 3.

[0120] As shown in Table 4 below, Table 4 presents the flick test data for the liquid crystal display panel provided by the related technology. The structure of the liquid crystal display panel provided by the related technology is as follows: the second electrode 14 of the thin film transistor T does not include the first part 141, the gate line does not include the vertical part 24, the thickness of the second passivation layer PVX2 is 3000 angstroms, and the impedance value of the materials of the first alignment layer and the second alignment layer is 10. 13 Ω, and LC1 corresponding to Tables 2 and 3; the test refresh rate includes static 10Hz, dynamic ZigzagSweep / Square Wave Sweep / Sine Wave Sweep / Random Frame Rate (refresh rate switches from 10 to 240Hz according to sawtooth waveform / square waveform / sine waveform / random waveform input), and the test points are as follows. Figure 15 As shown, 10 refers to 1 / 10 of the total length or width of the display area on the display panel, and H / 4 or W / 4 refers to 1 / 4 of the total length or width of the display area on the display panel. Each point was tested statically 5 times and dynamically 10 times (with a 2-second interval between each test). The average of the test results for each point was taken, and the judgment criterion was that the flicker values ​​at all 13 points must be ≤-60dB. Table 4 shows that the flicker results under both dynamic square waveforms and random waveforms do not meet the specifications.

[0121] Table 4. Flicker data for LCD panels of related technologies within the 10–240Hz range.

[0122]

[0123] As shown in Table 5, Table 5 presents the flicker test data for the liquid crystal display panel provided by the present invention. The liquid crystal display panel provided by the present invention is as follows: Figure 4 In the structure shown, the thickness of the second passivation layer PVX2 is 1500 angstroms, and the impedance values ​​of the materials of the first and second alignment layers are both 10. 15 Ω corresponds to LC2 in Tables 2 and 3; as can be seen from Table 5, the Flicker results of the present invention under both static and dynamic conditions meet the specification of ≤-60dB.

[0124] Table 5. Flicker data for the liquid crystal display panel provided by this invention within the 10-240Hz range.

[0125]

[0126] As shown in Table 6 below, the flicker of the liquid crystal display panel provided by the present invention (Table 5) can be improved by more than 5dB compared with the square waveform / random waveform that meets the specifications in the related technology (Table 4). Compared with the square waveform / random waveform that does not meet the specifications in the related technology, the flicker of the liquid crystal display panel provided by the present invention is improved by more than 11dB. The present invention significantly improves the flicker problem and is suitable for liquid crystal display panels with high and low frequency switching.

[0127] Table 6 Comparison of the average Flicker values ​​of the present invention and related technologies within the 10–240Hz range.

[0128] Item Min(10Hz) Zigzag Squarewave Sinewave Random Related technologies -61.43 -69.64 -54.72 -63.75 -55.52 This invention -67.07 -76.52 -66.28 -71.52 -66.78 Difference 5.63 6.88 11.56 7.78 11.26

[0129] In summary, the liquid crystal display panel provided by this embodiment of the invention, when high refresh rate products switch between high and low frequencies, not only extends the product's usage time, but also increases the pixel aperture ratio, reduces the product's backlight power consumption, improves the low-frequency flicker problem, and enhances the product's image quality.

[0130] In some embodiments of the present invention, the liquid crystal display panel provided above may also include other structures known to those skilled in the art.

[0131] Based on the same inventive concept, this disclosure also provides a display device, such as... Figure 16 As shown, it includes: the liquid crystal display panel provided in the embodiments of this disclosure, and a backlight module 100 located on the light-incident side of the array substrate 1. Since the principle by which this display device solves the problem is similar to that of the display panel described above, the implementation of the display device provided in the embodiments of this disclosure can refer to the implementation of the display panel described above, and repeated details will not be described again.

[0132] In some embodiments, in the display device provided in this disclosure, the backlight module 100 can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).

[0133] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0134] In specific implementation, the display device provided in the embodiments of this disclosure is a liquid crystal display device. The liquid crystal display device also includes other necessary components and parts, such as a housing, a main circuit board, a power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here and should not be regarded as a limitation of this disclosure.

[0135] In specific implementation, the display device provided in the embodiments of this disclosure may be a full-screen display device or a flexible display device, etc., and is not limited thereto.

[0136] In specific implementation, the display device provided in the embodiments of this disclosure can be as follows: Figure 17 The image shows a full-screen mobile phone. Of course, the display device provided in this embodiment can also be any product or component with display function, such as an in-vehicle display, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure. This display device includes, but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in this embodiment. In other words, the display device provided in this embodiment may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0137] The liquid crystal display panel and display device provided in this embodiment of the invention include a first part on the second electrode of the thin-film transistor. This first part at least partially overlaps with the orthographic projection of the gate line onto the first substrate. This effectively compensates for the parasitic capacitance formed between the gate and the second electrode. In cases of process alignment fluctuations, such as when the film layer containing the gate is shifted to the left under ideal alignment, the overlap capacitance between the third part and the gate of the left-hand thin-film transistor connected to the same data line increases, while the overlap capacitance between the first part and the gate decreases. Conversely, the overlap capacitance between the third part and the gate of the right-hand thin-film transistor connected to the same data line decreases, while the overlap capacitance between the first part and the gate increases. This added first part ensures that the Cgs of each sub-pixel on both sides of the same data line are approximately the same, thus the ΔV corresponding to each sub-pixel is... P This consistency improves the uniformity of the flicker and avoids flickering issues on the display surface.

[0138] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0139] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A liquid crystal display panel, characterized in that, The display panel comprises: opposite substrates and a liquid crystal layer between the array substrate and the opposite substrate; wherein the array substrate comprises a first substrate and a plurality of gate lines and a plurality of data lines on the side of the first substrate facing the opposite substrate, the plurality of gate lines arranged along the column direction, and the plurality of data lines arranged along the row direction; the plurality of gate lines and the plurality of data lines insulate and cross to define a plurality of sub-pixels, each of the sub-pixels in the same row is electrically connected to at least one of the gate lines, each of the data lines is electrically connected to part of the sub-pixels in each column of the adjacent two columns of the sub-pixels, and the adjacent two columns of the sub-pixels electrically connected by the data line are located on both sides of the data line; the sub-pixel comprises a pixel electrode and a thin film transistor on the side of the first substrate facing the opposite substrate, the gate of the thin film transistor is electrically connected to the gate line, the first electrode of the thin film transistor is electrically connected to the data line, and the second electrode of the thin film transistor comprises a first part, a second part and a third part arranged along the row direction and in an integrated structure, the second part is electrically connected to the pixel electrode, the first part at least partially overlaps the orthographic projection of the gate line on the first substrate, and the third part at least partially overlaps the orthographic projection of the gate on the first substrate.

2. The liquid crystal display panel according to claim 1, wherein each of the sub-pixels in the same row is electrically connected to one of the gate lines; each of the data lines is arranged on both sides of each column of the sub-pixels, and the 2n-1th row of sub-pixels and the 2nth row of sub-pixels in each column of the sub-pixels are electrically connected to the data lines on both sides of the column of the sub-pixels, wherein n is a positive integer.

3. The liquid crystal display panel according to claim 2, wherein the orthographic projection of the first part and the third part on the first substrate is in a linear shape.

4. The liquid crystal display panel according to claim 3, wherein the gate line and the gate are in an integrated structure, and the gate line between the adjacent two gates along the row direction comprises a horizontal part, a first inclined part connecting one of the two gates and one end of the horizontal part, and a second inclined part connecting the other of the two gates and the other end of the horizontal part; the included angle between the first inclined part and the horizontal part is obtuse, and the included angle between the second inclined part and the horizontal part is obtuse; the gate line between the adjacent two gates along the row direction further comprises a vertical part on the side of the horizontal part close to the thin film transistor electrically connected to the gate line, and the orthographic projection of the first part and the vertical part on the first substrate at least partially overlaps.

5. The liquid crystal display panel according to claim 3, wherein the gate line and the gate are in an integrated structure, and the gate line between the adjacent two gates along the row direction comprises an inclined part, a first horizontal part connecting one of the two gates and one end of the inclined part, and a second horizontal part connecting the other of the two gates and the other end of the inclined part; the included angle between the first horizontal part and the inclined part is obtuse, and the included angle between the inclined part and the second horizontal part is obtuse; The gate line between the two adjacent gate electrodes in the row direction further comprises a vertical portion located on the side of the thin film transistor close to the gate line electrically connected to the inclined portion, and the first portion and the vertical portion at least partially overlap in the orthographic projection on the first substrate.

6. The liquid crystal display panel according to claim 3, wherein The gate line and the gate electrode are integrated structures, and the gate line between the two adjacent gate electrodes in the row direction comprises a vertical portion, a first horizontal portion connecting one of the two adjacent gate electrodes and one end of the vertical portion, and a second horizontal portion connecting the other of the two adjacent gate electrodes and the other end of the vertical portion. The first portion and the vertical portion at least partially overlap in the orthographic projection on the first substrate.

7. The liquid crystal display panel according to any one of claims 1 to 6, wherein The gate line is located between the first substrate and the pixel electrode, and the data line is located between the gate line and the pixel electrode. The array substrate further comprises a first passivation layer located between the data line and the pixel electrode, a planarization layer located between the first passivation layer and the pixel electrode, a common electrode located between the planarization layer and the pixel electrode, and a second passivation layer located between the common electrode and the pixel electrode. The second passivation layer, the planarization layer and the first passivation layer correspond to the second portion and have a first via hole penetrating through the second passivation layer, the planarization layer and the first passivation layer in sequence, the pixel electrode is electrically connected to the second portion through a connecting portion located in the first via hole, and the distance between the first via hole and the adjacent two data lines in the row direction is 1-3 times the distance between the two data lines.

8. The liquid crystal display panel according to claim 7, wherein The thickness of the second passivation layer is 9. The liquid crystal display panel according to claim 7, wherein The pixel electrode is a block electrode, and the pixel electrode comprises a plurality of slits. The common electrode is a planar structure, the common electrode comprises a second via hole corresponding to the first via hole, and the connecting portion does not contact the inner wall of the second via hole.

10. The liquid crystal display panel according to any one of claims 1 to 6, 8 and 9, wherein, The liquid crystal layer comprises positive liquid crystal, and the liquid crystal elastic constant K of the positive liquid crystal is greater than or equal to 11.

2.

11. The liquid crystal display panel according to claim 10, wherein A dielectric constant in a direction parallel to the positive liquid crystal long axis is a horizontal dielectric constant ε ∥ A dielectric constant in a direction perpendicular to the positive liquid crystal long axis is a vertical dielectric constant ε ⊥ Δε = (ε ∥ - ε ⊥ ) < 4.

1.

12. The liquid crystal display panel according to claim 11, wherein The thickness d of the liquid crystal layer is less than 2.8 μm.

13. The liquid crystal display panel according to any one of claims 1 to 6, 8, 9, 11 and 12, wherein The array substrate side facing the liquid crystal layer is provided with a first alignment layer, and the opposite substrate side facing the liquid crystal layer is provided with a second alignment layer, the impedance value of the material of the first alignment layer and the second alignment layer is all ≥ 1 x 10 15 Ω.

14. The liquid crystal display panel according to any one of claims 1 to 6, 8, 9, 11 and 12, wherein The opposite substrate comprises a second substrate, a black matrix and a color resistance layer located on the side of the second substrate facing the array substrate, the black matrix comprises a plurality of pixel openings, and the color resistance layer comprises color resistance located in each pixel opening. The minimum width of the black matrix covering the data line region is 4 μm, and the minimum width of the black matrix covering the gate line region is 8.5 μm.

15. A display device comprising: The liquid crystal display panel comprises: The liquid crystal display panel comprises: The liquid crystal display panel comprises:

Images