Integrated TRX Switch

Abstract

The present disclosure relates to an integrated TRX switch. The integrated TRX switch includes a transceiver circuit, a series capacitor, and a shunt switch. The transceiver circuit may include a transmit chain and a receive chain. The transmit chain includes an output matching network, and the receive chain includes an input matching network. The output of the output matching network may be directly connected to the input / output of the transceiver circuit. The series capacitor may be connected between the input of the input matching network and the output of the output matching network. The shunt switch may be connected between the input of the input matching network and the circuit ground potential of the transceiver circuit.

Description

Technical Field

[0001] The present invention generally relates to transceiver circuits, and more particularly, to methods and / or apparatuses for implementing an integrated transmit-receive (TRX) switch. Background Art

[0002] The implementation of a conventional high isolation transmit-receive (TRX) switch increases chip area and increases: (i) losses at the output of the transmit chain (i.e., return loss, insertion loss, or power loss); and (ii) losses at the input of the receive chain (i.e., noise figure, additional loss, and noise). Conventional high isolation TRX switches require active technologies capable of withstanding high voltages, which will limit the linearity of the transmit chain.

[0003] There is a desire to implement an integrated transmit-receive (TRX) switch without degrading the performance of the transmit and receive chains. Summary of the Invention

[0004] The present invention relates to an apparatus including a transceiver circuit, a series capacitor, and a parallel switch. The transceiver circuit may include a transmit chain and a receive chain, the transmit chain including an output matching network and the receive chain including an input matching network. The output of the output matching network may be directly connected to the input / output of the transceiver circuit. The series capacitor may be connected between the input of the input matching network and the output of the output matching network. The parallel switch may be connected between the input of the input matching network and the circuit ground potential of the transceiver circuit. Brief Description of the Drawings

[0005] Embodiments of the present invention will become apparent from the following detailed description, along with the appended claims and drawings,

[0006] wherein:

[0007] Figure 1 is a transceiver circuit diagram illustrating an example context of the present invention.

[0008] Figure 2 is a phased array antenna system diagram illustrating another example context of the present invention.

[0009] Figure 3 is a diagram illustrating an example implementation of a single polarization phased array antenna panel according to an example embodiment of the present invention.

[0010] Figure 4 is a diagram illustrating an example implementation of a dual polarization phased array antenna panel according to an example embodiment of the present invention.

[0011] Figure 5 is a single polarization beamformer circuit diagram according to an example embodiment of the present invention.

[0012] Figure 6 is a circuit diagram of a dual-polarization beamformer according to an exemplary embodiment of the present invention.

[0013] Figure 7 is an illustration Figure 5 and Figure 6 is a block diagram of an exemplary implementation of a transceiver circuit in

[0014] Figure 8 is a diagram illustrating an exemplary implementation of a transmit-receive (TRX) switch topology according to a differential embodiment.

[0015] Figure 9 is a diagram illustrating another exemplary implementation of a TRX switch topology according to a single-ended embodiment.

[0016] Figure 10 is a diagram illustrating yet another exemplary implementation of a TRX switch topology according to a single-ended embodiment.

[0017] Figure 11 is a diagram illustrating yet another exemplary implementation of a TRX switch topology according to a differential embodiment.

[0018] Figure 12 is an illustration Figure 11 of an analog voltage waveform of the TRX switch topology in DETAILED DESCRIPTION

[0019] Embodiments of the present invention include providing an integrated transmit-receive (TRX) switch that can: (i) combine the output and input impedance matching networks of a transceiver circuit with additional series and shunt capacitors to achieve a high isolation switch; (ii) be used in differential applications; (iii) be used in single-ended applications; (iv) eliminate the need for high breakdown voltage devices in the TRX switch; (v) be suitable for implementation in advanced low voltage sub-micron transistor technologies; (vi) be incorporated into the impedance matching elements of a power amplifier and / or a low noise amplifier; (vii) reduce chip area; (viii) be used in transformer-based transmitter and receiver implementations; (ix) be suitable for implementation in short-channel bulk or silicon-on-insulator (SOI) CMOS technologies with low breakdown voltages; (x) provide high isolation between the transmit (TX) and receive (RX) circuits; (xi) be designed independently of the TX and RX circuits; (xii) be incorporated into the corresponding impedance matching network at any stage of development without co-design or co-optimization; and / or (xiii) be applicable to any transceiver that must operate in transmit and receive modes at different times and requires isolation between the two.

[0020] Reference Figure 1, which shows a block diagram of circuit 10, illustrates an exemplary context in which a transmit-receive (TRX) switch according to an example embodiment of the present invention can be implemented. In an example embodiment, circuit 10 can implement a transceiver circuit. A transceiver is generally capable of transmitting and receiving signals over a communication channel. In various embodiments, circuit 10 can be capable of transmitting and receiving radio frequency (RF), microwave, and / or millimeter wave signals. In various embodiments, circuit 10 can represent transceiver circuits utilized in applications including but not limited to: cellular base stations (e.g., 2G, 3G, 4G, 5G, etc.), wireless communication systems, wireless local area networks (WLANs), wireless backhaul channels, broadband repeaters, community antenna television (CATV) networks, macrocells, microcells, picocells, femtocells, mobile devices (MDs), and / or portable handheld devices (UEs). In some embodiments, circuit 10 can represent radar applications, which include but are not limited to target detection, ranging, and / or through-wall imaging.

[0021] In an example, transceiver circuit 10 generally includes a transmit chain and a receive chain. Both the transmit chain and the receive chain can include radio frequency (RF) amplifiers. In an example, the transmit chain can include an input amplifier 12, a variable phase shifter 14, a variable attenuator 16, and one or more output amplifier stages 18. In an example, input amplifier 12 can be implemented as a low noise amplifier (LMA). Output amplifier stage 18 can include a driver, a preamplifier, and / or a power amplifier. In an example, the receive chain can include an input amplifier 20, a variable phase shifter 22, and a variable attenuator 24. Input amplifier 20 can be implemented as a low noise amplifier (LNA). In an example, the output of the transmit chain and the input of the receive chain can be coupled to a transmission line or an antenna through an integrated transmit-receive (TRX) switch 100 implemented according to an embodiment of the present invention. In various embodiments, integrated TRX switch 100 can combine the output and input impedance matching networks of the transceiver circuit with additional series and parallel capacitors to achieve a high isolation switch. The topology of integrated TRX switch 100 can be applied to differential and single-ended applications. Integrated TRX switch 100 generally eliminates the need for high breakdown devices in high isolation TRX switches. Integrated TRX switch 100 is generally applicable to any transceiver that must operate in transmit and receive modes at different times and requires isolation between the two.

[0022] Reference Figure 2, shows a block diagram of system 80, which illustrates another example context of the present invention. System (or module or circuit or device) 80 may implement a radio frequency (RF) transceiver system according to an example embodiment of the present invention. The RF transceiver system 80 may be configured to operate at common radio frequencies, millimeter wave frequencies, and / or microwave frequencies. In an example, the RF transceiver system 80 may be configured to facilitate communication with and / or among multiple communication devices (or terminals) 90a - 90n. In an example, the communication devices 90a - 90n may include, but are not limited to: cellular phones, mobile devices, tablets, Internet of Things (IoT) devices, etc. In various embodiments, the RF transceiver system 80 and the communication devices 90a - 90n may be coupled using at least one phased array antenna panel 92. The phased array antenna panel 92 may include a plurality of antenna elements and a plurality of beamformer circuits (or chips), which will be described below in conjunction with Figures 3 to 7 According to an example embodiment of the present invention, the beamformer circuit may include an integrated transmit - receive (TRX) switch 100.

[0023] In an example, the RF transceiver system 80 may form part of a communication link. In some embodiments, the communication link may be part of a fifth - generation (5G) wireless communication system (e.g., the Next Generation Mobile Networks (NGMN) Alliance is currently developing standards for it). In other embodiments, the communication link may be part of a system that includes, but is not limited to: a fourth - generation (4G) wireless communication system (e.g., the International Mobile Telecommunications - Advanced (IMT - A) standard issued by the International Telecommunication Union Radiocommunication Sector (ITU - R)), a satellite communication (SATCOM) system, and a point - to - point communication system such as a Common Data Link (CDL). However, other communication standards may also be implemented to meet the design criteria of specific applications.

[0024] In an example, the RF transceiver system 80 may include block (or circuit) 82, block (or circuit) 84, block (or circuit) 86, and block (or circuit) 88. In various embodiments, blocks 82 - 88 may be implemented using hardware, a combination of hardware and software, and / or simulated using software. Signals (e.g., IF) may be exchanged between circuit 82 and circuit 84. The signal IF may implement an intermediate frequency signal. In an example, the signal IF may be configured to (e.g., using various modulation schemes) carry information to be transmitted from and / or received by the RF transceiver system 80. In an example, a signal (e.g., LO) may be presented to circuit 84. The signal LO may implement a local oscillator signal. Signals (e.g., RF) may be exchanged between circuit 84 and the phased array antenna panel 92. The signal RF may be a radio frequency, millimeter wave frequency, or microwave frequency signal that conveys the same information that would be found in the intermediate frequency signal IF.

[0025] In the transmit mode, the radio frequency signal RF can convey information to be broadcast from the phased array antenna panel 92 to the devices 90a - 90n. In the receive mode, the radio frequency signal RF can convey information received from the devices 90a - 90n via the phased array antenna panel 92. Signals (e.g., FSW) and one or more signals (e.g., CTRL) can be exchanged between the circuit 86 and the phased array antenna panel 92. The signal FSW can switch the phased array antenna panel 92 between the transmit mode and the receive mode. The signal CTRL can convey data, timing, and control elements. In an example, the signals FSW and CTRL can be part of a digital interface of the phased array antenna panel 92. In an example, the signal CTRL can be implemented as a serial link that conveys information for configuring and / or determining phase and / or gain settings for the antenna elements of the phased array antenna panel 92. In an example, the signal(s) CTRL can conform to one or more serial communication protocols or interfaces (e.g., Serial Peripheral Interface (SPI), Inter - Integrated Circuit Communication (I2C), daisy chain, etc.). One or more signals (e.g., PG) can be transmitted from the circuit 88 to the circuit 86. In an example, the signal(s) PG can convey phase information and gain information using the phased array antenna panel 92, and the phase information and gain information are used by the circuit 86 to implement (control) beam steering. In an example, the signal PG can convey multiple phase and gain values, and the phase and gain values can be programmed into multiple beamformer circuits of the phased array antenna panel 92 via the signal(s) CTRL.

[0026] The phased array antenna panel 92 typically implements a hard - wired address scheme. The hard - wired address scheme can be used to uniquely identify serial communications of elements (e.g., beamformer circuits) intended to be used for the phased array antenna panel 92. In various embodiments, multiple phased array antenna panels 92 can be combined to form a larger antenna array, thereby providing more transmission channels. Multiple phased array antenna panels 92 can share a serial communication channel, link, or bus. Each phased array antenna panel 92 that makes up the larger antenna array can be uniquely addressed using a corresponding hard - wired address.

[0027] The phased array antenna panel 92 can generate one or more fields (or beams) 102a - 102n. The fields 102a - 102n can represent a field pattern (or radio frequency beam pattern) created by the beamformer circuit of the phased array antenna panel 92 based on the phase and gain information (values) received via the signal(s) CTRL. The phased array antenna panel 92 can be configured to generate the directional beams 102a - 102n for communication with the communication devices 90a - 90n. In an example, the beamformer circuit of the phased array antenna panel 92 can be controlled to control the beams 102a - 102n based on the phase and gain information received via the signal(s) CTRL to track the movement of the communication devices 90a - 90n and / or switch between the communication devices 90a - 90n.

[0028] The circuit 82 can implement a baseband processor circuit. The circuit 82 can be operable to process information transmitted by and / or received in the intermediate frequency signal IF. The circuit 82 can process information within the RF transceiver system 80. Such processing can include but is not limited to: modulating / demodulating signals containing information and managing simultaneous communications between the RF transceiver system 80 and the multiple remote terminals 90a - 90n.

[0029] The circuit 84 can implement one or more mixer circuits. The circuit 84 is generally operable to perform frequency conversion (e.g., up - conversion, down - conversion, etc.) between the intermediate frequency used for the signal IF and the radio frequency, millimeter - wave frequency, or microwave frequency used for the signal RF. The frequency conversion can be based on one or more local oscillator frequencies provided by the signal LO. In various embodiments, the radio frequency signal RF can be in a frequency range centered around a center frequency of approximately 28 gigahertz (GHz) or 39 GHz (e.g., 24 GHz to 30 GHz or 37 GHz to 44 GHz). In embodiments implementing multiple intermediate frequencies, each intermediate frequency can cover a frequency band from approximately 2 GHz to approximately 6 GHz (e.g., approximately 4 GHz bandwidth). In an example, when the signal RF is centered around approximately 28 GHz, the range of each local oscillator frequency can be from approximately 22 GHz to 26 GHz. In another example, when the signal RF is centered around approximately 39 GHz, the range of each local oscillator frequency can be from approximately 33 GHz to 37 GHz. However, other frequency ranges can also be implemented to meet the design criteria of specific applications.

[0030] Circuit 86 may implement a control circuit. In various embodiments, one or more of the following may be used to implement circuit 86: an application specific integrated circuit (ASIC), a controller, a microprocessor, or a correspondingly configured circuitry. Circuit 86 is generally operable to control the operation of the phased array antenna panel 92. In some embodiments, circuit 86 may determine the set values used in each transceiver channel within the beamformer circuitry of the phased array antenna panel 92. The set values may establish the geometry of the field(s) or beam(s) 102a - 102n. In various embodiments, circuit 86 may be implemented as one or more integrated circuits.

[0031] In an example, circuit 88 may implement a value table (e.g., included in a memory circuit). In an example, the value table included in circuit 88 may be configured to store multiple gain (G) values and multiple phase (P) values. The phase values and the gain values may be used by the transceiver channels in the beamformer circuitry of the phased array antenna panel 92 to establish the field 102a - 102b. The phase values and the gain values may be obtained from circuit 88 via signal PG and programmed into a buffer associated with the beamformer circuitry of the phased array antenna panel 92 by circuit 86. In various embodiments, circuits 86 and 88 may be implemented on the same integrated circuit or on different (separate) integrated circuits.

[0032] In an example, the phased array antenna panel 92 may be implemented to include single - polarized (or monopole) antenna elements or dual - polarized (or dipole or bipolar) antenna elements. The phased array antenna panel 92 may be operable to transmit wireless signals to and receive wireless signals from devices (or terminals) 90a - 90n. The devices (or terminals) 90a - 90n may be located at positions remote from the RF transceiver system 80. The sensitivity to the wireless signals may be determined by the fields 102a - 102n created by the phased array antenna panel 92. The phased array antenna panel 92 may include multiple antenna elements and multiple beamformer circuits. Each beamformer circuit may implement multiple transceiver channels. Each transceiver channel generally includes a transmit channel (or chain) and a receive channel (or chain). According to an embodiment of the present invention, the transceiver channels may be coupled to the antenna elements via corresponding matching networks and integrated TRX switches for exchanging corresponding bidirectional radio frequency signals. The transceiver channels and the antenna elements generally form a two - dimensional antenna network.

[0033] Reference Figure 3, showing a diagram illustrating an example implementation of a single-polarization version of a phased array antenna panel 92 according to an embodiment of the present invention. In the example, the phased array antenna panel 92 may include a plurality of antenna elements 110, a plurality of beamformer circuits 112a - 112m, and a plurality of blocks (or circuits) 114a - 114k. In an embodiment implementing a single-polarization phased array antenna panel, the antenna elements 110 are typically implemented as single-polarization (or monopole) antenna elements. Each of the circuits 112a - 112m may implement a single-polarization beamformer circuit. Each of the circuits 114a - 114k may implement a combiner / splitter circuit. The circuits 112a - 112m and 114a - 114k may be implemented using hardware, a combination of hardware and software, and / or simulated using software. In the example, the signal RF may be exchanged with one of the circuits 114a - 114k. The signals FSW and CTRL may be exchanged with the circuits 112a - 112m.

[0034] The antenna elements 110 in the phased array antenna panel 92 can be used for both transmitting and receiving. The physical positioning of the antenna elements 110 generally provides two-dimensional (e.g., horizontal and vertical) control of the fields 102a - 102n. In the example, the antenna elements 110 may be arranged in a two-dimensional (e.g., N×M) grid pattern, where N is an integer value divisible by 2. However, other dimensions of the grid pattern may also be implemented accordingly to meet the design criteria of a particular implementation. The circuits 112a - 112m are generally operable to multiplex / demultiplex the signal RF with the plurality of antenna elements 110. In various embodiments, each of the circuits 112a - 112m may be mounted on a substrate of the phased array antenna panel 92 adjacent (e.g., centered) to a plurality (or a group) of antenna elements 110. In the example, each of the circuits 112a - 112m generally includes a plurality of transceiver channels coupled to the corresponding antenna elements 110. In the example, each of the circuits 112a - 112m may be coupled to four adjacent antenna elements 110 (e.g., arranged in a 2×2 grid around each of the circuits 112a - 112m). However, other numbers of adjacent antenna elements 110 (e.g., 1, 2, 4, 18, etc.) may also be implemented to meet the design criteria of a particular implementation.

[0035] Circuits 112a - 112m can be configured to switch between a transmit mode and a receive mode in response to signal FSW. In the transmit mode, circuits 112a - 112m can be operable to rapidly change the set values (e.g., phase values, gain values, etc.) used by the transceiver channels so as to control the beams (or fields) 102a - 102n and / or 104a - 104n formed by the phased array antenna panel 92. In various embodiments, each of circuits 112a - 112m can include a memory, register storage, and / or a look - up table (LUT) which can be used to store multiple phase and gain values for each channel of circuits 112a - 112m, the multiple phase and gain values corresponding to multiple beams in a predetermined beam space. In an example, the multiple phase and gain values for each channel can be associated with an index corresponding to each beam of the beam space. In various embodiments, each of circuits 112a - 112m can be implemented as one or more integrated circuits (e.g., in a package or a multi - chip module (MCM)).

[0036] In various embodiments, each of circuits 114a - 114k can be implemented as a combiner / splitter circuit. In an example, circuits 114a - 114k can be implemented as Wilkinson combiner / splitters. In various embodiments, circuits 114a - 114k can be coupled together to form a network that couples circuits 112a - 112m to the input / output of the phased array antenna panel 92, which is configured to present / receive signal RF. In the transmit mode, circuits 114a - 114k are generally operable to distribute the power in signal RF among circuits 112a - 112m. In the receive mode, circuits 114a - 114k can be operable to combine the power received in signals from circuits 112a - 112m into signal RF. Circuits 112a - 112n and 114a - 114k are generally configured to provide substantially equal path lengths between the RF input / output of the phased array antenna panel 92 and each of circuits 112a - 112m.

[0037] Reference Figure 4 , shows a diagram illustrating an example implementation of a dual - polarized phased array antenna panel 94 according to another example embodiment of the present invention. In embodiments implementing dual - polarized transceiver channels, the phased array antenna panel 94 can be used in place of Figure 1The phased array antenna panel 92 therein. In the example, the phased array antenna panel 94 may include a plurality of blocks (or circuits) 200a - 200m, a plurality of blocks (or circuits) 210, a plurality of blocks (or circuits) 212a - 212k, and a plurality of blocks (or circuits) 214a - 214k. In embodiments implementing a dual - polarized phased array antenna panel, the block 210 is typically implemented as a dual - polarized (or bipolar or dipole) antenna element. Each of the circuits 200a - 200m may implement a dual - polarized beamformer circuit. Each of the circuits 212a - 212k and 214a - 214k may implement a combiner / splitter circuit. The circuits 200a - 200m, 212a - 212k, and 214a - 214k may be implemented using hardware, a combination of hardware and software, and / or simulated using software. In embodiments implementing the dual - polarized phased array antenna panel 94, the signal RF may include a vertical polarization component (e.g., RFV) and a horizontal polarization component (e.g., RFH). In the example, the signal RFV may be exchanged with one of the circuits 212a - 212k, and the signal RFH may be exchanged with one of the circuits 214a - 214k. The signals FSW and CTRL may be exchanged with the circuits 200a - 200m.

[0038] The antenna element 210 in the phased array antenna panel 94 can be used for both transmitting and receiving. The physical positioning of the antenna element 210 generally provides two - dimensional (e.g., horizontal and vertical) control of the fields 102a - 102n. In the example, the antenna element 210 may be arranged in a two - dimensional (e.g., N×M) grid pattern, where N is an integer value divisible by 2. However, other dimensions of the grid pattern may also be implemented accordingly to meet the design criteria of a particular implementation.

[0039] The circuits 200a - 200m are generally operable to multiplex / demultiplex the signals RFV and RFH with the plurality of antenna elements 210. In various embodiments, each of the circuits 200a - 200m may be mounted on a substrate of the phased array antenna panel 94 adjacent to the plurality (or a group) of antenna elements 210. Each of the circuits 200a - 200m may have corresponding horizontal (H) and vertical (V) input / outputs, which may be coupled to the corresponding horizontal (H) and vertical (V) input / outputs (or feeds) of the adjacent antenna elements 210. In the example, each of the circuits 200a - 200m typically includes a plurality of transceiver channels coupled to the corresponding horizontal and vertical input / outputs. In the example, each of the circuits 200a - 200m may be coupled to four adjacent antenna elements 210 (e.g., arranged in a 2×2 grid around each circuit 200a - 200m).

[0040] Circuits 200a - 200m can be configured to switch between a transmit mode and a receive mode in response to signal FSW. In the transmit mode, circuits 200a - 200m can be operable to rapidly change set values (e.g., phase values, gain values, etc.) used by a transceiver channel so as to control fields 102a - 102n formed by phased array antenna panel 94. In various embodiments, each of circuits 200a - 200m can include a memory, register storage, and / or a look - up table (LUT) which can be used to store multiple phase and gain values for each channel of circuits 200a - 200m, the multiple phase and gain values corresponding to multiple beams in a predetermined beamspace. In an example, the multiple phase and gain values for each channel can be associated with an index corresponding to each beam of the beamspace. In various embodiments, each of circuits 200a - 200m can be implemented as one or more integrated circuits (e.g., in a package or a multi - chip module (MCM)). In an example, each of circuits 200a - 200m can be mounted on a substrate of phased array antenna panel 94 adjacent (e.g., centered) to a corresponding antenna element 210.

[0041] In various embodiments, each of circuits 212a - 212k and 214a - 214k can implement a combiner / splitter circuit. In an example, each of circuits 212a - 212k and 214a - 214k can be implemented as a Wilkinson combiner / splitter circuit. Circuits 212a - 212k can be coupled together to form a network that couples circuits 200a - 200m to the input / output of phased array antenna panel 94, which is configured to present / receive signal RFV. Circuits 214a - 214k can be coupled together to form a network that couples circuits 200a - 200m to the input / output of phased array antenna panel 94, which is configured to present / receive signal RFH. In the transmit mode, circuits 212a - 212k and 214a - 214k are generally operable to distribute power in signals RFV and RFH respectively among circuits 200a - 200m. In the receive mode, circuits 212a - 212k and 214a - 214k can be operable to combine the power received in signals from circuits 200a - 200m into signals RFV and RFH respectively. Circuits 212a - 212n, 212a - 212k, and 214a - 214k are generally configured to provide substantially equal path lengths between the RFV input / output and RFH input / output of phased array antenna panel 94 and each of circuits 200a - 200m.

[0042] Reference Figure 5, showing a diagram illustrating an example implementation of a single-polarization beamformer circuit 112i according to an example embodiment of the present invention. In the example, the single-polarization beamformer circuit 112i may represent Figure 2 the single-polarization beamformer circuits 112a - 112m in

[0043] In various embodiments, the signal RF may be presented / received by the common RF input / output RFC, and the antenna input / output ports RF1 - RFN may be coupled to the corresponding antenna elements 110. The single-polarization beamformer circuit 112i typically implements a number of transceiver channels corresponding to the number of antenna input / output ports RF1 - RFN. In various embodiments, each transceiver channel may include a corresponding transmit channel and a corresponding receive channel. The transceiver channels are typically configured to switch between transmit and receive based on the signal FSW.

[0044] The single-polarization beamformer circuit 112i typically implements a transmit mode and a receive mode. In the example, the state of the signal FSW may determine whether the transmit mode is active or the receive mode is active. In the transmit mode, the single-polarization beamformer circuit 112i is typically configured to receive a radio frequency signal RF at the common input / output port RFC and present the radio frequency signal at the antenna input / output ports RF1 - RFN. The signals presented at each of the antenna input / output ports RF1 - RFN are generated by the single-polarization beamformer circuit 112i in response to the radio frequency signal RF received at the common input / output port RFC and a corresponding number of setting values (e.g., gain, phase, etc.) for each transceiver channel, the corresponding number of setting values corresponding to each of the antenna input / output ports RF1 - RFN. In the receive mode, the single-polarization beamformer circuit 112i is typically configured to combine the radio frequency signals received at the antenna input / output ports RF1 - RFM to present as the signal RF at the common input / output port RFC.

[0045] The single-polarization beamformer circuit 112i may include block (or circuit) 302, block (or circuit) 304, a plurality of blocks (or circuits) 306a - 306n, and block (or circuit) 308. Circuit 302 may implement an interface circuit. In various embodiments, circuit 302 may implement a digital interface. Circuit 304 may implement a hardwired address (e.g., chip ID) for the beamformer circuit 112i. Circuits 306a - 306n may implement transceiver (TRX) channels. Circuit 308 may implement a 1-to-N combiner / splitter network.

[0046] In an example, signals FSW and CTRL are exchanged with circuit 302. In an example, circuit 302 may include a serial interface. Circuit 302 may be configured to conform to one or more serial interface standards, which include but are not limited to: Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), daisy chain, etc. In an example, circuit 302 may be configured to allow programming and control of the single-polarization beamformer circuit 112i using a serial communication link (or bus). In an example, circuit 302 may be configured to program and control circuits 306a - 306n in response to signals CTRL and FSW. In an example, circuit 302 may control whether circuits 306a - 306n operate in a transmit mode or a receive mode in response to signal FSW.

[0047] In an example, circuit 302 may implement a 4-wire embedded SPI core. In an example, circuit 302 may have a first pin that can receive a first signal (e.g., MOSI), a second pin that can present a second signal (e.g., MISO), a clock input pin that can receive a clock signal (e.g., SCLK), and a chip enable (or chip select) pin that can receive a signal (e.g., SS / CS). In an example, signals MOSI, MISO, SCLK, and SS / CS may be components of (a) signal CTRL. In an example, circuit 302 may include a transmit / receive function switching pin that can receive signal FSW. In an example, signals MOSI, MISO, SCLK, and SS / CS may be configured to implement a 4-wire SPI protocol interface as shown in Table 1 below:

[0048] Table 1

[0049] Signal Function MOSI Master Out Slave In MISO <![CDATA Master In Slave Out > SCLK Serial Clock SS / CS Slave Select / Chip Select

[0050] In an example, the circuit 304 may set the physical address of the beamformer circuit 112i based on hardware-coded address bits (or pins). In various embodiments, a hardwired address having a plurality (e.g., X) of input bits (e.g., ADD1, ADD2, ..., ADD(X)) may be implemented. In an example, the address may be implemented with six bits (or pins). In some embodiments, the hardwired address may be set to a predetermined logic level (e.g., 0 or 1) by coupling multiple address pins to a predetermined power supply voltage (e.g., GND, VSS, or VDD). In some embodiments, the hardwired address bits may be hard-coded within the chip implementing the beamformer 112i. In some embodiments, within the chip implementing the beamformer 112i, the hardwired address bits are programmable during manufacturing. In an example, fuses, antifuses, or other conventional techniques may be used to program the hardwired address bits.

[0051] Reference Figure 6 , shows a diagram illustrating an example implementation of a dual-polarization beamformer circuit 200i according to an example embodiment of the present invention. In an example, the dual-polarization beamformer circuit 200i may represent Figure 3 the dual-polarization beamformer circuits 200a - 200m in

[0052] In various embodiments, the signal RFV may be presented / received by the common RF input / output RFVC, the signal RFH may be presented / received by the common RF input / output RFHC, the vertical antenna input / output ports RFV1 - RFV(N) may be coupled to corresponding vertical inputs / outputs of the respective antenna elements 210, and the horizontal antenna input / output ports RFH1 - RFH(N) may be coupled to corresponding horizontal inputs / outputs of the respective antenna elements 210. The dual-polarization beamformer circuit 200i typically implements a corresponding number (e.g., N) of transceiver channels corresponding to the number of pairs of vertical and horizontal antenna input / output ports (RFV1, RFH1), (RFV2, RFH2), … (RFV(N), RFH(N)). In various embodiments, each transceiver channel may include a corresponding transmit channel and a corresponding receive channel. The transceiver channels are typically configured to switch between transmit and receive based on the signal FSW.

[0053] The dual-polarization beamformer circuit 200ii generally implements a transmit mode and a receive mode. In an example, the state of the signal FSW can determine whether the transmit mode is active or the receive mode is active. In the transmit mode, the dual-polarization beamformer circuit 200i is generally configured to receive radio frequency signals at the common input / output ports RFVC and RFHC and present radio frequency signals at the antenna input / output ports RFV1-RFV(N) and RFH1-RFH(N). The dual-polarization beamformer circuit 200i generates signals presented at each of the antenna input / output ports RFV1-RFV(M) and RFH1-RFH(N) in response to the radio frequency signals received at the common input / output ports RFVC and RFHC, and a corresponding number of set values (e.g., gain, phase, etc.), the corresponding number of set values corresponding to each of the antenna input / output ports RFV1-RFV(M) and RFH1-RFH(N).

[0054] In an example, the dual-polarization beamformer circuit 200i can include block (or circuit) 402, block (or circuit) 404, a plurality of blocks (circuits) 406a-406n, and block (or circuit) 408. Circuit 402 can implement an interface circuit. In various embodiments, circuit 402 can implement a digital interface. Circuit 404 can implement a hardwired address (e.g., chip ID) for the beamformer circuit 200i. Circuits 406a-406n can implement transceiver (TRX) channels. Circuit 408 can implement a 1-N dual-channel combiner / splitter network.

[0055] In an example, the signals FSW and CTRL are exchanged with circuit 402. In an example, circuit 402 can include a serial interface. Circuit 402 can be configured to conform to one or more serial interface standards, including but not limited to: Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), daisy chain, etc. In an example, circuit 402 can be configured to allow programming and control of the dual-polarization beamformer circuit 200i using a serial communication link (or bus). In an example, circuit 402 can be configured to program and control circuits 406a-406n in response to signals CTRL and FSW. In an example, circuit 402 can control whether circuits 406a-406n operate in the transmit mode or the receive mode in response to the signal FSW.

[0056] In an example, circuit 402 may implement a 4-wire embedded SPI core. In an example, circuit 402 may have a first pin that can receive a first signal (e.g., MOSI), a second pin that can present a second signal (e.g., MISO), a clock input pin that can receive a clock signal (e.g., SCLK), and a chip enable (or chip select) pin that can receive a signal (e.g., SS / CS). In an example, the signals MOSI, MISO, SCLK, and SS / CS may be components of the (multiple) signal CTRL. In an example, circuit 402 may include a transmit / receive function switching pin that can receive a signal FSW. In an example, the signals MOSI, MISO, SCLK, and SS / CS may be configured to implement a 4-wire SPI protocol interface as shown above in Table 1.

[0057] In an example, circuit 404 may set the physical address of the dual-polarization beamformer circuit 200i based on hardware-encoded address bits (or pins). In various embodiments, a hardwired address having multiple (e.g., X) input bits (e.g., ADD1, ADD2,..., ADD(X)) may be implemented. In an example, the address may be implemented with six bits (or pins). In some embodiments, the hardwired address may be set to a predetermined logic level (e.g., 0 or 1) by connecting multiple address pins to a predetermined power supply voltage (e.g., GND, VSS, or VDD). In some embodiments, within the chip implementing the beamformer 200i, the hardwired address bits may be hard-coded during manufacturing. In some embodiments, the hardwired address bits may be programmed within the chip implementing the beamformer 200i. In an example, fuses, antifuses, or other conventional techniques may be used to program the hardwired bits.

[0058] Reference Figure 7 , a block diagram of transceiver circuit 306i is shown, which illustrates Figure 5 and Figure 6 an example implementation of the transceiver circuit in Figure 6 . In an example, transceiver circuit 306i may represent a single-polarization beamformer transceiver circuit (or channel) 306a - 306d. In another example, transceiver circuit 306i may represent

[0059] In various embodiments, circuit 310 may represent transceiver circuitry used in applications including but not limited to: cellular base stations (e.g., 2G, 3G, 4G, 5G, etc.), wireless communication systems, wireless local area networks (WLANs), wireless backhaul channels, broadband repeaters, community antenna television (CATV) networks, macro cells, micro cells, picocells, femtocells, mobile devices (MDs), and / or portable handheld devices (UEs). In some embodiments, circuit 310 may represent a radar application including but not limited to target detection, ranging, and / or through-wall imaging. In an example, transceiver circuit 310 generally includes both a transmit chain and a receive chain. Both the transmit chain and the receive chain may include radio frequency (RF) amplifiers.

[0060] In an example, the transmit chain may include an input amplifier 320, a variable (programmable) phase shifter 322, a variable (programmable) attenuator 324, and one or more output amplifier stages 326. The output of the transmit chain may be coupled to the input of a matching network and an integrated transmit-receive (TRX) switch circuit 100 according to an embodiment of the present invention. In an example, input amplifier 320 may be implemented as a low noise amplifier (LMA). Output amplifier stage 326 may include a driver, a preamplifier, and / or a power amplifier (PA). In an example, the receive chain may include a low noise amplifier (LNA) 330, a variable (programmable) phase shifter 332, and a variable (programmable) attenuator 334. The output of circuit 100 may be coupled to the input of low noise amplifier (LNA) 330. In various embodiments, RF switch 312, variable phase shifter 322, variable attenuator 324, variable phase shifter 332, and variable attenuator 334 may be implemented using conventional techniques.

[0061] In one example, the input of the transmit chain and the output of the receive chain can be coupled to a transmission line or an RF transceiver system via an RF switch 312. In the example, the output of the transmit chain and the input of the receive chain can be coupled to a transmission line or an antenna (ANT) via circuit 100. In various embodiments, circuit 100 can implement an output matching network for the transmit chain, an input matching network for the receive chain, and an integrated TRX switch according to an embodiment of the present invention. The integrated TRX switch of circuit 100 generally has a topology that can be incorporated into impedance matching elements of a power amplifier stage 326 and a low noise amplifier 330. The integration of the TRX switch topology according to an embodiment of the present invention with the impedance matching elements of a power amplifier (PA) stage 326 and a low noise amplifier 330 generally results in minimal signal loss (e.g., a reduction in output power and PAE in the transmit chain or a reduction in noise figure (NF) in the receive chain). The integration of the TRX switch topology according to an embodiment of the present invention with the impedance matching elements of a power amplifier stage 326 and a low noise amplifier 330 generally also reduces the chip area (compared to conventional high isolation TRX switches).

[0062] In various embodiments, the TRX switch topology according to an embodiment of the present invention is particularly applicable to, but not limited to, differential or transformer-based transmitter and receiver implementations. The TRX switch topology generally does not include any components between the output of the transmit chain (e.g., the output of PA 326) and the input / output of the transceiver circuit. Thus, the TRX switch topology can be implemented without specific switch components that need to withstand high voltage swings. Since high breakdown voltage switch components are not required, the TRX switch topology according to an embodiment of the present invention is particularly suitable for implementation in advanced short channel body or silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technologies with low breakdown voltages (e.g., below 1 volt).

[0063] Although the TRX switch topology according to an embodiment of the present invention can be implemented using a minimum apparent number of components, the TRX switch topology generally provides high isolation between the transmit chain and the receive chain circuits. Although the TRX switch topology according to an embodiment of the present invention can be highly integrated with the transmit chain and the receive chain circuits, the TRX switch topology can be designed independently of the transmit chain and the receive chain circuits and can be incorporated into the corresponding impedance matching networks at any development stage. Generally, co-design and / or co-optimization are not required.

[0064] Now refer to Figure 8, showing a diagram illustrating an example implementation of a TRX switch circuit 100 according to a differential embodiment. In the example, output transformers 500 of a differential power amplifier 326 in a transmit chain and input transformers 502 of a differential low noise amplifier 330 in a receive chain can be respectively configured to incorporate and implement a TRX switch topology according to an embodiment of the present invention. In the example, the output of output transformer 500 can be directly connected to the input / output (e.g., 10 or 310) of a transceiver circuit.

[0065] A series capacitor 504 can be connected between the input of input transformer 502 and the output of output transformer 500. A shunt switch 506 can be connected in parallel with the input winding of input transformer 502. In the example, each of transformers 500 and 502 at the output matching network of a transmitter and the input matching network of a receiver can be implemented using planar coupled spiral transmission lines on a chip or a printed circuit board. In the example, capacitor 504 can be implemented as a metal-insulator-metal (MIM) capacitor or a finger capacitor on a chip, or as a ceramic capacitor on a printed circuit board. Capacitor 504 can also be implemented using one or more MOS devices.

[0066] Reference Figure 9 , showing a diagram illustrating another example implementation of a TRX switch 100 utilizing a topology according to a single-ended embodiment of the present invention. In the example, an impedance matching network and a bias choke (or inductor) 510 of a power amplifier 326 in a transmit chain and an impedance matching network and a bias choke (or inductor) 512 of a low noise amplifier 330 in a receive chain can be configured to incorporate and implement a TRX switch topology according to an embodiment of the present invention. In the example, the output of power amplifier 326 can be directly connected to the input / output of transceiver circuit 10 or 310. A series capacitor 504 can be connected between the input of low noise amplifier 330 and the output of power amplifier 326. A shunt switch 506 can be connected between the input of low noise amplifier 330 and the circuit ground potential of transceiver circuit 310. Each of the bias chokes (or inductors) 510 and 512 can be implemented using planar spiral transmission lines on a chip or a printed circuit board. Capacitor 504 can be implemented as a MIM capacitor or a finger capacitor on a chip, or as a ceramic capacitor on a printed circuit board. Capacitor 504 can also be implemented using one or more MOS devices.

[0067] Reference Figure 10 , showing a diagram illustrating another example implementation of a TRX switch 100 utilizing a topology according to a single-ended embodiment of the present invention. In the example, a shunt capacitor 508 can be added to Figure 9In the implementation. In the example, the impedance matching network and bias choke 510 of the power amplifier 326 in the transmit chain, and the impedance matching network and bias choke 512 of the low-noise amplifier 330 in the receive chain can be configured to incorporate and implement the TRX switch topology according to an embodiment of the present invention. In the example, the output of the power amplifier 326 can be directly connected to the input / output of the transceiver circuit 10 or 310.

[0068] In various embodiments, the series capacitor 504 can be connected between the input of the low-noise amplifier 330 and the output of the power amplifier 326. The shunt switch 506 can be connected between the input of the low-noise amplifier 330 and the circuit ground potential of the transceiver circuit 310. The shunt capacitor 508 can be connected between the input of the low-noise amplifier 330 and the circuit ground potential of the transceiver circuit 310. Each bias choke (or inductor) 510 and 512 can be implemented using planar spiral transmission lines on a chip or printed circuit board. The capacitors 504 and 508 can be implemented as MIM capacitors on a chip, or finger capacitors, or ceramic capacitors on a printed circuit board. The capacitors 504 and 508 can also be implemented using one or more MOS devices. In some embodiments, the parasitic capacitance of the switch 506 can be used to implement all or part of the shunt capacitor 508.

[0069] Reference Figure 11 , shows a diagram illustrating another example implementation of a TRX switch 100 utilizing a topology according to a differential embodiment of the present invention. In the example, the shunt capacitor 508 can be added to the Figure 8 implementation shown. The shunt capacitor 508 can be used to adjust the optimal impedance presented to the input of the receive chain to improve the noise behavior. The capacitor 508 generally does not affect the performance of the transmit chain (e.g., when the switch 506 is closed). In the example, the output transformer 500 of the differential power amplifier 326 in the transmit chain, and the input transformer 502 of the differential low-noise amplifier 330 in the receive chain, can be respectively configured to incorporate and implement the TRX switch topology according to an embodiment of the present invention.

[0070] In the example, the output of the output transformer 500 can be directly connected to the input / output of the transceiver circuit 10 or 310. A series capacitor 504 can be connected between the input of the input transformer 502 and the output of the output transformer 500. A parallel switch 506 and a parallel capacitor 508 can be connected in parallel with the input winding of the input transformer 502 and can be implemented using planar coupled spiral transmission lines on-chip or on a printed circuit board. Capacitors 504 and 508 can be implemented as on-chip MIM capacitors, or finger capacitors, or as ceramic capacitors on a printed circuit board. Capacitors 504 and 508 can also be implemented using one or more MOS devices. The parasitic capacitance of the switch 506 can be used to implement all or part of the parallel capacitor 508.

[0071] Reference Figure 12 , shows a plot of graph 800, which illustrates Figure 11 the simulated voltage waveforms of the TRX switch in

[0072] . Waveform 802 illustrates the voltage level at the node formed by the connection of the output of the transformer 500 to the input / output of the transceiver 10 or 310. Waveform 804 illustrates the voltage level at the node formed by the connection of the input of the transformer 502, the series capacitor 504, the parallel switch 506, and the parallel capacitor 508. Generally, the TRX switch topology according to embodiments of the present invention does not introduce distortion into the output signal of the transceiver channel 10 or 310. Additionally, the parallel switch 506 is not affected by the high voltage swings of the transmitter channel operation, and thus it can be implemented using low voltage sub-micron transistor technology (e.g., silicon-on-insulator CMOS transistors with a breakdown voltage below 1 volt).

[0073] When the terms "may" and "generally" are used in combination with "copulative verbs" and verbs, they are intended to convey the following intention: This specification is exemplary and is considered broad enough to cover the two specific examples presented in this disclosure and alternative examples that can be derived based on the content of this disclosure. As used herein, the terms "may" and "generally" should not be construed as necessarily implying an expectation or possibility of omitting the corresponding elements.

[0074] Although the present invention has been specifically shown and described with reference to embodiments of the present invention, those skilled in the art will understand that various changes in form and detail can be made without departing from the scope of the present invention.

Claims

1. A device for communication, comprising: a transceiver circuit; a series capacitor; and a parallel switch, wherein (i) the transceiver circuit includes a transmit chain and a receive chain, the transmit chain includes an output matching network and a first transformer, the receive chain includes an input matching network and a second transformer, (ii) the output of the output matching network is directly connected to the input / output of the transceiver circuit, (iii) the series capacitor is connected between the input of the input matching network and the output of the output matching network, (iv) the parallel switch is connected between the input of the input matching network and the circuit ground potential of the transceiver circuit, (v) the transceiver circuit, the series capacitor and the parallel switch are part of a beamformer integrated circuit, (vi) the input / output of the transceiver circuit is connected to one of a plurality of antenna elements constituting a phased array antenna, and (vii) only using the parallel switch connected between the input of the input matching network and the circuit ground potential of the transceiver circuit, the input / output of the transceiver circuit is switched between the transmit chain and the receive chain.

2. The device according to claim 1, wherein the beamformer integrated circuit includes a plurality of transceiver circuits, each transceiver circuit including a corresponding series capacitor and a corresponding parallel switch.

3. The device according to claim 2, wherein each of the plurality of transceiver circuits further includes a corresponding parallel capacitor connected in parallel with the parallel switch.

4. The device according to claim 1, further comprising a parallel capacitor connected in parallel with the parallel switch.

5. The device according to claim 4, wherein the value of the parallel capacitor is selected to adjust the impedance of the input presented to the receive chain to improve the noise behavior.

6. The device according to claim 5, wherein the value of the parallel capacitor is selected considering the parasitic capacitance of the parallel switch.

7. The device according to claim 1, wherein the parallel switch includes one or more transistors.

8. The device according to claim 7, wherein the parallel switch includes a stacked transistor device.

9. The device according to claim 7, wherein the transistor is implemented using at least one of the following various technologies: complementary metal oxide semiconductor (CMOS) technology, high electron mobility transistor (HEMT) technology, pseudomorphic high electron mobility transistor (pHEMT) technology, and silicon-on-insulator technology.

10. The device according to claim 7, wherein the transistor is implemented using a low-voltage sub-micron transistor having a low breakdown voltage.

11. The device according to claim 1, wherein the series capacitor and the parallel switch are implemented within the footprint of the input matching network and the output matching network of the transceiver circuit.

12. The device according to claim 1, wherein: the series capacitor includes at least one of a metal-insulator-metal capacitor, a finger capacitor, and a ceramic capacitor.

13. The apparatus according to claim 1, wherein the first transformer and the second transformer are implemented as planar coupled spiral transmission lines.

14. The apparatus according to claim 1, wherein the series capacitor comprises one or more metal-oxide semiconductor devices.

15. The apparatus according to claim 1, wherein the input winding of the second transformer is in parallel with the parallel switch.

16. The apparatus according to claim 1, wherein the differential output of the power amplifier of the transmit chain is connected to the input winding of the first transformer, and the output winding of the second transformer is connected to the differential input of the low-noise amplifier of the receive chain.

17. A method for switching a transmission medium between a transmitter channel and a receiver channel of a transceiver circuit, the method comprising the steps of: directly connecting an output of an output matching network of a transmit chain of the transceiver circuit to an input / output of the transceiver circuit, wherein the output matching network comprises a first transformer; connecting a series capacitor between an input of an input matching network of a receive chain of the transceiver circuit and the output of the output matching network, wherein the input matching network comprises a second transformer; and connecting a parallel switch between the input of the input matching network and a circuit ground potential of the transceiver circuit, wherein (i) the transceiver circuit, the series capacitor, and the parallel switch are part of a beamforming integrated circuit, (ii) the input / output of the transceiver circuit is connected to one of a plurality of antenna elements constituting a phased array antenna, and (iii) the input / output of the transceiver circuit is switched between the transmit chain and the receive chain only using the parallel switch connected between the input of the input matching network and the circuit ground potential of the transceiver circuit.

18. The method according to claim 17, further comprising connecting a parallel capacitor in parallel with the parallel switch.

19. The method according to claim 18, wherein the value of the parallel capacitor is selected to adjust an impedance presented to an input of the receive chain to improve noise behavior.

20. The method according to claim 19, wherein the value of the parallel capacitor is selected considering a parasitic capacitance of the parallel switch.

Images